Preparation method of power device, power device, semiconductor device and electronic equipment

Abstract

The invention relates to a preparation method of a power device, the power device, a semiconductor device and electronic equipment. The method comprises the following steps: providing a substrate; forming a front layer structure on the substrate; a first groove, a second groove and a third groove are formed in the front-layer structure, the second groove is located in the middle of the front-layer structure, the first groove and the third groove are located on the two opposite sides of the front-layer structure respectively, and the first groove, the second groove and the third groove are all exposed out of the top face of the substrate; forming a protective layer covering the top surface on the front layer structure; forming a patterned first photoresist layer on the protective layer, wherein the patterned first photoresist layer exposes the second groove covered by the protective layer; and performing ion implantation on the patterned first photoresist layer as a mask to form a body region of a first ion type. At least the source of stress can be reduced, the trouble of alignment deviation of polycrystalline silicon is avoided, and shallow junction ion implantation of a body region can be completely attached to the edge of a polycrystalline silicon gate.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit manufacturing technology, and particularly to a method for manufacturing a power device, a power device, a semiconductor device, and an electronic device. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, in the BCD process of the sub-micron generation, the process of forming the body region (e.g., p-body) of the power device (LDMOS) has always troubled engineers because the ions to be implanted in this region must ensure the intersection of the shallow junction and also exactly coincide with the edge of the polysilicon.

[0003] In the prior art, a thick mask layer is generally used, and the etching and ion implantation of polysilicon are carried out simultaneously during the formation of the body region. However, the thick mask layer will cause stress on the wafer surface, and during the etching of polysilicon, the thick mask layer causes the pattern loading effect. The process of simultaneously etching and ion implanting polysilicon results in misalignment between the body region and polysilicon due to etching the polysilicon gate twice, causing the polysilicon gate widths on the left and right sides of the common-source LDNMOS to be inconsistent, thereby leading to the problem of power device mismatch. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a method for manufacturing a power device, a power device, a semiconductor device, and an electronic device, which can at least reduce the source of stress, without worrying about the misalignment problem of polysilicon caused by etching two polysilicon layers, and can also make the shallow junction ion implantation in the body region completely fit the edge of the polysilicon gate.

[0005] To achieve the above object and other objects, in a first aspect, the present disclosure provides a method for manufacturing a power device, including: providing a substrate;

[0006] Forming a front-layer structure on the substrate, the front-layer structure including a gate oxide layer, a polysilicon layer, a mask layer, and a silicon oxide layer stacked in sequence along the direction perpendicular to the substrate;

[0007] Forming a first trench, a second trench, and a third trench in the front-layer structure, the second trench being located at the middle position of the front-layer structure, the first trench and the third trench being respectively located on opposite sides of the front-layer structure, and the first trench, the second trench, and the third trench all exposing the top surface of the substrate;

[0008] Forming a protective layer covering the top surface on the front-layer structure;

[0009] A patterned first photoresist layer is formed on the protection layer, and the patterned first photoresist layer exposes a second trench covered by the protection layer;

[0010] Using the patterned first photoresist layer as a mask for ion implantation to form a body region of a first ion type.

[0011] In the method for manufacturing a power device in the above embodiment, during the process of forming the power device, by pre-etching the front layer structure and forming the protection layer, silicon oxide layer and photoresist layer, at least the source of stress can be reduced, and there is no need to worry about the alignment deviation of polysilicon caused by etching two polysilicon layers. Moreover, the shallow junction ion implantation of the body region can be completely fitted to the edge of the polysilicon gate, achieving the ability to perform high-precision ion implantation.

[0012] In one embodiment, the method further includes: removing the first photoresist layer; removing the protection layer; removing the mask layer.

[0013] In one embodiment, the thickness of the protection layer is 80 Å - 120 Å.

[0014] In one embodiment, forming a front layer structure on the substrate includes: sequentially depositing a gate oxide layer, a polysilicon layer, a mask layer, and a silicon oxide layer on the substrate to form a first front layer structure; etching the first front layer structure to obtain a first trench, a second trench, and a third trench; removing the silicon oxide layer.

[0015] In one embodiment, etching the first front layer structure includes: forming a patterned second photoresist layer on the first front layer structure, and the patterned second photoresist layer exposes opposite sides and a middle position of the silicon oxide layer; using the patterned second photoresist layer as a mask to etch the first front layer structure to form a first trench, a second trench, and a third trench that expose the top surface of the substrate.

[0016] In one embodiment, the method further includes: removing the second photoresist layer and the silicon oxide layer.

[0017] In a second aspect, an embodiment of the present disclosure further provides a power device, including: a substrate;

[0018] A front layer structure, located on the substrate, the front layer structure includes a gate oxide layer, a polysilicon layer, a mask layer, and a silicon oxide layer stacked in sequence along the direction perpendicular to the substrate. A first trench, a second trench, and a third trench are formed in the front layer structure. The second trench is located in the middle position of the front layer structure, and the first trench and the third trench are respectively located on opposite sides of the front layer structure. The first trench, the second trench, and the third trench all expose the top surface of the substrate;

[0019] A protective layer, located on the front-layer mechanism;

[0020] A patterned first photoresist layer, located on the protective layer, and the patterned first photoresist layer exposes a second trench covered by the protective layer.

[0021] In the power device in the above embodiment, based on the self-alignment process, during the formation of the power device, by pre-etching the front-layer structure and forming the protective layer, silicon oxide layer and photoresist layer, at least the sources of stress can be reduced, and there is no need to worry about the alignment deviation of polysilicon caused by etching of two polysilicon layers. Moreover, the shallow junction ion implantation of the body region can be completely fitted to the edge of the polysilicon gate, achieving the ability to perform high-precision ion implantation.

[0022] In a third aspect, an embodiment of the present disclosure further provides a semiconductor device, including: the power device in any of the above embodiments, which can at least reduce parasitic capacitance, improve the operating frequency of the power device without affecting the on-resistance of the power device.

[0023] In a fourth aspect, an embodiment of the present disclosure further provides a memory, including: the semiconductor device in any of the above embodiments.

[0024] In a fifth aspect, an embodiment of the present disclosure further provides an electronic device, including: the semiconductor device in any of the above embodiments, or the memory in any of the above embodiments. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0026] Figure 1 It is a schematic flowchart of a method for manufacturing a power device provided in an embodiment;

[0027] Figure 2 It is a schematic structural diagram of the structure obtained in step S2000 in the method for manufacturing a power device provided in an embodiment;

[0028] Figure 3 It is a schematic structural diagram of the structure obtained in step S3000 in the method for manufacturing a power device provided in an embodiment Figure 1 ;

[0029] Figure 4 It is a schematic longitudinal sectional structure diagram of the structure obtained in step S3000 in the method for manufacturing a power device provided in an embodiment Figure 2 ;

[0030] Figure 5 Schematic diagram of the structure obtained in step S4000 of the method for manufacturing a power device provided in an embodiment;

[0031] Figure 6 Schematic diagram of the structure obtained in step S5000 of the method for manufacturing a power device provided in an embodiment;

[0032] Figure 7 Schematic diagram of the structure obtained in step S6000 of the method for manufacturing a power device provided in an embodiment;

[0033] Figure 8 Schematic diagram of the structure obtained by the method for manufacturing a power device provided in an embodiment Figure 1 ;

[0034] Figure 9 Schematic diagram of the structure obtained by the method for manufacturing a power device provided in an embodiment Figure 2 .

[0035] Description of reference numerals:

[0036] 201, substrate; 202, gate oxide layer; 203, polysilicon layer; 204, mask layer; 205, silicon oxide layer; 301, patterned second photoresist layer; 401, first trench; 402, second trench; 403, third trench; 501, protective layer; 601, patterned first photoresist layer. Detailed Description of the Invention

[0037] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0039] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, e.g., the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0040] Spatial relationship terms such as “under,” “below,” “lower,” “beneath,” “above,” “upper,” etc. are used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “under” or “beneath” or “underneath” another element or feature will be oriented “on” the other element or feature. Thus, the exemplary terms “under” and “beneath” can include both an upper and a lower orientation. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0041] As used herein, the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms “comprises” and / or “comprising” are used in this specification, the presence of features, integers, steps, operations, elements, and / or components can be identified, but one or more other features, integers, steps, operations, elements, components, and / or groups are not excluded from the presence or addition. Also, as used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, and thus variations in the shapes shown are to be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular will typically have rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0043] Please refer to Figures 1-9 , embodiments of the present disclosure provide a method for manufacturing a power device, including the following steps:

[0044] Step S1000: Provide a substrate 201.

[0045] In step S1000, the substrate 201 can be used to provide support for the front-layer structure. Among them, the substrate 201 can be composed of semiconductor materials, insulating materials, conductor materials, or any combination thereof. The substrate 201 can be a single-layer structure or a multi-layer structure. For example, the substrate 201 can be a silicon substrate 201, a silicon germanium substrate 201, a silicon germanium carbon substrate 201, a silicon carbide substrate 201, a gallium arsenide substrate 201, an indium arsenide substrate 201, an indium phosphide substrate 201, or other III / V semiconductor substrates 201 or II / VI semiconductor substrates 201. Or, for another example, the substrate 201 can be a layered substrate 201 including, for example, silicon / silicon carbide, silicon on insulator, or silicon germanium on insulator. Therefore, the type of the substrate 201 should not limit the protection scope of the present disclosure.

[0046] Step S2000: Form a front-layer structure on the substrate 201.

[0047] Among them, the front-layer structure includes a gate oxide layer 202, a polysilicon layer 203, a mask layer 204, and a silicon oxide layer 205 stacked in sequence along the direction perpendicular to the substrate 201.

[0048] Step S3000: Form a first trench 401, a second trench 402, and a third trench 403 in the front-layer structure.

[0049] Among them, the second trench 402 is located at the middle position of the front-layer structure, the first trench 401 and the third trench 403 are respectively located on opposite sides of the front-layer structure, and the first trench 401, the second trench 402, and the third trench 403 all expose the top surface of the substrate 201.

[0050] Step S4000: Form a protective layer 501 covering the top surface on the front-layer structure.

[0051] Step S5000: Form a patterned first photoresist layer 601 on the protective layer 501.

[0052] Among them, the patterned first photoresist layer 601 exposes the second trench 402 covered by the protective layer 501.

[0053] Step S6000: Use the patterned first photoresist layer 601 as a mask for ion implantation to form a body region of the first ion type.

[0054] In the preparation method of the power device in the above embodiment, during the formation of the power device, by pre-etching the front-layer structure and forming the protective layer 501, the silicon oxide layer 205 and the photoresist layer, at least the sources of stress can be reduced, and there is no need to worry about the alignment deviation of polysilicon caused by the etching of the two polysilicon layers 203. Moreover, the shallow junction ion implantation of the body region can be completely fitted to the edge of the polysilicon gate, achieving the ability of high-precision ion implantation.

[0055] In step S2000, please refer to Figure 2 , taking the depletion-type LDNMOS as an example, the front-layer structure includes a gate oxide layer 202, a polysilicon layer 203, a mask layer 204, and a silicon oxide layer 205 stacked in sequence along the direction perpendicular to the substrate 201.

[0056] Specifically, the front layer structure can be formed by a deposition process. As an example, the deposition process can be physical vapor deposition (PVD) or chemical vapor deposition (CVD). Specifically, physical vapor deposition (PVD) transfers materials from a source to the wafer surface by physical means, mainly including the following techniques: Sputtering, which uses high-energy ions to bombard the target material, causing target atoms to sputter onto the wafer surface, with a high deposition rate and suitable for large-area uniform deposition; Evaporation, which evaporates the material by heating, and the vapor condenses into a film on the wafer surface, with high purity and suitable for low-melting-point materials. Chemical vapor deposition (CVD) forms a thin film on the wafer surface through chemical reactions, mainly including atmospheric pressure CVD (APCVD), which deposits thin films through chemical reactions under atmospheric pressure and is mainly used for the deposition of insulating layers such as silicon oxide and silicon nitride; low-pressure CVD (LPCVD), which deposits thin films through chemical reactions under low pressure and is mainly applied to the deposition of thin films such as polysilicon and silicon nitride; plasma-enhanced CVD (PECVD), which uses plasma to enhance chemical reactions and reduces the deposition temperature, mainly used for low-temperature deposition of insulating layers (such as silicon oxide and silicon nitride); atomic layer deposition (ALD), which deposits thin films layer by layer by alternately introducing precursor gases and is mainly used for the deposition of high-k materials (such as HfO2, Al2O3).

[0057] In step S3000, please refer to Figures 3-4 , the second trench 402 is located at the middle position of the front layer structure, that is, the ion implantation position of the body region. The first trench 401 and the third trench 403 are respectively located on opposite sides of the front layer structure to avoid left-right asymmetry of the power device.

[0058] Please continue to refer to Figure 3 , specifically, a front layer structure is formed on the substrate 201, including: sequentially depositing a gate oxide layer 202, a polysilicon layer 203, a mask layer 204, and a silicon oxide layer 205 on the substrate 201 to form a first front layer structure; etching the first front layer structure to obtain the first trench 401, the second trench 402, and the third trench 403; removing the silicon oxide layer 205.

[0059] In some embodiments, etching the first front layer structure includes: forming a patterned second photoresist layer 301 on the first front layer structure, and the patterned second photoresist layer 301 exposes opposite sides and the middle position of the silicon oxide layer 205; using the patterned second photoresist layer 301 as a mask to etch the first front layer structure to form the first trench 401, the second trench 402, and the third trench 403 that expose the top surface of the substrate 201.

[0060] As an example, wet etching or dry etching can be used to etch the front structure. Wet etching (Wet Etching) uses a chemical solution to react with the material, dissolve and remove the material. The etching rate is the same in all directions, resulting in lateral etching. The etching rate of different materials varies greatly, with good selectivity, low cost, and simple operation. It is used to remove large-area materials, clean the surface, etc. Dry etching (Dry Etching) removes the material through physical or chemical methods, mainly including: Plasma Etching, which uses reactive ions in the plasma to react with the material and remove the material. It has strong etching directionality and is suitable for fine patterns. By selecting appropriate gases and process parameters, high selectivity can be achieved, and it is more suitable for etching materials such as polysilicon, silicon oxide, and silicon nitride; Reactive Ion Etching (RIE), which combines physical sputtering and chemical reactions, uses high-energy ions to bombard the material surface to enhance the etching effect. It is suitable for high-precision pattern etching. By adjusting parameters such as RF power and gas flow rate, the etching rate and morphology can be precisely controlled, and it is more suitable for etching complex structures such as trenches and vias; Deep Reactive Ion Etching (DRIE), which achieves high aspect ratio etching by alternately performing etching and passivation steps. It is suitable for etching MEMS and three-dimensional structures. By optimizing process parameters, smooth sidewalls can be obtained, and it is more suitable for MEMS devices, TSV (Through-Silicon Via), etc.

[0061] In some embodiments, the method further includes: removing the second photoresist layer and the silicon oxide layer 205.

[0062] Optionally, in this application, the trench can be etched by wet etching. After the etching is completed, APM cleaning can also be performed. Specifically, APM cleaning (Ammonium Peroxide Mixture Cleaning) is a commonly used wet cleaning process for removing organic contaminants and particles on the wafer surface. APM cleaning is part of the RCA standard cleaning process and is widely used in front-end and back-end processes. The APM cleaning solution consists of the following three chemical substances: ammonium hydroxide (NH4OH), which provides an alkaline environment and helps remove organic contaminants; hydrogen peroxide (H2O2), which is used to remove metal contaminants and particles; and deionized water (DI Water), which has a dilution and rinsing effect. Among them, the steps of APM cleaning include: pre-cleaning, rinsing the wafer with deionized water to remove large particles and contaminants on the surface; APM cleaning, immersing the wafer in the APM cleaning solution, usually at 60 - 80 °C for about 10 - 20 minutes; rinsing, rinsing the wafer with a large amount of deionized water to remove the remaining cleaning solution and contaminants; and drying, drying the wafer surface by spin drying or nitrogen blowing. APM cleaning can efficiently remove organic contaminants and particles. The APM cleaning solution can effectively remove various contaminants, is applicable to various materials and process steps, and the chemical substances used in it have low costs and are easy to obtain.

[0063] In step S4000, please refer to Figure 5 , a protective layer 501 covering the top surface is formed on the front layer structure.

[0064] As an example, the protective layer 501 can be a carbon hard mask layer (carbon hard mask).

[0065] Specifically, the thickness of the protective layer 501 is 80 Å - 120 Å.

[0066] As an example, the thickness of the protective layer 501 can be 80 Å, 100 Å, 120 Å, etc.

[0067] In step S5000, please refer to Figure 6 , a patterned first photoresist layer 601 is formed on the protective layer 501.

[0068] Among them, the patterned first photoresist layer 601 exposes the second trench 402 covered by the protective layer 501.

[0069] Here, the patterned first photoresist layer 601 can be used as a mask for ion implantation. In this way, it not only ensures the accuracy of ion implantation but also ensures the symmetry of the power device.

[0070] In step S6000, please refer to Figure 7, using the patterned first photoresist layer 601 as a mask for ion implantation to form a body region of the first ion type.

[0071] Among them, the ion implantation angle can be vertical implantation.

[0072] Here, the steps of ion implantation can include: cleaning the wafer surface to ensure no contamination; generating the required impurity ions in the ion source; accelerating the ions to the required energy through an electric field; bombarding the wafer surface with the ion beam and implanting to a specified depth; performing high-temperature annealing to repair lattice damage and activate impurity atoms.

[0073] As an example, the ion implantation equipment includes an ion source, an accelerator, a mass analyzer, a scanning system, a vacuum system, etc. Among them, the ion source is used to generate the required impurity ions; the accelerator is used to accelerate the ions to a high-energy state; the mass analyzer is used to select ions of a specific mass; the scanning system is used to control the scanning of the ion beam on the wafer; the vacuum system is used to maintain a high-vacuum environment and reduce the collision of ions with gas molecules.

[0074] In some embodiments, the method further includes: removing the first photoresist layer 601; removing the protective layer 501; removing the mask layer 204.

[0075] Please refer to Figure 8 , Figure 8 , for the structure of the power device formed after removing the first photoresist layer 601 and the protective layer 501.

[0076] Please refer to Figure 9 , Figure 9 , for the structure of the power device formed after removing the mask layer 204.

[0077] In the method for manufacturing the power device in the above embodiments, during the process of forming the power device, by pre-etching the front-layer structure and forming the protective layer 501, the silicon oxide layer 205, and the photoresist layer, at least the sources of stress can be reduced, and there is no need to worry about the misalignment problem of polysilicon caused by the etching of the two polysilicon layers 203. Moreover, the shallow junction ion implantation of the body region can be completely fitted to the edge of the polysilicon gate, achieving the ability to perform high-precision ion implantation.

[0078] It should be understood that although Figure 1 the steps in the flowchart are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figure 1At least a part of the steps therein may include multiple steps or multiple stages. These steps or stages are not necessarily executed and completed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0079] Based on the same inventive concept, embodiments of the present disclosure also provide a power device obtained by a preparation method of a power device in the foregoing embodiments. The solution for solving problems provided by the power device is similar to the solution described in the above method. Therefore, for the specific limitations in one or more embodiments of the power device provided below, reference can be made to the limitations on the preparation method of the depletion-type transistor in the foregoing text, and details will not be repeated here.

[0080] In some embodiments, please refer to Figure 7 , a power device, comprising: a substrate 201; a front-layer structure located on the substrate 201, the front-layer structure includes a gate oxide layer 202, a polysilicon layer 203, a mask layer 204 and a silicon oxide layer 205 stacked in sequence along the direction perpendicular to the substrate 201. A first trench 401, a second trench 402 and a third trench 403 are formed in the front-layer structure. The second trench 402 is located at the middle position of the front-layer structure. The first trench 401 and the third trench 403 are respectively located on opposite sides of the front-layer structure. The first trench 401, the second trench 402 and the third trench 403 all expose the top surface of the substrate 201; a protective layer 501 located on the front-layer mechanism; a patterned first photoresist layer 601 located on the protective layer 501, and the patterned first photoresist layer 601 exposes the second trench 402 covered by the protective layer 501.

[0081] In the power device in the above embodiments, during the process of forming the power device, by pre-etching the front-layer structure and forming the protective layer 501, the silicon oxide layer 205 and the photoresist layer, at least the source of stress can be reduced, and there is no need to worry about the alignment deviation of polysilicon caused by etching of the two polysilicon layers 203. Moreover, the shallow junction ion implantation of the body region can be completely fitted to the edge of the polysilicon gate, achieving the ability of high-precision ion implantation.

[0082] In some embodiments, embodiments of the present disclosure also provide a semiconductor device, comprising: the power device in any of the above embodiments, which can at least reduce the source of stress, and there is no need to worry about the alignment deviation of polysilicon caused by etching of the two polysilicon layers 203. Moreover, the shallow junction ion implantation of the body region can be completely fitted to the edge of the polysilicon gate, achieving the ability of high-precision ion implantation..

[0083] In some embodiments, the embodiments of the present disclosure further provide a memory, including: the semiconductor device in any of the above embodiments.

[0084] In some embodiments, the present disclosure provides an electronic device, including the memory in any of the embodiments of the present disclosure; or the semiconductor device in any of the embodiments of the present disclosure. The electronic device is, for example but not limited to, consumer electronic products, home electronic products, vehicle-mounted electronic products, financial terminal products and other suitable types of electronic products. Consumer electronic products such as mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products such as smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products such as vehicle-mounted navigation devices, vehicle-mounted DVDs, etc. Financial terminal products such as ATMs, terminals for self-service business handling, etc. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0085] The above embodiments only represent several implementation manners of the present disclosure. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the appended claims.

Claims

1. A method for preparing a power device, characterized in that: The method comprises: providing a substrate; forming a front layer structure on the substrate, wherein the front layer structure comprises a gate oxide layer, a polysilicon layer, a mask layer and a silicon oxide layer stacked in sequence along a direction perpendicular to the substrate; forming a first groove, a second groove and a third groove in the front layer structure, wherein the second groove is located in the middle of the front layer structure, the first groove and the third groove are respectively located on two opposite sides of the front layer structure, and the first groove, the second groove and the third groove all expose the top surface of the substrate; forming a protective layer covering the top surface on the front layer structure; forming a patterned first photoresist layer on the protective layer, wherein the patterned first photoresist layer exposes the second groove covered by the protective layer; Ion implantation is performed using the patterned first photoresist layer as a mask to form a body region of a first ion type.

2. The method according to claim 1, characterized in that The method further comprises: removing the first photoresist layer; removing the protective layer; The mask layer is removed.

3. The method according to claim 1, characterized in that The thickness of the protective layer is 80 Å-120 Å.

4. The method according to claim 1, characterized in that A front layer structure is formed on the substrate, comprising: Depositing a gate oxide layer, a polysilicon layer, a mask layer and a silicon oxide layer in sequence on the substrate to form a first front layer structure; Etching the first front layer structure to obtain the first groove, the second groove and the third groove; The silicon oxide layer is removed.

5. The method according to claim 4, characterized in that Etching the first front layer structure includes: forming a patterned second photoresist layer on the first front layer structure, wherein the patterned second photoresist layer exposes two opposite sides and a middle position of the silicon oxide layer; The first front layer structure is etched using the patterned second photoresist layer as a mask to form a first trench, a second trench and a third trench that expose the top surface of the substrate.

6. The method according to claim 5, characterized in that The method further comprises: The second photoresist layer and the silicon oxide layer are removed.

7. A power device, characterized in that: include: providing a substrate; A front layer structure is located on the substrate, the front layer structure comprises a gate oxide layer, a polysilicon layer, a mask layer and a silicon oxide layer stacked in sequence along a direction perpendicular to the substrate, a first trench, a second trench and a third trench are formed in the front layer structure, the second trench is located in the middle of the front layer structure, the first trench and the third trench are respectively located on two opposite sides of the front layer structure, and the first trench, the second trench and the third trench all expose the top surface of the substrate; A protective layer, located on the front layer structure; The patterned first photoresist layer is located on the protective layer, and the patterned first photoresist layer exposes the second groove covered by the protective layer.

8. A semiconductor device, characterized in that: include: The power device according to claim 7.

9. A memory, characterized in that: include: The semiconductor device according to claim 8.

10. An electronic device, characterized in that: include: The semiconductor device according to claim 8; or The memory as claimed in claim 9.

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