Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. An n-type drift region and a p-type well region are formed in a semiconductor substrate. An n-type first drain region and an n-type second drain region are formed in the n-type drift region, and an n-type source region and an n-type semiconductor region are formed in the p-type well region. The impurity concentration of the n-type semiconductor region is lower than the impurity concentration of the n-type source region. The gate electrode includes an n-type first gate electrode portion and an n-type second gate electrode portion extending in the Y direction, and a p-type gate connection portion connecting the first gate electrode portion and the second gate electrode portion. In plan view, the n-type source region is arranged between the first gate electrode portion and the second gate electrode portion.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-213010, filed on December 18, 2023, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be applied to, for example, a semiconductor device having a MOSFET and a method for manufacturing the same. Background Art

[0004] In a power conversion circuit such as an inverter circuit, for example, a power switching element such as a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) is used. The power switching element is formed on a semiconductor substrate.

[0005] The disclosed technologies are listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2019-46875

[0007] Patent Document 1 discloses a technology related to a semiconductor device having an LDMOSFET. Summary of the Invention

[0008] It is desirable to improve the performance of a semiconductor device having a MOSFET.

[0009] Other objects and novel features will become apparent from the description of this specification and the drawings.

[0010] According to one embodiment, a semiconductor device includes a gate electrode formed over a main surface of a semiconductor substrate via a gate dielectric film, a drift region of a first conductivity type and a well region of a second conductivity type formed in the semiconductor substrate, and a first drain region and a second drain region of the first conductivity type formed in the drift region. The semiconductor device further includes a source region of the first conductivity type and an LDD region formed in the well region. The gate electrode includes a first gate electrode portion and a second gate electrode portion of the first conductivity type extending in a first direction, and a gate connection portion of the second conductivity type connecting the first gate electrode portion and the second gate electrode portion. In a plan view, a part of the first gate electrode portion, a part of the second gate electrode portion, and a part of the gate connection portion overlap with the well region, and another part of the first gate electrode portion, another part of the second gate electrode portion, and another part of the gate connection portion overlap with the drift region. In a plan view, the LDD region is formed along the first gate electrode portion, the gate connection portion, and the second gate electrode portion.

[0011] According to one embodiment, the performance of a semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment.

[0013] Figure 2 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment.

[0014] Figure 3 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment.

[0015] Figure 4 is a plan view of a main part of a semiconductor device according to a first embodiment.

[0016] Figure 5 is a plan view of a main part of a semiconductor device according to a first embodiment.

[0017] Figure 6 is a plan view of a main part of a semiconductor device according to a first embodiment.

[0018] Figure 7 is a cross-sectional view of a main part during a manufacturing step of a semiconductor device according to a first embodiment.

[0019] Figure 8 is Figure 7 a cross-sectional view of a main part during a manufacturing step of a semiconductor device after

[0020] Figure 9 is as Figure 8 a cross-sectional view of a main part during a manufacturing step of a semiconductor device such as

[0021] Figure 10 is Figure 8 a cross-sectional view of a main part during a manufacturing step of a semiconductor device after

[0022] Figure 11 is as Figure 10 a cross-sectional view of a main part during a manufacturing step of a semiconductor device such as

[0023] Figure 12 is Figure 10 a cross-sectional view of a main part during a manufacturing step of a semiconductor device after

[0024] Figure 13 is as Figure 12 a cross-sectional view of a main part during a manufacturing step of a semiconductor device such as

[0025] Figure 14Yes Figure 10 Principal partial plan view during the manufacturing steps of a semiconductor device thereafter.

[0026] Figure 15 Yes Figure 12 Principal partial cross-sectional view during the manufacturing steps of a semiconductor device thereafter.

[0027] Figure 16 Is as Figure 15 Principal partial cross-sectional view during the manufacturing steps of a semiconductor device as such.

[0028] Figure 17 Yes Figure 15 Principal partial cross-sectional view during the manufacturing steps of a semiconductor device thereafter.

[0029] Figure 18 Is as Figure 17 Principal partial cross-sectional view during the manufacturing steps of a semiconductor device as such.

[0030] Figure 19 Yes Figure 17 Principal partial cross-sectional view during the manufacturing steps of a semiconductor device thereafter.

[0031] Figure 20 Is as Figure 19 Principal partial cross-sectional view during the manufacturing steps of a semiconductor device as such.

[0032] Figure 21 Yes Figure 19 Principal partial cross-sectional view during the manufacturing steps of a semiconductor device thereafter.

[0033] Figure 22 Is as Figure 21 Principal partial cross-sectional view during the manufacturing steps of a semiconductor device as such.

[0034] Figure 23 Yes Figure 21 Principal partial cross-sectional view during the manufacturing steps of a semiconductor device thereafter.

[0035] Figure 24 Is as Figure 23 Principal partial cross-sectional view during the manufacturing steps of a semiconductor device as such.

[0036] Figure 25 Yes Figure 23 Principal partial cross-sectional view during the manufacturing steps of a semiconductor device thereafter.

[0037] Figure 26 Is as Figure 25 Principal partial cross-sectional view during the manufacturing steps of a semiconductor device as such.

[0038] Figure 27 is Figure 25 a main part cross-sectional view during a manufacturing step of a semiconductor device thereafter.

[0039] Figure 28 is as Figure 27 a main part cross-sectional view during a manufacturing step of a semiconductor device.

[0040] Figure 29 is an explanatory diagram for explaining a problem of an example to be inspected.

[0041] Figure 30 is an explanatory diagram for explaining a problem of an example to be inspected.

[0042] Figure 31 is a main part cross-sectional view during a manufacturing step of a semiconductor device according to a second embodiment.

[0043] Figure 32 is a main part plan view during a manufacturing step of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION

[0044] In the following embodiments, for convenience, they are explained by dividing them into multiple sections or embodiments when necessary; unless otherwise specifically indicated, they are not unrelated to each other, and one can be related to the other as part or all of a modification example, details, supplementary explanations, etc. Further, in the following embodiments, when referring to the number of elements, etc. (including the number of elements, numerical values, quantities, ranges, etc.), it is not limited to a specific number, but can be not less than or equal to the specific number, except in cases where the number is specifically indicated and is clearly limited to the specific number in principle. Further, in the following embodiments, needless to say, constituent elements (including element steps, etc.) are not necessarily essential, except in cases where they are specifically specified and cases where they are considered obviously essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is assumed that these shapes, etc. are substantially approximate or similar to these shapes, etc., except in cases where they are specifically specified and cases where they are considered obvious in principle. This also applies to the above numerical values and ranges.

[0045] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

[0046] In the drawings used in the embodiments, even in the case of a cross-sectional view, hatching may be omitted to make the drawings easier to see. Also, even in the case of a plan view, hatching may be used to make the drawings easier to see.

[0047] In addition, the plan view corresponds to the case of viewing from a plane substantially parallel to the main surface or rear surface of the semiconductor substrate SB. The bottom surface and the lower surface mean the same thing. The height position corresponds to the distance from the rear surface of the semiconductor substrate SB. The depth position corresponds to the distance from the main surface of the semiconductor substrate SB.

[0048] In addition, in the present application, MOSFET (metal oxide semiconductor field effect transistor) or LDMOSFET (laterally diffused metal oxide semiconductor field effect transistor) includes not only MOSFET using an oxide film as a gate dielectric film, but also MOSFET using a dielectric film other than an oxide film as a gate dielectric film. Additionally, LDMOSFET may also be referred to as HV-MOSFET (high voltage metal oxide semiconductor field effect transistor) or DEMOSFET (drain extended metal oxide semiconductor field effect transistor).

[0049] Furthermore, an n-channel MOSFET may be considered an n-type MOSFET, and a p-channel MOSFET may be considered a p-type MOSFET. In this context, n-type means that the conductivity type of the channel during the on-state is n-type, and p-type means that the conductivity type of the channel during the on-state is p-type.

[0050] First embodiment

[0051] The structure of semiconductor devices

[0052] Figures 1 to 3 A cross-sectional view orthogonal to the main surface of the semiconductor substrate SB is shown. Figures 4 to 6 A plan view parallel to the main surface of the semiconductor substrate SB is shown. Figure 4 , Figure 5 and Figure 6 The planar areas shown are identical to one another. Figures 4 to 6 The cross-sectional view along line AA corresponds to Figure 1 , Figures 4 to 6 The cross-sectional view along line BB corresponds to Figure 2 ,and Figures 4 to 6 The cross-sectional view along line CC corresponds to Figure 3 .although Figure 4 is a plan view, but in Figure 4 , the gate electrode GE is marked by a hatching line. Figure 5 yes Figures 1 to 3 A plan view at a height position H1 is shown.Figure 6 Yes Figures 1 to 3 A plan view at the height position H2 shown. In Figure 6 it, the planar position of the gate electrode GE is indicated by a dashed line, and the planar positions of the n-type drain regions DR1 and DR2 are indicated by a dotted line.

[0053] The semiconductor device of this first embodiment includes a power switching element used in a power conversion circuit such as an inverter circuit, and herein, the transistor configuring the power switching element is an LDMOSFET.

[0054] As Figures 1 to 6 shown, the semiconductor device of this first embodiment includes a semiconductor substrate SB, an LDMOSFET 1 formed on the main surface of the semiconductor substrate SB, and a dielectric film IL formed on the main surface of the semiconductor substrate SB.

[0055] The semiconductor substrate SB can be made of, for example, p-type single crystal silicon into which a p-type impurity (such as boron (B)) is introduced.

[0056] The semiconductor substrate SB can use an epitaxial wafer. In this case, the semiconductor substrate SB includes a p-type substrate main body made of, for example, a single crystal silicon substrate and a p-type semiconductor layer formed on the p-type substrate main body by epitaxial growth. The main surface of the semiconductor substrate SB is formed by the main surface of the p-type semiconductor layer. In Figures 1 to 3 it, a structure including a p-type substrate main body and a p-type semiconductor layer is shown as the semiconductor substrate SB. An n-type buried layer can be formed in the upper part of the p-type substrate main body, and the p-type semiconductor layer can be formed on the n-type buried layer.

[0057] The LDMOSFET 1 is an n-type (n-channel) LDMOSFET.

[0058] The LDMOSFET 1 includes a p-type well region PB, an n-type drift region ND, n-type drain regions DR1, DR2, an n-type semiconductor region EX, a plurality of n-type source regions SR, a plurality of p-type semiconductor regions PR, a p-type resurf region RF, a p-type semiconductor region HP, a gate dielectric film GF, and a gate electrode GE.

[0059] A p-type well region PB, an n-type drift region ND, an n-type drain region DR1, an n-type drain region DR2, an n-type semiconductor region EX, a plurality of n-type source regions SR, a plurality of p-type semiconductor regions PR, a p-type resurf region RF, and a p-type semiconductor region HP are formed in a semiconductor substrate SB. A gate electrode GE is formed over a main surface of the semiconductor substrate SB via a gate dielectric film GF. A dielectric film IL is formed over the main surface of the semiconductor substrate SB so as to cover the LDMOSFET 1.

[0060] The gate electrode GE includes a gate electrode portion GE1, a gate electrode portion GE2, and a gate connection portion GEC connecting the gate electrode portion GE1 and the gate electrode portion GE2. The gate connection portion GEC, the gate electrode portion GE1, and the gate electrode portion GE2 are integrally formed.

[0061] The gate electrode portion GE1 and the gate electrode portion GE2 extend in the Y direction, respectively. The gate electrode portion GE1 and the gate electrode portion GE2 are spaced apart from each other in the X direction. One end of the gate electrode portion GE1 in the Y direction and one end of the gate electrode portion GE2 in the Y direction are connected to the gate connection portion GEC extending in the X direction.

[0062] Although Figure 4 not shown in the figure, the other end of the gate electrode portion GE1 in the Y direction and the other end of the gate electrode portion GE2 in the Y direction are connected to a gate connection portion similar to the gate connection portion GEC. The structure of the semiconductor substrate SB under the gate connection portion is similar to the structure of the semiconductor substrate SB under the gate connection portion GEC. The LDMOSFET 1 has a structure symmetric with respect to Figure 4 the D-D line shown.

[0063] Here, the Y direction corresponds to the gate width direction of each of the gate electrode portions in the gate electrode portion GE1 and the gate electrode portion GE2. The X direction corresponds to the gate length direction of each of the gate electrode portions in the gate electrode portion GE1 and the gate electrode portion GE2. The X direction and the Y direction intersect with each other and are preferably orthogonal to each other. Each of the X direction and the Y direction is parallel to the main surface of the semiconductor substrate SB.

[0064] As Figure 4As shown, the gate electrode portion GE1 includes a side surface S1 and a side surface S2 opposite to the side surface S1. The side surface S1 and the side surface S2 are substantially parallel to each other in the Y direction. The gate electrode portion GE2 includes a side surface S3 and a side surface S4 opposite to the side surface S3. The side surface S3 and the side surface S4 are substantially parallel to each other in the Y direction. The gate connection portion GEC includes a side surface S5 and a side surface S6 opposite to the side surface S5. The side surface S5 and the side surface S6 are substantially parallel to each other in the X direction. The side surface S2, the side surface S3, and the side surface S5 are the inner peripheral side surfaces of the gate electrode GE, and the side surface S1, the side surface S4, and the side surface S6 are the outer peripheral side surfaces of the gate electrode GE. The side surface S2 of the gate electrode portion GE1 and the side surface S3 of the gate electrode portion GE2 face each other in the X direction. The side surface S5 of the gate connection portion GEC intersects with the side surface S2 of the gate electrode portion GE1 and the side surface S3 of the gate electrode portion GE2.

[0065] As Figures 1 to 4 shown, sidewall spacers (sidewall dielectric films) SW1 formed of a dielectric film are formed on the inner peripheral side surfaces of the gate electrode GE. Sidewall spacers (sidewall dielectric films) SW2 formed of a dielectric film are formed on the outer peripheral side surfaces of the gate electrode GE. Accordingly, the sidewall spacer SW1 is formed on the side surface S2 of the gate electrode portion GE1, the side surface S3 of the gate electrode portion GE2, and the side surface S5 of the gate connection portion GEC. The sidewall spacer SW2 is formed on the side surface S1 of the gate electrode portion GE1, the side surface S4 of the gate electrode portion GE2, and the side surface S6 of the gate connection portion GEC.

[0066] As Figures 1 to 3 shown, a p-type well region (p-type semiconductor region) PB and an n-type drift region (n-type semiconductor region) ND are formed in the upper part of the semiconductor substrate SB. In Figures 1 to 3 the case of, a p-type resurf region (p-type semiconductor region) RF is formed below the bottom surface of the n-type drift region ND and the bottom surface of the p-type well region PB. The p-type impurity concentration of the p-type resurf region RF is higher than the p-type impurity concentration of the semiconductor substrate SB. The p-type resurf region RF may not be formed. In Figure 3 the case of, a p-type semiconductor region HP is formed below the gate connection portion GEC. The p-type impurity concentration of the p-type semiconductor region HP is higher than the p-type impurity concentration of the semiconductor substrate SB. The p-type semiconductor region HP may not be formed.

[0067] As Figure 4 and Figure 6As shown, in a plan view, the p-type well region PB is formed to include the region between the gate electrode portion GE1 and the gate electrode portion GE2. In the plan view, the p-type well region PB is surrounded by the n-type drift region ND. In the plan view, a part of the gate electrode portion GE1, a part of the gate electrode portion GE2, and a part of the gate connection portion GEC overlap with the p-type well region PB, and another part of the gate electrode portion GE1, another part of the gate electrode portion GE2, and another part of the gate connection portion GEC overlap with the n-type drift region ND.

[0068] A part of the p-type well region PB is located below the gate electrode portion GE1, another part of the p-type well region PB is located below the gate electrode portion GE2, and still another part of the p-type well region PB is located below the gate connection portion GEC. A part of the n-type drift region ND is located below the gate electrode portion GE1, another part of the n-type drift region ND is located below the gate electrode portion GE2, and still another part of the n-type drift region ND is located below the gate connection portion GEC.

[0069] As Figure 1 、 Figure 2 and Figure 6 shown, below the gate electrode portion GE1, the n-type drift region ND and the p-type well region PB are adjacent to each other in the X direction. Below the gate electrode portion GE2, the n-type drift region ND and the p-type well region PB are adjacent to each other in the X direction. As Figure 3 and Figure 6 shown, below the gate connection portion GEC, the n-type drift region ND and the p-type well region PB are adjacent to each other in the Y direction.

[0070] A PN junction is formed at the boundary between the p-type well region PB and the n-type drift region ND. The boundary between the p-type well region PB and the n-type drift region ND extends in the Y direction below the gate electrode portion GE1, extends in the X direction below the gate connection portion GEC, and extends in the Y direction below the gate electrode portion GE2.

[0071] As Figures 1 to 3As shown, a plurality of n-type source regions (n-type semiconductor regions) SR and a plurality of p-type semiconductor regions PR are formed in the p-type well region PB. The p-type impurity concentration of each p-type semiconductor region PR among the plurality of p-type semiconductor regions PR is higher than the p-type impurity concentration of the p-type well region PB. The p-type impurity concentration of the p-type well region PB is higher than the p-type impurity concentration of the semiconductor substrate SB. The upper surfaces of each n-type source region SR among the plurality of n-type source regions SR and the upper surfaces of each p-type semiconductor region PR among the plurality of p-type semiconductor regions PR reach the main surface of the semiconductor substrate SB. The bottom surfaces of each n-type source region SR among the plurality of n-type source regions SR and the bottom surfaces of each p-type semiconductor region PR among the plurality of p-type semiconductor regions PR are shallower than the bottom surface of the p-type well region PB.

[0072] As Figure 4 shown, in a plan view, the plurality of n-type source regions SR and the plurality of p-type semiconductor regions PR are arranged in rows in the Y direction in a region surrounded by the gate electrode GE. In a plan view, the p-type semiconductor regions PR and the n-type source regions SR are alternately arranged in the Y direction between the gate electrode portion GE1 and the gate electrode portion GE2. A PN junction is formed at the boundary between the n-type source region SR and the p-type semiconductor region PR adjacent in the Y direction. The plurality of n-type source regions SR and the plurality of p-type semiconductor regions PR arranged in the Y direction configure the array region RG. At both ends of the array region RG in the Y direction, p-type semiconductor regions PR are respectively arranged instead of n-type source regions SR. The p-type semiconductor region PR arranged at the end of the array region RG in the Y direction is referred to as the p-type semiconductor region PR1. In a plan view, the array region RG is surrounded by the gate electrode GE.

[0073] The p-type well region PB can be used as a back gate. The p-type well region PB can also be used as a punch-through blocking layer, which suppresses the depletion layer from extending from the drain of the LDMOSFET to the source. Each p-type semiconductor region PR among the plurality of p-type semiconductor regions PR can be used as a contact portion of the p-type well region PB.

[0074] As Figure 1 and Figure 2 shown, an n-type drain region (n-type semiconductor region) DR1 and an n-type drain region (n-type semiconductor region) DR2 are formed in the n-type drift region ND. The n-type impurity concentration of the n-type drain region DR1 and the n-type impurity concentration of the n-type drain region DR2 are higher than the n-type impurity concentration of the n-type drift region ND. The upper surfaces of the n-type drain region DR1 and the n-type drain region DR2 respectively reach the main surface of the semiconductor substrate SB. The bottom surfaces of the n-type drain region DR1 and the n-type drain region DR2 are respectively shallower than the bottom surface of the n-type drift region ND.

[0075] As Figure 4 shown, in a plan view, the n-type drain region DR1 extends in the Y direction such that the distance from the side surface S1 of the gate electrode portion GE1 to the n-type drain region DR1 is substantially constant. In the plan view, the n-type drain region DR2 extends in the Y direction such that the distance from the side surface S4 of the gate electrode portion GE2 to the n-type drain region DR2 is substantially constant. In the plan view, the n-type drain region DR1 and the n-type drain region DR2 are spaced apart from each other in the X direction. The gate electrode portion GE1 and the gate electrode portion GE2 are arranged between the n-type drain region DR1 and the n-type drain region DR2. The array region RG is arranged between the gate electrode portion GE1 and the gate electrode portion GE2. In the plan view, the gate electrode portion GE1 is arranged between the n-type drain region DR1 and the array region RG, and the gate electrode portion GE2 is arranged between the n-type drain region DR2 and the array region RG. In the plan view, the distance between the n-type drain region DR1 and the gate electrode portion GE1 is greater than the distance between the array region RG and the gate electrode portion GE1. In the plan view, the distance between the n-type drain region DR2 and the gate electrode portion GE2 is greater than the distance between the array region RG and the gate electrode portion GE2.

[0076] In the plan view, the n-type semiconductor region EX is formed so as to surround the array region RG. As Figures 1 to 3 shown, the n-type semiconductor region EX is formed in the p-type well region PB so as to contact the plurality of n-type source regions SR and the plurality of p-type semiconductor regions PR.

[0077] The n-type impurity concentration of the n-type semiconductor region EX is lower than the n-type impurity concentration of each of the plurality of n-type source regions SR. The upper surface of the n-type semiconductor region EX reaches the main surface of the semiconductor substrate SB. The bottom surface of the n-type semiconductor region EX is shallower than the bottom surface of each of the plurality of n-type source regions SR and is also shallower than the bottom surface of each of the plurality of p-type semiconductor regions PR. The n-type semiconductor region EX can be used as a lightly doped drain (LDD) region. Each n-type source region SR and the adjacent n-type semiconductor region EX can be used as a source region having an LDD structure.

[0078] The n-type semiconductor region EX is formed under the sidewall spacer SW1. In the plan view, the n-type semiconductor region EX extends along the sidewall spacer SW1 and overlaps with the sidewall spacer SW1. As Figure 4As shown, in a plan view, an n-type semiconductor region EX is formed along the inner peripheral side surface of a gate electrode GE. Accordingly, the n-type semiconductor region EX extends in the Y direction along the side surface S2 of a gate electrode portion GE1, extends in the X direction along the side surface S5 of a gate connection portion GEC, and further extends in the Y direction along the side surface S3 of a gate electrode portion GE2.

[0079] As Figures 1 to 3 shown, the n-type semiconductor region EX includes an n-type semiconductor region EX1 extending along the side surface S2 of the gate electrode portion GE1, an n-type semiconductor region EX2 extending along the side surface S5 of the gate connection portion GEC, and an n-type semiconductor region EX3 extending along the side surface S3 of the gate electrode portion GE2. The n-type semiconductor region EX is not formed under a sidewall spacer SW2.

[0080] As Figure 1 and Figure 5 shown, in the X direction, one side surface of each n-type source region SR among a plurality of n-type source regions SR and one side surface of each p-type semiconductor region PR among a plurality of p-type semiconductor regions PR are in contact with the n-type semiconductor region EX1. In the X direction, the other side surface of each n-type source region SR among the plurality of n-type source regions SR and the other side surface of each p-type semiconductor region PR among the plurality of p-type semiconductor regions PR are in contact with the n-type semiconductor region EX3. As Figure 2 and Figure 5 shown, in the Y direction, one side surface of the p-type semiconductor region PR1 is in contact with the n-type semiconductor region EX2. In the Y direction, the other side surface of the p-type semiconductor region PR1 is in contact with an adjacent n-type source region SR.

[0081] As Figure 5 shown, the n-type semiconductor region EX1 is in contact with the plurality of n-type source regions SR and the plurality of p-type semiconductor regions PR, and the n-type semiconductor region EX3 is in contact with the plurality of n-type source regions SR and the plurality of p-type semiconductor regions PR. Meanwhile, the n-type semiconductor region EX2 is in contact with the p-type semiconductor region PR1 but not in contact with any of the plurality of n-type source regions SR.

[0082] In a cross-sectional view orthogonal to the Y direction and intersecting the n-type source region SR, as Figure 1 shown, a part of a p-type well region PB and a part of an n-type drift region ND are located under the gate electrode portion GE1, and another part of the p-type well region PB and another part of the n-type drift region ND are located under the gate electrode portion GE2.

[0083] In a cross-sectional view orthogonal to the Y direction and intersecting the p-type semiconductor region PR, asFigure 2 As shown, a part of the p-type well region PB and a part of the n-type drift region ND are located under the gate electrode portion GE1, and another part of the p-type well region PB and another part of the n-type drift region ND are located under the gate electrode portion GE2.

[0084] In a cross-sectional view orthogonal to the X direction and intersecting the p-type semiconductor region PR1, as Figure 3 shown, a part of the p-type well region PB and a part of the n-type drift region ND are located under the gate connection portion GEC.

[0085] A channel (n-type inversion layer) is formed in the upper part of the p-type well region PB located under the gate electrode GE. Hereinafter, the region where the channel is formed is referred to as the channel formation region. The n-type semiconductor region EX is adjacent to the channel formation region. In a plan view, the n-type semiconductor region EX is interposed between the channel formation region and the array region RG. In a plan view, the n-type semiconductor region EX surrounds the array region RG, and the channel formation region surrounds the n-type semiconductor region EX and the array region RG.

[0086] The gate dielectric film GF is formed of, for example, a silicon oxide film. The gate electrode GE is formed of a silicon film, specifically, a polysilicon film (doped polysilicon film). The gate electrode portion GE1, the gate connection portion GEC, and the gate electrode portion GE2 are integrally formed, but the conductivity type of the gate connection portion GEC is different from the conductivity type of each of the gate electrode portion GE1 and the gate electrode portion GE2. The gate electrode portion GE1 is formed of an n-type silicon region PSN, the gate connection portion GEC is formed of a p-type silicon region PSP, and the gate electrode portion GE2 is formed of an n-type silicon region PSN. Therefore, the gate electrode portion GE1 and the gate electrode portion GE2 each have an n-type conductivity type, and the gate connection portion GEC has a p-type conductivity type.

[0087] When a voltage higher than the threshold voltage is applied to the gate electrode GE, a channel formed of an n-type inversion layer is formed in the upper part of the p-type well region PB located under the gate electrode GE. The n-type drain region DR1 and the plurality of n-type source regions SR are electrically connected to each other through the n-type drift region ND and the channel under the gate electrode portion GE1, and the n-type drain region DR2 and the plurality of n-type source regions SR are electrically connected to each other through the n-type drift region ND and the channel under the gate electrode portion GE2.

[0088] As Figures 4 to 6As shown, in a plan view, the n-type drift region ND is interposed between the p-type well region PB and the n-type drain region DR1, and the n-type drift region ND is interposed between the p-type well region PB and the n-type drain region DR2. Therefore, in the plan view, the n-type semiconductor region EX1, the channel formation region, and the n-type drift region ND exist between the array region RG and the n-type drain region DR1, and the n-type semiconductor region EX2, the channel formation region, and the n-type drift region ND exist between the array region RG and the n-type drain region DR2.

[0089] In addition, a metal silicide layer (not shown) may be formed on the n-type drain region DR1, on the n-type drain region DR2, on each of the plurality of n-type source regions SR among the plurality of n-type source regions SR, on each of the plurality of p-type semiconductor regions PR among the plurality of p-type semiconductor regions PR, and on the gate electrode GE.

[0090] Next, the structure above the semiconductor substrate SB will be described.

[0091] As Figures 1 to 3 shown, the semiconductor device of the first embodiment further includes a plurality of plugs (contact plugs) buried in the dielectric film IL and a plurality of wirings formed above the dielectric film IL.

[0092] The dielectric film IL is formed on the main surface of the semiconductor substrate SB so as to cover the gate electrode GE. The dielectric film IL may be formed of a laminated film including, for example, a silicon nitride film and a silicon oxide film on the silicon nitride film. The upper surface of the dielectric film IL is planarized.

[0093] A plurality of contact holes (via holes) are formed in the dielectric film IL, and a plurality of conductive plugs are formed in these plurality of contact holes. These plurality of plugs include a plurality of plugs P1, a plurality of plugs P2, a plurality of plugs P3, and a plurality of plugs P4. Each of the plugs P1, P2, P3, and P4 penetrates the dielectric film IL.

[0094] Each of the plurality of plugs P1 is disposed above the n-type drain region DR1 and is electrically connected to the n-type drain region DR1. Each of the plurality of plugs P2 is disposed above the n-type drain region DR2 and is electrically connected to the n-type drain region DR2. Each of the plurality of plugs P3 is disposed above each of the n-type source regions SR and is electrically connected to the n-type source region SR. Each of the plurality of plugs P4 is disposed above each of the p-type semiconductor regions PR and is electrically connected to the p-type semiconductor region PR. Therefore, each of the plugs P4 is electrically connected to the p-type well region PB via the p-type semiconductor region PR.

[0095] In addition, plugs are also arranged above the gate electrode GE, but the plugs above the gate electrode GE are not shown in Figures 1 to 3 the

[0096] A plurality of wirings are formed on the dielectric film IL. The plurality of wirings include a source wiring WS, a drain wiring WD1, and a drain wiring WD2.

[0097] The drain wiring WD1 is electrically connected to the n-type drain region DR1 via a plurality of plugs P1. The drain potential is supplied from the drain wiring WD1 to the n-type drain region DR1 via the plurality of plugs P1. The drain wiring WD2 is electrically connected to the n-type drain region DR2 via a plurality of plugs P2. The drain potential is supplied from the drain wiring WD2 to the n-type drain region DR2 via the plurality of plugs P2. The drain wiring WD1 and the drain wiring WD2 are electrically connected to each other via a wiring (not shown) located above the drain wiring WD1 and the drain wiring WD2.

[0098] The source wiring WS is electrically connected to a plurality of n-type source regions SR and a plurality of p-type semiconductor regions PR via a plurality of plugs P3 and a plurality of plugs P4, respectively. That is, the source wiring WS is electrically connected to the plurality of plugs P3 arranged above the plurality of n-type source regions SR and the plurality of plugs P4 arranged above the plurality of p-type semiconductor regions PR. Therefore, the source potential is supplied from the source wiring WS to the plurality of n-type source regions SR via the plurality of plugs P3, and is supplied from the source wiring WS to the plurality of p-type semiconductor regions PR via the plurality of plugs P4. Since the bottom surface of the plurality of p-type semiconductor regions PR is covered by the p-type well region PB, the source potential supplied to the plurality of p-type semiconductor regions PR is supplied from the plurality of p-type semiconductor regions PR to the p-type well region PB.

[0099] A gate wiring electrically connected to the gate electrode GE via a plug is formed on the dielectric film IL, but in Figures 1 to 3 it, the gate wiring is not shown.

[0100] The illustration and description of the structure located above the dielectric film IL, the drain wiring WD1, the drain wiring WD2, and the source wiring WS are omitted.

[0101] The LDMOSFET 1 can be configured by connecting a plurality of unit LDMOSFETs in parallel. In Figures 1 to 6 this case, the LDMOSFET 1 has a configuration in which two unit LDMOSFETs sharing a source are connected in parallel. The number of unit LDMOSFETs connected in parallel can be set as needed.

[0102] Manufacturing steps of the semiconductor device

[0103] Figure 9 and Figure 10 andFigure 12 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 and Figure 27 are cross-sectional views corresponding to the above Figure 1 and show a cross-sectional view along line A-A of Figures 4 to 6 . Figure 11 , Figure 13 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 and Figure 28 are cross-sectional views corresponding to the above Figure 3 and show a cross-sectional view along line C-C of Figures 4 to 6 .

[0104] As Figure 7 shown, a semiconductor substrate SB is prepared. The semiconductor substrate SB can be made of, for example, p-type single-crystalline silicon. An epitaxial wafer can be used as the semiconductor substrate SB. The semiconductor substrate SB can have an n-type buried layer formed therein.

[0105] Next, as Figure 8 and Figure 9 shown, a p-type resurf region RF and a p-type semiconductor region HP are formed in the semiconductor substrate SB using ion implantation or the like. In the first embodiment, the p-type resurf region RF and the p-type semiconductor region HP are formed, but one or both of the p-type RESURF region RF and the p-type semiconductor region HP may not be formed.

[0106] Next, as Figure 10 and Figure 11 shown, a photoresist pattern (mask layer) RP1 is formed on the main surface of the semiconductor substrate SB using photolithography technology. Thereafter, n-type impurities are implanted into the semiconductor substrate SB using the photoresist pattern RP1 as an ion implantation blocking mask to form an n-type drift region ND in the semiconductor substrate SB. After the ion implantation, the photoresist pattern RP1 is removed. The n-type drift region ND is formed from the main surface of the semiconductor substrate SB to a predetermined depth. In a plan view, the n-type drift region ND includes a region where a p-type well region PB will be formed later.

[0107] Next, as Figure 12 and Figure 13 shown, a silicon film PS is formed on the main surface of the semiconductor substrate SB via a gate dielectric film GF. The gate dielectric film GF is formed of, for example, a silicon oxide film. The silicon film PS is specifically formed of a polysilicon film.

[0108] Next, as Figure 14 shown, an n-type silicon region PSN and a p-type silicon region PSP are formed in the silicon film PS by ion implantation or the like.

[0109] Although Figure 14 it is a plan view, in Figure 14 , different hatching lines indicating different directions are applied to the n-type silicon region PSN and the p-type silicon region PSP. In Figure 14 , the position of the gate electrode GE formed later is indicated by a dashed line. As can be seen from Figure 14 and the above-mentioned Figure 4 , the regions of the gate electrode part GE1 and the gate electrode part GE2 forming the gate electrode GE are included in the n-type silicon region PSN, and the region of the gate connection part GEC forming the gate electrode GE is included in the p-type silicon region PSP.

[0110] Next, as Figure 12 and Figure 13 shown, a photoresist pattern (mask layer) RP2 is formed on the silicon film PS using a photolithography technique. The photoresist pattern RP2 has an opening part OP. The opening part OP has side surfaces OP1, OP2, and OP3. The side surfaces OP1 and OP2 are opposite to each other and parallel in the Y direction. The side surface OP3 intersects the side surfaces OP1 and OP2 and is parallel in the X direction. In Figure 12 and Figure 13 , the side surface facing the side surface OP3 is not shown.

[0111] Next, as Figure 15 and Figure 16 shown, by using the photoresist pattern RP2 as an etching mask to etch the silicon film PS, an opening part aligned with the opening part OP of the photoresist pattern RP2 is formed in the silicon film PS. Accordingly, side surfaces S2, S3, and S5 are formed as the side surfaces of the opening part of the silicon film PS. The side surface S2 of the silicon film PS is aligned with the side surface OP1 of the opening part OP, the side surface S3 of the silicon film PS is aligned with the side surface OP2 of the opening part OP, and the side surface S5 of the silicon film PS is aligned with the side surface OP3 of the opening part OP. Hereinafter, the entire combination of the opening part OP of the photoresist pattern RP2 and the opening part of the silicon film PS is referred to as the opening part OP.

[0112] Next, as Figure 17 and Figure 18As shown, by performing ion implantation using the silicon film PS and the photoresist pattern RP2 on the silicon film PS as an ion implantation blocking mask, p-type impurities are implanted into the semiconductor substrate SB, and a p-type well region PB is formed in the semiconductor substrate SB. The p-type well region PB is formed by implanting p-type impurities into a part of the n-type drift region ND. Therefore, the effective p-type impurity concentration of the p-type well region PB is defined by the difference between the n-type impurity concentration contained in the n-type drift region ND and the p-type impurity concentration implanted to form the p-type well region PB. The p-type impurity concentration of the p-type well region PB is higher than the p-type impurity concentration of the p-type semiconductor substrate SB. The p-type well region PB is formed from the main surface of the semiconductor substrate SB to a depth above a predetermined depth.

[0113] For the ion implantation for forming the p-type well region PB, inclined ion implantation is used. In the case of inclined ion implantation, the direction of ion implantation is inclined with respect to the normal direction of the main surface of the semiconductor substrate SB. By forming the p-type well region PB using inclined ion implantation, the p-type well region PB is formed at a position overlapping the opening portion OP in a plan view, and a part of the p-type well region PB is formed below the silicon film PS. Therefore, in the plan view, the p-type well region PB is formed to include the opening portion OP. The planar size (planar area) of the p-type well region PB is larger than the planar size (planar area) of the opening portion OP.

[0114] Next, as Figure 19 and Figure 20 shown, by performing ion implantation using the silicon film PS and the photoresist pattern RP2 on the silicon film PS as an ion implantation blocking mask, n-type impurities are implanted into the semiconductor substrate SB, and an n-type semiconductor region EX is formed in the semiconductor substrate SB. The n-type semiconductor region EX is formed from the main surface of the semiconductor substrate SB to a depth above a predetermined depth. The depth of the bottom surface of the n-type semiconductor region EX is shallower than the depth of the p-type well region PB.

[0115] For the ion implantation for forming the n-type semiconductor region EX, vertical ion implantation is used. In the case of vertical ion implantation, the direction of ion implantation is parallel to the normal direction of the main surface of the semiconductor substrate SB. By forming the n-type semiconductor region EX using vertical ion implantation, the n-type semiconductor region EX is formed in self-alignment with the opening portion OP. Therefore, in the plan view, the n-type semiconductor region EX is formed to overlap the opening portion OP, and the outer peripheral side surface of the n-type semiconductor region EX substantially corresponds to the side surfaces of the opening portion OP. Therefore, in the plan view, the outer peripheral side surface of the n-type semiconductor region EX substantially corresponds to the side surfaces S2, S3, and S5 of the silicon film PS. In the plan view, the n-type semiconductor region EX is included by the p-type well region PB.

[0116] In the first embodiment, the p-type well region PB is formed after the formation of the n-type semiconductor region EX. It is also possible to form the p-type well region PB after the formation of the n-type semiconductor region EX.

[0117] Subsequently, after removing the photoresist pattern RP2, as Figure 21 and Figure 22 shown, a photoresist pattern (mask layer) RP3 is formed using photolithography to fill the opening portion (OP) in the silicon film PS and cover a part of the silicon film PS. The opening portion (OP) of the silicon film PS is covered by the photoresist pattern RP2. Thereafter, the silicon film PS is etched using the photoresist pattern RP3 as an etching mask to pattern the silicon film PS. Then, the photoresist pattern RP3 is removed. As Figure 23 and Figure 24 shown, the gate electrode GE is formed of the patterned silicon film PS.

[0118] The outer peripheral side surface of the gate electrode GE is formed by etching using the photoresist pattern RP3. Accordingly, the side surfaces S1, S4, and S6 are formed by etching using the photoresist pattern RP3. The inner peripheral side surface of the gate electrode GE is formed by the side surface of the opening portion OP. Accordingly, the side surfaces S2, S3, and S5 are formed by the side surface of the opening portion OP. The gate electrode portion GE1 and the gate electrode portion GE2 of the gate electrode GE are formed of the n-type silicon region PSN (see Figure 14 ), and the gate connection portion GEC of the gate electrode GE is formed of the p-type silicon region PSP (see Figure 14 ).

[0119] Next, as Figure 25 and Figure 26 shown, sidewall spacers SW1 are formed on the inner peripheral side surface of the gate electrode GE, and sidewall spacers SW2 are formed on the outer peripheral side surface of the gate electrode GE. The sidewall spacers SW1 and the sidewall spacers SW2 can be formed in the same step. For example, after forming a dielectric film on the semiconductor substrate SB to cover the gate electrode GE, the sidewall spacers SW1 and the sidewall spacers SW2 can be formed by back etching the dielectric film.

[0120] Next, as Figure 25 and Figure 26 shown, an n-type drain region DR1, an n-type drain region DR2, and a plurality of n-type source regions SR are formed in the semiconductor substrate SB using a method such as ion implantation.

[0121] An n-type drain region DR1 and an n-type drain region DR2 are formed in the n-type drift region ND. The n-type impurity concentration of the n-type drain region DR1 and the n-type impurity concentration of the n-type drain region DR2 are higher than the n-type impurity concentration of the n-type drift region ND.

[0122] A plurality of n-type source regions SR are formed in the p-type well region PB. The n-type impurity concentration of each n-type source region SR among the plurality of n-type source regions SR is higher than the n-type impurity concentration of the n-type semiconductor region EX. The depth of the bottom surface of each n-type source region SR among the plurality of n-type source regions SR is deeper compared to the depth of the bottom surface of the n-type semiconductor region EX.

[0123] To form the plurality of n-type source regions SR, vertical ion implantation is used. Accordingly, the plurality of n-type source regions SR are formed self-aligned with the sidewall spacers SW1. Accordingly, the n-type semiconductor region EX remains under the sidewall spacers SW1 adjacent to the plurality of n-type source regions SR. The n-type drain region DR and the plurality of n-type source regions SR can be formed by the same ion implantation step, which can reduce the number of manufacturing steps, but they can also be formed by separate ion implantation steps.

[0124] Next, as Figure 25 and 26 shown, a plurality of p-type semiconductor regions PR are formed in the semiconductor substrate SB using a method such as ion implantation.

[0125] The plurality of p-type semiconductor regions PR are formed in the p-type well region PB. The impurity concentration of each p-type semiconductor region PR among the plurality of p-type semiconductor regions PR is higher than the impurity concentration of the p-type well region PB. The bottom surface of each p-type semiconductor region PR among the plurality of p-type semiconductor regions PR is deeper compared to the bottom surface of the p-type well region PB.

[0126] In the first embodiment, after forming the n-type drain region DR1, the n-type drain region DR2, and the plurality of n-type source regions SR, the plurality of p-type semiconductor regions PR are formed. It is also possible to form the n-type drain region DR1, the n-type drain region DR2, and the plurality of n-type source regions SR after forming the plurality of p-type semiconductor regions PR.

[0127] After forming the plurality of n-type source regions SR, the n-type drain region DR1, the n-type drain region DR2, and the plurality of p-type semiconductor regions PR, a metal silicide layer (not shown) can be formed on each n-type drain region DR1 in the n-type drain region DR1, on the n-type drain region DR2, on the plurality of n-type source regions SR, on the plurality of p-type semiconductor regions PR, and on the upper surface of the gate electrode GE. The self-aligned silicide (self-aligned silicide) technique is used to form the metal silicide layer.

[0128] Next, as Figure 26 and Figure 27 shown, a dielectric film IL is formed over the main surface of a semiconductor substrate SB using a method such as chemical vapor deposition (CVD) to cover the gate electrode GE. After forming the dielectric film IL, the upper surface of the dielectric film IL can be polished and planarized using a method such as CMP.

[0129] Next, as Figures 1 to 3 shown, a plurality of contact holes penetrating the dielectric film IL are formed by etching the dielectric film IL using a photoresist pattern (not shown) formed over the dielectric film IL as an etching mask. Subsequently, a plurality of conductive plugs are respectively formed in the plurality of contact holes. The plurality of plugs include a plurality of plugs P1, a plurality of plugs P2, a plurality of plugs P3, and a plurality of plugs P4.

[0130] Next, as Figures 1 to 3 shown, a plurality of wirings are formed over the dielectric film IL. The plurality of wirings include a drain wiring WD1, a drain wiring WD2, and a source wiring WS.

[0131] Illustrations and descriptions of steps for forming further upper dielectric films and wirings are omitted.

[0132] In the first embodiment, an n-type silicon region PSN and a p-type silicon region PSP are formed in a silicon film PS by performing implantation of n-type impurity and p-type impurity ions into the silicon film PS, and thereafter the silicon film PS is processed to form the gate electrode GE. After processing the silicon film PS to form the gate electrode GE, n-type impurity ions can be implanted into the interiors of the gate electrode portions GE1 and GE2, and p-type impurity ions can be implanted into the interior of the gate connection portion GEC. In this case, it is preferable to implant n-type impurities into the interiors of the gate electrode portions GE1 and GE2 during the ion implantation step for forming the plurality of n-type source regions SR, n-type drain regions DR1, and n-type drain regions DR2. Moreover, it is preferable to implant p-type impurities into the gate connection portion GEC during the ion implantation process for forming the plurality of p-type semiconductor regions PR.

[0133] History of the examined example

[0134] Figure 29 and Figure 30 show a planar region corresponding to the above Figures 4 to 6 corresponding.

[0135] In the semiconductor device of the examined example studied by the inventor, the entire gate electrode GE has n-type conductivity. Therefore, in the examined example, the gate electrode portion GE1, the gate electrode portion GE2, and the gate connection portion GEC are all formed of an n-type silicon film into which n-type impurities have been introduced, and they have n-type conductivity.

[0136] When a voltage higher than the threshold voltage of the LDMOSFET 1 is applied to the gate electrode GE, a channel formed of an n-type inversion layer is formed in the upper part of the p-type well region PB located below the gate electrode portion GE1 and the gate electrode portion GE2. Therefore, the n-type drain region DR1 and the plurality of n-type source regions SR are conductively connected to each other via the n-type drift region ND and the channel below the gate electrode portion GE1. The n-type drain region DR2 and the plurality of n-type source regions SR are conductively connected to each other via the n-type drift region ND and the channel below the gate electrode portion GE1. Thus, as Figure 29 shown, current flows from the n-type drain region DR1 to the plurality of n-type source regions SR in the X direction, passes below the gate electrode portion GE1, and as Figure 29 shown, current flows from the n-type drain region DR2 to the plurality of n-type source regions SR in the X direction and passes below the gate electrode portion GE2.

[0137] However, due to the formation of the gate connection portion GEC and the n-type semiconductor region EX2, a parasitic MOSFET 2 is formed on the main surface of the semiconductor substrate SB. In Figure 29 the region where the parasitic MOSFET 2 is formed is indicated by a dashed line. The gate connection portion GEC serves as the gate electrode of the parasitic MOSFET 2, the n-type semiconductor region EX2 serves as the source region of the parasitic MOSFET 2, and the n-type drift region ND below the gate connection portion GEC serves as the drain region of the parasitic MOSFET 2.

[0138] When a voltage higher than the threshold voltage of the parasitic MOSFET 2 is applied to the gate connection portion GEC, a channel formed of an n-type inversion layer is formed in the upper part of the p-type well region PB located below the gate connection portion GEC, and the parasitic MOSFET 2 is set to the on state.

[0139] When the parasitic MOSFET 2 is turned on, in the Figure 3 shown cross-section, the n-type semiconductor region EX2 and the n-type drift region ND below the gate connection portion GEC are electrically connected to each other via the channel below the gate connection portion GEC. Therefore, as Figure 3 and Figure 29As shown by the current path LP therein, current flows from the n-type drain regions DR1 and DR2 to the n-type semiconductor region EX2 via the channel and the n-type drift region ND under the gate connection part GEC, and further flows to the n-type source region SR via the n-type semiconductor region EX1 and the n-type semiconductor region EX3.

[0140] The current path LP is not the intended current path of the LDMOSFET, but a leakage current path flowing through the parasitic MOSFET 2. As in the current path LP, current flowing from the n-type drain regions DR1 and DR2 to the n-type source region SR via the parasitic MOSFET 2 may cause leakage current and is therefore undesirable. For this reason, it is desirable to suppress or prevent current from flowing from the n-type drain regions DR1 and DR2 to the n-type source region SR via the parasitic MOSFET 2.

[0141] The p-type impurity concentration in the p-type well region PB under the gate connection part GEC tends to be lower than the p-type impurity concentration in the p-type well region PB under each of the gate electrode parts GE1 and GE2 of the gate electrode. Figure 29 The p-type regions PB1, PB2, and PB3 are shown hatched. The p-type region PB1 corresponds to the p-type well region PB located under the gate electrode part GE1. The p-type region PB2 corresponds to the p-type well region PB located under the gate connection part GEC. The p-type region PB3 corresponds to the p-type well region PB located under the gate electrode part GE2. The p-type impurity concentration in the p-type region PB2 tends to be lower than the p-type impurity concentration in each of the p-type regions PB1 and PB3.

[0142] In the examined example, it is reflected that the p-type impurity concentration in the p-type region PB2 is lower than that in each of the p-type regions PB1 and PB3, and the threshold voltage of the parasitic MOSFET 2 becomes lower than the threshold voltage of the LDMOSFET 1. This is because, in the case of an n-type MOSFET, the lower the p-type impurity concentration in the p-type well region under the gate electrode, the lower the threshold voltage tends to be. The threshold voltage of the LDMOSFET 1 corresponds to the threshold voltage based on the current paths DP1 and DP2. The threshold voltage of the parasitic MOSFET 2 corresponds to the threshold voltage based on the current path LP.

[0143] If the threshold voltage of the parasitic MOSFET 2 is lower than the threshold voltage of the LDMOSFET 1, then when a voltage is applied to the gate electrode GE, the parasitic MOSFET 2 operates before the LDMOSFET 2. This is undesirable because it may cause an increase in leakage current or lead to punch-through.

[0144] The reason why the p-type impurity concentration in the p-type well region PB (p-type region PB2) under the gate connection portion GEC is lower than the p-type impurity concentrations in the p-type well regions PB (p-type regions PB1, PB3) under each of the gate electrode portions GE1 and GE2 of the gate electrode is as follows.

[0145] The p-type well region PB is formed by tilted ion implantation. During the tilted ion implantation, p-type impurity ions are reflected by the side surfaces of the opening portion OP, and the reflected p-type impurity ions are also implanted into the semiconductor substrate SB, contributing to the formation of the p-type well region PB. In the p-type well region PB under the gate electrode portion GE1, p-type impurity ions reflected by the side surface OP2 of the opening portion OP during the tilted ion implantation are also implanted (see Figure 17 ). In the p-type well region PB under the gate electrode portion GE2, p-type impurity ions reflected by the side surface OP1 of the opening portion OP during the tilted ion implantation are also implanted (see Figure 17 ). However, in the p-type well region PB under the gate connection portion GEC, p-type impurity ions that are hardly reflected by any side surface of the opening portion OP during the tilted ion implantation are implanted. This is because the size (length) of the opening portion OP in the Y direction is larger than the size (length) of the opening portion OP in the X direction. The distance between the side surface OP3 of the opening portion OP and the side surface facing the side surface OP3 is larger than the distance between the side surfaces OP1 and OP2 of the opening portion OP. Therefore, p-type impurity ions reflected by the side surfaces of the opening portion OP hardly affect the p-type impurity concentration in the p-type region PB2. Thus, the p-type impurity concentration in the p-type well region PB (p-type region PB2) under the gate connection portion GEC is lower than the p-type impurity concentrations in the p-type well regions PB (p-type regions PB1, p-type region PB3) under the gate electrode portion GE1 and the gate electrode portion GE2, respectively.

[0146] Features and effects of the first embodiment

[0147] In the first embodiment, the conductivity type of the gate electrode GE is non-uniform. The gate electrode portions GE1 and GE2 each have n-type conductivity, and the gate connection portion GEC has p-type conductivity. Specifically, the gate electrode portion GE1 is formed of an n-type silicon region PSN, the gate connection portion GEC is formed of a p-type silicon region PSP, and the gate electrode portion GE2 is formed of an n-type silicon region PSN. Therefore, the influence of the parasitic MOSFET 2 can be suppressed or prevented, thereby improving the performance of the semiconductor device including the LDMOSFET1.

[0148] Comparing the use of an n-type silicon gate with a p-type silicon gate as the gate electrode of an n-channel MOSFET, if the structures other than the gate electrode are the same, the threshold voltage of the n-channel MOSFET using the p-type silicon gate is higher than that of the n-channel MOSFET using the n-type silicon gate. Therefore, an n-type silicon gate is generally used as the gate electrode of an n-channel MOSFET. This is because reducing the threshold voltage of the n-channel MOSFET allows the operating voltage of the n-channel MOSFET to be reduced.

[0149] However, it is desirable to suppress the operation of the parasitic MOSFET 2 during the operation of the LDMOSFET 1. Therefore, in the first embodiment, the gate electrode portion GE1 and the gate electrode portion GE2 each have n-type conductivity, and the gate connection portion GEC has p-type conductivity. This allows the threshold voltage of the LDMOSFET 1 using the gate electrode portions GE1 and GE2 as the gate electrode to be maintained at a predetermined voltage, while increasing the threshold voltage of the parasitic MOSFET 2 using the gate connection portion GEC as the gate electrode. Specifically, when comparing the examined example with the first embodiment, the threshold voltage of the LDMOSFET1 in the first embodiment is the same as the threshold voltage in the examined example, and the threshold voltage of the parasitic MOSFET2 in the first embodiment is higher than the threshold voltage in the examined example. Therefore, in the first embodiment, the influence of the parasitic MOSFET 2 can be suppressed or prevented, thereby improving the performance of the semiconductor device including the LDMOSFET 1. For example, when a voltage is applied to the gate electrode GE, the operation of the parasitic MOSFET 2 can be suppressed or prevented before the operation of the LDMOSFET 1. Therefore, leakage current can be suppressed. Or punch-through caused by the parasitic MOSFET 2 can be prevented.

[0150] Contrary to the first embodiment, it can be imagined that an n-type semiconductor region EX is formed such that the n-type semiconductor region EX2 is not formed along the side surface S5 of the gate connection portion GEC. Since the n-type semiconductor region EX2 serves as the source region of the parasitic MOSFET 2, if the n-type semiconductor region EX2 is not formed along the side surface S5 of the gate connection portion GEC, the parasitic MOSFET 2 will not be formed.

[0151] However, in order to form the n-type semiconductor region EX such that the n-type semiconductor region EX2 is not formed, it is necessary to use an ion implantation blocking mask (photoresist pattern) different from the ion implantation blocking mask (the above-mentioned photoresist pattern RP2) used in the ion implantation step for forming the p-type well region PB during the ion implantation step for forming the n-type semiconductor region EX. This results in an increase in the number of manufacturing steps and the cost of manufacturing the semiconductor device.

[0152] In contrast, in the case of the first embodiment, a common ion implantation blocking mask (the above-mentioned photoresist pattern RP2) can be used in the ion implantation step for forming the n-type semiconductor region EX and the ion implantation step for forming the p-type well region PB. Therefore, the number of manufacturing steps and the cost of manufacturing the semiconductor device can be suppressed.

[0153] When a common ion implantation blocking mask (the above-mentioned photoresist pattern RP2) is used in the ion implantation step for forming the n-type semiconductor region EX and the ion implantation step for forming the p-type well region PB, the n-type semiconductor region EX includes an n-type semiconductor region EX2 along the side surface S5 of the gate connection portion GEC. If the n-type semiconductor region EX includes the n-type semiconductor region EX2, a parasitic MOSFET 2 is formed. In the case of the first embodiment, although as described above, the n-type semiconductor region EX2 is formed along the side surface S5 of the gate connection portion GEC, the threshold voltage of the parasitic MOSFET 2 can be increased. Therefore, it is possible to tolerate the formation of the parasitic MOSFET 2 by the n-type semiconductor region EX2 along the side surface S5 of the gate connection portion GEC. Therefore, improvements in both the semiconductor device performance and the suppression of the manufacturing cost of the semiconductor device can be achieved.

[0154] The technical idea of the first embodiment is to lower the threshold voltage of the LDMOSFET 1 in the current paths DP1 and DP2, and increase the threshold voltage of the parasitic MOSFET 2 in the current path LP.

[0155] In the current paths DP1 and DP2, in order to lower the threshold voltage of the LDMOSFET 1, the gate electrode portions GE1 and GE2 above the channel formation region are configured by an n-type silicon region PSN. Therefore, in a cross-sectional view orthogonal to the Y direction, in any cross-section across any one of the plurality of n-type source regions SR, the gate electrode portions GE1 and GE2 above the p-type well region PB are configured by an n-type silicon region PSN. This allows the threshold voltage of the LDMOSFET 1 in the current paths DP1 and DP2 to be lowered.

[0156] In the current paths DP1 and DP2, in order to increase the threshold voltage of the parasitic MOSFET 2, the gate connection portion GEC above the channel formation region is configured by a p-type silicon region PSP. Therefore, in a cross-sectional view orthogonal to the X direction, the gate connection portion GEC above the p-type well region PB is configured by a p-type silicon region PSP at any position of the side surface S5. This allows the threshold voltage of the parasitic MOSFET 2 in the current paths DP1 and DP2 to be increased.

[0157] Second Embodiment

[0158] Figure 31 is a cross-sectional view corresponding to the above Figure 11 and shows a cross-sectional view along line C-C of Figures 4 to 6 . Figure 32 The position of the gate electrode GE formed later is shown by a dashed line, and the positions of the n-type drain regions DR1 and DR2 formed later are shown by a dotted line.

[0159] The difference between the second embodiment and the first embodiment lies in the step of forming the n-type drift region ND.

[0160] In the first embodiment, the n-type drift region ND is formed by vertical ion implantation without using inclined ion implantation. Therefore, in the first embodiment, Figure 10 and Figure 11 the n-type impurity concentration in the surface portion of the n-type drift region ND shown is substantially constant and independent of the planar position.

[0161] In the second embodiment, as Figure 31 shown, after forming a photoresist pattern RP1 on the main surface of the semiconductor substrate SB using photolithography technology, n-type impurities are implanted into the semiconductor substrate SB using the photoresist pattern RP1 as a mask, thereby forming an n-type semiconductor region ND1 in the semiconductor substrate SB. The n-type semiconductor region ND1 is formed using inclined ion implantation. Next, n-type impurities are implanted into the semiconductor substrate SB using the photoresist pattern RP1 as a mask, and an n-type semiconductor region ND2 is formed in the semiconductor substrate SB. The n-type semiconductor region ND2 is formed using vertical ion implantation. Thereafter, the photoresist pattern RP1 is removed.

[0162] The ion implantation energy for forming the n-type semiconductor region ND1 is lower than the ion implantation energy for forming the n-type semiconductor region ND2. Therefore, in the semiconductor substrate SB, the n-type semiconductor region ND2 is formed below the n-type semiconductor region ND1. The n-type drift region ND is formed by the n-type semiconductor region ND1 and the n-type semiconductor region ND2 located below the n-type semiconductor region ND1. The n-type semiconductor region ND1 configures the upper part of the n-type drift region ND, and the n-type semiconductor region ND2 configures the lower part of the n-type drift region ND.

[0163] When performing inclined ion implantation using the photoresist pattern RP1 as a mask, due to the shielding effect of the photoresist pattern RP1, the impurity density implanted into the semiconductor substrate SB is locally reduced near the side surface of the photoresist pattern RP1. Therefore, when forming the n-type semiconductor region ND1 by inclined ion implantation, the n-type impurity concentration in the n-type semiconductor region ND1 is locally reduced near the side surface of the photoresist pattern RP1. Therefore, Figure 31 and Figure 32 the n-type impurity concentration in the n-type semiconductor region ND1b shown is lower than the n-type impurity concentration in the n-type semiconductor region ND1a. The n-type impurity concentration in the surface portion of the n-type semiconductor region ND1a is substantially constant and independent of the planar position.

[0164] The n-type semiconductor region ND1b is a part of the n-type semiconductor region ND1, and the n-type semiconductor region ND1a is another part of the n-type semiconductor region ND1. The n-type semiconductor region ND1b and the n-type semiconductor region ND1a are adjacent to each other in the Y direction. The side surface RP1a of the photoresist pattern RP1 is parallel to the X direction. In a plan view, the side surface RP1a of the photoresist pattern RP1 intersects the region where the gate connection portion GEC is formed. In a plan view, the side surface RP1a of the photoresist pattern RP1 and the n-type semiconductor region ND1a are spaced apart from each other in the X direction, and the n-type semiconductor region ND1b exists between the side surface RP1a of the photoresist pattern RP1 and the n-type semiconductor region ND1a. In a plan view, the implantation angle of the inclined ion implantation is preferably set such that the region where the gate connection portion GEC is formed is located in the n-type semiconductor region ND2. The formation step of the n-type semiconductor region ND1 can be performed after the formation step of the n-type semiconductor region ND2.

[0165] For the steps after the formation step of the n-type drift region ND, this second embodiment is similar to the first embodiment.

[0166] In the case of this second embodiment, compared with the first embodiment, the threshold voltage of the parasitic MOSFET 2 can be further increased. Therefore, the performance of the semiconductor device can be further improved.

[0167] The reason why the threshold voltage of the parasitic MOSFET 2 can be further increased in this second embodiment will be explained.

[0168] After forming the n-type drift region ND, a p-type well region PB is formed. In a plan view, the p-type well region PB is formed in the n-type drift region ND. Therefore, in the p-type well region PB, there are n-type impurities implanted by the ion implantation for forming the n-type drift region ND and p-type impurities implanted by the ion implantation for forming the p-type well region PB. Since the density of the p-type impurities in the p-type well region PB is greater than the density of the n-type impurities in the p-type well region PB, the effective conduction type of the p-type well region PB becomes p-type. Therefore, the difference between the p-type impurity density and the n-type impurity density defines the effective p-type impurity concentration of the p-type well region PB.

[0169] In this second embodiment, the n-type impurity concentration of the n-type semiconductor region ND1b is lower than the n-type impurity concentration of the n-type semiconductor region ND1a. The later-formed gate connection portion GEC is located in the n-type semiconductor region ND1b in a plan view. By using this, the effective p-type impurity concentration of the upper part of the p-well region PB (PB2) located under the gate connection portion GEC can be increased. Therefore, the effective p-type impurity concentration of the channel formation region of the parasitic MOSFET 2 can be increased.

[0170] On the other hand, in the case of the first embodiment, the n-type impurity concentration of the n-type semiconductor region ND1b is the same as the n-type impurity concentration of the n-type semiconductor region ND1a. Therefore, in the case of the second embodiment, compared with the first embodiment, the effective p-type impurity concentration in the upper part of the p-type well region PB (PB2) located under the gate connection portion GEC can be increased. Therefore, compared with the first embodiment, the threshold voltage of the parasitic MOSFET 2 in the second embodiment can be increased.

[0171] A channel is formed in the upper part of the p-type well region PB located under the gate electrode GE. Therefore, the n-type impurity concentration of the n-type semiconductor region ND1 affects the impurity concentration of the channel formation region, but the n-type impurity concentration of the n-type semiconductor region ND2 hardly affects the impurity concentration of the channel formation region. Therefore, the n-type semiconductor region ND2 can be formed by vertical ion implantation. Therefore, the n-type impurity concentration of the n-type semiconductor region ND2 is almost constant and independent of the planar position. Therefore, the characteristics of the semiconductor device can be stabilized.

[0172] On the other hand, in the case of the first embodiment, since the n-type drift region ND can be formed by vertical ion implantation without using inclined ion implantation, the steps of forming the n-type drift region ND can be simplified. For example, this allows shortening the manufacturing time of the semiconductor device. Alternatively, the manufacturing cost of the semiconductor device can be reduced.

[0173] If the n-type drift region ND forming step of the second embodiment is applied when the gate connection portion GEC is formed of p-type silicon as in the first embodiment, the threshold voltage of the parasitic MOSFET 2 can be further increased.

[0174] Different from the first embodiment, when the gate electrode portion GE1, the gate electrode portion GE2, and the gate connection portion GEC are formed of n-type silicon, the n-type drift region ND forming step of the second embodiment can also be applied. In this case, compared with not applying the n-type drift region ND forming step of the second embodiment, the threshold voltage of the parasitic MOSFET 2 can be increased. This allows suppressing the influence of the parasitic MOSFET 2, thereby improving the performance of the semiconductor device including the LDMOSFET.

[0175] The present invention made by the present inventors has been described in detail above based on embodiments, but the present invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from its gist.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; a gate electrode formed on the main surface of the semiconductor substrate via a gate dielectric film; A drift region of a first conductivity type is formed in the semiconductor substrate; A well region of a second conductivity type opposite to the first conductivity type is formed in the semiconductor substrate; A first drain region of the first conductivity type is formed in the drift region, the first drain region having a higher impurity concentration than the drift region; A second drain region of the first conductivity type is formed in the drift region, the second drain region having a higher impurity concentration than the drift region; The first semiconductor region of the first conductivity type is formed in the well region; as well as at least one source region of the first conductivity type is formed in the well region, the at least one source region having a higher impurity concentration than the first semiconductor region, The gate electrode comprises: The first gate electrode portion of the first conductivity type extends in a first direction; a second gate electrode portion of the first conductivity type extending in the first direction, the second gate electrode portion being spaced apart from the first gate electrode portion in a second direction orthogonal to the first direction; and the second conductive type gate connection portion connecting the first gate electrode portion and the second gate electrode portion, wherein in a plan view, the first drain region and the second drain region are spaced apart from each other in the second direction, wherein in a plan view, the first gate electrode portion and the second gate electrode portion are arranged between the first drain region and the second drain region, wherein in a plan view, the at least one source region is arranged between the first gate electrode portion and the second gate electrode portion, wherein in a plan view, the well region is surrounded by the drift region, wherein in a plan view, a portion of the first gate electrode portion, a portion of the second gate electrode portion, and a portion of the gate connection portion overlap with the well region, wherein in a plan view, another portion of the first gate electrode portion, another portion of the second gate electrode portion, and another portion of the gate connection portion overlap the drift region, wherein the first gate electrode portion has a first side surface facing the second gate electrode portion, wherein the second gate electrode portion has a second side surface facing the first gate electrode portion, wherein the gate connection portion has a third side surface intersecting the first side surface and the second side surface, Wherein, in a plan view, the first semiconductor region is formed along the first side surface of the first gate electrode portion, along the third side surface of the gate connection portion, and along the second side surface of the second gate electrode portion.

2. The semiconductor device according to claim 1, wherein the first gate electrode portion is made of silicon of the first conductivity type, wherein the second gate electrode portion is made of silicon of the first conductivity type, and The gate connection portion is made of silicon of the second conductivity type.

3. The semiconductor device according to claim 2, wherein the first conductivity type is n-type, and The second conductivity type is p-type.

4. The semiconductor device according to claim 2, The first gate electrode portion, the gate connecting portion and the second gate electrode portion are integrally formed.

5. The semiconductor device according to claim 1, The at least one source region is in contact with the first semiconductor region along the first side surface of the first gate electrode portion and the first semiconductor region along the second side surface of the second gate electrode portion.

6. The semiconductor device according to claim 1, comprising: a plurality of second semiconductor regions of the second conductivity type, wherein the at least one source region comprises a plurality of source regions, and Wherein in a plan view, the plurality of source regions and the plurality of second semiconductor regions are alternately arranged between the first gate electrode portion and the second gate electrode portion in the first direction.

7. The semiconductor device according to claim 1, The first semiconductor region along the third side surface of the gate connection portion is in contact with any one of the plurality of second semiconductor regions.

8. The semiconductor device according to claim 1, The impurity concentration of the well region under the gate connection portion is lower than the impurity concentration of the well region under the first gate electrode portion, and lower than the impurity concentration of the well region under the second gate electrode portion.

9. The semiconductor device according to claim 1, wherein each of the first side surface of the first gate electrode portion and the second side surface of the second gate electrode portion is parallel to the first direction, and The third side surface of the gate connection portion is parallel to the second direction.

10. A method for manufacturing a semiconductor device, the method comprising: (a) preparing a semiconductor substrate; (b) forming a drift region of a first conductivity type in the semiconductor substrate; (c) forming a silicon film over the main surface of the semiconductor substrate via a gate dielectric film; (d) etching the silicon film to form an opening portion in the silicon film; (e) after (d), forming a well region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate so as to include the opening portion in a plan view; (f) after (d), forming a first semiconductor region of the first conductivity type in the semiconductor substrate so as to overlap with the opening portion in a plan view; (g) after (e) and (f), etching the silicon film to form a gate electrode; (h) forming sidewall spacers on side surfaces of the gate electrode; as well as (i) after (h), forming a first drain region of the first conductivity type and a second drain region of the first conductivity type in the drift region, the first drain region having a higher impurity concentration than the drift region, the second drain region having a higher impurity concentration than the drift region, and forming at least one source region of the first conductivity type in the well region, the at least one source region having a higher impurity concentration than the first semiconductor region, The gate electrode comprises: The first gate electrode portion of the first conductivity type extends in a first direction; a second gate electrode portion of the first conductivity type extending in the first direction, the second gate electrode portion being spaced apart from the first gate electrode portion in a second direction orthogonal to the first direction; and the second conductive type gate connection portion connecting the first gate electrode portion and the second gate electrode portion, wherein in a plan view, the first drain region and the second drain region are spaced apart from each other in the second direction, wherein in a plan view, the first gate electrode portion and the second gate electrode portion are located between the first drain region and the second drain region, wherein in a plan view, the at least one source region is located between the first gate electrode portion and the second gate electrode portion, wherein in a plan view, a portion of the first gate electrode portion, a portion of the second gate electrode portion, and a portion of the gate connection portion overlap with the well region, wherein in a plan view, another portion of the first gate electrode portion, another portion of the second gate electrode portion, and another portion of the gate connection portion overlap the drift region, wherein the first gate electrode portion has a first side surface facing the second gate electrode portion, wherein the second gate electrode portion has a second side surface facing the first gate electrode portion, wherein the gate connection portion has a third side surface intersecting the first side surface and the second side surface, and The first side surface, the second side surface, and the third side surface configure a portion of a side surface of the opening portion.

11. The method according to claim 10, wherein in (e), the well region is formed by oblique ion implantation, and In (f), the first semiconductor region is formed by vertical ion implantation.

12. The method according to claim 11, comprising: (d1) after (c) and before (d), forming a first mask layer on the silicon film; as well as (h1) after (e) and (f) and before (g), removing the first mask layer, wherein in the (d), the silicon film is etched using the first mask layer as an etching mask to form an opening portion in the silicon film, wherein in (e), the silicon film and the first mask layer are used as ion implantation blocking masks, the well region is formed by implanting impurities of the second conductivity type into the semiconductor substrate using oblique ion implantation, and In (f), the silicon film and the first mask layer are used as the ion implantation blocking mask, and the first semiconductor region is formed by implanting impurities of the first conductivity type into the semiconductor substrate using vertical ion implantation.

13. The method according to claim 12, comprising: (h2) after (h1) and before (g), forming a second mask layer over the main surface of the semiconductor substrate so as to cover the opening portion and partially cover the silicon film, In the (g), the gate electrode is formed by etching the silicon film using the second mask layer as an etching mask.

14. The method according to claim 10, comprising: (k) after (h), forming a plurality of second semiconductor regions of the second conductivity type in the well region, the plurality of second semiconductor regions having a higher impurity concentration than the well region, wherein the at least one source region comprises a plurality of source regions, Wherein in a plan view, the plurality of source regions and the plurality of second semiconductor regions are alternately arranged between the first gate electrode portion and the second gate electrode portion in the first direction.

15. The method according to claim 14, In the (k), the first semiconductor region along the third side surface of the gate connection portion is in contact with any one of the plurality of second semiconductor regions.

16. The method according to claim 10, wherein said (b) comprises: (b1) forming a third mask layer over the main surface of the semiconductor substrate; (b2) after (b1), forming the drift region in the semiconductor substrate by ion implantation; as well as (b3) After (b2), removing the third mask layer.

17. The method according to claim 16, wherein said (b2) comprises: (b4) using the third mask layer as an ion implantation blocking mask, and implanting the second conductivity type impurity into the semiconductor substrate using an inclined ion implantation; as well as (b5) using the third mask layer as the ion implantation blocking mask, and implanting the second conductivity type impurity into the semiconductor substrate by vertical ion implantation, The implantation energy of the oblique ion implantation in (b4) is lower than the implantation energy of the vertical ion implantation in (b5).

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