Transistor, array substrate and display panel

Abstract

The invention relates to a transistor, an array substrate and a display panel. The transistor includes a substrate; the active layer is arranged on one side of the substrate; the active layer comprises a plurality of sub-active layers stacked in the thickness direction of the substrate, the plurality of sub-active layers comprise at least one first sub-active layer and at least one second sub-active layer, the first sub-active layers and the second sub-active layers are alternately arranged, the carrier mobility of the first sub-active layers is smaller than that of the second sub-active layers, and the carrier mobility of the second sub-active layers is smaller than that of the first sub-active layers. The sum of the thicknesses of all the first sub-active layers is larger than the sum of the thicknesses of all the second sub-active layers. Therefore, according to the transistor, the array substrate and the display panel provided by the invention, the electrical performance of the transistor can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a transistor, an array substrate, and a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) display technology is regarded as the next-generation most potential new flat panel display technology. Compared with liquid crystal display technology, the OLED display panel has the advantages of low power consumption, low cost, self-luminescence, wide viewing angle, and fast response speed. However, the electrical properties of thin film transistors in the above display panel need to be improved. Summary of the Invention

[0003] Based on this, it is necessary to provide a transistor, an array substrate, and a display panel, which can improve the electrical properties of the transistor.

[0004] In a first aspect, an embodiment of the present application provides a transistor, including:

[0005] A substrate;

[0006] An active layer disposed on one side of the substrate;

[0007] Wherein, the active layer includes multiple sub-active layers stacked along the thickness direction of the substrate. The multiple sub-active layers include at least one first sub-active layer and at least one second sub-active layer. The first sub-active layer and the second sub-active layer are alternately arranged. The carrier mobility of the first sub-active layer is less than that of the second sub-active layer. The sum of the thicknesses of all the first sub-active layers is greater than the sum of the thicknesses of all the second sub-active layers.

[0008] In the transistor provided by the embodiment of the application, by alternately arranging the first sub-active layer and the second sub-active layer, without affecting the carrier mobility of the active layer, the thickness ratio of the second sub-active layer in the active layer can be reduced, so as to reduce the proportion of carriers of the second sub-active layer in the conductorized region in the active layer, thereby reducing the diffusion of carriers in the active layer from the conductorized region to the channel region, improving the problem of negative bias divergence of the device, making the device show positive bias convergence, and thus improving the electrical properties of the transistor.

[0009] In one embodiment, the carrier concentration of the first sub-active layer is less than that of the second sub-active layer;

[0010] Preferably, the electron concentration of the first sub-active layer is less than that of the second sub-active layer.

[0011] In one embodiment, in the multiple sub-active layers, the sub-active layer farthest from the substrate is the first sub-active layer;

[0012] Preferably, in the multi-layer sub-active layer, the thickness of the sub-active layer farthest from the substrate ranges from 5 nm to 30 nm;

[0013] Preferably, the thickness of the second sub-active layer ranges from 1 nm to 6 nm.

[0014] In one embodiment, the material of the sub-active layer includes a metal oxide semiconductor material;

[0015] Preferably, the metal in the sub-active layer includes one or more of indium, gallium, and zinc;

[0016] Preferably, the material of the sub-active layer includes one or more of indium gallium oxide, indium zinc oxide, and indium gallium zinc oxide.

[0017] In one embodiment, in the first sub-active layer, the sum of the atomic numbers of indium, gallium, and zinc is a first value, and the ratio of the atomic number of indium to the first value is a first ratio; in the second sub-active layer, the sum of the atomic numbers of indium, gallium, and zinc is a second value, and the ratio of the atomic number of indium to the second value is a second ratio, and the first ratio is less than the second ratio.

[0018] In one embodiment, the range of the first ratio is 30% - 70%;

[0019] Preferably, in the first sub-active layer, the ratio of the atomic number of gallium to the first value ranges from 10% to 40%;

[0020] Preferably, in the first sub-active layer, the ratio of the atomic number of zinc to the first value ranges from 10% to 40%.

[0021] In one embodiment, the range of the second ratio is 50% - 100%;

[0022] Preferably, in the second sub-active layer, the ratio of the atomic number of gallium to the second value ranges from 0% to 30%;

[0023] Preferably, in the second sub-active layer, the ratio of the atomic number of zinc to the second value ranges from 0% to 30%.

[0024] In one embodiment, the multi-layer sub-active layer includes one layer of the first sub-active layer and one layer of the second sub-active layer, and the sum of the thicknesses of the first sub-active layer and the second sub-active layer is a third value;

[0025] Preferably, the ratio of the thickness of the first sub-active layer to the third value ranges from 60% to 90%;

[0026] Preferably, the ratio of the thickness of the second sub-active layer to the third value ranges from 10% to 40%.

[0027] In one embodiment, the multi-layer sub-active layer includes two first sub-active layers and one second sub-active layer, the second sub-active layer is arranged between the two first sub-active layers, and the sum of the thicknesses of the two first sub-active layers and the second sub-active layer is a fourth value;

[0028] Preferably, the ratio of the thickness of the second sub-active layer to the fourth value is in the range of 5%-30%;

[0029] Preferably, the ratio of the thickness of the first sub-active layer located on the side of the second sub-active layer away from the substrate to the fourth value is in the range of 30%-70%;

[0030] Preferably, the thickness of the first sub-active layer located on the side of the second sub-active layer facing the substrate is in the range of 1nn-30nm;

[0031] Preferably, a ratio of the thickness of the first sub-active layer located on the side of the second sub-active layer facing the substrate to the fourth value is in a range of 10%-40%.

[0032] In one embodiment, the active layer includes a channel region and conductive regions disposed on opposite sides of the channel region, and the first sub-active layer is located in the channel region and the conductive region;

[0033] The orthographic projection of at least one first sub-active layer on the substrate coincides with the orthographic projection of the active layer on the substrate;

[0034] Preferably, the multi-layer sub-active layer includes a multi-layer first sub-active layer, and in at least one first sub-active layer, the orthographic projection of the first sub-active layer on the substrate covers the orthographic projection of the channel region on the substrate, and the dimension of the first sub-active layer located in the conductorized region from the conductorized region to the channel region is smaller than the dimension of the conductorized region from the conductorized region to the channel region; or, the orthographic projections of each first sub-active layer on the substrate overlap with the orthographic projection of the active layer on the substrate;

[0035] Preferably, in at least one first sub-active layer, a dimension of the first sub-active layer located in the conductive region from the conductive region to the channel region is less than or equal to 1 μm.

[0036] In one embodiment, the active layer includes a channel region and conductive regions disposed on opposite sides of the channel region; the second sub-active layer is located in the channel region and the conductive region;

[0037] The orthographic projection of the second sub-active layer on the substrate coincides with the orthographic projection of the active layer on the substrate; or,

[0038] In at least one second sub-active layer, the orthographic projection of the second sub-active layer on the substrate covers the orthographic projection of the channel region on the substrate, and the dimension of the second sub-active layer located in the conductorized region from the conductorized region to the channel region is smaller than the dimension of the conductorized region from the conductorized region to the channel region;

[0039] Preferably, in at least one second sub-active layer, a dimension of the second sub-active layer located in the conductive region from the conductive region to the channel region is less than or equal to 1 μm.

[0040] In one embodiment, the transistor includes a first conductive layer, the first conductive layer is disposed on one side of the substrate, and the first conductive layer is disposed on a side of the active layer facing away from the substrate;

[0041] Preferably, the transistor comprises a second conductive layer, and the second conductive layer is arranged on a side of the active layer facing the substrate;

[0042] Preferably, the orthographic projection of the first conductive layer on the substrate coincides with the orthographic projection of the channel region on the substrate.

[0043] In one embodiment, the active layer includes a channel region and conductive regions located on opposite sides of the channel region, the transistor includes a first electrode and a second electrode, the conductive regions located on opposite sides of the channel region are respectively the first conductive region and the second conductive region, the first electrode contacts the active layer located in the first conductive region, and the second electrode contacts the active layer located in the second conductive region;

[0044] Preferably, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode;

[0045] Preferably, the first conductive layer and the second conductive layer are electrically connected, and the first conductive layer and the second conductive layer are configured as gates; or, one of the first pole and the second pole is electrically connected to the first conductive layer, and the second conductive layer is configured as a gate; or, one of the first pole and the second pole is electrically connected to the second conductive layer, and the first conductive layer is configured as a gate.

[0046] In one embodiment, the first electrode and the second electrode are both in contact with the first sub-active layer;

[0047] Preferably, the first sub-active layer in contact with the first pole and the second pole is the one of the multiple sub-active layers closest to the substrate; or,

[0048] The first sub-active layer in contact with the first pole and the second pole is the one farthest from the substrate among the multiple sub-active layers.

[0049] In one embodiment, the transistor includes a first insulating layer disposed between the active layer and the first conductive layer;

[0050] Preferably, an orthographic projection of a surface of the first conductive layer facing the substrate on the substrate coincides with an orthographic projection of a surface of the first insulating layer facing away from the substrate on the substrate;

[0051] Preferably, the transistor comprises a second insulating layer, and the second insulating layer is arranged between the active layer and the second conductive layer.

[0052] Second aspect, an embodiment of the present application provides a transistor,

[0053] a substrate;

[0054] an active layer disposed on one side of the substrate;

[0055] wherein, the active layer includes multiple sub-active layers stacked along the thickness direction of the substrate, the multiple sub-active layers include at least one first sub-active layer and at least one second sub-active layer, the first sub-active layer and the second sub-active layer are alternately arranged, the carrier concentration of the first sub-active layer is less than the carrier concentration of the second sub-active layer, and the sum of the thicknesses of all the first sub-active layers is greater than the sum of the thicknesses of all the second sub-active layers.

[0056] In one embodiment, the electron concentration of the first sub-active layer is less than the electron concentration of the second sub-active layer;

[0057] Preferably, the active layer includes a channel region and conductive regions disposed on opposite sides of the channel region;

[0058] Preferably, the transistor includes a first conductive layer disposed on one side of the substrate, and the orthographic projection of the first conductive layer on the substrate coincides with the orthographic projection of the channel region on the substrate;

[0059] Preferably, among the multiple sub-active layers, the sub-active layer farthest from the substrate is the first sub-active layer;

[0060] Preferably, among the multiple sub-active layers, the thickness range of the sub-active layer farthest from the substrate is 5 nm - 30 nm;

[0061] Preferably, the thickness range of the second sub-active layer is 1 nm - 6 nm.

[0062] In one embodiment, the material of the sub-active layer includes a metal oxide semiconductor material;

[0063] Preferably, the metal in the sub-active layer includes one or more of indium, gallium, and zinc;

[0064] Preferably, the material of the sub-active layer includes one or more of indium gallium oxide, indium zinc oxide, and indium gallium zinc oxide.

[0065] Third aspect, an embodiment of the present application provides an array substrate including the transistor of the first aspect or the second aspect above.

[0066] Fourth aspect, an embodiment of the present application provides a display panel including the array substrate of the third aspect above. Description of the Drawings

[0067] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments or exemplary embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0068] Figure 1 A cross-sectional view of the transistor provided by the embodiment of the present application.

[0069] Figure 2 Another cross-sectional view of the transistor provided by the embodiment of the present application.

[0070] Figure 3 Another cross-sectional view of the transistor provided by the embodiment of the present application.

[0071] Figure 4 Another cross-sectional view of the transistor provided by the embodiment of the present application.

[0072] Figure 5 A top view of the active layer provided by the embodiment of the present application.

[0073] Figure 6 Another cross-sectional view of the transistor provided by the embodiment of the present application.

[0074] Figure 7 Another cross-sectional view of the transistor provided by the embodiment of the present application.

[0075] Figure 8 A schematic structural diagram after forming the second insulating layer provided by the embodiment of the present application.

[0076] Figure 9 A schematic structural diagram after forming the active layer provided by the embodiment of the present application.

[0077] Figure 10 Another schematic structural diagram after forming the active layer provided by the embodiment of the present application.

[0078] Figure 11 A Vgs-Ids curve graph of the transistor provided by the embodiment of the present application.

[0079] Figure 12 Another Vgs-Ids curve graph of the transistor provided by the embodiment of the present application.

[0080] Figure 13 Another Vgs-Ids curve graph of the transistor provided by the embodiment of the present application.

[0081] Figure 14 Another Vgs-Ids curve graph of the transistor provided by the embodiment of the present application.

[0082] Description of Reference Numerals

[0083] 100. Transistor; 110. Substrate; 120. Active layer; 120a. Channel region; 120b. Conductive region; 120b1. First conductive region; 120b2. Second conductive region; 121. Sub-active layer; 1211. First sub-active layer; 1212. Second sub-active layer; 131. First conductive layer; 132. Second conductive layer; 141. First electrode; 142. Second electrode; 151. First insulating layer; 152. Second insulating layer; 160. Buffer layer; 170. Interlayer insulating layer. Detailed Embodiments

[0084] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the understanding of the disclosure of the present application can be more thorough and comprehensive.

[0085] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, they do not denote any order, quantity, or importance, but are only used to distinguish different components. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. Words such as "including" or "comprising" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0086] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0087] Organic Light Emitting Diode (OLED) display technology is regarded as the most potential new flat panel display technology for the next generation. Compared with liquid crystal display technology, OLED display panels have the advantages of low power consumption, low cost, self-luminescence, wide viewing angle, and fast response speed.

[0088] In the process of implementing the present application, the inventors found the following problems in the related art: The thin film transistor (TFT) in the display panel may include a high-mobility oxide TFT. The high-mobility oxide TFT may include a substrate and an active layer disposed on the substrate. The active layer includes a channel region and conductive regions located on both sides of the channel region.

[0089] However, in the high-mobility oxide TFT, carriers are likely to diffuse from the conductive regions to the channel region, resulting in negative bias divergence of the device, thereby having an adverse effect on the electrical performance of the thin film transistor.

[0090] In view of the above at least one problem, the embodiments of the present application provide a transistor, an array substrate, and a display panel, which can improve the negative bias divergence of the transistor, thereby improving the electrical performance of the transistor.

[0091] The following will be combined with Figures 1-14 to describe the transistor, the array substrate, and the display panel provided by the embodiments of the present application.

[0092] The embodiments of the present application provide a transistor 100. The transistor 100 can be a short-channel device, which is beneficial to reducing the size of the transistor 100, reducing the power consumption of the transistor 100, increasing the switching speed of the transistor 100, and increasing the integration density of the transistors 100 in the array substrate 110.

[0093] Referring to Figure 1 , the transistor 100 includes a substrate 110 and an active layer 120. The active layer 120 is disposed on one side of the substrate 110. The active layer 120 includes a channel region 120a and conductive regions 120b disposed on opposite sides of the channel region 120a.

[0094] Exemplarily, the substrate 110 can provide support for the remaining structural layers to be subsequently provided. In some examples, the substrate 110 can be a rigid substrate. For example, the material of the substrate 110 can be glass. In some other examples, the substrate 110 can be a flexible substrate, and the material of the substrate 110 can include at least one of polyimide (PI for short), polyethylene terephthalate, polyethylene naphthalate, polyethylene, polyacrylate, polyetherimide, polycarbonate, polyarylate, and polyethersulfone.

[0095] Referring to Figure 1, the active layer 120 includes multiple sub-active layers 121 stacked along the thickness direction of the substrate 110. The multiple sub-active layers 121 include at least one first sub-active layer 1211 and at least one second sub-active layer 1212. The first sub-active layer 1211 and the second sub-active layer 1212 are arranged alternately. The carrier mobility of the first sub-active layer 1211 is less than that of the second sub-active layer 1212. Thus, by setting the first sub-active layer 1211 with a lower carrier mobility, the carriers in the conducting region 120b of the first sub-active layer 1211 are less likely to diffuse into the channel region 120a compared to the carriers in the conducting region 120b of the second sub-active layer 1212. This can reduce the diffusion of carriers in the active layer 120 from the conducting region 120b to the channel region 120a. Additionally, by setting the second sub-active layer 1212 with a higher carrier mobility, the active layer 120 can transmit carriers more quickly, ensuring the efficient movement of carriers in the channel region 120a, thereby improving the response speed of the transistor 100. In summary, by alternately setting the first sub-active layer 1211 and the second sub-active layer 1212, without affecting the carrier mobility of the active layer 120, the thickness ratio of the second sub-active layer 1212 in the active layer 120 can be reduced, so as to reduce the proportion of carriers of the second sub-active layer 1212 in the conducting region 120b in the active layer 120, thereby reducing the diffusion of carriers in the active layer 120 from the conducting region 120b to the channel region 120a, improving the problem of negative bias divergence of the device, making the device exhibit positive bias convergence, and thus improving the electrical performance of the transistor 100.

[0096] Among them, when the transistor 100 is turned on, the conducting region 120b transmits carriers through the first sub-active layer 1211 and the second sub-active layer 1212, and the channel region 120a mainly transmits carriers through the second sub-active layer 1212.

[0097] Exemplarily, the sum of the thicknesses of all the first sub-active layers 1211 is greater than the sum of the thicknesses of all the second sub-active layers 1212. Thus, the sum of the thicknesses of all the first sub-active layers 1211 is relatively large, and the sum of the thicknesses of all the second sub-active layers 1212 is relatively small, which can better reduce the thickness ratio of the second sub-active layer 1212 in the active layer 120, so as to reduce the diffusion of carriers in the active layer 120 from the conducting region 120b to the channel region 120a, improving the problem of negative bias divergence of the device, making the device exhibit positive bias convergence, and thus improving the electrical performance of the transistor 100.

[0098] In some embodiments, the carrier concentration of the first sub-active layer 1211 is less than that of the second sub-active layer 1212. Thus, the carrier concentration of the first sub-active layer 1211 is relatively low, which is conducive to a relatively low carrier mobility of the first sub-active layer 1211, reducing the diffusion of carriers in the active layer 120 from the conductive region 120b to the channel region 120a, improving the problem of negative bias divergence of the device, making the device exhibit positive bias convergence, and thus improving the electrical performance of the transistor 100. Additionally, the carrier concentration of the second sub-active layer 1212 is relatively high. When the transistor 100 is turned on, the second sub-active layer 1212 can provide more carriers to ensure the efficient movement of carriers in the channel region 120a, thereby improving the response speed of the transistor 100.

[0099] Exemplarily, the electron concentration of the first sub-active layer 1211 is less than that of the second sub-active layer 1212. Thus, the electron concentration of the first sub-active layer 1211 is relatively low, resulting in a relatively low carrier concentration of the first sub-active layer 1211 and a relatively low carrier mobility of the first sub-active layer 1211, reducing the diffusion of carriers in the active layer 120 from the conductive region 120b to the channel region 120a, improving the problem of negative bias divergence of the device, making the device exhibit positive bias convergence, and thus improving the electrical performance of the transistor 100. Additionally, the electron concentration of the second sub-active layer 1212 is relatively high, resulting in a higher carrier concentration of the second sub-active layer 1212, ensuring the efficient movement of carriers in the channel region 120a, and thus improving the response speed of the transistor 100.

[0100] It should be noted that the distance between the sub-active layer 121 and the substrate 110 refers to the distance between the surface of the sub-active layer 121 located in the channel region 120a facing the substrate 110 and the surface of the substrate 110 facing the active layer 120.

[0101] In some embodiments, among the multi-layer sub-active layers 121, the sub-active layer 121 farthest from the substrate 110 is the first sub-active layer 1211, that is Figure 1 the topmost sub-active layer 121 among them is the first sub-active layer 1211. Thus, all the second sub-active layers 1212 are located on the side of the first sub-active layer 1211 facing the substrate 110. The first sub-active layer 1211 can protect all the second sub-active layers 1212, and the first sub-active layer 1211 can also reduce the diffusion of elements or carriers in all the second sub-active layers 1212 into the first insulating layer 151.

[0102] Exemplarily, in the multi-layer sub-active layer 121, the thickness range of the sub-active layer 121 farthest from the substrate 110 is 5 nm - 30 nm, which can avoid the thickness of this sub-active layer 121 being too small, improve the protection effect of this sub-active layer 121 on the remaining sub-active layers 121, and in addition, can avoid the thickness of this sub-active layer 121 being too large, which is beneficial to the thinning of the transistor 100. For example, the thickness of the sub-active layer 121 farthest from the substrate 110 can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm or any value between 5 nm - 30 nm.

[0103] Exemplarily, the thickness range of the second sub-active layer 1212 is 1 nm - 6 nm, which can avoid the thickness of the second sub-active layer 1212 being too small, being beneficial to reducing the preparation difficulty of the second sub-active layer 1212 and improving the response speed of the transistor 100. In addition, it can also avoid the thickness of the second sub-active layer 1212 being too large, being beneficial to reducing the thickness ratio of the second sub-active layer 1212 in the active layer 120, reducing the diffusion of carriers in the active layer 120 from the conductive region 120b to the channel region 120a, improving the problem of negative bias divergence of the device, and making the device show positive bias convergence. For example, the thickness of the second sub-active layer 1212 can be 1 nm, 2 nm, 4 nm, 6 nm or any value between 1 nm - 6 nm.

[0104] In some embodiments, the material of the sub-active layer 121 includes a metal oxide semiconductor material, and the transistor 100 can be a Metal Oxide (abbreviated as MO) thin film transistor. The MO thin film transistor has a small leakage current, can enable the display panel to maintain a good display effect at a low frame rate, and reduce the power consumption of the display panel.

[0105] Exemplarily, the metal in the sub-active layer 121 includes one or more of indium, gallium, and zinc.

[0106] Exemplarily, the metal oxide in the sub-active layer 121 includes one or more of indium oxide (In Oxide), indium-zinc oxide (In-Zn Oxide), indium-tin oxide (In-Sn Oxide), indium-titanium oxide (In-Ti Oxide), indium-gallium oxide (In-Ga Oxide), indium-gallium-aluminum oxide (In-Ga-Al Oxide), indium-gallium-tin oxide (In-Ga-Sn Oxide, also written as IGTO), gallium-zinc oxide (Ga-Zn Oxide, also written as GZO), aluminum-zinc oxide (Al-Zn Oxide, also written as AZO), indium-aluminum-zinc oxide (In-Al-Zn Oxide, also written as IAZO), indium-tin-zinc oxide (In-Sn-Zn Oxide, also written as ITZO), indium-ti-zinc oxide (In-Ti-Zn Oxide), indium-gallium-zinc oxide (In-Ga-Zn Oxide, also written as IGZO), indium-gallium-tin-zinc oxide (In-Ga-Sn-Zn Oxide, also written as IGZTO), indium-gallium-aluminum-zinc oxide (In-Ga-Al-Zn Oxide, also written as IGAZO, IGZAO or IAGZO), gallium-tin oxide (Ga-Sn Oxide), and aluminum-tin oxide (Al-Sn Oxide).

[0107] In some embodiments, in the first sub-active layer 1211, the sum of the atomic numbers of indium, gallium, and zinc is a first value, and the ratio of the atomic number of indium to the first value is a first ratio. In the second sub-active layer 1212, the sum of the atomic numbers of indium, gallium, and zinc is a second value, and the ratio of the atomic number of indium to the second value is a second ratio. The first ratio is less than the second ratio. In this way, the proportion of the atomic number of indium in the first sub-active layer 1211 is relatively low, which is conducive to making the first sub-active layer 1211 have a lower carrier mobility and a lower carrier concentration, thereby facilitating the positive-bias convergence of the device. The principle has been described above and will not be elaborated further. Additionally, the proportion of the atomic number of indium in the second sub-active layer 1212 is relatively high, making the second sub-active layer 1212 have a higher carrier mobility and a higher carrier concentration, thereby facilitating the improvement of the response speed of the transistor 100. The principle has been described above and will not be elaborated further.

[0108] Exemplarily, the range of the first ratio is 30% - 70%. This can avoid the first ratio being too small, which is conducive to avoiding the carrier mobility of the first sub-active layer 1211 being too low and affecting the response speed of the transistor 100. Additionally, it can also avoid the first ratio being too large, which is conducive to the positive-bias convergence of the device. For example, the first ratio can be 30%, 40%, 50%, 60%, 70% or any value between 30% - 70%.

[0109] Exemplarily, in the first sub-active layer 1211, the ratio of the number of gallium atoms to the first value ranges from 10% to 40%. For example, the ratio of the number of gallium atoms to the first value can be 10%, 20%, 30%, 40%, or any value between 10% and 40%.

[0110] Exemplarily, in the first sub-active layer 1211, the ratio of the number of zinc atoms to the first value ranges from 10% to 40%. For example, the ratio of the number of zinc atoms to the first value can be 10%, 20%, 30%, 40%, or any value between 10% and 40%.

[0111] Exemplarily, the range of the second ratio is 50% - 100%, so that the carrier mobility of the second sub-active layer 1212 can be relatively large, which is beneficial to improving the response speed of the transistor 100. For example, the second ratio can be 50%, 60%, 70%, 80%, 90%, 100% or any value between 50% and 100%.

[0112] Exemplarily, in the second sub-active layer 1212, the ratio of the number of gallium atoms to the second value ranges from 0% to 30%. For example, the ratio of the number of gallium atoms to the second value can be 0%, 10%, 20%, 30% or any value between 0% and 30%.

[0113] Exemplarily, in the second sub-active layer 1212, the ratio of the number of zinc atoms to the second value ranges from 0% to 30%. For example, the ratio of the number of zinc atoms to the second value can be 0%, 10%, 20%, 30% or any value between 0% and 30%.

[0114] It should be noted that the number of the first sub-active layers 1211 in the active layer 120 can be 1 layer, 2 layers, 3 layers or any number greater than 3 layers. The number of the second sub-active layers 1212 in the active layer 120 can be 1 layer, 2 layers, 3 layers or any number greater than 3 layers.

[0115] The following describes the case where the active layer 120 includes 1 layer of the first sub-active layer 1211 and 1 layer of the second sub-active layer 1212.

[0116] See Figure 1, in an embodiment where the active layer 120 includes one layer of the first sub-active layer 1211 and one layer of the second sub-active layer 1212, the number of the first sub-active layer 1211 and the second sub-active layer 1212 is small, which is conducive to reducing the manufacturing difficulty and cost of the active layer 120. The sum of the thicknesses of the first sub-active layer 1211 and the second sub-active layer 1212 is a third value. Exemplarily, the ratio range of the thickness of the first sub-active layer 1211 to the third value is 60% - 90%, so as to avoid the thickness of the first sub-active layer 1211 in the active layer 120 being too small, which is beneficial to reducing the diffusion of carriers from the conductive region 120b to the channel region 120a in the active layer 120, improving the problem of negative bias divergence of the device, and making the device show positive bias convergence. In addition, it can also avoid the thickness of the first sub-active layer 1211 in the active layer 120 being too large to avoid the thickness ratio of the second sub-active layer 1212 in the active layer 120 being too small, which is beneficial to ensuring the efficient movement of carriers in the channel region 120a, thereby improving the response speed of the transistor 100.

[0117] For example, the ratio of the thickness of the first sub-active layer 1211 to the third value can be 60%, 70%, 80%, 90% or any value between 60% - 90%.

[0118] Exemplarily, the ratio range of the thickness of the second sub-active layer 1212 to the third value is 10% - 40%, so as to avoid the thickness ratio of the second sub-active layer 1212 in the active layer 120 being too small, which is beneficial to ensuring the efficient movement of carriers in the channel region 120a, thereby being beneficial to improving the response speed of the transistor 100. In addition, it can also avoid the thickness ratio of the second sub-active layer 1212 in the active layer 120 being too large, resulting in serious diffusion of carriers from the conductive region 120b to the channel region 120a in the active layer 120, which is beneficial to improving the problem of negative bias divergence of the device and making the device show positive bias convergence.

[0119] For example, the ratio of the thickness of the second sub-active layer 1212 to the third value can be 10%, 20%, 30%, 40% or any value between 10% - 40%.

[0120] The following describes the case where the active layer 120 includes two layers of the first sub-active layer 1211 and one layer of the second sub-active layer 1212.

[0121] See Figure 2, the multi-layer sub-active layer 121 includes two layers of first sub-active layers 1211 and one layer of second sub-active layer 1212. The second sub-active layer 1212 is disposed between the two layers of first sub-active layers 1211. In this way, the two layers of first sub-active layers 1211 can provide good protection for the middle second sub-active layer 1212, which is beneficial to reducing the diffusion of elements or carriers in the second sub-active layer 1212 into the first insulating layer 151 and the second insulating layer 152.

[0122] The sum of the thicknesses of the two layers of first sub-active layers 1211 and the second sub-active layer 1212 is a fourth value. Exemplarily, the ratio range of the thickness of the second sub-active layer 1212 to the fourth value is 5% - 30%. Thereby, it can be avoided that the thickness proportion of the second sub-active layer 1212 in the active layer 120 is too small, which is beneficial to ensuring the efficient movement of carriers in the channel region 120a, thereby improving the response speed of the transistor 100. In addition, it can also be avoided that the thickness proportion of the second sub-active layer 1212 in the active layer 120 is too large, resulting in a relatively serious diffusion of carriers in the active layer 120 from the conductive region 120b to the channel region 120a, which is beneficial to improving the problem of negative bias divergence of the device, making the device show positive bias convergence.

[0123] For example, the ratio of the thickness of the second sub-active layer 1212 to the fourth value can be 5%, 10%, 20%, 30% or any value between 5% - 30%.

[0124] Exemplarily, the ratio range of the thickness of the first sub-active layer 1211 on the side of the second sub-active layer 1212 facing away from the substrate 110 to the fourth value is 30% - 70%. In this way, by reasonably setting the thickness proportion of the first sub-active layer 1211 in the active layer 120, it is beneficial to improving the problem of negative bias divergence of the device, making the device show positive bias convergence.

[0125] For example, the ratio of the thickness of the first sub-active layer 1211 on the side of the second sub-active layer 1212 facing away from the substrate 110 to the fourth value can be 30%, 40%, 50%, 60%, 70% or any value between 30% - 70%.

[0126] Exemplarily, the thickness range of the first sub-active layer 1211 on the side of the second sub-active layer 1212 facing the substrate 110 is 1nm - 30nm. Thereby, it can be avoided that the thickness of the first sub-active layer 1211 is too small, which is beneficial to reducing the preparation difficulty of the first sub-active layer 1211. In addition, it is also beneficial to avoiding that the thickness of the first sub-active layer 1211 is too large, thereby being beneficial to reducing the thickness of the transistor 100.

[0127] For example, the thickness of the first sub-active layer 1211 on the side of the second sub-active layer 1212 facing the substrate 110 can be 1nn, 5nn, 10nn, 20nn, 30nn, or any value between 1nn and 30nm.

[0128] Exemplarily, the ratio range of the thickness of the first sub-active layer 1211 on the side of the second sub-active layer 1212 facing the substrate 110 to the fourth value is 10% - 40%. Thus, by reasonably setting the thickness ratio of the first sub-active layer 1211 in the active layer 120, it is beneficial to improve the problem of negative bias divergence of the device, making the device show positive bias convergence.

[0129] For example, the ratio of the thickness of the first sub-active layer 1211 on the side of the second sub-active layer 1212 facing the substrate 110 to the fourth value can be 10%, 20%, 30%, 40%, or any value between 10% and 40%.

[0130] The following describes the distribution of the first sub-active layer 1211 in the channel region 120a and the conductive region 120b.

[0131] The first sub-active layer 1211 is located in the channel region 120a and the conductive region 120b.

[0132] Exemplarily, referring to Figure 1 and Figure 4 , the orthographic projection of at least one layer of the first sub-active layer 1211 on the substrate 110 coincides with the orthographic projection of the active layer 120 on the substrate 110. At this time, the dimension of at least one layer of the first sub-active layer 1211 along the direction from the channel region 120a to the conductive region 120b is equal to the sum of the dimensions of the channel region 120a and the conductive region 120b along the direction from the channel region 120a to the conductive region 120b, so that at least one layer of the first sub-active layer 1211 completely covers the channel region 120a and the conductive region 120b at the same time, which is beneficial to improving the problem of negative bias divergence of the device and beneficial to the positive bias convergence of the device.

[0133] In some embodiments, referring to Figure 6 , the multi-layer sub-active layer 121 includes multiple layers of the first sub-active layer 1211. In at least one layer of the first sub-active layer 1211, the orthographic projection of the first sub-active layer 1211 on the substrate 110 covers the orthographic projection of the channel region 120a on the substrate 110, and the dimension of the first sub-active layer 1211 in the conductive region 120b along the direction from the conductive region 120b to the channel region 120a is smaller than the dimension of the conductive region 120b along the direction from the conductive region 120b to the channel region 120a. At this time, the first sub-active layer 1211 partially covers the conductive region 120b.

[0134] For example, referring to Figure 6, in an embodiment where the active layer 120 includes one layer of the second sub-active layer 1212 and two layers of the first sub-active layer 1211, the first sub-active layer 1211 located on the side of the second sub-active layer 1212 facing the substrate 110 may completely cover the channel region 120a and the conductivized region 120b, and the first sub-active layer 1211 located on the side of the second sub-active layer 1212 facing away from the substrate 110 partially covers the conductivized region 120b. Or, refer to Figure 7 , in an embodiment where the active layer 120 includes one layer of the second sub-active layer 1212 and two layers of the first sub-active layer 1211, the first sub-active layer 1211 located on the side of the second sub-active layer 1212 facing the substrate 110 may partially cover the conductivized region 120b, and the first sub-active layer 1211 located on the side of the second sub-active layer 1212 facing away from the substrate 110 may completely cover the channel region 120a and the conductivized region 120b.

[0135] Exemplarily, in at least one layer of the first sub-active layer 1211, the dimension of the first sub-active layer 1211 located in the conductivized region 120b along the conductivized region 120b to the channel region 120a is less than or equal to 1 μm. For example, this dimension may be 0.1 μm, 0.3 μm, 0.5 μm, 0.7 μm, 1 μm or any value less than 1 μm.

[0136] In some other embodiments, refer to Figure 2 , the multi-layer sub-active layer 121 includes multiple layers of the first sub-active layer 1211. The orthographic projection of each first sub-active layer 1211 on the substrate 110 coincides with the orthographic projection of the active layer 120 on the substrate 110. In this way, all the first sub-active layer 1211 can completely cover the channel region 120a and the conductivized region 120b simultaneously, which can better improve the problem of negative bias divergence of the device and make the device show positive bias convergence.

[0137] The distribution of the second sub-active layer 1212 in the channel region 120a and the conductivized region 120b will be described below.

[0138] The second sub-active layer 1212 is located in the channel region 120a and the conductivized region 120b.

[0139] In some embodiments, refer to Figure 1 , the orthographic projection of the second sub-active layer 1212 on the substrate 110 coincides with the orthographic projection of the active layer 120 on the substrate 110. When the orthographic projection of at least one layer of the first sub-active layer 1211 on the substrate 110 coincides with the orthographic projection of the active layer 120 on the substrate 110, the second sub-active layer 1212 and the at least one layer of the first sub-active layer 1211 can be patterned synchronously to simplify the manufacturing process of the second sub-active layer 1212 and the at least one layer of the first sub-active layer 1211 and reduce the manufacturing cost.

[0140] In some other embodiments, referring to Figure 4 and Figure 5 , in at least one layer of the second sub-active layer 1212, the orthographic projection of the second sub-active layer 1212 on the substrate 110 covers the orthographic projection of the channel region 120a on the substrate 110. The dimension D1 of the second sub-active layer 1212 located in the conductive region 120b along the direction from the conductive region 120b to the channel region 120a is smaller than the dimension D2 of the conductive region 120b along the direction from the conductive region 120b to the channel region 120a. In this way, at least one layer of the second sub-active layer 1212 partially covers the conductive region 120b, reducing the area ratio of at least one layer of the second sub-active layer 1212 in the conductive region 120b, so as to reduce the proportion of carriers of the second sub-active layer 1212 in the conductive region 120b in the active layer 120, thereby reducing the diffusion of carriers in the active layer 120 from the conductive region 120b to the channel region 120a, improving the problem of negative bias divergence of the device, and making the device show positive bias convergence.

[0141] Exemplarily, in at least one layer of the second sub-active layer 1212, the dimension D1 of the second sub-active layer 1212 located in the conductive region 120b along the direction from the conductive region 120b to the channel region 120a is less than or equal to 1 μm. Thus, the dimension D1 of the second sub-active layer 1212 located in the conductive region 120b along the direction from the conductive region 120b to the channel region 120a can be made smaller, reducing the diffusion of carriers in the active layer 120 from the conductive region 120b to the channel region 120a, improving the problem of negative bias divergence of the device, and making the device show positive bias convergence. For example, the dimension D1 of the second sub-active layer 1212 located in the conductive region 120b along the direction from the conductive region 120b to the channel region 120a can be 0.1 μm, 0.3 μm, 0.5 μm, 0.7 μm, 1 μm or any value less than 1 μm.

[0142] The following describes the first conductive layer 131, the second conductive layer 132, the first electrode 141 and the second electrode 142 provided in the embodiments of the present application.

[0143] In some embodiments, referring to Figure 1 , the transistor 100 includes a first conductive layer 131, and the first conductive layer 131 is disposed on the side of the active layer 120 away from the substrate 110. The orthographic projection of the first conductive layer 131 on the substrate 110 intersects (i.e., at least partially overlaps) the orthographic projection of the channel region 120a on the substrate 110.

[0144] Exemplarily, the orthographic projection of the first conductive layer 131 on the substrate 110 coincides with the orthographic projection of the channel region 120a on the substrate 110.

[0145] In some embodiments, the transistor 100 includes a second conductive layer 132 disposed on a side of the active layer 120 facing the substrate 110.

[0146] It should be noted that the transistor 100 may be provided with at least one of the first conductive layer 131 and the second conductive layer 132.

[0147] In some examples, the first conductive layer 131 and the second conductive layer 132 are electrically connected, and both the first conductive layer 131 and the second conductive layer 132 are configured as gates. The transistor 100 is a double-gate transistor, and the two gates of the double-gate transistor can work together to enhance the control ability of carriers in the channel region 120a. In other examples, one of the first pole 141 and the second pole 142 is electrically connected to the first conductive layer 131, and the second conductive layer 132 is configured as a gate. The first conductive layer 131 can play a role in light shielding and can also improve the stability of the transistor 100. In some other examples, one of the first pole 141 and the second pole 142 is electrically connected to the second conductive layer 132, and the first conductive layer 131 is configured as a gate. The second conductive layer 132 can play a role in light shielding and can also improve the stability of the transistor 100.

[0148] In some embodiments, referring to Figure 1 , the transistor 100 includes a first pole 141 and a second pole 142. The conductorized regions 120b located on both sides of the channel region 120a are the first conductorized region 120b1 and the second conductorized region 120b2 respectively. The first pole 141 is in contact with the active layer 120 located in the first conductorized region 120b1, and the second pole 142 is in contact with the active layer 120 located in the second conductorized region 120b2. One of the first pole 141 and the second pole 142 may be a source electrode, and the other of the first pole 141 and the second pole 142 may be a drain electrode.

[0149] Exemplarily, the material of at least one of the first conductive layer 131, the second conductive layer 132, the first pole 141, and the second pole 142 may include a metal material. For example, it may be at least one of molybdenum (Mo), aluminum (Al), titanium (Ti), and copper (Cu).

[0150] In some embodiments, referring to Figure 1 and Figure 6 , both the first pole 141 and the second pole 142 are in contact with the first sub-active layer 1211. In some examples, referring to Figure 6 , the first sub-active layer 1211 in contact with the first pole 141 and the second pole 142 is the one closest to the substrate 110 in the multi-layer sub-active layer 121. Or, referring to Figure 1 , the first sub-active layer 1211 in contact with the first pole 141 and the second pole 142 is the one farthest from the substrate 110 in the multi-layer sub-active layer 121.

[0151] The following describes the first insulating layer 151 and the second insulating layer 152 provided in the embodiments of the present application.

[0152] In some embodiments, referring to Figure 1 , the transistor 100 includes a first insulating layer 151. The first insulating layer 151 is disposed between the active layer 120 and the first conductive layer 131, and the first insulating layer 151 is used to electrically isolate the active layer 120 and the first conductive layer 131.

[0153] Exemplarily, referring to Figure 3 , the orthographic projection of the surface of the first conductive layer 131 facing the substrate 110 on the substrate 110 coincides with the orthographic projection of the surface of the first insulating layer 151 facing away from the substrate 110 on the substrate 110. In this way, the first conductive layer 131 can be used as a mask to pattern the first insulating layer 151, which can simplify the patterning process of the first insulating layer 151 and reduce the manufacturing cost. In addition, in the embodiment where the first conductive layer 131 is used as a gate, the first insulating layer 151 serves as a gate insulating layer, and the sizes of the gate and the gate insulating layer are substantially the same, so that the electric field generated by applying a voltage to the gate can be more evenly distributed in the gate insulating layer and the channel region 120a therebelow, and the movement of carriers in the channel region 120a can be more evenly controlled, which can improve the stability of the transistor 100.

[0154] In some embodiments, referring to Figure 3 , the transistor 100 includes a second insulating layer 152. The second insulating layer 152 is disposed between the active layer 120 and the second conductive layer 132, and the second insulating layer 152 is used to electrically isolate between the active layer 120 and the second conductive layer 132. In the embodiment where the second conductive layer 132 is used as a gate, the second insulating layer 152 serves as a gate insulating layer.

[0155] In some embodiments, referring to Figure 3 , the transistor 100 includes a buffer layer 160. The buffer layer 160 is disposed between the second conductive layer 132 and the substrate 110, and the buffer layer 160 is used to isolate between the substrate 110 and the film layers on the substrate 110, and prevent impurities in the substrate 110 from entering the film layers on the substrate 110, thereby affecting the performance of the transistor 100. In addition, it can also reduce the influence of high temperature on the substrate 110 during subsequent high-temperature processes.

[0156] In some embodiments, referring to Figure 3 , the transistor 100 includes an interlayer insulating layer 170. The interlayer insulating layer 170 is disposed on the side of the first conductive layer 131 facing away from the substrate 110, and the interlayer insulating layer 170 is used to isolate and protect the first conductive layer 131, the active layer 120, etc., which is beneficial to preventing current short circuits and interference.

[0157] Exemplarily, the material of at least one of the first insulating layer 151, the second insulating layer 152, the interlayer insulating layer 170, and the buffer layer 160 may be silicon nitride, silicon oxynitride, silicon oxide, or various novel organic insulating materials, or high-k metal oxides such as aluminum oxide and tantalum oxide.

[0158] Figures 11-14 is the Vgs-Ids curve diagram of the transistor 100 provided by the embodiment of the present application. Figures 11-14 In the transistor 100, the active layer 120 includes a first sub-active layer 1211, a second sub-active layer 1212, and a first sub-active layer 1211 arranged in sequence. The ratio of the second sub-active layer 1212 to the sum of the thicknesses of the first sub-active layer 1211, the second sub-active layer 1212, and the first sub-active layer 1211 arranged in sequence is 16.6%. Figure 11 In the transistor 100, the threshold voltage Vth = 0.3V - 0.6V, and the length L of the channel region 120a is 10μm. The length of its channel region 120a is relatively large, belonging to a long-channel device. Figure 12 In the transistor 100, the threshold voltage Vth = 0.1V - 0.4V, and the length L of the channel region 120a is 4μm. Figure 13 In the transistor 100, the threshold voltage Vth = 0V - 0.3V, and the length L of the channel region 120a is 2μm. Figure 14 In the transistor 100, the threshold voltage Vth = -0.2V - 0.1V, and the length L of the channel region 120a is 1.5μm. Figures 12-14 In, the length of the channel region 120a is relatively small, all belonging to short-channel devices. Figures 11-14 It can be seen that by using the active layer 120 provided by the embodiment of the present application, whether it is a short-channel device or a long-channel device, its Vgs-Ids curve converges and is not easily negatively biased and diverges.

[0159] The following describes the manufacturing method of the transistor 100 provided by the embodiment of the present application.

[0160] First, refer to Figure 8 and Figure 9 , and provide a substrate 110.

[0161] In some embodiments, after providing the substrate 110, an active layer 120 may be formed on one side of the substrate 110. Forming the active layer 120 may include forming an initial active layer (the initial active layer is an active layer that has not been made conductive) on one side of the substrate 110. The initial active layer includes a first region and second regions on both sides of the first region. The first region is used to form a channel region subsequently, and the second regions are used to form conductive regions subsequently. Then, the initial active layer in the second regions is made conductive so that the second regions form conductive regions 120b, the first region forms a channel region, and the initial active layer forms the active layer 120.

[0162] Exemplarily, the second regions may be made conductive by ion implantation.

[0163] In some embodiments, referring to Figure 9 , in an embodiment where the active layer 120 includes one layer of a first sub-active layer 1211 and one layer of a second sub-active layer 1212, forming the active layer 120 may include forming the second sub-active layer 1212 and the first sub-active layer 1211, and the first sub-active layer 1211 is disposed on the side of the second sub-active layer 1212 away from the substrate 110.

[0164] In some embodiments, referring to Figure 10 , in an embodiment where the active layer 120 includes two layers of a first sub-active layer 1211 and one layer of a second sub-active layer 1212, forming the active layer 120 may include forming the second sub-active layer 1212 and two layers of the first sub-active layer 1211, and the two layers of the first sub-active layer 1211 are respectively located on both sides of the second sub-active layer 1212.

[0165] In some embodiments, referring to Figure 8 , after providing the substrate 110 and before forming the active layer 120, it may include forming a buffer layer 160 on one side of the substrate 110.

[0166] In some embodiments, referring to Figure 8 , after forming the buffer layer 160 and before forming the active layer 120, it may include forming a second conductive layer 132 on the side of the buffer layer 160 away from the substrate 110.

[0167] In some embodiments, referring to Figure 8 and Figure 9 , after forming the second conductive layer 132 and before forming the active layer 120, it may include forming a second insulating layer 152 on the side of the second conductive layer 132 away from the substrate 110. Forming the active layer 120 may include forming the active layer 120 on the side of the second insulating layer 152 away from the substrate 110.

[0168] In some embodiments, referring to Figure 1, after forming the initial active layer, it may include forming a first insulating layer 151 on a side of the initial active layer facing away from the substrate 110.

[0169] In some embodiments, referring to Figure 1 , after forming the first insulating layer 151, it may include forming a first conductive layer 131 on a side of the first insulating layer 151 facing away from the substrate 110.

[0170] Exemplarily, the first insulating layer 151 can be etched using the first conductive layer 131 as a mask. A surface of the first conductive layer 131 facing the substrate 110 coincides with a surface of the first insulating layer 151 facing away from the substrate 110. After the etching is completed, ion doping treatment can be performed on the initial active layer in the second region, so as to conductivize the second region. When the initial active layer undergoes conductivization treatment, a portion of the initial active layer overlapping with the first conductive layer 131 does not become a conductor, that is, the initial active layer in the first region is not doped and does not form a conductor, and a portion of the initial active layer not overlapping with the first conductive layer 131 can be made into a conductor and has conductivity, that is, the initial active layer in the first region is doped to form a conductor.

[0171] In some embodiments, referring to Figure 1 , after forming the first conductive layer 131, it may include forming an interlayer insulating layer 170 on a side of the first conductive layer 131 facing away from the substrate 110.

[0172] In some embodiments, referring to Figure 1 , after forming the interlayer insulating layer 170, it may include forming a first electrode 141 and a second electrode 142 on a side of the interlayer insulating layer 170 facing away from the substrate 110, and the first electrode 141 and the second electrode 142 penetrate the interlayer insulating layer 170 to contact a conductivized region 120b of the active layer 120.

[0173] An embodiment of the present application provides an array substrate, and the array substrate includes the transistor 100 in the above embodiment. There may be multiple transistors 100 in the array substrate.

[0174] An embodiment of the present application provides a display panel, and the display panel includes the array substrate in the above embodiment.

[0175] Exemplarily, the display panel may be an Organic Light-Emitting Diode (OLED) display panel, a Micro Organic Light-Emitting Diode (Micro OLED) display panel, a light emitting diode (LED) display panel, a quantum dot light emitting diodes (QLED) display panel, a Mini light emitting diodes (MiniLED) display panel, a Micro LightEmitting Diode (Micro LED) display panel, or a Liquid Crystal Display (LCD) display panel, etc.

[0176] An embodiment of the present application provides a display device, which may include the display panel in the above embodiment. The display device may be an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a smart bracelet, a smart watch, a super personal computer, a navigator, a wireless device, a Personal Digital Assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a clock, a calculator, a TV monitor, a computer monitor, an in-vehicle display (e.g., an odometer display, etc.), a cockpit controller and / or display, a display for a camera view (e.g., a display for a rearview camera in a vehicle), an electronic billboard or sign, a projector, or other mobile or fixed terminals.

[0177] When using "including", "having", and "comprising" described herein, unless an explicit limiting term is used, such as "only", "consisting of", etc., another component may be added. Unless otherwise mentioned, a term in the singular form may include the plural form and should not be construed as having a quantity of one.

[0178] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0179] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patented application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application.

Claims

1. A transistor, characterized in that: include: substrate; An active layer, disposed on one side of the substrate; Wherein, the active layer includes multiple sub-active layers stacked along the thickness direction of the substrate, the multiple sub-active layers include at least one first sub-active layer and at least one second sub-active layer, the first sub-active layers and the second sub-active layers are arranged alternately, the carrier mobility of the first sub-active layer is less than the carrier mobility of the second sub-active layer, and the sum of the thicknesses of all the first sub-active layers is greater than the sum of the thicknesses of all the second sub-active layers.

2. The transistor according to claim 1, characterized in that The carrier concentration of the first sub-active layer is less than the carrier concentration of the second sub-active layer; Preferably, the electron concentration of the first sub-active layer is less than the electron concentration of the second sub-active layer.

3. The transistor according to claim 1, characterized in that Among the multiple sub-active layers, the sub-active layer farthest from the substrate is the first sub-active layer; Preferably, in the multi-layer sub-active layer, the sub-active layer farthest from the substrate has a thickness ranging from 5 nm to 30 nm; Preferably, the thickness of the second sub-active layer is in the range of 1 nm to 6 nm.

4. The transistor according to any one of claims 1 to 3, characterized in that: The material of the sub-active layer includes a metal oxide semiconductor material; Preferably, the metal in the sub-active layer includes one or more of indium, gallium and zinc; Preferably, the material of the sub-active layer includes one or more of indium gallium oxide, indium zinc oxide, and indium gallium zinc oxide.

5. The transistor according to claim 4, characterized in that In the first sub-active layer, the sum of the numbers of atoms of indium, gallium and zinc is a first value, and the ratio of the number of atoms of indium to the first value is a first ratio; in the second sub-active layer, the sum of the numbers of atoms of indium, gallium and zinc is a second value, and the ratio of the number of atoms of indium to the second value is a second ratio, and the first ratio is smaller than the second ratio.

6. The transistor according to claim 5, characterized in that The first ratio ranges from 30% to 70%; Preferably, in the first sub-active layer, the ratio of the number of gallium atoms to the first value is in the range of 10%-40%; Preferably, in the first sub-active layer, the ratio of the number of zinc atoms to the first value is in the range of 10%-40%.

7. The transistor according to claim 5, characterized in that The range of the second ratio is 50%-100%; Preferably, in the second active sub-layer, the ratio of the number of gallium atoms to the second value is in the range of 0%-30%; Preferably, in the second active sub-layer, the ratio of the number of zinc atoms to the second value is in the range of 0%-30%.

8. The transistor according to any one of claims 1 to 3, characterized in that: The multi-layer sub-active layer includes a layer of the first sub-active layer and a layer of the second sub-active layer, and the sum of the thicknesses of the first sub-active layer and the second sub-active layer is a third value; Preferably, the ratio of the thickness of the first sub-active layer to the third value is in the range of 60%-90%; Preferably, the ratio of the thickness of the second sub-active layer to the third value is in the range of 10%-40%.

9. The transistor according to any one of claims 1 to 3, characterized in that: The multi-layer sub-active layer includes two layers of the first sub-active layer and one layer of the second sub-active layer, the second sub-active layer is arranged between the two layers of the first sub-active layer, and the sum of the thicknesses of the two layers of the first sub-active layer and the second sub-active layer is a fourth value; Preferably, the ratio of the thickness of the second sub-active layer to the fourth value is in the range of 5%-30%; Preferably, a ratio of a thickness of the first sub-active layer located on a side of the second sub-active layer away from the substrate to the fourth value is in a range of 30%-70%; Preferably, the thickness of the first sub-active layer located on the side of the second sub-active layer facing the substrate is in the range of 1nn-30nm; Preferably, a ratio of a thickness of the first sub-active layer located on a side of the second sub-active layer facing the substrate to the fourth value is in a range of 10%-40%.

10. The transistor according to any one of claims 1 to 3, characterized in that: The active layer includes a channel region and conductive regions disposed on opposite sides of the channel region, and the first sub-active layer is located in the channel region and the conductive region; An orthographic projection of at least one layer of the first sub-active layer on the substrate coincides with an orthographic projection of the active layer on the substrate; Preferably, the multi-layer sub-active layer includes a plurality of the first sub-active layers, and in at least one layer of the first sub-active layer, the orthographic projection of the first sub-active layer on the substrate covers the orthographic projection of the channel region on the substrate, and the dimension of the first sub-active layer located in the conductorized region from the conductorized region to the channel region is smaller than the dimension of the conductorized region from the conductorized region to the channel region; or, the orthographic projections of each of the first sub-active layers on the substrate overlap with the orthographic projection of the active layer on the substrate; Preferably, in at least one layer of the first sub-active layer, a dimension of the first sub-active layer located in the conductive region from the conductive region to the channel region is less than or equal to 1 μm.

11. The transistor according to any one of claims 1 to 3, characterized in that: The active layer includes a channel region and conductive regions disposed on opposite sides of the channel region; the second sub-active layer is located in the channel region and the conductive region; The orthographic projection of the second sub-active layer on the substrate coincides with the orthographic projection of the active layer on the substrate; or, In at least one layer of the second sub-active layer, an orthographic projection of the second sub-active layer on the substrate covers an orthographic projection of the channel region on the substrate, and a dimension of the second sub-active layer located in the conductorized region from the conductorized region to the channel region is smaller than a dimension of the conductorized region from the conductorized region to the channel region; Preferably, in at least one layer of the second sub-active layer, a dimension of the second sub-active layer located in the conductive region from the conductive region to the channel region is less than or equal to 1 μm.

12. The transistor according to any one of claims 1 to 3, characterized in that: The transistor includes a first conductive layer, and the first conductive layer is disposed on one side of the substrate; The first conductive layer is disposed on a side of the active layer away from the substrate; Preferably, the transistor comprises a second conductive layer, and the second conductive layer is arranged on a side of the active layer facing the substrate; Preferably, the active layer comprises a channel region and conductive regions disposed on opposite sides of the channel region, and an orthographic projection of the first conductive layer on the substrate coincides with an orthographic projection of the channel region on the substrate.

13. The transistor according to claim 12, characterized in that The active layer includes a channel region and conductive regions located at opposite sides of the channel region, the transistor includes a first electrode and a second electrode, the conductive regions located at opposite sides of the channel region are respectively a first conductive region and a second conductive region, the first electrode contacts the active layer located at the first conductive region, and the second electrode contacts the active layer located at the second conductive region; Preferably, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode; Preferably, the first conductive layer and the second conductive layer are electrically connected, and the first conductive layer and the second conductive layer are configured as gates; or, one of the first pole and the second pole is electrically connected to the first conductive layer, and the second conductive layer is configured as a gate; or, one of the first pole and the second pole is electrically connected to the second conductive layer, and the first conductive layer is configured as a gate.

14. The transistor according to claim 13, characterized in that The first pole and the second pole are both in contact with the first sub-active layer; Preferably, the first sub-active layer in contact with the first pole and the second pole is the one of the multiple sub-active layers closest to the substrate; or, The first sub-active layer in contact with the first pole and the second pole is the one of the multiple sub-active layers farthest from the substrate.

15. The transistor according to claim 12, characterized in that The transistor comprises a first insulating layer, wherein the first insulating layer is disposed between the active layer and the first conductive layer; Preferably, an orthographic projection of a surface of the first conductive layer facing the substrate on the substrate coincides with an orthographic projection of a surface of the first insulating layer facing away from the substrate on the substrate; Preferably, the transistor comprises a second insulating layer, and the second insulating layer is arranged between the active layer and the second conductive layer.

16. A transistor, characterized in that: include substrate; An active layer, disposed on one side of the substrate; Among them, the active layer includes multiple sub-active layers stacked along the thickness direction of the substrate, the multiple sub-active layers include at least one first sub-active layer and at least one second sub-active layer, the first sub-active layers and the second sub-active layers are arranged alternately, the carrier concentration of the first sub-active layer is less than the carrier concentration of the second sub-active layer, and the sum of the thicknesses of all the first sub-active layers is greater than the sum of the thicknesses of all the second sub-active layers.

17. The transistor according to claim 16, characterized in that The electron concentration of the first sub-active layer is less than the electron concentration of the second sub-active layer; Preferably, the active layer includes a channel region and conductive regions disposed on opposite sides of the channel region; Preferably, the transistor comprises a first conductive layer, the first conductive layer is provided on one side of the substrate, and an orthographic projection of the first conductive layer on the substrate coincides with an orthographic projection of the channel region on the substrate; Preferably, in the multiple sub-active layers, the sub-active layer farthest from the substrate is the first sub-active layer; Preferably, in the multi-layer sub-active layer, the sub-active layer farthest from the substrate has a thickness ranging from 5 nm to 30 nm; Preferably, the thickness of the second sub-active layer is in the range of 1 nm to 6 nm.

18. The transistor according to claim 16, characterized in that The material of the sub-active layer includes a metal oxide semiconductor material; Preferably, the metal in the sub-active layer includes one or more of indium, gallium and zinc; Preferably, the material of the sub-active layer includes one or more of indium gallium oxide, indium zinc oxide, and indium gallium zinc oxide.

19. An array substrate, characterized in that: A transistor comprising any one of claims 1-18.

20. A display panel, characterized in that: Comprising the array substrate as claimed in claim 19.

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