Semiconductor structure and preparation method thereof

Abstract

The present application provides a semiconductor structure and a method for fabricating the same. The method comprises: providing a substrate; the substrate comprising a substrate and a shallow trench isolation structure; wherein the substrate comprises a first region defined by the shallow trench isolation structure; etching the substrate to form a groove located in the first region; wherein a plane where the bottom of the groove lies and a sidewall facing each other of an adjacent shallow trench isolation structure form a target region; wherein the target region comprises a substrate etch residue formed during the etching of the substrate; and converting the material of the substrate etch residue to form a first gate oxide layer in the target region. By converting the material of the substrate etch residue, the substrate material residue in the target region after the first gate oxide layer is formed can be reduced, thereby improving the reliability of the first gate oxide layer.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing process technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of integrated circuits, to improve chip switching characteristics, power consumption, and other performance, it is often necessary to integrate power devices with different operating voltages and logic control circuits on a single chip. For MOS devices with higher operating voltages, the gate oxide layer needs to have a certain thickness to meet the high voltage resistance requirements.

[0003] When preparing thicker gate oxide layers, a dry etching process is typically used. A groove of a certain depth is etched on the substrate surface between adjacent shallow trench isolation (STI) structures, and then the gate oxide layer is formed in the groove. This allows for a thicker gate oxide layer to be prepared while maintaining a roughly consistent surface height with the thinner gate oxide layer.

[0004] However, due to the inherent structural characteristics of STI, which is wide at the top and narrow at the bottom, and the anisotropic characteristics of dry etching, there are substrate material residues on the STI sidewalls on both sides of the grooves etched on the substrate surface, which can easily cause current tunneling and thus reduce the reliability of the gate oxide layer formed in the grooves. Summary of the Invention

[0005] In view of this, multiple embodiments of the present application are directed to providing a semiconductor structure and a method for manufacturing the same, which can reduce substrate material residue and improve the reliability of the gate oxide layer.

[0006] An embodiment of the present application provides a method for preparing a semiconductor structure, comprising: providing a substrate; the substrate comprising a substrate and a shallow trench isolation structure; wherein the substrate comprises a first area defined by the shallow trench isolation structure; etching the substrate to form a groove located in the first area; wherein a plane where the bottom of the groove is located and the sidewalls facing each other of the adjacent shallow trench isolation structure form a target area; the target area has a substrate etching residue formed during the etching process; and converting the material of the substrate etching residue to obtain a first gate oxide layer in the target area.

[0007] Optionally, a patterned mask layer defining the first area is also formed on the substrate; the step of converting the material of the substrate etching residue to form a first gate oxide layer in the target area includes: converting the material of the substrate etching residue into the same material as the patterned mask layer; removing the patterned mask layer; wherein the substrate etching residue in the target area is also removed; and forming a first gate oxide layer in the target area.

[0008] Optionally, the material of the substrate is silicon; the material of the patterned mask layer is silicon nitride; the step of converting the material of the substrate etching residue into the same material as the patterned mask layer includes: performing a decoupled plasma nitridation deposition process on the substrate etching residue made of silicon material to form a substrate etching residue made of silicon nitride material.

[0009] Optionally, during the decoupled plasma nitridation deposition process, N2 is used as an ion source, and the deposition rate of silicon nitride falls within the range of 5 um / cm2 to 20 um / cm2.

[0010] Optionally, the step of converting the material of the substrate etching residue to form a first gate oxide layer in the target area includes: converting the material of the substrate etching residue into the same material as the first gate oxide layer.

[0011] Optionally, the material of the substrate is silicon; the material of the first gate oxide layer is silicon dioxide; the step of converting the material of the substrate etching residue into the same material as the first gate oxide layer includes: under low temperature and high pressure conditions, using oxygen to oxidize the substrate etching residue made of silicon material to form a substrate etching residue made of silicon dioxide.

[0012] Optionally, under low temperature and high pressure conditions, in the process of oxidizing the substrate etching residue of silicon material using oxygen, the substrate etching residue and the bottom of the groove are both affected by oxygen pressure; wherein, the oxygen pressure acting on the substrate etching residue is greater than the oxygen pressure acting on the bottom of the groove.

[0013] Optionally, a transition gate oxide portion made of silicon dioxide is formed at the bottom of the groove; after the material of the substrate etching residue is converted into the same material as the first gate oxide layer, the material of the substrate etching residue is converted to form a first gate oxide layer in the target area, and the step also includes: using the transition gate oxide portion and the substrate etching residue made of silicon dioxide as masking layers, performing an ion implantation process on the substrate; removing at least part of the masking layer consumed in the ion implantation process; and the remaining masking layer serves as part of the first gate oxide layer.

[0014] Optionally, the substrate also includes a second area defined by the shallow trench isolation structure; the base also includes an oxide layer located on the surface of the substrate; accordingly, in the step of etching the substrate to form a groove located in the first area, the oxide layer located in the first area is removed; the remaining oxide layer located in the second area serves as a second gate oxide layer; wherein the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

[0015] An embodiment of the present application provides a semiconductor structure, which is prepared using the semiconductor structure preparation method described in the above embodiments.

[0016] The unexpected effect of the multiple embodiments provided in the present application is that, in the process of preparing a thick gate oxide layer, the substrate etching residue located in the target area is formed during the etching process of the substrate in the first area. By converting the material of the substrate etching residue and then producing the first gate oxide layer, the substrate material residue in the target area after the first gate oxide layer is formed can be reduced, thereby improving the reliability of the first gate oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of substrate material residue during the preparation of a thicker gate oxide layer in the related art.

[0018] Figure 2 A schematic diagram of a method for preparing a semiconductor structure provided in one embodiment of the present application.

[0019] Figure 3 A schematic diagram of a substrate is provided in a method for preparing a semiconductor structure according to an embodiment of the present application.

[0020] Figure 4 and Figure 5 A schematic diagram of etching to form grooves in a method for preparing a semiconductor structure provided in one embodiment of the present application.

[0021] Figure 6 A schematic diagram of converting the material of a substrate etching residue in a method for preparing a semiconductor structure provided by one embodiment of the present application.

[0022] Figure 7 A schematic diagram of removing a patterned mask layer in a method for preparing a semiconductor structure provided in one embodiment of the present application.

[0023] Figure 8 A schematic diagram of converting the material of a substrate etching residue in a method for preparing a semiconductor structure provided by another embodiment of the present application.

[0024] Figure 9A schematic diagram of forming a first gate oxide layer in a method for preparing a semiconductor structure provided in another embodiment of the present application.

[0025] Description of reference numerals:

[0026] 101. Thick gate oxide region; 102. Shallow trench isolation; 103. Thin gate oxide layer; 104. Patterned mask layer; 105. Etched groove; 106. Residual substrate material; 10. Base; 11. Substrate; 111. First region; 112. Second region; 12. Shallow trench isolation structure; 13. Oxide layer; 14. Mask layer; 15. Groove; 16. Target region; 17. Substrate etching residue; 171. Sacrificial residue; 172. Oxide residue; 141. Patterned mask layer; 18. Transition gate oxide; 19. Shielding layer; 131. Second gate oxide layer. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0028] In this application, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show details of the local features.

[0029] Unless otherwise indicated, all technical and scientific terms used in this application have the same meaning as those generally understood by those skilled in the art in the technical field of this application. The terms used in this application are only for the purpose of describing the specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms of "a", "above" and "the" used in the embodiments of this application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0030] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0031] In the description of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of a simplified description of this application, and do not indicate that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation to this application.

[0032] In the description of this application, unless otherwise expressly defined, the terms "installed," "connected," "connect," "fixed," and "disposed" should be understood broadly. For example, "connection" can mean fixed, removable, or integrated; it can mean mechanical or electrical; it can mean direct or indirect connection through an intermediary; it can also mean internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0033] See also Figure 1 In related art, the preparation of a thicker gate oxide layer generally includes the following steps:

[0034] S1: providing a substrate; the substrate includes a substrate and shallow trench isolation; wherein the substrate includes a thick gate oxide region defined by the shallow trench isolation; an oxide layer is formed on the surface of the substrate; a mask layer is provided on the oxide layer and the surface of the shallow trench isolation.

[0035] S2: etching the mask layer, the oxide layer, and the substrate in sequence using a dry etching process to form an etched groove in the thick gate oxide region.

[0036] S3: forming a thick gate oxide layer in the groove.

[0037] The etched groove formed by the dry etching process in step S2 can be as follows: Figure 1 shown. Figure 1 In the figure, 101 is a thick gate oxide region, 102 is a shallow trench isolation, 103 and 104 are respectively a thin gate oxide layer and a patterned mask layer formed by the oxide layer and the mask layer remaining after etching, and 105 is an etching groove formed by step S2.

[0038] However, since the width of the shallow trench isolation 102 gradually decreases from its surface to its bottom, i.e., it has a structure that is wide at the top and narrow at the bottom, and the dry etching has anisotropic characteristics, residual substrate material 106 that has not been etched away may exist on the sidewalls of the shallow trench isolation 102. In this case, if a thick gate oxide layer is directly formed in the etched groove 105, this residual substrate material 106 may easily cause current tunneling, reducing the reliability of the thick gate oxide layer and even causing the subsequent semiconductor device to fail. If this residual substrate material 106 is etched or removed using an isotropic etching method, it will further damage the shallow trench isolation 102 and will also cause the surface of the thick gate oxide region 101 to have a large curvature, which will still affect the reliability of the prepared thick gate oxide layer.

[0039] Therefore, it is necessary to provide a method for preparing a semiconductor structure, which can reduce the substrate material residue during the preparation of a thicker gate oxide layer and improve reliability.

[0040] See also Figure 2-Figure 9 One embodiment of the present application provides a method for preparing a semiconductor structure. The method for preparing a semiconductor structure may include the following steps.

[0041] S110: providing a substrate.

[0042] In this embodiment, if Figure 3 As shown in , the base 10 may include a substrate 11 , a shallow trench isolation structure 12 , an oxide layer 13 located on a surface of the substrate 11 , and a mask layer 14 covering surfaces of the shallow trench isolation structure 12 and the oxide layer 13 .

[0043] In this embodiment, substrate 11 serves as the foundation of the semiconductor structure, providing not only mechanical support but also, through ion doping, affecting the semiconductor structure's electrical properties, such as operating voltage and carrier mobility. Specifically, substrate 11 may be made of silicon (Si) or, as required, other semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN).

[0044] In this embodiment, shallow trench isolation (STI) structure 12 is used to effectively electrically isolate different device regions by etching shallow trenches in substrate 11 and filling them with an insulating material, such as silicon dioxide. This reduces parasitic capacitance and leakage current, improving the performance and reliability of the semiconductor structure. For example, shallow trench isolation structure 12 can isolate devices with different operating voltages, such as power devices and logic devices.

[0045] In this embodiment, the oxide layer 13 can be used to form a thinner gate oxide layer located on the low-voltage device area during subsequent processing. Specifically, during the etching process, the portion of the oxide layer 13 located on other areas can be removed, and the remaining portion of the oxide layer 13 can serve as the thinner gate oxide layer. Specifically, the material of the oxide layer 13 can be silicon dioxide.

[0046] It should be noted that, in some embodiments, the base 10 may also include only the substrate 11 and the shallow trench isolation structure 12 , the mask layer 14 may be provided during the etching process, and the oxide layer 13 may also be manufactured separately later.

[0047] In this embodiment, the substrate 11 includes a first region 111 and a second region 112 defined by a shallow trench isolation structure 12. The first region 111 is a location region between adjacent shallow trench isolation structures 12. In this embodiment, the operating voltage requirements of the first region 111 and the second region 112 are different. Specifically, the first region 111 can be a high-voltage device region with a higher operating voltage requirement, such as a power device, and the gate oxide layer required to be made in this region is thicker. The second region 112 can be a low-voltage device region with a lower operating voltage requirement, and the gate oxide layer required to be made in this region is thinner. It should be noted that the voltage requirements referred to in this application are relative, that is, the first region 111 is higher than the second region 112, and is not necessarily the same as the voltage values corresponding to the high and low voltages in actual applications such as circuit design.

[0048] S120: etching the substrate to form a groove in the first region.

[0049] In this embodiment, if Figure 4 and Figure 5 As shown in FIG, a photolithography and etching process can be used, with the narrowest spacing between adjacent shallow trench isolation structures 12 as a position reference for etching. After removing a portion of the mask layer, oxide layer, and substrate located in the first region 111, a patterned mask layer 141, a second gate oxide layer 131, and a recess 15 are formed. The patterned mask layer 141 is located on the substrate 11 and defines the first region 111, and can be removed in a subsequent step. It can be understood that the recess 15 is located in the first region 111.

[0050] In this embodiment, reference Figure 5 , the plane where the bottom of the groove 15 is located (such as Figure 5 The sidewalls of the adjacent shallow trench isolation structure 12 (shown by the dashed line) facing each other can form a target region 16. The target region 16 can be used as the location region for the first gate oxide layer to be subsequently produced. Figure 5In the target region, there are mask layers, oxide layers, and substrate materials remaining on the sidewalls of the shallow trench isolation structure 12 facing the groove 15. Therefore, to clearly illustrate the position of the target region 16, please refer to Figure 7 Specifically, the target region 16 has a boundary formed by the plane where the bottom of the groove 15 is located and the sidewalls of the adjacent shallow trench isolation structures 12 facing each other, wherein the portion of the plane where the bottom of the groove 15 is located that is defined by the adjacent shallow trench isolation structures 12 can serve as the bottom boundary of the target region 16, and the portions of the sidewalls of the adjacent shallow trench isolation structures 12 facing each other that are located above the bottom boundary can serve as the two side boundaries of the target region 16.

[0051] In this embodiment, the target region 16 includes a substrate etch residue 17 formed during the etching process of the substrate 11. The substrate etch residue 17 is located on the sidewall of the shallow trench isolation structure 12 facing the recess 15. The substrate etch residue 17 has a side surface that contacts the shallow trench isolation structure 12, and its other side surface can serve as the sidewall of the recess 15. The bottom surface of the substrate etch residue 17 is located on the plane of the bottom of the recess 15, and the bottom surface of the substrate etch residue 17 and the bottom surface of the recess 15 can together constitute the bottom boundary of the target region 16.

[0052] It should be noted that in the related art, due to the presence of substrate etching residues 17 in the target area 16, there will be substrate material residues between the first gate oxide layer and the shallow trench isolation structure 12 formed subsequently, thereby affecting the reliability of the first gate oxide layer.

[0053] In this embodiment, the target region 16 also has some oxide residues and some mask layer residues formed during the etching process of the substrate 11 , wherein the some mask layer residues can be removed together when the mask is subsequently removed.

[0054] In this embodiment, since the oxide layer located in the first region 111 is removed, the remaining oxide layer located in the second region 112 can serve as the second gate oxide layer 131 , that is, as a thinner gate oxide layer in the low-voltage device region.

[0055] S130: transforming the material of the etching residue of the substrate to form a first gate oxide layer in the target area.

[0056] In this embodiment, the material properties of the substrate etch residue 17 can be changed or reacted to generate new compounds through specific processes, such as plasma bombardment and wet chemical treatment, to achieve the transformation of the material of the substrate etch residue 17. Specifically, the material of the substrate etch residue 17 can be transformed into a non-conductive material to prevent the subsequent first gate oxide layer from being prone to current tunneling and affecting reliability. In some embodiments, the material of the substrate etch residue 17 can also be transformed into an easily removable material, which is removed separately before forming the first gate oxide layer, and then the first gate oxide layer is formed in the target area 16, which can also solve the problem of residual substrate material in the target area 16.

[0057] In some embodiments, the step of converting the material of the substrate etching residue to form a first gate oxide layer in the target area may include: converting the material of the substrate etching residue into the same material as the patterned mask layer; removing the patterned mask layer; wherein the substrate etching residue in the target area is also removed; and forming the first gate oxide layer in the target area.

[0058] Specifically, such as Figure 6 As shown, since the patterned mask layer 141 formed during the etching process needs to be removed after the groove 15 is formed, the material of the substrate etching residue 17 is converted into the same material as the patterned mask layer 141. The substrate etching residue 17 can be removed together with the step of removing the patterned mask layer 141, and no additional cleaning step is required. This not only simplifies the process steps, but also can reduce damage to the surface of the shallow trench isolation structure 12 and the substrate 11 while removing the substrate etching residue 17 based on the high selectivity of the material of the patterned mask layer 141 relative to the material of the shallow trench isolation structure 12 and the substrate 11.

[0059] In some embodiments, the substrate may be made of silicon; the patterned mask layer may be made of silicon nitride; and the step of converting the material of the substrate etching residue into the same material as the patterned mask layer may include: performing a decoupled plasma nitridation (DPN) deposition process on the substrate etching residue made of silicon to form a substrate etching residue made of silicon nitride. Figure 6 In the process of decoupling plasma nitridation process for the substrate etching residue 17, N2 can be used as an ion source, wherein the deposition rate of silicon nitride on the substrate etching residue 17 falls within 5 um / cm 2 ~20um / cm 2 Within the range of , when the material of the substrate etching residue 17 is completely converted into silicon nitride, the plasma bombardment is stopped to form a sacrificial residue 171 made of silicon nitride.

[0060] Of course, if Figure 6 As shown in FIG, during the decoupled plasma nitridation process, a certain thickness of silicon nitride is formed at the bottom of the groove 15 and can be removed when the patterned mask layer 141 is removed.

[0061] In some embodiments, when the material of the first gate oxide layer to be prepared is different from the material of the second gate oxide layer 131, it is also necessary to remove part of the oxide layer residue in the target area 16, thereby forming a gate oxide layer 131. Figure 7 Of course, if the material of the first gate oxide layer to be prepared is the same as that of the second gate oxide layer 131, such as silicon dioxide, it is not necessary to remove the portion of the oxide layer residue in the target area 16, and the portion can be directly used as part of the second gate oxide layer to be subsequently prepared.

[0062] It can be understood that at this time the target area 16 is fully opened, and then a first gate oxide layer can be formed in the target area 16, wherein the height of the surface of the first gate oxide layer can be flush with the height of the surface of the second gate oxide layer 131, and can be higher than the height of the surface of the second gate oxide layer 131.

[0063] In some embodiments, the step of converting the material of the substrate etching residue to form the first gate oxide layer in the target area may include converting the material of the substrate etching residue into the same material as the first gate oxide layer.

[0064] In some embodiments, the material of the substrate etching residue 17 can be directly converted into the same material as the first gate oxide layer. When the first gate oxide layer is subsequently manufactured, the substrate etching residue 17 after the conversion can be directly used as part of the first gate oxide layer, which can also reduce the residual substrate material.

[0065] In some embodiments, the material of the substrate may be silicon; the material of the first gate oxide layer may be silicon dioxide; the step of converting the material of the substrate etching residue into the same material as the first gate oxide layer includes: using oxygen to oxidize the substrate etching residue of silicon material under low temperature and high pressure conditions to form a substrate etching residue of silicon dioxide.

[0066] In some embodiments, please refer to Figure 5 and Figure 8 , the silicon substrate etching residue 17 can be rapidly oxidized by passing oxygen under low temperature and high pressure conditions to convert it into silicon dioxide material, forming an oxidation residue 172. Similarly, part of the silicon dioxide will also grow at the bottom of the groove 15 to form a transition gate oxide portion 18. Figure 8 As shown in Figure 8The portion of silicon dioxide between the two dotted lines is the transition gate oxide portion 18 , and the portions of silicon dioxide on both sides are the oxidation residue portions 172 .

[0067] In some embodiments, during the oxidation of the silicon substrate etch residue 17 using oxygen under low temperature and high pressure conditions, both the substrate etch residue 17 and the bottom of the recess 15 are subjected to oxygen pressure. The oxygen pressure acting on the substrate etch residue 17 is greater than the oxygen pressure acting on the bottom of the recess 15. This accelerates the silicon oxidation rate of the substrate etch residue 17 and reduces the consumption of silicon material at the bottom of the recess 15. As a result, after the substrate etch residue 17 on the sidewalls of the shallow trench isolation structure 12 is completely oxidized, less silicon material is oxidized at the bottom of the recess 15, thereby reducing the thickness of the transition gate oxide 18 and facilitating subsequent processing.

[0068] In some embodiments, after converting the material of the substrate etching residue into the same material as the first gate oxide layer, the step of converting the material of the substrate etching residue to form the first gate oxide layer in the target area may also include: performing an ion implantation process on the substrate using the transition gate oxide portion and the substrate etching residue as a masking layer; removing at least a portion of the masking layer consumed in the ion implantation process; and using the remaining masking layer as part of the first gate oxide layer.

[0069] In some embodiments, as Figure 9 As shown, the patterned mask layer 141 can be removed first, and then ion implantation can be performed on the substrate 11 to form a well region. During the ion implantation, the oxide residue 172 and the transition gate oxide portion 18 can just serve as a masking layer 19 for the ion implantation. After the ion implantation is completed, at least part of the masking layer 19 consumed in the ion implantation process can be removed, and the remaining masking layer 19 is already located in the target area 16, that is, it can serve as part of the first gate oxide layer. Then, the remaining first gate oxide layer is formed in the target area 16 to complete the production of the first gate oxide layer. In this way, without adding additional process steps, the substrate material residue in the target area 16 can be reduced on the basis of the existing process steps, and the uniformity and reliability of the first gate oxide layer in the subsequent target area 16 can be improved. Without the need for additional cleaning steps, the damage to the shallow trench isolation structure 12 and the substrate 11 can also be effectively reduced.

[0070] It should be noted that a relatively thin masking layer is typically required during the ion implantation process. Therefore, when the substrate is oxidized and the etch residue 17 is etched, the transition gate oxide portion 18 formed by controlling the oxygen pressure is also relatively thin, precisely matching the required thickness of the masking layer. This eliminates the need for a separate masking layer, thus simplifying the process.

[0071] In some embodiments, the thickness of the transition gate oxide 18 does not exceed 100 Å.

[0072] In some embodiments, during the step of oxidizing the silicon substrate etching residue using oxygen to form the silicon dioxide substrate etching residue, the ratio of the oxygen pressure acting on the substrate etching residue to the oxygen pressure acting on the bottom of the groove can be within a range of 2 to 10. In this way, the thickness of the formed transition gate oxide portion 18 is more consistent with the thickness requirement for the ion implantation mask layer.

[0073] In this embodiment, the first gate oxide layer formed in the first region 111 and the second gate oxide layer 131 in the second region 112 may together constitute a double gate oxide layer, wherein the thickness of the second gate oxide layer 131 is smaller than that of the first gate oxide layer.

[0074] In this embodiment, an unexpected effect is that in the process of preparing the thick gate oxide layer, the substrate etching residue 17 located in the target area 16 is formed during the etching process of the substrate of the first area 111. By converting the material of the substrate etching residue 17 and then producing the first gate oxide layer, the substrate material residue in the target area 16 after the first gate oxide layer is formed can be reduced, thereby improving the reliability of the first gate oxide layer.

[0075] An embodiment of the present application provides a semiconductor structure, which is prepared using the method for preparing a semiconductor structure as described in any of the aforementioned embodiments.

[0076] It should be understood that the specific examples in this article are only intended to help those skilled in the art better understand the embodiments of the present application, and are not intended to limit the scope of the present invention.

[0077] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0078] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0079] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art in the technical field of the present application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms of "a", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0080] The above description is merely a specific embodiment of the present application, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; The base includes a substrate and a shallow trench isolation structure; wherein the substrate includes a first area defined by the shallow trench isolation structure; and a patterned mask layer defining the first area is further formed on the substrate; Etching the substrate to form a groove located in the first region; wherein a plane where the bottom of the groove is located and a sidewall facing each other of an adjacent shallow trench isolation structure form a target region; and the target region has a substrate etching residue formed during the substrate etching process; The material of the substrate etching residue is converted to obtain a first gate oxide layer in the target area, including: converting the material of the substrate etching residue into the same material as the patterned mask layer; removing the patterned mask layer; wherein the substrate etching residue in the target area is also removed; and forming a first gate oxide layer in the target area.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The material of the substrate is silicon; the material of the patterned mask layer is silicon nitride; and the step of converting the material of the etching residue of the substrate into the same material as the patterned mask layer comprises: A decoupled plasma nitridation deposition process is performed on a substrate etching residue portion made of silicon material to form a substrate etching residue portion made of silicon nitride material.

3. The method for preparing a semiconductor structure according to claim 2, wherein: In the decoupled plasma nitridation deposition process, N2 is used as the ion source and the deposition rate of silicon nitride is within 5 um / cm 2 ~20um / cm 2 within the range.

4. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; The base includes a substrate and a shallow trench isolation structure; wherein the substrate includes a first area defined by the shallow trench isolation structure; the substrate is made of silicon; Etching the substrate to form a groove located in the first region; wherein a plane where the bottom of the groove is located and a sidewall facing each other of an adjacent shallow trench isolation structure form a target region; and the target region has a substrate etching residue formed during the substrate etching process; The material of the substrate etching residue is converted to form a first gate oxide layer in the target area, including: under low temperature and high pressure conditions, using oxygen to oxidize the substrate etching residue made of silicon material to form a substrate etching residue made of silicon dioxide, so as to convert the substrate etching residue into the same material as the first gate oxide layer; wherein the substrate etching residue and the bottom of the groove are both subjected to oxygen pressure; the oxygen pressure acting on the substrate etching residue is greater than the oxygen pressure acting on the bottom of the groove.

5. The method for preparing a semiconductor structure according to claim 4, wherein: A transition gate oxide portion made of silicon dioxide is formed at the bottom of the groove; after the material of the substrate etching residue is converted into the same material as the first gate oxide layer, the material of the substrate etching residue is converted to form the first gate oxide layer in the target area, further comprising: Performing an ion implantation process on the substrate using the transition gate oxide portion and the substrate etching residue of the silicon dioxide material as a masking layer; At least a portion of the masking layer consumed in the ion implantation process is removed; the remaining masking layer serves as a portion of the first gate oxide layer.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that: The substrate also includes a second area defined by the shallow trench isolation structure; the base also includes an oxide layer located on the surface of the substrate; accordingly, in the step of etching the substrate to form a groove located in the first area, the oxide layer located in the first area is removed; the remaining oxide layer located in the second area serves as a second gate oxide layer; wherein the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

7. A semiconductor structure, characterized in that The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 6.

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