Semiconductor device

Abstract

The purpose of the present disclosure is to provide a semiconductor device in which short-circuit tolerance is improved and delay of a gate signal is reduced. The first and second surface electrodes are disposed so as to sandwich the finger wiring (3) extending in the first direction. The gate electrode (7) extends in the second direction. The third surface electrode connects the first surface electrode and the second surface electrode between the tip of the finger wiring (3) and the gate wiring (5). The finger wiring extension section (3A) extends in the direction of the gate wiring (5) from the tip of the finger wiring (3) while avoiding the third surface electrode. A gate electrode (7) that traverses the third surface electrode in plan view is electrically connected to the finger wiring extension (3A).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] In a vertical semiconductor device in which current flows between the front surface and the back surface of a semiconductor substrate, there is provided a linear electrode called a gate liner or a finger electrode for transmitting a gate signal. Such a linear electrode is arranged to divide an emitter electrode formed on the front surface of the semiconductor substrate (for example, refer to Patent Document 1).

[0003] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2006-210519

[0004] The gate liner as shown in Patent Document 1 improves the delay of the gate signal. On the other hand, since the emitter electrode is divided by the gate liner, the current distribution becomes an unbalanced state, and the short-circuit withstand is reduced. Summary of the Invention

[0005] In order to solve the above problems, an object of the present disclosure is to provide a semiconductor device with improved short-circuit withstand and reduced delay of a gate signal.

[0006] The semiconductor device according to the present disclosure includes a finger wiring, a surface electrode, a gate wiring, and a plurality of gate electrodes. The finger wiring extends along a first direction in the plane of the semiconductor substrate. The surface electrode includes a first surface electrode and a second surface electrode arranged so as to sandwich the finger wiring. The gate wiring has a ring shape in a plan view and is arranged so as to surround the surface electrode. The plurality of gate electrodes extend along a second direction in the plane of the semiconductor substrate. The surface electrode includes a third surface electrode. The third surface electrode is provided on an extension line of the finger wiring. The third surface electrode connects the first surface electrode and the second surface electrode between the end of the finger wiring and the gate wiring. The finger wiring includes a finger wiring extension portion. The finger wiring extension portion extends from the end of the finger wiring toward the gate wiring while avoiding the third surface electrode. A gate electrode that crosses the third surface electrode in a plan view among the plurality of gate electrodes is electrically connected to the finger wiring extension portion.

[0007] According to the present disclosure, it is possible to provide a semiconductor device with improved short-circuit withstand and reduced delay of a gate signal.

[0008] The object, features, aspects, and advantages of the present disclosure will become clearer through the following detailed description and drawings. Brief Description of the Drawings

[0009] Figure 1 It is a plan view showing the structure of the semiconductor device in Embodiment 1.

[0010] Figure 2 It is an enlarged plan view showing the structure of the semiconductor device.

[0011] Figure 3 It is an enlarged top view showing the structure of the semiconductor device in Modification 1 of Embodiment 1.

[0012] Figure 4 It is an enlarged top view showing the structure of the semiconductor device in Modification 2 of Embodiment 1.

[0013] Figure 5 It is an enlarged top view showing the structure of the semiconductor device in Modification 3 of Embodiment 1.

[0014] Figure 6 It is a top view showing the structure of the semiconductor device in Embodiment 2.

[0015] Figure 7 It is a cross-sectional view showing the structure of the semiconductor device.

[0016] Figure 8 It is a top view showing the structure of the semiconductor device in Embodiment 3.

[0017] Figure 9 It is a top view showing the structure of the semiconductor device in the modification of Embodiment 3.

[0018] Figure 10 It is a cross-sectional view showing the structure of the semiconductor device.

[0019] Figure 11 It is a top view showing the structure of the semiconductor device in Embodiment 4.

[0020] Figure 12 It is a cross-sectional view showing the structure of the semiconductor device.

[0021] Figure 13 It is a top view showing the structure of the semiconductor device in Embodiment 5.

[0022] Figure 14 It is a diagram showing the schematic three-dimensional shape of the electrode (AlSi) in the emitter connection region.

[0023] Figure 15 It is a top view showing the structure of the semiconductor device in Embodiment 6.

[0024] Figure 16 It is a diagram showing the structure of the semiconductor device in Embodiment 7.

[0025] Figure 17 It is a diagram showing the structure of the semiconductor device in Embodiment 7.

[0026] Figure 18 It is a diagram showing the structure of the semiconductor device in Embodiment 8.

[0027] Description of Reference Numerals

[0028] 1... Gate pad; 2... Emitter electrode; 2A... First emitter electrode; 2B... Second emitter electrode; 2C... Third emitter electrode; 2D... Fourth emitter electrode; 3... Finger-like wiring; 3A... Extension of finger-like wiring; 5... Gate wiring; 5A - 5D... Extensions of gate wiring; 7... Gate electrode; 7A - 7E... Gate electrodes; 8A - 8B... Gate connection wiring; 10... Semiconductor substrate; 11... Oxide film; 12... Trench; 13... Island-type wiring; 14... Lead; 15... Metal plate; 51D - 52D... Branch wiring; 101 - 108... Semiconductor devices. Detailed Embodiments

[0029] <Embodiment 1>

[0030] Figure 1 is a top view showing the structure of the semiconductor device 101 in Embodiment 1. Figure 2 is an enlarged top view showing the structure of the semiconductor device 101. Figure 2 Shows Figure 1 the structure in the area P shown. Among them, Figure 1 and Figure 2 Since it is illustrative, the two are not exactly the same. Figure 1 and Figure 2 shows the upper surface of the semiconductor device 101, which is a vertical semiconductor device that controls the current flowing between the upper and lower surfaces of the semiconductor substrate 10.

[0031] The semiconductor device 101 includes: an active portion (not shown), a gate pad 1, an emitter electrode 2, finger-like wiring 3, an extension 3A of the finger-like wiring, gate wiring 5, an extension 5A of the gate wiring, and a plurality of gate electrodes 7.

[0032] The active portion is provided on the semiconductor substrate 10 (refer to Figure 7) is disposed at a position closer to the inside than the outer peripheral portion of the semiconductor substrate 10. The active portion includes semiconductor elements (not shown). The semiconductor elements are formed of semiconductors such as Si, for example. The semiconductor is preferably a so-called wide bandgap semiconductor such as SiC, GaN, Ga2O3, GeO2, diamond, etc. The semiconductor elements are power semiconductor elements, control ICs (Integrated Circuit) for controlling the power semiconductor elements, etc. The semiconductor elements are, for example, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), Schottky barrier diodes, etc. Alternatively, the semiconductor element may be an RC-IGBT (Reverse-Conducting IGBT) in which an IGBT and a freewheeling diode are formed in one semiconductor substrate 10. The semiconductor element in Embodiment 1 is an IGBT.

[0033] The gate pad 1 is disposed on the upper surface of the semiconductor substrate 10. The gate pad 1 functions as a terminal for inputting a gate signal from the outside of the semiconductor device 101.

[0034] The emitter electrode 2 is a surface electrode disposed on the active portion. The emitter electrode 2 includes: a first emitter electrode 2A, a second emitter electrode 2B, and a third emitter electrode 2C. The first emitter electrode 2A corresponds to the first surface electrode. The second emitter electrode 2B corresponds to the second surface electrode. The third emitter electrode 2C corresponds to the third surface electrode.

[0035] The first emitter electrode 2A and the second emitter electrode 2B are disposed so as to sandwich the finger-like wiring 3. In other words, the first emitter electrode 2A is disposed on one side of the finger-like wiring 3, and the second emitter electrode 2B is disposed on the other side of the finger-like wiring 3. As Figure 2 shown by the thick line, the third emitter electrode 2C is disposed on the extension line of the finger-like wiring 3. The third emitter electrode 2C is disposed between the end of the finger-like wiring 3 and the gate wiring 5 and connects the first emitter electrode 2A and the second emitter electrode 2B. The first emitter electrode 2A, the second emitter electrode 2B, and the third emitter electrode 2C are one component, and in the active portion, the portions other than the finger-like wiring 3, the finger-like wiring extension portion 3A, and the gate wiring extension portion 5A are continuous without being disconnected. In the drawings, although the emitter electrode 2 (2A, 2B, 2C) appears to be striped and disconnected due to the multiple horizontal lines depicting the plurality of gate electrodes 7, it is actually continuously formed on the upper layer of the gate electrode 7.

[0036] The emitter electrode 2 is electrically insulated from the gate pad 1, the finger-shaped wiring 3, the finger-shaped wiring extension 3A, the gate wiring 5, the gate wiring extension 5A, and the gate electrode 7. That is, the emitter electrode 2 is electrically insulated from the electrodes and wirings that transmit gate signals. An oxide film or the like is used as the insulating material. In Figure 1 and Figure 2 In the top view for convenience of illustration, the emitter electrode 2 is depicted as being in contact with the finger-shaped wiring 3, the finger-shaped wiring extension 3A, the gate wiring 5, and the gate wiring extension 5A, but actually there is no contact.

[0037] The finger-shaped wiring 3 extends along a first direction in the plane of the semiconductor substrate 10 and is arranged to run through the active portion. The first direction in Embodiment 1 corresponds to the Figure 1 longitudinal direction in

[0038] The finger-shaped wiring extension 3A extends from the end of the finger-shaped wiring 3 toward the gate wiring 5 while avoiding the third emitter electrode 2C. In Embodiment 1, the finger-shaped wiring extension 3A extends from the end of the finger-shaped wiring 3 in a second direction and then further extends in the first direction. The second direction is orthogonal to the first direction. The second direction in Embodiment 2 corresponds to the Figure 1 and Figure 2 lateral direction in

[0039] The gate wiring 5 has a ring shape in a top view. The gate wiring 5 is arranged to surround the emitter electrode 2 provided in the active portion. The gate wiring 5 is electrically connected to the gate pad 1. The gate wiring 5 is formed of a metal such as aluminum.

[0040] The gate wiring extension 5A branches off from the gate wiring 5. The gate wiring extension 5A extends toward the inside of the ring of the gate wiring 5 while avoiding the third emitter electrode 2C. In Embodiment 1, the gate wiring extension 5A branches off from the gate wiring 5 and extends in the first direction.

[0041] A plurality of gate electrodes 7 extend along a second direction in the plane of the semiconductor substrate 10 and are provided under the emitter electrode 2 with an insulating layer therebetween. Both ends of the gate electrode 7 are electrically connected to the gate wiring 5, for example. The gate electrode 7 is formed of polysilicon, for example.

[0042] Among the plurality of gate electrodes 7, the gate electrode 7 that crosses the third emitter electrode 2C in a top view is electrically connected to one of the finger-shaped wiring extension 3A and the gate wiring extension 5A in the region inside the ring of the gate wiring 5. As Figure 2As shown, in Embodiment 1, a part of the gate electrode 7A is in contact with the gate wiring extension 5A. A part of the gate electrodes 7B and 7C is in contact with the finger-like wiring extension 3A. A part of the gate electrode 7D is in contact with the finger-like wiring extension 3A and the finger-like wiring 3. A part of the gate electrode 7E is in contact with the finger-like wiring 3. In this way, the gate electrode 7 is in contact with any one of the finger-like wiring 3, the finger-like wiring extension 3A, and the gate wiring extension 5A. In other words, the gate electrode 7 is electrically connected to the gate pad 1 via these wirings.

[0043] In such a structure, the third emitter electrode 2C connects the first emitter electrode 2A and the second emitter electrode 2B to each other, so the potential in the emitter electrode 2 is stable.

[0044] In the case where the gate electrode 7 is formed of polysilicon and the finger-like wiring 3 and the gate wiring 5 are formed of metal, the resistance value per unit length of the gate electrode 7 is larger than that of the finger-like wiring 3 and the gate wiring 5. Therefore, compared with the gate signal transmitted in the finger-like wiring 3 or the gate wiring 5, the gate signal transmitted in the gate electrode 7 is delayed. However, in the semiconductor device 101 of Embodiment 1, the gate electrode 7 is electrically connected to any one of the finger-like wiring 3, the finger-like wiring extension 3A, and the gate wiring extension 5A in the region inside the ring of the gate wiring 5. Therefore, the delay of the gate signal is reduced.

[0045] To summarize the above, the semiconductor device 101 in Embodiment 1 includes the finger-like wiring 3, the emitter electrode 2, the gate wiring 5, and a plurality of gate electrodes 7. The finger-like wiring 3 extends in a first direction in the plane of the semiconductor substrate 10. The emitter electrode 2 includes a first emitter electrode 2A and a second emitter electrode 2B arranged to sandwich the finger-like wiring 3. The gate wiring 5 has a ring shape in a top view and is provided so as to surround the emitter electrode 2. The plurality of gate electrodes 7 extend in a second direction in the plane of the semiconductor substrate 10. The emitter electrode 2 includes a third emitter electrode 2C. The third emitter electrode 2C is provided on the extension line of the finger-like wiring 3. The third emitter electrode 2C connects the first emitter electrode 2A and the second emitter electrode 2B between the end of the finger-like wiring 3 and the gate wiring 5. The finger-like wiring 3 includes a finger-like wiring extension 3A. The finger-like wiring extension 3A extends from the end of the finger-like wiring 3 toward the gate wiring 5 while avoiding the third emitter electrode 2C. The gate electrode 7 that crosses the third emitter electrode 2C in a top view among the plurality of gate electrodes 7 is electrically connected to the finger-like wiring extension 3A. The emitter electrode 2 is a surface electrode, and its name can also be changed according to the type of semiconductor element formed on the semiconductor substrate 10.

[0046] In such a semiconductor device 101, although the finger-shaped wiring 3 is provided, the third emitter electrode 2C connects the first emitter electrode 2A and the second emitter electrode 2B. Therefore, the potential in the emitter electrode 2 is stabilized and the short-circuit tolerance is improved. In addition, the gate electrode 7 is electrically connected to the finger-shaped wiring extension 3A. Therefore, the delay of the gate signal is reduced.

[0047] (Modification 1 of Embodiment 1)

[0048] Figure 3 It is an enlarged plan view showing the structure of the semiconductor device 101A in Modification 1 of Embodiment 1. The semiconductor device 101A includes a finger-shaped wiring extension 3A and a gate wiring extension 5B. Similar to Embodiment 1, after the finger-shaped wiring extension 3A extends from the end of the finger-shaped wiring 3 in the second direction, it further extends in the first direction. The gate wiring extension 5B branches from the gate wiring 5 and extends in the first direction, then extends in the second direction, and further extends in the first direction.

[0049] The gate electrodes 7A to 7D that cross the third emitter electrode 2C are electrically connected to one of the finger-shaped wiring extension 3A and the gate wiring extension 5B in the region inside the ring of the gate wiring 5. Specifically, a part of the gate electrodes 7A and 7B is in contact with the gate wiring extension 5B. A part of the gate electrodes 7C and 7D is in contact with the finger-shaped wiring extension 3A.

[0050] In addition, a part of the gate electrode 7E that does not cross the third emitter electrode 2C is in contact with the finger-shaped wiring 3. In this way, the gate electrode 7 is in contact with any one of the finger-shaped wiring 3, the finger-shaped wiring extension 3A, and the gate wiring extension 5B. In the semiconductor device 101A, the same effects as those in Embodiment 1 can also be obtained.

[0051] (Modification 2 of Embodiment 1)

[0052] Figure 4 It is an enlarged plan view showing the structure of the semiconductor device 101B in Modification 2 of Embodiment 1. The semiconductor device 101B includes a gate wiring extension 5C. The finger-shaped wiring extension 3A is not provided. The gate wiring extension 5C branches from the gate wiring 5 and extends in the first direction, then branches into two in the second direction. The ends of the gate wiring extension 5C further extend in the first direction.

[0053] The gate electrodes 7A to 7D that cross the third emitter electrode 2C are electrically connected to the gate wiring extension 5C in the region inside the ring of the gate wiring 5. Specifically, a part of the gate electrodes 7A to 7D is in contact with the gate wiring extension 5C.

[0054] In addition, a part of the gate electrode 7E that does not cross the third emitter electrode 2C is in contact with the finger-shaped wiring 3. In this way, the gate electrode 7 is in contact with either the finger-shaped wiring 3 or the gate wiring extension part 5C. In the semiconductor device 101B, the same effect as in the first embodiment can also be obtained.

[0055] (Modification Example 3 of the First Embodiment)

[0056] Figure 5 It is an enlarged plan view showing the structure of the semiconductor device 101C in Modification Example 3 of the first embodiment. The semiconductor device 101C includes a gate wiring extension part 5D. The finger-shaped wiring extension part 3A is not provided. The gate wiring extension part 5D includes a plurality of branch wirings 51D and 52D. The plurality of branch wirings 51D and 52D branch from a plurality of branch points in the gate wiring 5 and extend in the first direction.

[0057] The gate electrodes 7A and 7B that cross the third emitter electrode 2C are electrically connected to the gate wiring extension part 5D in the region inside the ring of the gate wiring 5. Specifically, a part of the gate electrodes 7A and 7B is in contact with the gate wiring extension part 5D.

[0058] In addition, a part of the gate electrodes 7C to 7E that do not cross the third emitter electrode 2C is in contact with the finger-shaped wiring 3. In this way, the gate electrode 7 is in contact with either the finger-shaped wiring 3 or the gate wiring extension part 5D. In the semiconductor device 101C, the same effect as in the first embodiment can also be obtained.

[0059] <Embodiment 2>

[0060] Figure 6 It is a plan view showing the structure of the semiconductor device 102 in the second embodiment. Figure 6 The structure around the third emitter electrode 2C is shown.

[0061] After the finger-shaped wiring extension part 3A extends from the end of the finger-shaped wiring 3 in the second direction and then further extends in the first direction. The gate wiring extension part 5A branches from the gate wiring 5 and extends in the first direction.

[0062] The gate electrodes 7A to 7D that cross the third emitter electrode 2C are electrically connected to at least one of the finger-shaped wiring extension part 3A and the gate wiring extension part 5A in the region inside the ring of the gate wiring 5. Specifically, a part of the gate electrode 7A is in contact with the gate wiring extension part 5A. A part of the gate electrodes 7B and 7C is in contact with both the gate wiring extension part 5A and the finger-shaped wiring extension part 3A. A part of the gate electrode 7D is in contact with the finger-shaped wiring extension part 3A.

[0063] Figure 7It is a cross-sectional view showing the structure of the semiconductor device 102. Figure 7 It shows along Figure 6 the structure of the cross-section taken along A-A' shown. In Figure 6 the top view, the emitter electrode 2 is depicted as being in contact with the finger-shaped wiring extension 3A and the gate wiring extension 5A, but actually as Figure 7 shown, there is no contact. Also, an oxide film 11 is formed under the wiring, and the emitter electrode 2 is insulated from the finger-shaped wiring extension 3A and the gate wiring extension 5A. The gate electrode 7C is in contact with the gate wiring extension 5A and the finger-shaped wiring extension 3A respectively. In such a structure, the delay of the gate signal is further reduced.

[0064] <Embodiment 3>

[0065] Figure 8 It is a top view showing the structure of the semiconductor device 103 in Embodiment 3. Figure 8 It shows the structure around the third emitter electrode 2C. The finger-shaped wiring extension 3A and the gate wiring extension 5A are not provided.

[0066] Among the plurality of gate electrodes 7, the gate electrodes 7A and 7B disposed below the third emitter electrode 2C in a top view include the gate connection wiring 8A. The gate connection wiring 8A bends and extends in the first direction below the third emitter electrode 2C. The gate connection wiring 8A is electrically connected to the gate wiring 5 in the region outside the third emitter electrode 2C.

[0067] The gate electrodes 7A and 7B disposed below the third emitter electrode 2C are electrically connected to the gate wiring 5 via the gate connection wiring 8A. Therefore, the delay of the gate signal is reduced. Also, since the finger-shaped wiring extension 3A and the gate wiring extension 5A are not provided, a reduction in the effective region that operates as an IGBT in the active portion is suppressed.

[0068] (Modification of Embodiment 3)

[0069] Figure 9 It is a top view showing the structure of the semiconductor device 103A in the modification of Embodiment 3. Figure 10 It is a cross-sectional view showing the structure of the semiconductor device 103A. Figure 10 It shows along Figure 9 the cross-section taken along B-B' shown.

[0070] Among the plurality of gate electrodes 7, the gate electrodes 7A and 7B disposed below the third emitter electrode 2C in a top view respectively include gate connection wirings 8A and 8B. The gate connection wiring 8A bends and extends in the first direction below the third emitter electrode 2C. The gate connection wiring 8A is electrically connected to the gate wiring 5 in a region outside the third emitter electrode 2C. The gate connection wiring 8B bends and extends in the first direction below the third emitter electrode 2C, but bends in a direction opposite to that of the gate connection wiring 8A. The gate connection wiring 8B is electrically connected to the finger-like wiring 3 in a region outside the third emitter electrode 2C.

[0071] The gate electrode 7A is electrically connected to the gate wiring 5 via the gate connection wiring 8A. The gate electrode 7B is electrically connected to the finger-like wiring 3 via the gate connection wiring 8B. Therefore, the delay of the gate signal is reduced. In addition, since the finger-like wiring extension 3A and the gate wiring extension 5A are not provided, a reduction in the effective region that operates as an IGBT in the active portion is suppressed.

[0072] <Embodiment 4>

[0073] Figure 11 It is a top view showing the structure of the semiconductor device 104 in Embodiment 4. Figure 12 It is a cross-sectional view showing the structure of the semiconductor device 104. Figure 12 Shows along Figure 11 The cross-section of C-C' shown.

[0074] The semiconductor device 104 includes a plurality of trenches 12. The plurality of trenches 12 are provided in the semiconductor substrate 10 and extend in the second direction. The plurality of gate electrodes 7 are respectively formed in the plurality of trenches 12. Since the gate electrodes 7 are buried in the trenches 12, the JFET (Junction Field Effect Transistor) resistance is reduced.

[0075] <Embodiment 5>

[0076] Figure 13 It is a top view showing the structure of the semiconductor device 105 in Embodiment 5. Figure 13 Shows the structure around the third emitter electrode 2C. Figure 14 It is a diagram showing the schematic three-dimensional shape of the electrode (AlSi) in the emitter connection region.

[0077] The second emitter electrode 2B includes a fourth emitter electrode 2D. The fourth emitter electrode 2D corresponds to the fourth surface electrode. The fourth emitter electrode 2D is disposed between the end of the finger-like wiring extension 3A and the gate wiring 5 in the first direction.

[0078] Let the length of the third emitter electrode 2C in the first direction and the width of the fourth emitter electrode 2D in the second direction be x. Let the width of the third emitter electrode 2C in the second direction and the length of the fourth emitter electrode 2D in the first direction be y. Let the thickness of the chip be z. Let the resistivity be ρ.

[0079] When the pitch of the gate electrodes 7 is 2.4 μm, the third emitter electrode 2C and the fourth emitter electrode 2D preferably satisfy the following formulas (1) and (2).

[0080]

[0081]

[0082] When the pitch of the gate electrodes 7 is 4.0 μm, the third emitter electrode 2C and the fourth emitter electrode 2D preferably satisfy the following formulas (3) and (4).

[0083]

[0084]

[0085] Formulas (1) and (3) are formulas regarding the inductance in the emitter electrode region. Formulas (2) and (4) are formulas regarding the resistance. When both the inductance and the resistance are low, the short-circuit tolerance is improved.

[0086] <Embodiment 6>

[0087] Figure 15 It is a top view showing the structure of the semiconductor device 106 in Embodiment 6. Figure 15 The structure around the third emitter electrode 2C is shown. The semiconductor device 106 includes the island-type wiring 13.

[0088] The island-type wiring 13 is provided in a region where one of the first emitter electrode 2A and the second emitter electrode 2B is arranged. In Figure 15 The island-type wiring 13 is provided in the region where the second emitter electrode 2B is arranged. The island-type wiring 13 is electrically insulated from the first emitter electrode 2A and the second emitter electrode 2B. On the other hand, the island-type wiring 13 is electrically connected to the gate electrode 7C that crosses the third emitter electrode 2C among the plurality of gate electrodes 7, and the gate electrodes 7B and 7D other than the gate electrode 7C that crosses the third emitter electrode 2C.

[0089] A part of the gate electrode 7B is in contact with the gate wiring extension 5A and the island wiring 13. A part of the gate electrode 7C is in contact with the island wiring 13. A part of the gate electrode 7D is in contact with the finger wiring 3 and the island wiring 13. That is, the gate electrode 7C that crosses the third emitter electrode 2C is electrically connected to the finger wiring 3 and the gate wiring extension 5A via the island wiring 13. Even with such a structure, the same effect as in the first embodiment can be obtained.

[0090] Even if the gate electrode 7C is electrically connected to either the finger wiring 3 or the gate wiring extension 5A via the island wiring 13, the same effect as described above can be obtained. In addition, although not shown in the figure, in the case where the finger wiring extension 3A is provided, the island wiring 13 can also be electrically connected to the finger wiring extension 3A. In this case, the gate electrode 7C that crosses the third emitter electrode 2C is electrically connected to the finger wiring extension 3A via the island wiring 13. That is, the gate electrode 7C may be electrically connected to any one of the finger wiring 3, the finger wiring extension 3A, and the gate wiring extension 5A via the island wiring 13.

[0091] <Embodiment 7>

[0092] Figure 16 It is a diagram showing the structure of the semiconductor device 107A in the seventh embodiment. As Figure 16 shown, the semiconductor device 107A includes a lead 14 that connects the first emitter electrode 2A and the second emitter electrode 2B. The potentials of the first emitter electrode 2A and the second emitter electrode 2B are stabilized, and the short-circuit tolerance is further improved.

[0093] Figure 17 It is a diagram showing the structure of the semiconductor device 107B in the seventh embodiment. As Figure 17 shown, the semiconductor device 107B includes a metal plate 15 that connects the first emitter electrode 2A and the second emitter electrode 2B. The metal plate 15 is directly bonded to the first emitter electrode 2A and the second emitter electrode 2B by, for example, DLB (direct lead bonding). The potentials of the first emitter electrode 2A and the second emitter electrode 2B are stabilized, and the short-circuit tolerance is further improved. The heat dissipation during the switching operation is also improved.

[0094] <Embodiment 8>

[0095] Figure 18This is a diagram showing the structure of the semiconductor device 108 in Embodiment 8. The semiconductor device 108 includes a plurality of finger-shaped wirings 3 and a plurality of gate wiring extension portions 5A. Although not shown in the figure, the semiconductor device 108 may also include a plurality of finger-shaped wiring extension portions 3A. That is, the number of the finger-shaped wirings 3, the finger-shaped wiring extension portions 3A, and the gate wiring extension portions 5A may be two or more. In Figure 18 in the case where the left finger-shaped wiring 3 is used as a reference, the electrode on the left side of the finger-shaped wiring 3 is the first emitter electrode 2A, and the electrode on the right side is the second emitter electrode 2B. In the case where the right finger-shaped wiring 3 is used as a reference, the electrode on the left side of the finger-shaped wiring 3 is the first emitter electrode 2A, and the electrode on the right side is the second emitter electrode 2B. Figure 18 The electrode shown in the center of

[0096]

[0097] can be defined as the first emitter electrode 2A or the second emitter electrode 2B according to the finger-shaped wiring 3 serving as a reference. The present disclosure can freely combine the respective embodiments, or can appropriately deform or omit the respective embodiments.

[0098] Hereinafter, the respective aspects of the present disclosure are collectively described as appendices.

[0099] (Appendix 1)

[0100] A semiconductor device, wherein,

[0101] comprises:

[0102] finger-shaped wirings extending along a first direction in the plane of the semiconductor substrate;

[0103] surface electrodes including a first surface electrode and a second surface electrode arranged to sandwich the above-mentioned finger-shaped wiring;

[0104] gate wirings having a ring shape in a top view and arranged to surround the above-mentioned surface electrodes; and

[0105] a plurality of gate electrodes extending along a second direction in the plane of the semiconductor substrate,

[0106] the above-mentioned surface electrodes include: a third surface electrode provided on an extension line of the above-mentioned finger-shaped wiring and connecting the first surface electrode and the second surface electrode between the end of the above-mentioned finger-shaped wiring and the above-mentioned gate wiring,

[0107] The above-mentioned finger-shaped wiring includes a finger-shaped wiring extension portion that extends from the end of the above-mentioned finger-shaped wiring in the direction of the above-mentioned gate wiring while avoiding the above-mentioned third surface electrode.

[0108] Among the above-mentioned plurality of gate electrodes, the gate electrode that crosses the above-mentioned third surface electrode in a top view is electrically connected to the above-mentioned finger-shaped wiring extension portion.

[0109] (Supplementary Note 2)

[0110] According to the semiconductor device described in Supplementary Note 1, wherein,

[0111] After the above-mentioned finger-shaped wiring extension portion extends from the end of the above-mentioned finger-shaped wiring in the second direction, it further extends in the first direction.

[0112] (Supplementary Note 3)

[0113] According to the semiconductor device described in Supplementary Note 1 or 2, wherein,

[0114] The above-mentioned gate wiring includes a gate wiring extension portion that branches off from the above-mentioned gate wiring and extends toward the inside of the above-mentioned ring-shaped gate wiring while avoiding the above-mentioned third surface electrode.

[0115] The gate electrode that crosses the above-mentioned third surface electrode is electrically connected to at least one of the above-mentioned gate wiring extension portion and the above-mentioned finger-shaped wiring extension portion.

[0116] (Supplementary Note 4)

[0117] According to the semiconductor device described in Supplementary Note 3, wherein,

[0118] After the above-mentioned gate wiring extension portion branches off from the above-mentioned gate wiring and extends in the first direction, it extends in the second direction, and then extends in the first direction.

[0119] (Supplementary Note 5)

[0120] A semiconductor device, wherein,

[0121] It includes:

[0122] Finger-shaped wiring that extends in the first direction in the plane of the semiconductor substrate;

[0123] Surface electrodes that include a first surface electrode and a second surface electrode arranged to sandwich the above-mentioned finger-shaped wiring;

[0124] Gate wiring that has a ring shape in a top view and is arranged to surround the above-mentioned surface electrodes; and

[0125] A plurality of gate electrodes that extend in the second direction in the plane of the above-mentioned semiconductor substrate,

[0126] The above surface electrodes include: a third surface electrode provided on an extension of the above finger-shaped wiring and connecting the above first surface electrode and the above second surface electrode between the end of the above finger-shaped wiring and the above gate wiring,

[0127] The above gate wiring includes a gate wiring extension portion that branches from the above gate wiring and extends toward the inside of the above circular ring of the above gate wiring while avoiding the above third surface electrode,

[0128] Among the above plurality of gate electrodes, the gate electrode that crosses the above third surface electrode in a top view is electrically connected to the above gate wiring extension portion.

[0129] (Supplementary Note 6)

[0130] According to the semiconductor device described in Supplementary Note 5, wherein,

[0131] After the above gate wiring extension portion branches from the above gate wiring and extends in the above first direction, it branches into two strands in the above second direction, and the end of the above gate wiring extension portion extends in the above first direction.

[0132] (Supplementary Note 7)

[0133] According to the semiconductor device described in Supplementary Note 5 or 6, wherein,

[0134] The above gate wiring extension portion includes a plurality of branch wirings that branch from a plurality of branch points in the above gate wiring and extend in the above first direction respectively.

[0135] (Supplementary Note 8)

[0136] According to the semiconductor device described in Supplementary Note 3, wherein,

[0137] The above gate electrode that crosses the above third surface electrode is electrically connected to both the above gate wiring extension portion and the above finger-shaped wiring extension portion.

[0138] (Supplementary Note 9)

[0139] A semiconductor device, wherein,

[0140] It includes:

[0141] Finger-shaped wiring that extends in a first direction in the plane of the semiconductor substrate;

[0142] Surface electrodes that include a first surface electrode and a second surface electrode arranged to sandwich the above finger-shaped wiring;

[0143] Gate wiring that has a circular shape in a top view and is arranged to surround the above surface electrodes; and

[0144] A plurality of gate electrodes extending along a second direction in the plane of the semiconductor substrate.

[0145] The surface electrode includes: a third surface electrode provided on an extension line of the finger-shaped wiring and connecting the first surface electrode and the second surface electrode between the end of the finger-shaped wiring and the gate wiring.

[0146] The gate electrode among the plurality of gate electrodes disposed below the third surface electrode in a top view includes a gate connection wiring.

[0147] The gate connection wiring bends and extends in the first direction below the third surface electrode and is electrically connected to the gate wiring in a region outside the third surface electrode.

[0148] (Supplementary Note 10)

[0149] According to the semiconductor device described in Supplementary Note 9, wherein

[0150] The gate connection wiring bends and extends in the first direction below the third surface electrode and is electrically connected to the finger-shaped wiring in a region outside the third surface electrode.

[0151] (Supplementary Note 11)

[0152] According to the semiconductor device described in any one of Supplementary Notes 1 to 10, wherein

[0153] The plurality of gate electrodes are formed in a plurality of trenches provided in the semiconductor substrate and extending along the second direction.

[0154] (Supplementary Note 12)

[0155] According to the semiconductor device described in Supplementary Note 1, wherein

[0156] The second surface electrode includes a fourth surface electrode provided between the end of the extension of the finger-shaped wiring and the gate wiring in the first direction.

[0157] When the length of the third surface electrode in the first direction and the width of the fourth surface electrode in the second direction are set as x, the width of the third surface electrode in the second direction and the length of the fourth surface electrode in the first direction are set as y, and the thickness of the chip is set as z, the third surface electrode and the fourth surface electrode satisfy the following two equations.

[0158]

[0159]

[0160] (Supplementary Note 13)

[0161] The semiconductor device according to Supplementary Note 1, wherein

[0162] the first surface electrode includes a fourth surface electrode disposed between the end of the finger-shaped wiring extension portion and the gate wiring in the first direction.

[0163] When the length of the third surface electrode in the first direction and the width of the fourth surface electrode in the second direction are set to x, the width of the third surface electrode in the second direction and the length of the fourth surface electrode in the first direction are set to y, and the thickness of the chip is set to z, the third surface electrode and the fourth surface electrode satisfy the following two equations.

[0164]

[0165]

[0166] (Supplementary Note 14)

[0167] The semiconductor device according to any one of Supplementary Notes 3 to 8, wherein

[0168] an island-shaped wiring is further provided in a region where one of the first surface electrode and the second surface electrode is disposed and is insulated from the first surface electrode and the second surface electrode.

[0169] the island-shaped wiring is electrically connected to the gate electrode that crosses the third surface electrode and the gate electrodes other than the gate electrode that crosses the third surface electrode among the plurality of gate electrodes.

[0170] The gate electrode that crosses the third surface electrode is electrically connected to any one of the finger-shaped wiring and the gate wiring extension portion via the island-shaped wiring.

[0171] (Supplementary Note 15)

[0172] The semiconductor device according to any one of Supplementary Notes 1 to 14, wherein

[0173] a lead connecting the first surface electrode and the second surface electrode is further provided.

[0174] (Supplementary Note 16)

[0175] The semiconductor device according to any one of Supplementary Notes 1 to 15, wherein

[0176] a metal plate connecting the first surface electrode and the second surface electrode is further provided.

[0177] (Supplementary Note 17)

[0178] The semiconductor device according to Note 3 or 4, wherein

[0179] the number of the finger-shaped wirings, the finger-shaped wiring extension portions, and the gate wiring extension portions is two or more.

Claims

1. A semiconductor device, wherein: have: The finger wiring extends along a first direction within the plane of the semiconductor substrate; The surface electrodes include a first surface electrode and a second surface electrode arranged in a manner of sandwiching the finger wiring; A gate wiring has a ring shape when viewed from above and is arranged so as to surround the surface electrode; as well as A plurality of gate electrodes extending along a second direction within the plane of the semiconductor substrate, The surface electrode includes: a third surface electrode provided on an extension line of the finger wiring and connecting the first surface electrode and the second surface electrode between an end of the finger wiring and the gate wiring; The finger wiring includes a finger wiring extension portion extending from the end of the finger wiring toward the gate wiring avoiding the third surface electrode, Among the plurality of gate electrodes, a gate electrode that crosses the third surface electrode in a plan view is electrically connected to the finger wiring extension portion.

2. The semiconductor device according to claim 1, wherein The finger wiring extension portion extends from the end of the finger wiring in the second direction and then extends in the first direction.

3. The semiconductor device according to claim 1 or 2, wherein: The gate wiring includes a gate wiring extension portion branching from the gate wiring and extending toward the inner side of the ring shape of the gate wiring avoiding the third surface electrode, The gate electrode that crosses the third surface electrode is electrically connected to at least one of the gate wiring extension portion and the finger wiring extension portion.

4. The semiconductor device according to claim 3, wherein: The gate wiring extension portion branches off from the gate wiring and extends in the first direction, then extends in the second direction, and further extends in the first direction.

5. A semiconductor device, wherein: have: The finger wiring extends along a first direction within the plane of the semiconductor substrate; The surface electrodes include a first surface electrode and a second surface electrode arranged in a manner of sandwiching the finger wiring; A gate wiring has a ring shape when viewed from above and is arranged so as to surround the surface electrode; as well as A plurality of gate electrodes extending along a second direction within the plane of the semiconductor substrate, The surface electrode includes: a third surface electrode provided on an extension line of the finger wiring and connecting the first surface electrode and the second surface electrode between an end of the finger wiring and the gate wiring; The gate wiring includes a gate wiring extension portion branching from the gate wiring and extending toward the inner side of the ring shape of the gate wiring avoiding the third surface electrode, Among the plurality of gate electrodes, a gate electrode that crosses the third surface electrode in a plan view is electrically connected to the gate wiring extension portion.

6. The semiconductor device according to claim 5, wherein: The gate wiring extension portion branches from the gate wiring and extends in the first direction, and then branches into two branches in the second direction, and the end of the gate wiring extension portion extends in the first direction.

7. The semiconductor device according to claim 5 or 6, wherein: The gate wiring extension portion includes a plurality of branch wirings branched from a plurality of branch points in the gate wiring and extending in the first direction, respectively.

8. The semiconductor device according to claim 3, wherein: The gate electrode that crosses the third surface electrode is electrically connected to both the gate wiring extension portion and the finger wiring extension portion.

9. A semiconductor device, wherein: have: The finger wiring extends along a first direction within the plane of the semiconductor substrate; The surface electrodes include a first surface electrode and a second surface electrode arranged in a manner of sandwiching the finger wiring; A gate wiring has a ring shape when viewed from above and is arranged so as to surround the surface electrode; as well as A plurality of gate electrodes extending along a second direction within the plane of the semiconductor substrate, The surface electrode includes: a third surface electrode provided on an extension line of the finger wiring and connecting the first surface electrode and the second surface electrode between an end of the finger wiring and the gate wiring; The gate electrode disposed below the third surface electrode in a plan view among the plurality of gate electrodes includes a gate connection wiring. The gate connection wiring bends and extends in the first direction below the third surface electrode, and is electrically connected to the gate wiring in a region outside the third surface electrode.

10. The semiconductor device according to claim 9, wherein The gate connection wiring bends and extends in the first direction below the third surface electrode, and is electrically connected to the finger wiring in a region outside the third surface electrode.

11. The semiconductor device according to any one of claims 1 to 10, wherein: The plurality of gate electrodes are formed in a plurality of trenches disposed in the semiconductor substrate and extending along the second direction.

12. The semiconductor device according to claim 1, wherein The second surface electrode includes a fourth surface electrode disposed between the end of the finger wiring extension and the gate wiring in the first direction, When the length of the third surface electrode in the first direction and the width of the fourth surface electrode in the second direction are set to x, the width of the third surface electrode in the second direction and the length of the fourth surface electrode in the first direction are set to y, and the thickness of the chip is set to z, the third surface electrode and the fourth surface electrode satisfy the following two equations:

13. The semiconductor device according to claim 1, wherein The first surface electrode includes a fourth surface electrode disposed between the end of the finger wiring extension and the gate wiring in the first direction, When the length of the third surface electrode in the first direction and the width of the fourth surface electrode in the second direction are set to x, the width of the third surface electrode in the second direction and the length of the fourth surface electrode in the first direction are set to y, and the thickness of the chip is set to z, the third surface electrode and the fourth surface electrode satisfy the following two equations:

14. The semiconductor device according to any one of claims 3 to 8, wherein: further comprising an island wiring provided in a region where one of the first surface electrode and the second surface electrode is arranged and insulated from the first surface electrode and the second surface electrode, The island wiring is electrically connected to the gate electrode that crosses the third surface electrode and gate electrodes other than the gate electrode that crosses the third surface electrode among the plurality of gate electrodes. The gate electrode crossing the third surface electrode is electrically connected to any one of the finger wiring and the gate wiring extension via the island wiring.

15. The semiconductor device according to any one of claims 1 to 14, wherein: A lead wire connecting the first surface electrode and the second surface electrode is further provided.

16. The semiconductor device according to any one of claims 1 to 15, wherein A metal plate connecting the first surface electrode and the second surface electrode is further provided.

17. The semiconductor device according to claim 3 or 4, wherein: The number of the finger wirings, the finger wiring extensions, and the gate wiring extensions is two or more.

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