Semiconductor device having plurality of device regions and

Abstract

The present invention relates to a semiconductor device comprising: a silicon (Si) base substrate having a first crystal orientation; the semiconductor device includes a Si base substrate, a first device region formed over the Si base substrate, where the first device region includes a gallium nitride (GaN) layer formed over the Si base substrate, and a transition layer having a second crystal orientation disposed between the GaN layer and the Si base substrate. First and second current-carrying electrodes are formed over the GaN layer in the first active region with a first control electrode between the first and second current-carrying electrodes. A second device region is formed laterally adjacent to the first device region, wherein the second device region includes a second Si layer formed over the Si base substrate. Third and fourth current-carrying electrodes are formed in a second active region over the second Si layer, with a second control electrode formed between the third and fourth current-carrying electrodes.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to semiconductor devices and methods for manufacturing such devices. Background Art

[0002] Semiconductor devices are applied to various electronic components and systems. High-power, high-frequency transistors are applied to radio frequency (RF) systems and power electronics systems. Gallium nitride (GaN) device technology is particularly suitable for these RF power applications and power electronics applications due to its excellent electronic and thermal properties. Specifically, the high electron velocity and high breakdown field strength of GaN make devices fabricated from this material ideal for RF power amplifiers and high-power switching applications. At the same time, compared with GaN device technology, other technologies such as silicon metal oxide field effect transistor (Si MOSFET) technology and silicon germanium (SiGe) bipolar technology have increased integration capabilities. Therefore, there is a need for semiconductor devices that combine GaN device technology with Si MOSFET and SiGe HBT technology. Summary of the Invention

[0003] In one aspect, embodiments may include a semiconductor device including: a silicon (Si) substrate having a first crystal orientation; a first device region formed over the Si substrate, wherein the first device region includes a gallium nitride (GaN) layer formed over the Si substrate, and a transition layer having a second crystal orientation is disposed between the GaN layer and the Si substrate. A first active region may be formed in the GaN layer. First and second current-carrying electrodes may be formed over the GaN layer, electrically coupled to the first active region, and configured to support current flow within the first active region. A first control electrode may be formed over the GaN layer, electrically coupled to the first active region, and configured to control the current flow between the first and second current-carrying electrodes. A second device region may be formed laterally adjacent to the first device region, wherein the second device region may include: a first Si layer formed over the Si substrate; third and fourth current-carrying electrodes formed over the Si layer and configured to support current flow within a second active region of the second device region. A second control electrode may be formed over the Si layer, electrically coupled to the second device region, and configured to control the current flow between the third and fourth current-carrying electrodes.

[0004] In an embodiment, the first crystal orientation may be (1 0 0) and the second crystal orientation may be (11 1).

[0005] An embodiment may include a bonding layer formed between the transition layer and the Si substrate.

[0006] According to an embodiment, the bonding layer may include a buried oxide layer.

[0007] In an embodiment, the transition layer may include a material selected from the group consisting of silicon, silicon carbide, gallium nitride, and aluminum nitride.

[0008] An embodiment may include a passivation dielectric region formed between a first sidewall of the first device region and a second sidewall of the second device region.

[0009] According to an embodiment, the passivation dielectric region may include silicon nitride.

[0010] In an embodiment, a first upper surface of the first device region and a second upper surface of the second device region may be coplanar.

[0011] In an embodiment, the first current-carrying electrode may be configured as a first source electrode, the second current-carrying electrode may be configured as a first drain electrode, and the first control electrode may be configured as a first gate electrode.

[0012] In an embodiment, the third current-carrying electrode may be configured as an element selected from the group consisting of a source electrode and an emitter electrode, the fourth current-carrying electrode may be configured as an element selected from the group consisting of a drain electrode and a collector electrode, and the second control electrode may be configured as an element selected from the group consisting of a gate electrode and a base electrode.

[0013] An embodiment may include a third device region formed laterally adjacent to the first device region, where the third device region may include: a second Si layer formed above the Si substrate; a fifth current-carrying electrode and a sixth current-carrying electrode formed above the second Si layer, electrically coupled to a third active region and configured to support current flow within the third device region; and a third control electrode formed above the second Si layer, electrically coupled to the third active region and configured to control the current flow between the fifth and sixth current-carrying electrodes.

[0014] In an embodiment, the first current-carrying electrode may be configured as a first source electrode, the second current-carrying electrode may be configured as a first drain electrode, the first control electrode may be configured as a first gate electrode, the third current-carrying electrode may be configured as an element selected from the group consisting of a source electrode and an emitter electrode, the fourth current-carrying electrode may be configured as an element selected from the group consisting of a drain electrode and a collector electrode, the second control electrode may be configured as an element selected from the group consisting of a gate electrode and a base electrode, the fifth current-carrying electrode may be configured as an element selected from the group consisting of a source electrode and an emitter electrode, the sixth current-carrying electrode may be configured as an element selected from the group consisting of a drain electrode and a collector electrode; and the third control electrode may be configured as an element selected from the group consisting of a gate electrode and a base electrode.

[0015] In another aspect, an embodiment may include a method for forming a semiconductor device. In an embodiment, the method may include forming a bonding layer over a Si substrate having a first crystal orientation and forming a transition layer having a second crystal orientation over the bonding layer. According to an embodiment, the method may further include forming a gallium nitride (GaN) layer over the transition layer. According to an embodiment, the method may further include etching a first portion of the GaN layer to expose a first surface of the Si substrate and forming a first device region including the GaN layer having a first sidewall at a first edge of the GaN layer and a second device region over the first surface of the Si substrate. In an embodiment, the method may include forming first and second current-carrying electrodes over the GaN layer in the first device region and forming a first control electrode over the GaN layer in the first device region. According to an embodiment, the method may further include forming a first Si layer over the Si substrate in the second device region. An embodiment of the method may include forming third and fourth current-carrying electrodes over the Si layer in the second device region and forming a second control electrode over the Si layer in the second device region.

[0016] In an embodiment, the method may include forming a passivation dielectric region over the GaN layer.

[0017] In an embodiment of the method, the first crystal orientation may be (1 0 0) and the second crystal orientation may be (1 1 1).

[0018] In an embodiment of the method, forming the bonding layer may include forming a buried oxide layer.

[0019] According to an embodiment, the method may further include forming a passivation dielectric region between the first sidewall of the first device region and the second sidewall of the second device region.

[0020] In an embodiment of the method, forming the passivation dielectric region may include depositing silicon nitride.

[0021] In an embodiment of the method, forming the first current-carrying electrode may include forming a first source electrode, forming the second current-carrying electrode may include forming a first drain electrode, and forming the first control electrode may include forming a first gate electrode.

[0022] In an embodiment of the method, forming the third current-carrying electrode may include forming an element selected from the group consisting of a source electrode and an emitter electrode, forming the fourth current-carrying electrode may include forming an element selected from the group consisting of a drain electrode and a collector electrode, and forming the second control electrode may include forming an element selected from the group consisting of a gate electrode and a base electrode.

[0023] An embodiment of the method may include forming a third device region laterally adjacent to the first device region, wherein forming the third device region may include forming a second Si layer over the Si substrate; forming a fifth current-carrying electrode; and forming a sixth current-carrying electrode over the second Si layer; and forming a third control electrode over the second Si layer.

[0024] In an embodiment of the method, forming the first current-carrying electrode may include forming a first source electrode, forming the second current-carrying electrode may include forming a first drain electrode, forming the first control electrode may include forming a first gate electrode, forming the third current-carrying electrode may include forming an element selected from the group consisting of a source electrode and an emitter electrode, forming the fourth current-carrying electrode may include forming an element selected from the group consisting of a drain electrode and a collector electrode, forming the second control electrode may include forming an element selected from the group consisting of a gate electrode and a base electrode, forming the fifth current-carrying electrode may include forming an element selected from the group consisting of a source electrode and an emitter electrode, forming the sixth current-carrying electrode may include forming an element selected from the group consisting of a drain electrode and a collector electrode, and forming the third control electrode may include forming an element selected from the group consisting of a gate electrode and a base electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] A more complete understanding of the subject matter may be obtained by reference to the detailed description and claims considered in conjunction with the following figures, in which like reference numerals throughout the figures refer to similar elements.

[0026] Figure 1is a cross-sectional side view of an exemplary semiconductor device according to an embodiment; and

[0027] Figures 2 to 5 is a cross-sectional side view of an exemplary semiconductor device shown along with process steps, both describing a method for fabricating Figure 1 A method for a semiconductor device. DETAILED DESCRIPTION

[0028] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the words "exemplary" and "example" mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" or "example" is not necessarily to be construed as being preferred or superior to other embodiments. In addition, it is not intended to be bound by any explicit or implicit theory present in the aforementioned technical field, background technology, or the following detailed description.

[0029] Figure 1 1 is a cross-sectional side view of an exemplary semiconductor device 100 according to an embodiment. The semiconductor device 100 may include a silicon (Si) base substrate 101 having a first crystal orientation, a first device region 120, a second device region 150, and a third device region 170, wherein the first device region 120, the second device region 150, and the third device region 170 are formed above the Si base substrate 101.

[0030] The first device region 120 includes GaN transistors 130 and may include one or more gallium nitride (GaN) epitaxial layers (i.e., "GaN layers") 110 formed over a Si substrate 101, a bonding layer 102 disposed over the Si substrate 101, and a transition layer 104 disposed between the GaN epitaxial layer 110 and the Si substrate 101. The silicon substrate 101 may be formed of Si, silicon-on-insulator (SOI), or other suitable materials. In an embodiment, the Si substrate 101 may have a first crystal orientation and the transition layer 104 may include a second crystal orientation. In an embodiment, the first crystal orientation may be (1 0 0) and the second crystal orientation may be (1 1 1). Thus, in some embodiments, the Si substrate 101 may have a (1 0 0) crystal orientation that can be used to fabricate metal-oxide-semiconductor (MOS) devices, and the transition layer 104 may have a (1 1 1) crystal orientation that can serve as a surface on which the GaN epitaxial layer 110 is grown. According to an embodiment, the thickness of the Si substrate 101 may be between about 10 microns and about 2000 microns, but other thicker or thinner thicknesses may also be used. According to an embodiment, the transition layer 104 may be formed of Si and may have a thickness between about 10 nanometers and about 10,000 nanometers, but other thicker or thinner thicknesses may also be used. In other embodiments, other materials may be used instead of Si to form the transition layer 104. In these other embodiments, silicon carbide (SiC), diamond, GaN, aluminum nitride (AlN), or other suitable materials may be used to form the transition layer 104.

[0031] In an embodiment, the bonding layer 102 may be formed between the transition layer 104 and the Si substrate. In an embodiment, the bonding layer 102 may include a buried oxide (BOx) layer. In other embodiments, the bonding layer 102 may include silicon nitride, silicon dioxide (SiO2), aluminum oxide (Al2O3), or other suitable materials. In some embodiments, the thickness of the BOx layer 102 may be between about 10 nanometers and about 50 nanometers. In other embodiments, the thickness of the bonding layer 102 may be between about 3 nanometers and about 1000 nanometers. However, according to an embodiment, other thicker or thinner thicknesses may also be used.

[0032] In an embodiment, the GaN epitaxial layer 110 may include a buffer layer 114 disposed above the transition layer 104, a channel layer 116 disposed above the buffer layer 114, a barrier layer 118 disposed above the channel layer 116, and a cap layer 119 disposed above the barrier layer 118. A nucleation layer 112 may be formed on the upper surface 103 of the substrate Si substrate 101 between the buffer layer 114 and the substrate Si substrate 101. In an embodiment, the nucleation layer may include AlN. The buffer layer 114 may include a plurality of III-N semiconductor layers and be supported by the transition layer 104. Each of the semiconductor layers of the buffer layer 114 may include an epitaxially grown group III nitride epitaxial layer. For example, the group III nitride epitaxial layer constituting the buffer layer 114 may be an N (nitrogen) face or Ga (gallium) face material. In other embodiments, the semiconductor layers of the buffer layer 114 may not be epitaxially grown. In still other embodiments, the semiconductor layers of the buffer layer 114 may include Si, GaAs, InP, or other suitable materials.

[0033] In an embodiment, the buffer layer 114 may be epitaxially grown above the nucleation layer 112. The buffer layer 114 may include at least one AlGaN mixed crystal layer having a composition represented by Al X Ga 1-X N, where X may take a value between 0 and 1. The total thickness of the buffer layer 114 and all its layers may be between about 200 angstroms and about 100,000 angstroms, but other thicknesses may also be used. The limiting X value of 0 results in pure GaN, while the value of 1 results in pure aluminum nitride (AlN). Embodiments may include a buffer layer 114 and a nucleation layer (not shown) disposed above a main substrate. The buffer layer 114 may include additional Al X Ga 1-X N layers. The thickness of the additional Al X Ga 1-X N layers may be between about 200 angstroms and about 50,000 angstroms, but other thicknesses may also be used. In an embodiment, the additional Al X Ga 1-X N layer may be configured as GaN (X = 0), where Al X Ga 1-X N is unintentionally doped (NID). The additional Al X Ga 1-X N layer may also be configured as one or more GaN layers, where the one or more GaN layers are intentionally doped with a dopant, and the dopant may include iron (Fe), chromium (Cr), carbon I, or other suitable dopants that make the buffer layer 114 substantially insulating or have a high resistivity. The dopant concentration may be between about 10 17 cm -3 and 10 19 cm-3 between, but other higher or lower concentrations may also be used. Additional Al X Ga 1-X N layers may be configured with X = 0.01 to 0.10, where Al X Ga 1-X N is NID, or alternatively, where Al X Ga 1-X N is intentionally doped with Fe, Cr, C, or other suitable dopant materials. In other embodiments (not shown), the additional layer may be configured as a superlattice, where the additional layer includes a series of alternating NID layers or doped Al X Ga 1-X N layers, where the X value takes a value between 0 and 1. In still other embodiments, buffer layer 114 may further include one or more indium gallium nitride (InGaN) layers having a composition denoted as In Y Ga 1-Y N, where the indium mole fraction Y may take a value between 0 and 1. The thickness of the InGaN layer may be between about 50 angstroms and about 2,000 angstroms, but other thicknesses may also be used.

[0034] In an embodiment, channel layer 116 may be formed over buffer layer 114. Channel layer 116 may include one or more Group III-N semiconductor layers and may be supported by buffer layer 114. Channel layer 116 may include Al X Ga 1-X N layers, where X takes a value between 0 and 1. In an embodiment, channel layer 116 is configured as GaN (X = 0), but other X values may be used without departing from the scope of the subject matter of the present invention. The thickness of channel layer 116 may be between about 50 angstroms and about 10,000 angstroms, but other thicknesses may also be used. Channel layer 116 may be NID, or alternatively, may include Si, germanium (Ge), C, Fe, Cr, or other suitable dopants. The dopant concentration may be between about 10 15 cm -3 and about 10 19 cm -3 between, but other higher or lower concentrations may also be used. In other embodiments, channel layer 116 may include NID or doped In Y Ga 1-Y N, where the indium mole fraction Y may take a value between 0 and 1.

[0035] According to an embodiment, the barrier layer 118 can be formed above the channel layer 116. The barrier layer 118 can include one or more III-N semiconductor layers and be supported by the channel layer 116. In some embodiments, the barrier layer 118 can have a larger bandgap and larger spontaneous polarization than the channel layer 116, and when the barrier layer 118 is in direct contact with the channel layer 116, the channel 117 is generated in the form of a two-dimensional electron gas (2-DEG) within the channel layer 116 near the interface between the channel layer 116 and the barrier layer 118. Additionally, the strain between the barrier layer 118 and the channel layer 116 can cause additional piezoelectric charges to be introduced into the 2-DEG and the channel 117. The barrier layer 118 can include at least one NxAl1-xGaxN layer, where x takes a value between 0 and 1. In some embodiments, x can take a value from 0.1 to 0.35, but other x values can also be used. The thickness of the barrier layer 118 can be between about 50 angstroms and about 1000 angstroms, but other thicknesses can also be used. The barrier layer 118 can be NxAl1-xGaxN, or alternatively, can include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration can be between about 1018 cm-3 and 1020 cm-3, but other higher or lower concentrations can also be used. In an embodiment, according to an embodiment, an additional AlN inter-barrier layer (not shown) can be formed between the channel layer 116 and the barrier layer 118. The AlN inter-barrier layer can increase the channel charge and improve the electron confinement of the resulting 2-DEG. In other embodiments, the barrier layer 118 can include an indium aluminum nitride (InAlN) layer denoted as InyAl1-yN, where the indium mole fraction y can take a value between about 0.1 and about 0.2, but other y values can also be used. In the case of an InAlN barrier, the thickness of the barrier layer 118 can be between about 30 angstroms and about 1000 angstroms, but other thicknesses can also be used. In the case of using InAlN to form the barrier layer 118, the InAlN can be NxAl1-xGaxN, or alternatively, can include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration can be between about 1018 cm-3 and about 1020 cm-3, but other higher or lower concentrations can also be used. X Ga 1-X N layer, where X takes a value between 0 and 1. In some embodiments, X can take a value from 0.1 to 0.35, but other X values can also be used. The thickness of the barrier layer 118 can be between about 50 angstroms and about 1000 angstroms, but other thicknesses can also be used. The barrier layer 118 can be NxAl1-xGaxN, or alternatively, can include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration can be between about 10 16 cm -3 and 10 19 cm -3 between, but other higher or lower concentrations can also be used. In an embodiment, according to an embodiment, an additional AlN inter-barrier layer (not shown) can be formed between the channel layer 116 and the barrier layer 118. The AlN inter-barrier layer can increase the channel charge and improve the electron confinement of the resulting 2-DEG. In other embodiments, the barrier layer 118 can include an indium aluminum nitride (InAlN) layer denoted as In Y Al 1-Y N of indium aluminum nitride (InAlN), where the indium mole fraction Y can take a value between about 0.1 and about 0.2, but other Y values can also be used. In the case of an InAlN barrier, the thickness of the barrier layer 118 can be between about 30 angstroms and about 1000 angstroms, but other thicknesses can also be used. In the case of using InAlN to form the barrier layer 118, the InAlN can be NxAl1-xGaxN, or alternatively, can include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration can be between about 10 16 cm -3 and about 10 19 cm -3 between, but other higher or lower concentrations can also be used.

[0036] In Figure 1In the illustrated embodiment, a cap layer 119 may be formed over the barrier layer 118. The cap layer 119 may present a stable surface of the GaN epitaxial layer 110 and may protect the surface of the GaN epitaxial layer 110 from chemical and environmental exposures that occur during wafer processing. The cap layer 119 may include one or more III-N semiconductor layers and is supported by the barrier layer 118. In an embodiment, the cap layer 119 is GaN. The thickness of the cap layer 119 may be between about 5 angstroms and about 100 angstroms, although other thicknesses may also be used. The cap layer 119 may be NID, or alternatively, may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be between about 10 16 cm -3 and 10 19 cm -3 , although other higher or lower concentrations may also be used. It should be understood that the material selection and layer arrangement for forming the GaN epitaxial layer 110 are exemplary without departing from the scope of the subject matter of the present invention. It should be understood that including the nucleation layer 112, buffer layer 114, channel layer 116, barrier layer 118, and cap layer 119 in the GaN epitaxial layer 110 is exemplary, and the functions and operations of the respective layers may be combined and may vary depending on the materials used in any particular embodiment. For example, in some embodiments, the cap layer 119 may be omitted (not shown). In other embodiments using N-polarity materials, the channel layer 116 may be disposed above the barrier layer 118 to create a 2-DEG (not shown) directly below the cap layer 119 and the gate electrode 136.

[0037] In an embodiment, the first device region 120 may be formed by: removing one or more of the epitaxial layer and / or other semiconductor layers of the GaN epitaxial layer 110; forming a first sidewall 121 and a second sidewall 122; and then using ion implantation to disrupt and further enhance the semi-insulating properties of the remaining layers of the GaN epitaxial region 110, and leaving a "boss" of the first active region 125 surrounded by a highly resistive or semi-insulating isolation region 123 into which the implantation has been performed. According to an embodiment, one or more isolation regions 123 may be formed in the GaN epitaxial layer 110 to partially define the first active region 125 above and along the upper surface 105 of the transition layer 104. The isolation regions 123 may be formed via an implantation process configured to damage the epitaxy and / or other semiconductors, such that the GaN epitaxial layer 110 is highly resistive or semi-insulating in those isolation regions 123 while keeping the crystal structure intact in the first active region 125. In other embodiments, the isolation regions 123 may be omitted and the first active region 125 may be defined only using etching of the GaN epitaxial layer 110.

[0038] In an embodiment, the passivation dielectric region 127 may encapsulate the first device region 120 and may be formed between the first sidewalls 121 and 122 of the first device region 120 and the first Si layer 152 and the second Si layer 172 of the second device region 150 and the third device region 170.

[0039] In an embodiment, the passivation dielectric region 127 may include one or more layers of silicon nitride (SiN). In other embodiments, the passivation dielectric region 127 may be formed of one or more suitable materials, including silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), aluminum nitride (AlN), and hafnium oxide (HfO2), but other substantially insulating materials may also be used. In an embodiment, the passivation dielectric region 127 may have a thickness between 200 angstroms and 1000 angstroms. In other embodiments, the passivation dielectric region 127 may have a thickness between 50 angstroms and 10,000 angstroms, but other thicknesses may also be used.

[0040] In other embodiments, the passivation dielectric region 127 may include silicon dioxide SiO2, Al2O3, or other suitable materials with or without one or more layers of SiN. In an embodiment, the thickness of the passivation dielectric region 127 may be between about 100 angstroms and about 2000 angstroms, but other thicker or thinner values may also be used.

[0041] The source electrode 132 and the drain electrode 134 (i.e., "the first and second current-carrying electrodes") may be formed over the GaN epitaxial layer, electrically coupled to the channel 117 (i.e., "the channel region"), and configured to support current flow within the channel 117. The first gate electrode 136 (i.e., "the first control electrode") may be formed over the GaN epitaxial layer 110, electrically coupled to the channel 117, and configured to control the current flow between the first current-carrying electrode 132 and the second current-carrying electrode 134.

[0042] In an embodiment, a source electrode 132 and a drain electrode 134 may be formed over a source region 133 and a drain region 135 and contact the source region 133 and the drain region 135, the source region and the drain region being formed in a GaN epitaxial layer 110 in a first active region 125. The source electrode 132 and the drain electrode 134 may be formed inside an opening (e.g., opening 137) in a passivation dielectric region 127 and may be formed of one or more conductive layers. In some embodiments, ion implantation may be used to form an ohmic contact with a channel 117 to create the source region 133 and the drain region 135. In an embodiment, the one or more conductive layers used to form the source electrode 132 and the drain electrode 134 may include titanium (Ti), gold (Au), aluminum (Al), molybdenum (Mo), nickel (Ni), silicon (Si), germanium (Ge), platinum (Pt), tantalum (Ta), or other suitable materials. In other embodiments, the one or more conductive layers used to form the source electrode 132 and the drain electrode 134 may include titanium-tungsten (TiW), titanium-aluminum (TiAl), or titanium-tungsten nitride (TiWN). In an embodiment, the source electrode 132 and the drain electrode 134 may be formed over a cap layer 119 and contact the cap layer 119. In other embodiments (not shown), one or both of the source electrode 132 and the drain electrode 134 may be recessed through the cap layer 119 and partially extend through a barrier layer 118. In an embodiment, the source electrode 132 and the drain electrode 134 may be formed of a multi-layer stack. In an embodiment, the multi-layer stack used to form the source electrode 132 and the drain electrode 134 may include an adhesion layer and one or more layers (not shown) that allow an ohmic contact to be formed between the channel 117 and the source electrode 132 and the drain electrode 134 upon annealing. In an embodiment, the adhesion layer may include titanium (Ti), tantalum (Ta), silicon (Si), or other suitable materials. In an embodiment, the adhesion layer may have a work function of less than 4.5 electron volts.

[0043] A first gate electrode 136 may be formed over the GaN epitaxial layer 110, electrically coupled to the channel 117, and configured to control current flow between the first and second current-carrying electrodes. In an embodiment, the first gate electrode 136 may be characterized by a gate length 138. In an embodiment, the gate length 138 may be between about 0.05 micrometers and about 1 micrometer. In other embodiments, the gate length 138 may be between about 0.02 micrometers and about 5 micrometers, but other suitable dimensions may also be used.

[0044] A change in the potential applied to the first gate electrode 136 can shift the quasi-Fermi level of the barrier layer 118 relative to the quasi-Fermi level of the channel layer 116, and thereby modulate the electron concentration in the channel 117 within the GaN epitaxial layer 110 beneath the first gate electrode 136. According to an embodiment, one or more Schottky materials such as Ni, palladium (Pd), Pt, iridium (Ir), or copper (Cu) can be combined with one or more low-stress conductive materials such as Au, Al, Cu, polysilicon, or other suitable materials in the metal stack to form the first gate electrode 136 for the low-loss first gate electrode 136 that is electrically coupled to the channel 117.

[0045] Still referring to Figure 1 , according to an embodiment, the second device region 150 can be formed laterally adjacent to the first device region 120 (e.g., using selective growth well-known to those skilled in the art, as described below). The second device region 150 can include a Si MOSFET device 160, and can include a first Si layer 152 formed over the Si substrate 101, a second source electrode 162 (i.e., the "third current-carrying electrode") and a second drain electrode 164 (i.e., the "fourth current-carrying electrode") formed over the first Si layer 152, and can be configured to support current flow within the second active region 155 of the second device region 150. A second gate electrode 166c (i.e., the "control electrode") can be formed over the first Si layer 152, electrically coupled to the second device region 152, and configured to control the current flow between the second source electrode 162 and the second drain electrode 164. In an embodiment, the first upper surface 129 of the first device region 120, the second upper surface 159 of the second device region 150, and the third upper surface 179 of the third device region 170 can be coplanar.

[0046] In an embodiment, the second device region 150 may be configured as a PMOS region or an NMOS region. The first Si layer 152 may be formed of Si having the same crystal orientation (e.g., (10 0) orientation) as the Si substrate 101. In an embodiment, an n or p well (also referred to herein as "n / p well") 156 may be formed within the first Si layer 152. In an embodiment, the second source region 161 and the second drain region 163 may be formed within the n / p well 156. The channel region 165 may be formed laterally adjacent to and between the second source region 161 and the second drain region 163, and may include an n-type region for a PMOS device or a p-type region for an NMOS device. According to an embodiment, the second gate electrode 166a / b / c includes a gate oxide 166a, a gate polysilicon 166b, and a gate contact layer 166c. In an embodiment, the gate dielectric 166a may include a gate oxide layer (e.g., SiO2) formed over the n / p well 156. The gate polysilicon 166b may be formed over and in contact with the gate oxide 166a. According to an embodiment, the gate polysilicon 166b may be formed of polysilicon or other suitable conductive material. The gate contact layer 166c may be formed over or within the gate polysilicon layer 166b. A plurality of NMOS or PMOS devices may be formed in a plurality of device regions similarly configured to the second device region 150.

[0047] Still referring to Figure 1 And in an embodiment, the third device region 170 may be formed laterally adjacent to the first device region 120, wherein the third device region 170 may include a second Si layer 172 formed over the Si substrate 101. In some embodiments, the first Si layer 152 and the second Si layer 172 may be formed simultaneously. In other embodiments, the first Si layer 152 and the second Si layer 172 may be formed separately. An emitter electrode 182b and a collector electrode 184b (i.e., "the fifth and sixth current-carrying electrodes") may be formed over the second Si layer 172, electrically coupled to the third device region 170, and configured to support current flow within a third active region 175 of the third device region 170. According to an embodiment, a base electrode 187b (i.e., "the third control electrode") may be formed over the second Si layer 152, electrically coupled to the second active region 175, and may be configured to control the current flow between the emitter electrode 182b and the collector electrode 184b.

[0048] In an embodiment, the semiconductor device 100 may be configured as a transistor finger, wherein the first source electrode 132 and the second source electrode 162, the first drain electrode 134 and the second drain electrode 164b, the first gate electrode 136 and the second gate electrode 166a / b / c, the emitter electrode 182b, the collector electrode 184b, and the base electrode 187b may be configured as elongated elements forming an active device finger. The semiconductor device 100 may be partially defined by isolation regions 123, 153, 173, wherein the gate width of the gate finger and / or the emitter finger (i.e., the dimension extending along an axis perpendicular to the plane of the semiconductor device 100) is significantly greater than the gate length 138 of the first gate electrode 136 (i.e., the dimension extending along an axis perpendicular to the width). In some embodiments, the gate width may be between about 50 micrometers and about 500 micrometers. In other embodiments, the gate width may be between about 1 micrometer and about 10,000 micrometers. Figure 1 The dimension of the semiconductor device 100 extending along an axis perpendicular to the plane is significantly greater than the gate length 138 of the first gate electrode 136 (i.e., the dimension extending along an axis perpendicular to the width).

[0049] In other embodiments, additional dielectric and metal layers may be formed over the semiconductor device 100. These additional dielectric and metal layers may include, but are not limited to, a passivation layer, an interconnect metallization, additional active devices, and additional circuitry.

[0050] Figures 2 to 5 Describes embodiments of a method for manufacturing Figure 1 the semiconductor device of Figures 2 to 5 A cross-sectional side view showing a series of manufacturing steps according to an exemplary embodiment and a flowchart describing the series of manufacturing steps for producing Figure 1 the semiconductor device of

[0051] Now refer to Figure 2, Step 210 and in an embodiment, the method may include forming a mask oxide (BOx) layer 102 (i.e., "bonding layer") over a Si substrate 101 having a first crystal orientation and forming a transition layer 104 having a second crystal orientation over the BOx layer 102. In an embodiment, the BOx layer 102 may include a material selected from SiN, Al2O3, SiO2, AlN, and HfO2. The BOx layer 102 may be formed using one or more of low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), sputtering, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), inductively coupled plasma (ICP) deposition, electron cyclotron resonance (ECR) deposition, or other suitable techniques. In an embodiment of the method, the crystal orientation of the Si substrate may be (1 0 0) (i.e., "first crystal orientation") and the crystal orientation of the transition layer 104 (i.e., "second crystal orientation") may be (1 1 1). In an embodiment, the transition layer 104 may be formed by bonding a bonding wafer having a second crystal orientation (e.g., (1 1 1) crystal orientation of Si) (e.g., Si, SiC, GaN, AlN) to the BOx layer 102 using wafer bonding techniques known to those skilled in the art (not shown). Using wafer separation techniques well known to those skilled in the art (not shown), the bonding wafer may be pre-implanted with a damaged layer placed at the thickness of the transition layer 104. Then, the bonding wafer may be annealed after bonding the Si bonding wafer to the BOx layer such that the transition layer 104 separates from the rest of the bonding wafer at the level of the damaged layer, such that only a portion of the bonding wafer including the transition layer 104 may be retained. Structure 219 is produced.

[0052] Now refer to Figure 2, Step 220. According to an embodiment, the method may further include forming a GaN epitaxial layer 110 (i.e., "GaN layer") over the transition layer 104. Forming the GaN epitaxial layer 110 may include forming a plurality of semiconductor layers on or over the Si substrate 101 and the transition layer 104. Forming the semiconductor layers may include forming a nucleation layer 112 on or over the upper surface 105 of the transition layer 104, forming a buffer layer 114 on or over the nucleation layer 112, forming a channel layer 116 on or over the buffer layer 114, forming a barrier layer 118 on or over the channel layer 116, and forming a cap layer 119 on or over the barrier layer 118. As previously discussed, embodiments of the buffer layer 114, the channel layer 116, the barrier layer 118, and the cap layer 119 may include materials selected from AlN, GaN, AlGaN, InAlN, InGaN, or other suitable materials. The semiconductor layers 114, 116, 118, and 119 may be grown using one of metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or a combination of these techniques, but other suitable techniques may alternatively be used. Structure 229 is produced.

[0053] Now referring to Figure 2 Step 230, embodiments of the method may include forming a dielectric layer 232 on or over the GaN epitaxial layer 110. In an embodiment, the dielectric layer 232 may include materials selected from SiN, Al2O3, SiO2, AlN, and HfO2. The dielectric layer 232 may be formed using one or more of LPCVD, ALD, sputtering, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques. In other embodiments, the dielectric layer 232 may be formed in-situ immediately after the growth of the semiconductor layers of the GaN epitaxial layer 110 and in the same chamber or deposition system (e.g., MOCVD or MBE) as the growth of the semiconductor layers of the GaN epitaxial layer 110. Structure 239 is produced.

[0054] Now referring to Figure 3In step 310, embodiments of the method may include forming source region 133 and drain region 135 such that first current-carrying electrode 132 and second current-carrying electrode 134 can be formed over GaN epitaxial layer 110 in first device region 120. Embodiments of the method may include forming doped (e.g., ion implanted) source region 133 and drain region 135. In these embodiments, dielectric layer 232 may be used as a sacrificial layer. Embodiments of the method may include patterning implantation mask 312 and implanting dopant species 314 through openings 316 in implantation mask 312 into GaN epitaxial layer 110 to form source region 133 and drain region 135 within GaN epitaxial layer 110. Once implantation mask 312 is patterned, dopant species 314 may be implanted through dielectric layer 232 into GaN epitaxial layer 110. In an embodiment, one or more of Si, Ge, O, or other suitable n-type dopants may be implanted through implantation mask 312 into GaN epitaxial layer 110 to form source region 133 and drain region 135. Activation annealing at a temperature between about 1000 degrees Celsius (°C) and about 1300 °C may be used to activate the implants. Structure 319 is produced.

[0055] Now referring to Figure 3 , step 320, according to an embodiment, embodiments of the method may additionally include etching a first portion of GaN epitaxial layer 110, exposing first surface 322 and second surface 323 of Si substrate 101, and forming first device region 120 including GaN epitaxial layer 110 having first sidewall 324 at first edge 326 of the GaN layer and a second device region above the first surface of the Si substrate. In some embodiments, dielectric layer 232 may be stripped after activation annealing and after etching GaN epitaxial layer 110. Passivation dielectric region 127 may be formed over first sidewall 121 and second sidewall 122 and first upper surface 128 of GaN epitaxial layer 110. In an embodiment, passivation dielectric region 127 may include a material selected from SiN, Al2O3, SiO2, AlN, and HfO2. Passivation dielectric region 127 may be formed using one or more of LPCVD, ALD, sputtering, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques. Structure 329 is produced.

[0056] Now referring to Figure 3, Step 330, according to an embodiment, the method may further include forming a first Si layer 152 and a second Si layer 172 above the Si substrate in the second device region by selectively growing the first Si layer 152 and the second Si layer 172 on a first surface 322 and a second surface 323 of the Si substrate 101. Forming the first Si layer 152 and the second Si layer 172 may include epitaxially growing Si using a crystal orientation (e.g., (1 0 0)) that is the same as the crystal orientation of the Si substrate 101. The epitaxial growth of Si may be achieved using CVD, MOCVD, or other suitable crystal growth techniques. After the epitaxial growth of the first Si layer 152 and the second Si layer 172, the first Si layer 152 and the second Si layer 172 may be planarized together with the passivation dielectric region 127 using chemical mechanical polishing (CMP) or other suitable techniques. Structure 339 is produced.

[0057] Now refer to Figure 4 , Step 410, an embodiment of the method may include forming a sacrificial layer 412 above the passivation dielectric region 127 and the first Si layer 152 and the second Si layer 172. In an embodiment, the sacrificial layer 412 may include a material selected from SiN, Al2O3, SiO2, AlN, and HfO2. The sacrificial layer 412 may be formed using one or more of LPCVD, ALD, sputtering, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques. Structure 419 is produced.

[0058] Now refer to Figure 4 , Step 420, an embodiment of the method may include forming isolation regions 153, 173 in the first Si layer 152 and the second Si layer 172 to form a second device region 150 and a third device region 170. In an embodiment, the isolation regions may be formed by etching (e.g., dry etching using an F-based chemical) the first Si layer 152 and the second Si layer 172 and backfilling with a dielectric material (e.g., silicon dioxide). The etching may be achieved using ICP, RIE, ECR dry etching, wet etching, or other suitable etching techniques. The backfilling may be achieved using LPCVD, PVD, PECVD, ICP deposition, ECR deposition, or other suitable techniques. A portion of the sacrificial layer 412 remains above the first Si layer 152 and the second Si layer 172 and above the passivation dielectric region 127. Structure 429 is produced.

[0059] Now refer to Figure 4, Step 430, an embodiment of the method may include stripping the sacrificial layer 412 above the first device region 120, the second device region 150, and the third device region 170. The etching can be achieved using ICP, RIE, ECR dry etching, wet etching, or other suitable etching techniques. The oxide regions within the isolation regions 153, 173 are retained. Structure 439 is produced.

[0060] Now referring to Figure 5 , Step 520, an embodiment of the method may include forming NMOS / PMOS devices 160 and / or SiGe HBT devices 180 in the second device region 150 and the third device region 170. By forming the isolation regions 153, 173 in the first device region 150 and the second device region 170, the NMOS / PMOS devices 160 and / or SiGe HBT devices 180 can be formed using techniques well-known to those skilled in the art.

[0061] In an embodiment, forming the NMOS / PMOS device 160 may include forming an n / p well 156 in the first Si layer 152, and then forming a second source region 161 and a second drain region 163 within the n / p well 156 for ohmic contact with the n / p well 156. The method may further include forming a channel region 165 and a gate oxide 166a within and above the n / p well 156. Gate polysilicon material 166b may be formed above the gate oxide 166a.

[0062] Still referring to Figure 5 , Step 520, in an embodiment, forming the SiGe HBT device 180 may include forming a collector well 176 in the second Si layer 172. According to an embodiment, the method may further include: forming a collector region 183 in the collector well 176; forming a collector contact region 184a; forming a base region 186 above the collector region 183; forming an extrinsic base region 187a above the collector well 176; forming an intrinsic emitter region 181 above the base region 186; and forming an extrinsic emitter region 182a above the intrinsic emitter region 181. Forming the collector well 176, the collector region 183, the collector contact region 184a, the base region 186, the extrinsic base region 187a, and the intrinsic emitter region 181 can be achieved using techniques known to those skilled in the art (such as patterning, diffusion, implantation, etching, etc.). Structure 529 is produced.

[0063] Now referring to Figure 5, Step 540, an embodiment of the method may include forming a first source electrode 132 and a first drain electrode 134 (i.e., "first and second current-carrying electrodes") and a first gate electrode 136 (i.e., "first control electrode") in a first device region 120 above the GaN epitaxial layer 110. The first source electrode 132 and the first drain electrode 134 may be formed by patterning and forming openings in the passivation dielectric region 127 by etching (e.g., dry etching of SiN using an F-based chemical such as SF6 or other suitable chemicals by ICP or RIE) and depositing and patterning ohmic contact metal (e.g., Ti / Al or other suitable metal) above the source region 133 and the drain region 135 using suitable techniques (e.g., PVD and dry etching). In an embodiment, the first gate electrode 136 may be formed by patterning an opening in the passivation dielectric region 127 (e.g., by dry etching SiN), and then depositing (e.g., using PVD) and patterning the gate metal (e.g., using dry etching).

[0064] Still referring to Figure 5 , Step 540, in an embodiment, the method may further include forming a second source electrode 162 and a second drain electrode 164 (i.e., "third and fourth current-carrying electrodes") and forming a second gate electrode 166a / b / c (i.e., "second control electrode") above the gate polysilicon material 166b above the first Si layer 152 in the second device region 150.

[0065] Still referring to Figure 5 , Step 540, in an embodiment, the method may include: forming a collector electrode 184b (i.e., "fourth current-carrying electrode" or "sixth current-carrying electrode") above the collector contact region 184a; forming a base electrode 186b (i.e., "second control electrode" or "third control electrode") above the intrinsic base region 187a; and forming an emitter electrode 182b (i.e., "third current-carrying electrode" or "fifth current-carrying electrode") above the intrinsic emitter region 182b in the third device region 170. The formation of the collector electrode 184b, the base electrode 186b, and the emitter electrode 182b may be achieved using techniques known to those skilled in the art (e.g., patterning, conductor deposition (e.g., in the form of silicide), etching, etc.).

[0066] Still referring to Figure 5, Step 540. According to an embodiment, an embodiment of the method may include depositing and patterning a first interlayer dielectric (ILD) layer 191, a second interlayer dielectric (ILD) layer 193, a first metal layer 192, and a second metal layer 196 over a first device region 120, a second device region 150, and a third device region 170. In an embodiment, according to an embodiment, the first ILD layer 191 may be deposited over a device surface 435. In an embodiment, the first ILD layer 191 may be formed of SiO, TEOS, SiN, or other suitable materials using CVD, PECVD, PVD, or other suitable deposition techniques. In some embodiments, it may be desirable to use a low-stress film (i.e., a film having a stress less than 100 MPa) to implement the first ILD layer 191. Device connection vias 139, 169, 189 may be formed in the first ILD layer 191 by connection with the first metal layer 192 using techniques known to those skilled in the art (e.g., tungsten filling and planarization). The first vias 194 and the second metal layer 196 may be formed using techniques known to those skilled in the art (e.g., tungsten or Cu damascene-filled vias and Al or Cu damascene metal layers). Structure 549 is produced. According to an embodiment, additional processing (not shown) may include additional dielectric layers, vias, metal layers, openings, and bond pads for external connection.

[0067] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that a vast number of variations exist. It should also be understood that one or more of the exemplary embodiments described herein are not intended in any way to limit the scope, applicability, or configuration of the claimed subject matter. Indeed, the foregoing detailed description will provide those skilled in the art with a convenient guide for implementing one or more of the described embodiments. It should be understood that various changes may be made in the function and arrangement of elements without departing from the scope defined by the claims, which scope includes known equivalents and foreseeable equivalents at the time of filing this patent application.

[0068] For the sake of brevity, conventional semiconductor manufacturing techniques may not be described in detail herein. Additionally, certain terms may be used herein for reference purposes only, and thus these terms are not intended to be limiting, and unless the context clearly indicates otherwise, the numerical terms “first,” “second,” and other such terms referring to structures do not imply order or sequence.

[0069] The foregoing description refers to an element or node or feature being “connected” or “coupled” together. As used herein, unless stated otherwise explicitly, “connected” means that an element is directly joined to another element (or directly communicates with another element), and not necessarily joined mechanically. Similarly, unless stated otherwise explicitly, “coupled” means that an element is directly or indirectly joined to another element (or directly or indirectly communicates with another element), and need not be joined mechanically. Thus, although the schematic illustrations shown in the figures depict an exemplary arrangement of elements, additional intervening elements, devices, features or components may be present in embodiments of the subject matter depicted.

Claims

1. A semiconductor device, characterized in that: include: A silicon (Si) base substrate, wherein the Si base substrate has a first crystal orientation; A first device region is formed above the Si base substrate, wherein the first device region comprises: A gallium nitride (GaN) layer, wherein the GaN layer is formed on the Si base substrate; a transition layer having a second crystal orientation, the transition layer being disposed between the GaN layer and the Si base substrate; a channel region formed in the GaN layer; first and second current carrying electrodes formed over the GaN layer, electrically coupled to the first active region, and configured to support current flow within the first active region; and a first control electrode formed above the GaN layer, electrically coupled to the first active region, and configured to control the current flow between the first and second current carrying electrodes; a second device region formed laterally adjacent to the first device region, wherein the second device region comprises: A first Si layer, wherein the first Si layer is formed on the Si base substrate; third and fourth current carrying electrodes formed over the first Si layer and configured to support current flow within an active region of the second device region; and A second control electrode is formed over the first Si layer, electrically coupled to the second device region, and configured to control the current flow between the third and fourth current carrying electrodes.

2. The semiconductor device according to claim 1, wherein: The first crystal orientation is (1 0 0) and the second crystal orientation is (1 1 1).

3. The semiconductor device according to claim 1, wherein: Also included is a bonding layer formed between the transition layer and the Si base substrate.

4. The semiconductor device according to claim 3, wherein: The bonding layer includes a buried oxide layer.

5. The semiconductor device according to claim 1, wherein: The transition layer can include a material selected from the group consisting of: silicon, silicon carbide, gallium nitride, and aluminum nitride.

6. The semiconductor device according to claim 1, wherein: Also included is a passivation dielectric region formed between a first sidewall of the first device region and a second sidewall of the second device region.

7. The semiconductor device according to claim 6, wherein: The passivation dielectric region includes silicon nitride.

8. The semiconductor device according to claim 1, wherein: A first upper surface of the first device region and a second upper surface of the second device region are coplanar.

9. The semiconductor device according to claim 1, wherein: The first current-carrying electrode is configured as a first source electrode; The second current carrying electrode is configured as a first drain electrode; and The first control electrode is configured as a first gate electrode.

10. A method for forming a semiconductor device, characterized in that: The method comprises: forming a bonding layer over a Si base substrate having a first crystal orientation; forming a transition layer having a second crystal orientation over the bonding layer; forming a gallium nitride (GaN) layer on the transition layer; etching a first portion of the GaN layer, exposing a first surface of the Si base substrate and forming a first device region including the GaN layer having a first sidewall at a first edge of the GaN layer and a second device region above the first surface of the Si base substrate; forming first and second current carrying electrodes in the first device region over the GaN layer; forming a first control electrode over the GaN layer in the first device region; forming a first Si layer over the Si base substrate in the second device area; forming third and fourth current carrying electrodes over the Si layer in the second device region; and A second control electrode is formed over the Si layer in the second device region.

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