Semiconductor wafer and semiconductor device

Abstract

The invention discloses a semiconductor wafer and a semiconductor device. The semiconductor wafer includes a first semiconductor die, a second semiconductor die, a filling layer, a transparent conductive layer, and a reflective layer. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The filling layer surrounds a side wall of the first semiconductor die and a side wall of the second semiconductor die. The transparent conductive layer is disposed on the second semiconductor die and the fill layer and electrically connected to the second semiconductor die. And the reflecting layer is arranged on one side wall of the filling layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor wafer and a semiconductor device, and more particularly to a semiconductor wafer and a semiconductor device including a plurality of semiconductor dies. Background Art

[0002] In existing light-emitting diode display devices driven by an active matrix, since the voltage consumed by driving elements (such as thin-film transistors) is greater than the voltage consumed when a single light-emitting diode emits light, it may reduce the energy utilization efficiency or increase the power consumption of the display device. Therefore, how to solve the above problems remains an important issue in this field. Summary of the Invention

[0003] An object of the present invention is to provide a semiconductor wafer and a semiconductor device.

[0004] The present invention provides a semiconductor wafer, which includes a first semiconductor die, a second semiconductor die, a filling layer, a transparent conductive layer, and a reflective layer. The second semiconductor die is disposed on the first semiconductor die and electrically connected to the first semiconductor die. The filling layer surrounds a sidewall of the first semiconductor die and a sidewall of the second semiconductor die. The transparent conductive layer is disposed on the second semiconductor die and the filling layer and electrically connected to the second semiconductor die. The reflective layer is disposed on a sidewall of the filling layer.

[0005] The present invention further provides a semiconductor device, which includes a substrate, a first semiconductor die, a second semiconductor die, a first filling layer, a second filling layer, a first transparent conductive layer, a first reflective layer, and a second reflective layer. The first semiconductor die is disposed on the substrate. The second semiconductor die is disposed on the first semiconductor die and electrically connected to the first semiconductor die. The first filling layer surrounds a sidewall of the first semiconductor die. The second filling layer surrounds a sidewall of the second semiconductor die. The first transparent conductive layer is disposed on the second semiconductor die and electrically connected to the second semiconductor die. The first reflective layer is disposed on a sidewall of the first filling layer. The second reflective layer is disposed on a sidewall of the second filling layer. Brief Description of the Drawings

[0006] Figure 1 A cross-sectional schematic view of a semiconductor wafer according to a first embodiment of the present invention.

[0007] Figure 2 A schematic diagram of the electrical connection manner between the first semiconductor die and the second semiconductor die in the semiconductor wafer of the present invention.

[0008] Figure 3 A cross-sectional schematic view of a semiconductor wafer according to a variant embodiment of a first embodiment of the present invention.

[0009] Figure 4 A cross-sectional schematic view of a semiconductor wafer according to the second embodiment of the present invention.

[0010] Figure 5 A cross-sectional schematic view of a semiconductor device according to the third embodiment of the present invention.

[0011] Figure 6 A cross-sectional schematic view of a semiconductor device according to the fourth embodiment of the present invention.

[0012] Figure 7 A cross-sectional schematic view of a semiconductor device according to the fifth embodiment of the present invention.

[0013] Figure 8 A circuit schematic diagram of the semiconductor device according to the fifth embodiment of the present invention under different operating modes.

[0014] Description of reference numerals: A1, A2 - switching elements; AL1, AL2 - active layers; BL - bonding layer; CE - conductive element; DI1 - first semiconductor die; DI2 - second semiconductor die; DIS - die stack structure; DS - distance; E1 - first electrode; E2 - second electrode; FL - filling layer; FL1 - first filling layer; FL2 - second filling layer; FM - filling material; LO - light-emitting surface; MA - metal material layer; OM - ohmic contact layer; OP, OP1, OP2, OP3, OP4 - openings; PD1, PD2 - bonding pads; PL, IN1, IN2 - insulating layers; RL - reflective layer; RL1 - first reflective layer; RL2 - second reflective layer; S11, S21 - first semiconductor layers; S12, S22 - second semiconductor layers; SB - substrate; SC, SC1, SC2 - semiconductor wafers; SD, SD1, SD2 - semiconductor devices; SL1 - first sub-layer; SL2 - second sub-layer; SO - solder; SR1, SR2, SR3, SR4, SR5, SR6, SR7 - surfaces; SW1, SW2, SW3, SW4, SW5, SW6, SW7 - sidewalls; TL - transparent conductive layer; TL1 - first transparent conductive layer; TL2 - second transparent conductive layer; UF - underfill; W1, W2 - widths; Z - direction; θ1 - included angle. Detailed description of the specific embodiments

[0015] The present invention can be understood by referring to the following detailed description and simultaneously combining the accompanying drawings. It should be noted that, for the convenience of the reader's understanding and for the simplicity of the drawings, only a part of the device is shown in the multiple drawings of the present invention, and the specific elements in the drawings are not drawn according to the actual ratio. In addition, the number and size of each element in the drawings are only for illustration and are not used to limit the scope of the present invention.

[0016] Throughout the specification of the present invention and the appended claims, certain terms will be used to refer to specific elements. Those of ordinary skill in the art should understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names.

[0017] In the specification and claims of the present invention, words such as "comprising" and "including" are open-ended terms, and thus should be interpreted as meaning "including but not limited to...".

[0018] It should be understood that when an element or film layer is said to be "disposed on" or "connected to" another element or film layer, it can be directly on this other element or film layer or directly connected to this other element or film layer, or there may be intervening elements or film layers between the two (non-direct case). On the contrary, when an element is said to be "directly" on another element or film layer or "directly connected to" another element or film layer, there are no intervening elements or film layers between the two. When an element or film layer is said to be "electrically connected" to another element or film layer, it can be interpreted as a direct electrical connection or a non-direct electrical connection. The electrical connections or couplings described in the present invention can refer to either direct connections or indirect connections. In the case of a direct connection, the endpoints of the components on two circuits are directly connected or interconnected by a conductor segment. In the case of an indirect connection, there are switches, diodes, capacitors, inductors, resistors, other suitable components, or combinations of the above components between the endpoints of the components on two circuits, but not limited thereto.

[0019] Although terms such as "first", "second", "third",... may be used to describe various components, the components are not limited to these terms. These terms are only used to distinguish a single component in the specification from other components. The same terms may not be used in the claims, and the first, second, third,... may be used in place of the order in which the components are claimed. Therefore, in the specification of the present invention, the first component may be the second component in the claims.

[0020] In the present invention, the measurement methods of thickness, length, and width can be obtained by measuring with an optical microscope, and the thickness or width can be measured from the cross-sectional image in an electron microscope, but not limited thereto.

[0021] In addition, there may be a certain error between any two values or directions used for comparison. Terms such as "about", "equal to", "equivalent", or "the same", "substantially" or "approximately" are generally interpreted as being within plus or minus 20% of the given value, or within plus or minus 10%, plus or minus 5%, plus or minus 3%, plus or minus 2%, plus or minus 1%, or plus or minus 0.5% of the given value.

[0022] In addition, the terms "a given range from a first value to a second value" and "a given range falls within the range from the first value to the second value" mean that the given range includes the first value, the second value, and other values therebetween.

[0023] If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction can be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the technical field to which the present invention pertains. It is understood that these terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning consistent with the relevant technology and the background or context of the present invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the present invention.

[0025] It should be noted that, without departing from the spirit of the present invention, the technical features in several different embodiments can be replaced, reorganized, and mixed to complete other embodiments in the following examples.

[0026] The semiconductor wafer and semiconductor device of the present invention can be applied to any suitable electronic device, where the electronic device may include a display device, a sensing device, a backlight device, an antenna device, a splicing device, or other suitable devices. The electronic device can be a bendable, flexible, or stretchable electronic device. The display device can be applied to, for example, a laptop computer, a public display, a splicing display, a vehicle display, a touch display, a television, a monitor, a smart phone, a tablet computer, a light source module, a lighting device, or an electronic device applied to the above products, but not limited thereto. The sensing device can include a biosensor, a touch sensor, a fingerprint sensor, other suitable sensors, or a combination of the above types of sensors. The antenna device can be a liquid crystal type antenna device or a non-liquid crystal type antenna device, such as including a liquid crystal antenna device, but not limited thereto. The splicing device can include, for example, a display splicing device or an antenna splicing device, but not limited thereto. The shape of the electronic device can be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device can include an electronic unit, where the electronic unit can include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. The diode can include a light emitting diode or a photodiode. The light emitting diode can include, for example, an organic light emitting diode (OLED) or an inorganic light emitting diode, and the inorganic light emitting diode can include, for example, a mini light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (quantum dot LED), but not limited thereto. It should be noted that the electronic device of the present invention can be various combinations of the above devices, but not limited thereto. The electronic device can have peripheral systems such as a driving system, a control system, a light source system, etc. to support a display device, an antenna device, a wearable device (such as including augmented reality or virtual reality), a vehicle-mounted device (such as including an automotive windshield), or a splicing device.

[0027] Please refer to Figure 1 , Figure 1 FIG. is a cross-sectional schematic view of a semiconductor wafer according to a first embodiment of the present invention. The semiconductor wafer SC of the present invention can be applied to any suitable electronic device, such as a display device, a sensing device, other suitable devices, or a combination of the above devices. As Figure 1 shown, the semiconductor wafer SC of the present invention can include a first semiconductor die DI1, a second semiconductor die DI2, a filling layer FL, a transparent conductive layer TL, and a reflective layer RL, but not limited thereto. The structures and arrangement relationships of the components and film layers in the semiconductor wafer SC will be described in detail below.

[0028] According to the present invention, the semiconductor wafer SC may include a plurality of semiconductor dies, such as two semiconductor dies, but not limited thereto. Specifically, as Figure 1 shown, the semiconductor wafer SC may include a first semiconductor die DI1 and a second semiconductor die DI2, wherein the second semiconductor die DI2 is disposed on the first semiconductor die DI1. Specifically, the first semiconductor die DI1 and the second semiconductor die DI2 may be stacked along the normal direction of the semiconductor wafer SC (i.e., the direction Z, which will not be described further below). In other words, the semiconductor wafer SC may include a die stack structure DIS formed by stacking the first semiconductor die DI1 and the second semiconductor die DI2 along the normal direction of the semiconductor wafer SC. In this embodiment, in a cross-sectional view of the semiconductor wafer SC (such as Figure 1 ), one side of the first semiconductor die DI1 has a sidewall SW1, and this side of the second semiconductor die DI2 has a sidewall SW2, wherein the sidewall SW1 may be flush with the sidewall SW2, but not limited thereto. In addition, the first semiconductor die DI1 further includes a sidewall SW3 relative to the sidewall SW1, and the second semiconductor die DI2 further includes a sidewall SW4 relative to the sidewall SW2, wherein the sidewall SW3 may be flush with the sidewall SW4. In this case, in the cross-sectional view of the semiconductor wafer SC, the first semiconductor die DI1 may have a width W1, and the second semiconductor die DI2 may have a width W2, wherein the width W1 may be substantially the same as the width W2, but not limited thereto. The first semiconductor die DI1 and the second semiconductor die DI2 may include any suitable semiconductor elements, depending on the type or use of the semiconductor wafer SC. The semiconductor elements here may refer to any suitable elements including semiconductor layers or formed by semiconductor processes. For example, in this embodiment, the semiconductor wafer SC may be applied to a display device, and the first semiconductor die DI1 and the second semiconductor die DI2 may include light-emitting diodes, but not limited thereto. The light-emitting diodes may include organic light-emitting diodes (OLEDs) or inorganic light-emitting diodes. The inorganic light-emitting diodes may, for example, include mini light-emitting diodes (mini LEDs), micro light-emitting diodes (micro LEDs), or quantum dot light-emitting diodes (quantum dot LEDs). For example, in this embodiment, the first semiconductor die DI1 and the second semiconductor die DI2 may include micro light-emitting diodes, but not limited thereto. In this case, as Figure 1As shown, the first semiconductor die DI1 may include a first semiconductor layer S11, a second semiconductor layer S12, and an active layer AL1 disposed between the first semiconductor layer S11 and the second semiconductor layer S12; the second semiconductor die DI2 may include a first semiconductor layer S21, a second semiconductor layer S22, and an active layer AL2 disposed between the first semiconductor layer S21 and the second semiconductor layer S22. The above-mentioned first semiconductor layer S11 and the first semiconductor layer S21 may be one of an n-type semiconductor layer and a p-type semiconductor layer, and the second semiconductor layer S12 and the second semiconductor layer S22 may be the other of the n-type semiconductor layer and the p-type semiconductor layer. The first semiconductor layer S11, the active layer AL1, and the second semiconductor layer S12 may be stacked in sequence along the normal direction of the semiconductor wafer SC to form the first semiconductor die DI1, and the first semiconductor layer S21, the active layer AL2, and the second semiconductor layer S22 may be stacked in sequence along the normal direction of the semiconductor wafer SC to form the second semiconductor die DI2, but not limited thereto. In some embodiments, the first semiconductor die DI1 (or the second semiconductor die DI2) may be formed by stacking the second semiconductor layer S12 (or the second semiconductor layer S22), the active layer AL1 (or the active layer AL1), and the first semiconductor layer S11 (or the first semiconductor layer S21) in sequence along the normal direction of the semiconductor wafer SC. In this embodiment, the first semiconductor die DI1 and the second semiconductor die DI2 may be light-emitting diodes that emit the same color of light, but not limited thereto. For example, the first semiconductor die DI1 and the second semiconductor die DI2 may both emit one of red light, green light, or blue light, but not limited thereto. In some embodiments, the first semiconductor die DI1 and the second semiconductor die DI2 may emit different colors of light. In some embodiments, at least one of the first semiconductor die DI1 and the second semiconductor die DI2 includes a light-emitting diode. That is, one of the first semiconductor die DI1 and the second semiconductor die DI2 may include a light-emitting diode, and the other may include other suitable semiconductor components. It should be noted that the application scenario of the semiconductor wafer SC and the structures of the first semiconductor die DI1 and the second semiconductor die DI2 are not limited to the above. In some embodiments, the semiconductor wafer SC may be applied to a sensing device, and at least one of the first semiconductor die DI1 and the second semiconductor die DI2 may include a photodiode. In some embodiments, the semiconductor wafer SC may be applied to other types of electronic devices, and the first semiconductor die DI1 and the second semiconductor die DI2 may include suitable types of semiconductor components.

[0029] According to the present invention, the second semiconductor die DI2 may be electrically connected to the first semiconductor die DI1. Specifically, the first semiconductor die DI1 and the second semiconductor die DI2 may be connected in series with each other. In this case, as Figure 1As shown, the second semiconductor layer S12 of the first semiconductor die DI1 is adjacent to the first semiconductor layer S21 of the second semiconductor die DI2, but not limited thereto. In some embodiments, the first semiconductor layer S11 of the first semiconductor die DI1 is adjacent to the second semiconductor layer S22 of the second semiconductor die DI2. Specifically, the semiconductor wafer SC may further include a bonding layer BL disposed between the first semiconductor die DI1 and the second semiconductor die DI2. The bonding layer BL may include any suitable conductive material and is used to electrically connect the first semiconductor die DI1 and the second semiconductor die DI2. The electrical connection manner of the first semiconductor die DI1 and the second semiconductor die DI2 of the present invention is described in detail below.

[0030] Please refer to Figure 2 , Figure 2 which is a schematic diagram of the electrical connection manner between the first semiconductor die and the second semiconductor die in the semiconductor wafer of the present invention. Specifically, Figure 2 illustrates several embodiments of the electrical connection manner between the first semiconductor die DI1 and the second semiconductor die DI2. It should be noted that, in some embodiments, as Figure 2 shown, the first semiconductor die DI1 and the second semiconductor die DI2 each further include an ohmic contact layer OM. The ohmic contact layer OM of the second semiconductor die DI2 is disposed on the side of the first semiconductor layer S21 away from the active layer AL2 and adjacent to the first semiconductor die DI1, while the ohmic contact layer OM of the first semiconductor die DI1 is disposed on the side of the first semiconductor layer S11 away from the active layer AL1 and away from the second semiconductor die DI2. In other words, the semiconductor die may be formed by sequentially stacking an ohmic contact layer, a first semiconductor layer, an active layer, and a second semiconductor layer along the normal direction of the semiconductor wafer SC, but not limited thereto. The ohmic contact layer OM may include, for example, indium tin oxide (ITO), but not limited thereto.

[0031] In some embodiments, the first semiconductor die DI1 and the second semiconductor die DI2 may be electrically connected to each other, for example, by a metal-metal bonding method. Specifically, as Figure 2As shown in Structure (I), a metal material layer MA can be first formed on one side of the first semiconductor die DI1 adjacent to the second semiconductor die DI2, and another metal material layer MA can be formed on one side of the second semiconductor die DI2 adjacent to the first semiconductor die DI1. That is, the metal material layer MA of the first semiconductor die DI1 can be formed on the second semiconductor layer S12, and the metal material layer MA of the second semiconductor die DI2 can be formed under the ohmic contact layer OM, but not limited thereto. Then, the first semiconductor die DI1 and the second semiconductor die DI2 can be bonded by bringing the metal material layer MA of the first semiconductor die DI1 into contact with the metal material layer MA of the second semiconductor die DI2. The metal material layer MA can include, for example, copper, but not limited thereto. In this case, the bonding layer BL can refer to the conductive structure formed by the metal material layer MA. The bonding layer BL can include a single-layer structure or a multi-layer structure, depending on the materials or structures of the metal material layer MA of the first semiconductor die DI1 and the metal material layer MA of the second semiconductor die DI2. For example, in some embodiments, the bonding layer BL can include a single-layer structure formed by one metal material. In some embodiments, the bonding layer BL can include a multi-layer structure formed by stacking multiple metal materials.

[0032] In some embodiments, the first semiconductor die DI1 and the second semiconductor die DI2 can be electrically connected to each other, for example, by solder bonding. Specifically, as Figure 2 As shown in Structure (II), a metal material layer MA can be first formed on one side of the first semiconductor die DI1 adjacent to the second semiconductor die DI2, and another metal material layer MA can be formed on one side of the second semiconductor die DI2 adjacent to the first semiconductor die DI1. The features of the metal material layer MA can be referred to the above, so they will not be elaborated here. Then, the metal material layer MA of the first semiconductor die DI1 can be bonded to the metal material layer MA of the second semiconductor die DI2 through a solder SO to electrically connect the first semiconductor die DI1 and the second semiconductor die DI2. That is, the solder SO is sandwiched between the metal material layer MA of the first semiconductor die DI1 and the metal material layer MA of the second semiconductor die DI2. In this case, the bonding layer BL can refer to the multi-layer conductive structure formed by stacking the metal material layer MA and the solder SO.

[0033] In some embodiments, the first semiconductor die DI1 and the second semiconductor die DI2 can be electrically connected to each other, for example, by fusion bonding. Specifically, as Figure 2As shown in the structure (III), the ohmic contact layer OM of the second semiconductor die DI2 can directly contact the second semiconductor layer S12 of the first semiconductor die DI1 to electrically connect the first semiconductor die DI1 and the second semiconductor die DI2, but this is not limited thereto. In some embodiments, the semiconductor die may not include the ohmic contact layer OM, and the first semiconductor layer S21 of the second semiconductor die DI2 can directly contact the second semiconductor layer S12 of the first semiconductor die DI1. In this case, the first semiconductor die DI1 may not be electrically connected to the second semiconductor die DI2 through the bonding layer BL, that is, the semiconductor wafer SC may not include the bonding layer BL.

[0034] It should be noted that Figure 2 the electrical connection manner of the first semiconductor die DI1 and the second semiconductor die DI2 shown is only exemplary, and the present invention is not limited thereto. The first semiconductor die DI1 and the second semiconductor die DI2 can be electrically connected to each other through other suitable manners.

[0035] Return reference Figure 1, the semiconductor wafer SC of the present invention further includes a filling layer FL, where the filling layer FL can surround the sidewalls of the first semiconductor die DI1 (such as sidewalls SW1 and SW3) and the sidewalls of the second semiconductor die DI2 (such as sidewalls SW2 and SW4). Specifically, in a top view (not shown) of the semiconductor wafer SC, the filling layer FL can be disposed along the outer edges of the first semiconductor die DI1 and the second semiconductor die DI2 and surround the first semiconductor die DI1 and the second semiconductor die DI2. In this case, the filling layer FL can contact the sidewalls of the first semiconductor die DI1 and the second semiconductor die DI2. In detail, the first semiconductor die DI1 and the second semiconductor die DI2 can be bonded in the above manner to form a die stack structure DIS first, and then the filling layer FL can be disposed to surround the die stack structure DIS. In this embodiment, the filling layer FL can also partially contact the surface of the first semiconductor die DI1 away from the second semiconductor die DI2, but not limited thereto. For example, the first semiconductor die DI1 can include a surface SR1 away from the second semiconductor die DI2, and the filling layer FL can partially cover the surface SR1. Specifically, the filling layer FL can include a surface SR2 adjacent to the surface SR1, where the surface SR2 can be located below the surface SR1, and a part of the filling layer FL can extend on the surface SR1 and partially cover the surface SR1. In some embodiments, the surface SR1 can be flush with the surface SR2. The portion of the surface SR1 not covered by the filling layer FL can be used to dispose a first electrode E1 electrically connected to the first semiconductor die DI1. In addition, in this embodiment, the filling layer FL may not cover the surface of the second semiconductor die DI2 away from the first semiconductor die DI1. For example, the second semiconductor die DI2 can include a surface SR3 away from the first semiconductor die DI1, and the filling layer FL may not cover the surface SR3. Specifically, the filling layer FL can include a surface SR4 adjacent to the surface SR3, where the surface SR4 can be flush with the surface SR3, but not limited thereto. By this setting method, it is beneficial to subsequently dispose a transparent conductive layer TL on the filling layer FL and the second semiconductor die DI2. The filling layer FL can include any suitable material with a high light transmittance, such as acrylic, siloxane, silica, other suitable materials, or a combination of the above materials. For example, the filling layer FL of this embodiment can have a light transmittance greater than 90% for visible light. According to the present invention, in a top view of the semiconductor wafer SC, the outer edge shape of the semiconductor wafer SC can be determined by the outer edge shape of the filling layer FL, that is, the outer edge shape of the filling layer FL can be determined according to the shape requirements of the semiconductor wafer SC. For example, in one embodiment, the outer edge of the filling layer FL (such as the outer edge of the surface SR4 or the outer edge of the surface SR2) can be circular, so that the semiconductor wafer SC has a circular contour in a top view. In one embodiment, the outer edge of the filling layer FL can be rectangular, so that the semiconductor wafer SC has a rectangular contour in a top view.In addition, in a cross-sectional view of the semiconductor wafer SC, the filling layer FL may have sidewalls SW5, where the sidewalls SW5 are connected between the surface SR4 and the surface SR2 of the filling layer FL. In this embodiment, the sidewalls SW5 may not be perpendicular to the surface SR2 and the surface SR4, and the sizes (such as areas) of the surface SR2 and the surface SR4 may be different. For example, the size of the surface SR2 is smaller than the size of the surface SR4, but this is not limiting. In this case, an included angle θ1 may exist between the sidewalls SW5 and the surface SR2. According to this embodiment, the range of the included angle θ1 may be from 100 degrees to 170 degrees (i.e., 100° ≤ θ1 ≤ 170°), but this is not limiting. In some embodiments, the range of the included angle θ1 may be from 110 degrees to 150 degrees (i.e., 110° ≤ θ1 ≤ 150°). The value of the included angle θ1 can be determined by the shape design of the filling layer FL. Through the above design of the range of the included angle θ1, the light-emitting effect of the semiconductor wafer SC can be improved after the subsequent setting of the reflective layer RL. In some embodiments, the intersection of the sidewalls SW5 and the surface SR2 is arc-shaped in the cross-sectional view. Specifically, an arc-shaped surface exists between the sidewalls SW5 and the surface SR2.

[0036] According to the present invention, the semiconductor wafer SC may further include a first electrode E1, where the first electrode E1 is disposed under the first semiconductor die DI1 and electrically connected to the first semiconductor die DI1. Specifically, as Figure 1 shown, the first electrode E1 may be disposed corresponding to the portion of the surface SR1 of the first semiconductor die DI1 that is not covered by the filling layer FL. Or, in other words, the portion of the filling layer FL extending on the surface SR1 may include an opening OP, and the first electrode E1 may be filled into the opening OP. The first electrode E1 may contact the first semiconductor die DI1, or in other words, contact the first semiconductor layer S11 of the first semiconductor die DI1, but this is not limiting. In some embodiments, the first electrode E1 may contact the above-mentioned ohmic contact layer OM. The first electrode E1 may include any suitable conductive material, such as a metal material or a transparent conductive material.

[0037] According to the present invention, the semiconductor wafer SC further includes a reflective layer RL disposed on the sidewall (e.g., sidewall SW5) of the filling layer FL. Specifically, the reflective layer RL can surround the filling layer FL and cover the side surface of the filling layer FL. In addition, in this embodiment, the reflective layer RL can further extend on the surface SR2 of the filling layer FL but does not contact the first electrode E1. Specifically, in the bottom view of the semiconductor wafer SC (or viewed from the bottom of the semiconductor wafer SC), the portion of the reflective layer RL located on the surface SR2 can have an annular structure, where the annular structure can expose at least a part of the first electrode E1 and the filling layer FL. The reflective layer RL can have high reflectivity and conductivity. For example, in some embodiments, the reflective layer RL can include a single-layer structure, and in this case, a highly reflective conductive material can be selected as the material of the reflective layer RL, such as silver (Ag) or aluminum (Al), but not limited thereto. That is, the reflective layer RL can include a metal material. In other embodiments, the reflective layer RL can include a multi-layer structure, where each sub-layer in the multi-layer structure can be respectively selected with a highly reflective or conductive material. In some embodiments, the first electrode E1 and the reflective layer RL can include the same material, or the first electrode E1 and the reflective layer RL can be formed by the same process. By providing the reflective layer RL, the light emitted by the first semiconductor die DI1 and the second semiconductor die DI2 can be reflected by the reflective layer RL, thereby increasing the light output. It should be noted that the above included angle θ1 can also be regarded as the included angle between a part of the reflective layer RL extending on the surface SR2 and another part of the reflective layer RL extending on the sidewall SW5. By making the included angle θ1 fall within the above range, the light output effect of the semiconductor wafer SC can be improved.

[0038] According to the present invention, the semiconductor wafer SC further includes a transparent conductive layer TL disposed on the second semiconductor die DI2 and the filling layer FL. Specifically, the transparent conductive layer TL may be disposed on the surface SR3 of the second semiconductor die DI2 and the surface SR4 of the filling layer FL, and contact the second semiconductor die DI2 and the filling layer FL. In detail, the transparent conductive layer TL may directly contact the second semiconductor layer S22 of the second semiconductor die DI2. Thus, the transparent conductive layer TL can be electrically connected to the second semiconductor die DI2. The transparent conductive layer TL may include any suitable transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium oxide (IGO), but is not limited thereto. In some embodiments, the transparent conductive layer TL may include a metal with a high light transmittance, such as magnesium (Mg), silver (Ag), but is not limited thereto. Specifically, a very thin metal layer (such as a magnesium layer, a silver layer, or a magnesium-silver alloy layer) may be formed as the transparent conductive layer TL. In some embodiments, a metal mesh layer with light-transmitting openings may be formed by screen printing or other patterning processes to form the transparent conductive layer TL. In addition, according to this embodiment, the transparent conductive layer TL may also be disposed on the reflective layer RL and contact the reflective layer RL. For example, the transparent conductive layer TL may also extend on the surface SR5 of the reflective layer RL. In this case, the transparent conductive layer TL can be electrically connected to the second semiconductor die DI2 and the reflective layer RL, or in other words, the transparent conductive layer TL is electrically connected between the second semiconductor die DI2 and the reflective layer RL. In this embodiment, the transparent conductive layer TL may be disposed entirely on the second semiconductor die DI2, the filling layer FL, and the reflective layer RL, but is not limited thereto. In other embodiments, as long as the transparent conductive layer TL can be electrically connected to the second semiconductor die DI2 and the reflective layer RL, the transparent conductive layer TL may have any suitable pattern.

[0039] According to the present invention, the semiconductor wafer SC may further include a second electrode E2, wherein the second electrode E2 is disposed below the filling layer FL. Specifically, in the present embodiment, a part of the reflective layer RL extending on the surface SR2 of the filling layer FL (or a part of the reflective layer RL not disposed on the sidewall of the filling layer FL) may be defined as the second electrode E2. In this case, the second electrode E2 is located below the filling layer FL and is electrically connected to the reflective layer RL, and is electrically connected to the transparent conductive layer TL through the reflective layer RL. That is, the second semiconductor die DI2 can be electrically connected to the second electrode E2 through the transparent conductive layer TL and the reflective layer RL. In addition, the material of the second electrode E2 may be the same as the material of the reflective layer RL. In the present embodiment, one of the first electrode E1 and the second electrode E2 may be used as a p-pole electrode, and the other may be used as an n-pole electrode, depending on the types of the above-mentioned first semiconductor layer and second semiconductor layer. According to the present embodiment, through the above structural design, the first electrode E1 electrically connected to the first semiconductor die DI1 and the second electrode E2 electrically connected to the second semiconductor die DI2 can be located on the same side of the semiconductor wafer SC. Thus, when the semiconductor wafer SC is subsequently bonded to other electronic units through the first electrode E1 and the second electrode E2, the semiconductor wafer SC can be bonded to other electronic units in a flip chip manner, for example. In this case, the semiconductor wafer SC of the present embodiment may have a vertical embedded flip chip structure. Specifically, the first semiconductor die DI1 and the second semiconductor die DI2 in the semiconductor wafer SC may include vertical type light emitting diode elements. After encapsulating the first semiconductor die DI1 and the second semiconductor die DI2 through the filling layer FL and disposing elements such as the reflective layer RL, the first electrode E1, and the transparent conductive layer TL, the semiconductor wafer SC can be bonded to other electronic units in a flip chip manner through the first electrode E1 and the second electrode E2 located on the same side. It should be noted that the semiconductor wafer SC of the present invention may also have other suitable structures, and is not limited to Figure 1 the structure shown.

[0040] According to the present embodiment, by making the semiconductor wafer SC include a plurality of semiconductor dies connected in series with each other, during the process of driving the semiconductor wafer SC to emit light, the voltage consumed by the semiconductor wafer SC can increase, or the proportion of the voltage consumed by the semiconductor wafer SC in the overall voltage consumed during the driving process of the semiconductor wafer SC can increase. Thus, the energy utilization efficiency of the electronic device to which the semiconductor wafer SC is applied can be improved, or the driving efficiency of the semiconductor wafer SC can be improved. It should be noted that the semiconductor wafer SC of the present invention may further include other suitable elements or film layers, and is not limited to Figure 1The structure shown is limited. More embodiments of the present invention will be described hereinafter. For the sake of simplicity, the same film layers or components in the following embodiments will be labeled with the same notations, and their features will not be repeated. The differences between the embodiments will be described in detail hereinafter.

[0041] Please refer to Figure 3 , Figure 3 is a cross-sectional schematic view of a semiconductor wafer of a variant embodiment of the first embodiment of the present invention. In this variant embodiment, the sizes of the two semiconductor dies in the semiconductor wafer SC1 may be different. Specifically, the size of the semiconductor die closer to the light-emitting surface of the semiconductor wafer SC1 in the semiconductor wafer SC1 may be smaller than the size of the semiconductor die farther from the light-emitting surface of the semiconductor wafer SC1, but not limited thereto. In detail, as Figure 3 shown, the semiconductor wafer SC1 may have a light-emitting surface LO, where the light-emitting surface LO is located on the side where the transparent conductive layer TL is located. For example, the surface of the transparent conductive layer TL away from the filling layer FL may be defined as the light-emitting surface LO of the semiconductor wafer SC1, but not limited thereto. According to this variant embodiment, in the die stack structure DIS, the second semiconductor die DI2 may be closer to the light-emitting surface LO than the first semiconductor die DI1, and the size of the second semiconductor die DI2 may be smaller than the size of the first semiconductor die DI1. Here, the "size of the first semiconductor die DI1 (or the second semiconductor die DI2)" may refer to the width of the first semiconductor die DI1 (or the second semiconductor die DI2) in the cross-sectional view of the semiconductor wafer SC1, but not limited thereto. For example, as Figure 3As shown, in a cross-sectional view of a semiconductor wafer SC1, a first semiconductor die DI1 may have a width W1, and a second semiconductor die DI2 may have a width W2, where the width W2 may be smaller than the width W1. The width W1 of the first semiconductor die DI1 may be defined as the maximum width of the first semiconductor die DI1, and the width W2 of the second semiconductor die DI2 may be defined as the maximum width of the second semiconductor die DI2. In this case, in the cross-sectional view of the semiconductor wafer SC1, the sidewall SW1 of the first semiconductor die DI1 may not be flush with the sidewall SW2 of the second semiconductor die DI2, or the sidewall SW3 of the first semiconductor die DI1 may not be flush with the sidewall SW4 of the second semiconductor die DI2. In some embodiments, the "size of the first semiconductor die DI1 (or the second semiconductor die DI2)" as described above may refer to the area of the first semiconductor die DI1 (or the second semiconductor die DI2) in a top view of the semiconductor wafer SC1, but is not limited thereto. In other words, in the top view of the semiconductor wafer SC1, the area of the second semiconductor die DI2 may be smaller than the area of the first semiconductor die DI1. That is, the second semiconductor die DI2 does not cover at least a part of the first semiconductor die DI1. Through the above size design, the influence of the second semiconductor die DI2 on the light-emitting effect of the first semiconductor die DI1 can be reduced, thereby improving the light extraction effect of the semiconductor wafer SC, or improving the display effect of the electronic device (such as a display device) to which the semiconductor wafer SC is applied. It should be noted that the size relationship between the first semiconductor die DI1 and the second semiconductor die DI2 in this variant embodiment can be applied to all embodiments and variant embodiments of the present invention.

[0042] In addition, the reflective layer RL of this variant embodiment may include a multi-layer structure. For example, as Figure 3As shown, the reflective layer RL may include a first sub-layer SL1 and a second sub-layer SL2, but is not limited thereto. The first sub-layer SL1 may be disposed on the sidewall (e.g., sidewall SW5) of the filling layer FL, and the second sub-layer SL2 may be disposed on the first sub-layer SL1. That is, the first sub-layer SL1 may be located between the second sub-layer SL2 and the filling layer FL. The reflectivity of the first sub-layer SL1 to visible light may be greater than that of the second sub-layer SL2 to visible light, and the conductivity of the second sub-layer SL2 may be greater than that of the first sub-layer SL1. Thus, the first sub-layer SL1 may be used to reflect the light emitted by the first semiconductor die DI1 and the second semiconductor die DI2, and the second sub-layer SL2 may be used to electrically connect the reflective layer RL (or the second electrode E2) to the transparent conductive layer TL. The first sub-layer SL1 may include any suitable element or film layer with high reflectivity, such as a distributed bragg reflector (DBR), but is not limited thereto. The second sub-layer SL2 may include a material with high conductivity, such as gold (Au), silver (Ag), or copper (Cu), but is not limited thereto. The first sub-layer SL1 and the second sub-layer SL2 may respectively include a single-layer structure or a multi-layer structure, and the present invention is not limited thereto. It should be noted that the structure of the reflective layer RL in this variant embodiment can be applied to various embodiments and variant embodiments of the present invention.

[0043] Please refer to Figure 4 , Figure 4 a cross-sectional schematic view of a semiconductor wafer according to the second embodiment of the present invention. One of the main differences between the semiconductor wafer SC2 of this embodiment and the Figure 1 semiconductor wafer SC shown lies in the setting position of the reflective layer RL. Specifically, as Figure 4As shown, the reflective layer RL in the semiconductor wafer SC2 can be disposed on the sidewall (such as sidewall SW5) of the filling layer FL, extend on the surface SR2 of the filling layer FL, and contact the first electrode E1. In this case, the reflective layer RL can be electrically connected to the first electrode E1. In addition, in this embodiment, the reflective layer RL may not contact the transparent conductive layer TL, or in other words, may not be electrically connected to the transparent conductive layer TL. Specifically, the reflective layer RL does not contact the transparent conductive layer TL and the first electrode E1 simultaneously. It should be noted that in other embodiments, the reflective layer RL may contact the transparent conductive layer TL but not contact the first electrode E1. Through the above structural design, when the semiconductor wafer SC2 is bonded to other electronic units, the contact area between the first electrode E1 and other electronic units can be increased, thereby improving the bonding process of the semiconductor wafer SC2. In some embodiments, the reflective layer RL may be disposed only on the sidewall SW5 of the filling layer FL, that is, the reflective layer RL does not contact the first electrode E1 and the transparent conductive layer TL. In some embodiments, regardless of whether the reflective layer RL contacts the first electrode E1 and / or the transparent conductive layer TL, the reflective layer RL may not be electrically connected to the first electrode E1 and / or the transparent conductive layer TL. For example, the reflective layer RL may only include a highly reflective material and does not need to include a conductive material.

[0044] In this embodiment, the transparent conductive layer TL of the semiconductor wafer SC2 can serve as an electrode electrically connected to the second semiconductor die DI2, that is, the second electrode E2 described above. In other words, the first electrode E1 and the second electrode E2 of the semiconductor wafer SC2 can be located on opposite sides of the semiconductor wafer SC2 respectively. In this case, the semiconductor wafer SC2 can have a vertical embedded chip structure. Specifically, the first semiconductor die DI1 and the second semiconductor die DI2 can include vertical type light emitting diode elements and be embedded in the filling layer FL to form the semiconductor wafer SC2.

[0045] In addition, in this embodiment, the semiconductor wafer SC2 may further include an insulating layer PL disposed on the sidewall SW6 of the reflective layer RL. As Figure 4 shown, the insulating layer PL can be disposed conformally with the reflective layer RL generally and can cover the reflective layer RL. That is, the insulating layer PL may not expose the reflective layer RL. The insulating layer PL can include any suitable insulating material and can be used to provide a protective effect (such as a waterproof and oxygen-proof effect) for the components and / or film layers (such as the first semiconductor die DI1, the second semiconductor die DI2, and the reflective layer RL) in the semiconductor wafer SC2. The insulating layer PL in this embodiment can be applied to the semiconductor wafers in various embodiments and variant embodiments of the present invention.

[0046] In addition, in the present embodiment, the first semiconductor die DI1 in the semiconductor wafer SC2 may not be flush with the second semiconductor die DI2, but this is not limiting. Specifically, in the bonding process of the first semiconductor die DI1 and the second semiconductor die DI2, an offset between the first semiconductor die DI1 and the second semiconductor die DI2 may occur due to process tolerances, but this is not limiting. In detail, in a cross-sectional view of the semiconductor wafer SC2, the sidewall SW1 of the first semiconductor die DI1 may not be flush with the sidewall SW2 of the second semiconductor die DI2, or the sidewall SW3 of the first semiconductor die DI1 may not be flush with the sidewall SW4 of the second semiconductor die DI2. In this case, a distance DS may exist between the sidewall SW1 of the first semiconductor die DI1 and the sidewall SW2 of the second semiconductor die DI2, where the range of the distance DS may be from 0 to 3 micrometers (i.e., 0 ≤ DS ≤ 3 μm), but this is not limiting. The distance DS here can be regarded as the offset distance of the second semiconductor die DI2 offset from the first semiconductor die DI1.

[0047] Please refer to Figure 5 , Figure 5 a cross-sectional schematic view of a semiconductor device according to a third embodiment of the present invention. The semiconductor device SD of the present invention may include any suitable electronic device, such as a display device, a sensing device, other suitable devices, or a combination of the above devices. As Figure 5 shown, the semiconductor device SD may include a substrate SB, a first semiconductor die DI1, a first semiconductor die DI2, a first filling layer FL1, a second filling layer FL2, a first reflective layer RL1, a second reflective layer RL2, and a first transparent conductive layer TL1, but this is not limiting. The structures and setting relationships of the various elements and film layers in the semiconductor device SD will be described in detail below.

[0048] According to the present embodiment, the substrate SB may include a driving substrate, such as an array substrate, but this is not limiting. For example, although Figure 5Not shown, the substrate SB may include a base and a circuit layer disposed on the base. The base may support the components and film layers located thereon. The base may include a rigid material or a flexible material. Rigid materials include, for example, glass, quartz, sapphire, ceramics, other suitable materials, or combinations of the above materials. Flexible materials include, for example, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials, or combinations of the above materials. The circuit layer may include various wires, circuits, and electronic units applicable to the semiconductor device SD. The electronic units may include any suitable active components and / or passive components. For example, the circuit layer may include a structure formed by stacking a conductive layer and an insulating layer, where the conductive layer may form the above-mentioned wires, circuits, or electronic units, but is not limited thereto. The circuit layer may include a driving unit, where the driving unit may be electrically connected to the first semiconductor die DI1 and the second semiconductor die DI2, thereby controlling the light emission of the first semiconductor die DI1 and the second semiconductor die DI2. The driving unit may include, for example, thin film transistor (TFT) elements, but is not limited thereto. It should be noted that the circuit layer may also include other suitable electronic units and is not limited to the above.

[0049] The first semiconductor die DI1, the first filling layer FL1, and the first reflective layer RL1 may be disposed on the substrate SB. Specifically, the semiconductor device SD further includes an insulating layer IN1 disposed on the substrate SB, where the insulating layer IN1 includes an opening OP1, and the first semiconductor die DI1, the first filling layer FL1, and the first reflective layer RL1 may be disposed in the opening OP1. The first filling layer FL1 may surround the sidewall (e.g., sidewall SW1) of the first semiconductor die DI1. Specifically, in a top view (not shown) of the semiconductor device SD, the first filling layer FL1 may be disposed along the outer edge of the first semiconductor die DI1 and surround the first semiconductor die DI1. The first reflective layer RL1 may be disposed on the sidewall SW5 of the first filling layer FL1. Specifically, the first reflective layer RL1 may surround the first filling layer FL1 and cover the side surface of the first filling layer FL1. In this embodiment, the first reflective layer RL1 may further extend on the surface SR2 of the first filling layer FL1, but is not limited thereto. In some embodiments, the first reflective layer RL1 may be disposed only on the sidewall SW5 of the first filling layer FL1 and does not extend on the surface SR2. The semiconductor device SD of this embodiment may further include a first electrode E1, where the first electrode E1 may be disposed in the opening OP1. Specifically, the first electrode E1 may be disposed under the first semiconductor die DI1 and electrically connected to the first semiconductor die DI1. For example, the first electrode E1 may contact the surface SR1 of the first semiconductor die DI1 facing the substrate SB, but is not limited thereto. The first electrode E1 may be used to electrically connect the first semiconductor die DI1 to the substrate SB, or rather, to the circuit layer of the substrate SB. For example, the opening OP1 may expose the bonding pad PD1 in the circuit layer of the substrate SB, and the first electrode E1 may be disposed on the bonding pad PD1 and electrically connected to the bonding pad PD1 to electrically connect the first semiconductor die DI1 to the circuit layer, such as electrically connecting to a driving unit in the circuit layer, but is not limited thereto. The material selection or structural features of the first electrode E1 and the first semiconductor die DI1 may refer to the above description and will not be elaborated here. The material of the first filling layer FL1 may refer to the material of the above filling layer FL. The material of the first reflective layer RL1 may refer to the material of the above reflective layer RL. It should be noted that in some embodiments, the first reflective layer RL1 may have high reflectivity and conductivity. In this case, although not shown in the figure, the first reflective layer RL1 may contact the first electrode E1 and be electrically connected to the first electrode E1 to improve the bonding between the first electrode E1 and the bonding pad PD1. In some embodiments, the first reflective layer RL1 may have high reflectivity but no conductivity. In this embodiment, the bonding pad PD1 may include any suitable conductive material, such as gold (Au), tin (Sn), indium (In), copper (Cu), or other suitable metal materials, but is not limited thereto.

[0050] In this embodiment, the first semiconductor die DI1 may be encapsulated by first being embedded in the first filling layer FL1 and then transferred to the opening OP1 of the insulating layer IN1, but it is not limited thereto. Specifically, the first semiconductor die DI1 may be provided first, and the first filling layer FL1 surrounding the first semiconductor die DI1, the first reflective layer RL1 surrounding the first filling layer FL1, and the first electrode E1 may be provided to form an encapsulation structure. Then, the insulating layer IN1 may be provided on the substrate SB, the opening OP1 may be formed in the insulating layer IN1, and the above encapsulation structure including the first semiconductor die DI1 may be disposed in the opening OP1 with the first electrode E1 facing the bonding pad PD1, such that the first electrode E1 is electrically connected to the bonding pad PD1, thereby completing the setting of the first semiconductor die DI1. In other embodiments, the first semiconductor die DI1, the first filling layer FL1, the first reflective layer RL1, and the first electrode E1 may be disposed in the opening OP1 in a suitable order.

[0051] According to this embodiment, the semiconductor device SD may further include an underfill UF disposed in the opening OP1. Specifically, after the above encapsulation structure including the first semiconductor die DI1 is disposed in the opening OP1, the underfill UF may be filled in the opening OP1 to fix the first semiconductor die DI1, or rather, fix the encapsulation structure including the first semiconductor die DI1. In this case, the underfill UF may contact the first reflective layer RL1. The underfill UF may include acrylic, silicone, silica, other suitable materials, or a combination of the above materials. The underfill UF may at least expose the surface SR6 of the first semiconductor die DI1 away from the substrate SB, such that a second semiconductor die DI2 electrically connected to the first semiconductor die DI1 may be provided on the first semiconductor die DI1 subsequently. In this embodiment, the upper surfaces (or rather, the surfaces away from the substrate SB) of the insulating layer IN1, the underfill layer UF, the first reflective layer RL1, the first filling layer FL1, and the first semiconductor die DI1 may be coplanar, but it is not limited thereto. In other embodiments, as long as the surface SR6 of the first semiconductor die DI1 is not covered by the underfill UF, any suitable height relationship may exist between the upper surfaces of the insulating layer IN1, the underfill layer UF, the first reflective layer RL1, the first filling layer FL1, and the first semiconductor die DI1.

[0052] According to this embodiment, the second semiconductor die DI2 can be disposed on the first semiconductor die DI1 and electrically connected to the first semiconductor die DI1. In this way, the first semiconductor die DI1 and the second semiconductor die DI2 can form a die stack structure DIS. Specifically, the semiconductor device SD further includes an insulating layer IN2 disposed on the insulating layer IN1, where the insulating layer IN2 may include an opening OP2, and the second semiconductor die DI2 is disposed in the opening OP2. The opening OP2 can correspond to the opening OP1, or rather the opening OP2 at least partially overlaps the opening OP1 in the normal direction (i.e., the direction Z) of the semiconductor device SD, such that the second semiconductor die DI2 can be electrically connected to the first semiconductor die DI1. In detail, after the underfill UF is disposed, the insulating layer IN2 can be disposed on the insulating layer IN1, and an opening OP2 corresponding to the opening OP1 is formed in the insulating layer IN2, where the opening OP2 can expose the first semiconductor die DI1, or rather expose the surface SR6 of the first semiconductor die DI1. Then, the second semiconductor die DI2 can be disposed at a position corresponding to the first semiconductor die DI1 in the opening OP2 to electrically connect the second semiconductor die DI2 to the first semiconductor die DI1. Specifically, the semiconductor device SD further includes a bonding layer BL disposed between the first semiconductor die DI1 and the second semiconductor die DI2, where the bonding layer BL can be used to electrically connect the first semiconductor die DI1 and the second semiconductor die DI2. Regarding the electrical connection manner between the first semiconductor die DI1 and the second semiconductor die DI2 and the structural features of the bonding layer BL, reference can be made to Figure 2 and the above content, so it will not be elaborated here. It should be noted that during the process of disposing the second semiconductor die DI2, the second semiconductor die DI2 may be offset from the first semiconductor die DI1 due to process tolerances. In this case, as Figure 5 shown, the sidewall SW2 of the second semiconductor die DI2 can be offset from the sidewall SW1 of the first semiconductor die DI1. The range of the offset distance between the sidewall SW2 and the sidewall SW1 can refer to the range of the above distance DS, so it will not be elaborated here.

[0053] According to this embodiment, the second filling layer FL2 can be disposed in the opening OP2 and surround the sidewall (such as the sidewall SW2) of the second semiconductor die DI2. Specifically, in a top view (not shown) of the semiconductor device SD, the second filling layer FL2 can be disposed along the outer edge of the second semiconductor die DI2 and surround the second semiconductor die DI2. The second reflective layer RL2 can be disposed in the opening OP2 and on the sidewall SW7 of the second filling layer FL2. Specifically, the second reflective layer RL2 can surround the second filling layer FL2 and cover the side surface of the second filling layer FL2. The second reflective layer RL2 is not connected to the first reflective layer RL1, or in other words, the first reflective layer RL1 and the second reflective layer RL2 are discontinuous, but this is not limiting. In some embodiments, after the second semiconductor die DI2 is disposed, the second reflective layer RL2 can be formed on the sidewall of the opening OP2 first, and then the second filling layer FL2 can be disposed between the second reflective layer RL2 and the second semiconductor die DI2. In some embodiments, after the second semiconductor die DI2 is disposed, the second filling layer FL2 surrounding the second semiconductor die DI2 can be disposed in the opening OP2 first, and then the second reflective layer RL2 can be disposed between the second filling layer FL2 and the sidewall of the opening OP2. The surface SR3 of the second semiconductor die DI2 away from the first semiconductor die DI1 can be not lower than the upper surface of the insulating layer IN2 (i.e., the surface SR7), so that the first transparent conductive layer TL1 disposed on the insulating layer IN2 subsequently can contact the second semiconductor die DI2 and thus be electrically connected to the second semiconductor die DI2. For example, in this embodiment, the upper surfaces of the insulating layer IN2, the second reflective layer RL2, the second filling layer FL2, and the second semiconductor die DI2 (or the surface away from the substrate SB) can be coplanar with each other, but this is not limiting. The material selection or structural features of the second semiconductor die DI2 can refer to the above description and will not be elaborated here. The material of the second filling layer FL2 can refer to the material of the filling layer FL described above. The material of the second reflective layer RL2 can refer to the material of the reflective layer RL described above. It should be noted that, in some embodiments, the second reflective layer RL2 can have high reflectivity and conductivity. In some embodiments, the second reflective layer RL2 can have high reflectivity but no conductivity.

[0054] According to this embodiment, the first transparent conductive layer TL1 can be disposed on the second semiconductor die DI2 and electrically connected to the second semiconductor die DI2. Specifically, the first transparent conductive layer TL1 can be disposed on the insulating layer IN2 and extend through the opening OP2 to contact the second semiconductor die DI2 and thus be electrically connected to the second semiconductor die DI2. The material of the first transparent conductive layer TL1 can refer to the material of the transparent conductive layer TL described above. According to this embodiment, the first transparent conductive layer TL1 can be electrically connected to the substrate SB, or in other words, electrically connected to the circuit layer of the substrate SB. Specifically, as Figure 5As shown, the semiconductor device SD may include an opening OP3, which may be formed by removing portions of the insulating layer IN1 and the insulating layer IN2. The opening OP3 may expose a suitable conductive element in the circuit layer of the substrate SB, such as a bonding pad PD2, and the first transparent conductor TL1 may extend into the opening OP3 and contact the bonding pad PD2, thereby electrically connecting to the bonding pad PD2. In other words, the second semiconductor die DI2 may be electrically connected to the substrate SB through the first transparent conductive layer TL1. The material of the bonding pad PD2 may refer to the material of the above-mentioned bonding pad PD1, so it will not be elaborated here.

[0055] According to this embodiment, the first transparent conductive layer TL1 may serve as an electrode electrically connected to the second semiconductor die DI2, that is, the second electrode E2 mentioned above. That is, the first electrode E1 and the second electrode E2 may be located on opposite sides of the die stack structure DIS. In addition, the bonding pad PD1 and the bonding pad PD2 may be bonding pads electrically connected to the first electrode E1 and the second electrode E2 respectively. Through the above structural design, the light emission of the die stack structure DIS (or rather, the first semiconductor die DI1 and the second semiconductor die DI2) can be controlled by the substrate SB (such as a driving unit in the circuit layer of the substrate SB).

[0056] According to this embodiment, the first semiconductor die DI1 located in the opening OP1 and the second semiconductor die DI2 located in the opening OP2 corresponding to the opening OP1 may be semiconductor dies in a pixel (or sub-pixel) of the semiconductor device SD. That is, a pixel (or sub-pixel) of the semiconductor device SD may include a die stack structure DIS formed by stacking two (or more) semiconductor dies, but not limited thereto. In this case, the first semiconductor die DI1 and the second semiconductor die DI2 in the die stack structure DIS may emit light of the same color, for example, they may both emit red light, green light or blue light, but not limited thereto. In some embodiments, the first semiconductor die DI1 and the second semiconductor die DI2 in the die stack structure DIS may emit light of different colors. In addition, although Figure 5 not shown, the semiconductor device SD may further include other openings OP1 and die stack structures DIS disposed in these openings OP1, where these die stack structures DIS may emit light of one color respectively. It should be noted that the colors of the light emitted by these die stack structures DIS may be the same or different, and the present invention is not limited thereto. Therefore, the insulating layer IN1 and the insulating layer IN2 of this embodiment may serve as a pixel defining layer (PDL), but not limited thereto. In this case, the insulating layer IN1 and the insulating layer IN2 may include an organic photoresist, such as a transparent photoresist, a black photoresist or a white photoresist, but not limited thereto.

[0057] According to this embodiment, in a cross-sectional view of the semiconductor device SD, the opening OP2 may, for example, have a trapezoidal shape, where the width of the side of the opening OP2 closer to the substrate SB may be smaller than the width of the side farther from the substrate SB. In addition, the size of the opening OP2 may be larger than the size of the corresponding opening OP1. Here, the "size of the opening OP1 (or opening OP2)" may refer to the maximum width of the opening OP1 (or opening OP2) in the cross-sectional view of the semiconductor device SD, but is not limited thereto. For example, as Figure 5 shown, in the cross-sectional view of the semiconductor device SD, the maximum width of the opening OP2 (e.g., the width of the side away from the substrate SB) may be larger than the maximum width of the opening OP1. In other words, the maximum width of the second filling layer FL2 may be larger than the maximum width of the first filling layer FL1. In some embodiments, the "size of the opening OP1 (or opening OP2)" may refer to the area of the opening OP1 (or opening OP2) in the top view of the semiconductor device SD. For example, in the top view of the semiconductor device SD (not shown), the area of the opening OP1 may be smaller than the area of the opening OP2. Furthermore, although Figure 5 not labeled, in this embodiment, the range of the angle between the sidewall of the opening OP2 (or the sidewall of the second reflective layer RL2, the sidewall SW7 of the second filling layer FL2) and the surface of the insulating layer IN1 away from the substrate SB, and the range of the angle between the sidewall SW5 of the first filling layer FL1 and the surface SR2 of the first filling layer FL1 may refer to the range of the above-mentioned angle θ1, but is not limited thereto. Through the above-mentioned size design or structural design, the light-emitting effect of the semiconductor device SD can be improved.

[0058] It should be noted that the semiconductor device SD of this embodiment may further include other suitable components or film layers, and is not limited to Figure 5 the shown structure.

[0059] Please refer to Figure 6 , Figure 6 is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment of the present invention. The semiconductor device SD1 of this embodiment is the same as Figure 5One of the differences of the semiconductor device SD shown is the setting method of the second semiconductor die DI2. Specifically, in this embodiment, the second semiconductor die DI2 may be encapsulated by being embedded in the second filling layer FL2 first, and then transferred to the opening OP2 of the insulating layer IN2, but not limited thereto. Specifically, after the first semiconductor die DI1 and the underfill UF are provided, the second semiconductor die DI2 may be provided first, and the second filling layer FL2 surrounding the second semiconductor die DI2 and the second reflective layer RL2 surrounding the second filling layer FL2 may be provided to form a packaging structure. Then, the insulating layer IN2 may be provided on the insulating layer IN1, the opening OP2 may be formed in the insulating layer IN2, and the above packaging structure including the second semiconductor die DI2 may be provided in the opening OP2, so that the second semiconductor die DI2 may be electrically connected to the first semiconductor die DI1, for example, electrically connected to the first semiconductor die DI1 through the bonding layer BL. In addition, in this embodiment, the semiconductor device SD1 may further include a filling material FM provided in the opening OP2. Specifically, after the packaging structure including the second semiconductor die DI2 is provided in the opening OP2, the filling material FM may be filled into the opening OP2 to fix the packaging structure of the second semiconductor die DI2. The material of the filling material FM may refer to the material of the above underfill UF, but not limited thereto. The structural features of other components or film layers in the semiconductor device SD1 may refer to the structural description of the above semiconductor device SD, so they will not be elaborated here.

[0060] Please refer to Figure 7 , Figure 7 is a cross-sectional schematic diagram of the semiconductor device according to the fifth embodiment of the present invention. According to this embodiment, the semiconductor device SD2 may further include a second transparent conductive layer TL2 provided between the first semiconductor die DI1 and the second semiconductor die DI2. Specifically, after the underfill UF and the first semiconductor die DI1 are provided in the opening OP1, the second transparent conductive layer TL2 may be provided on the first semiconductor die DI1, and then the insulating layer IN2 may be provided. The second transparent conductive layer TL2 may contact the first semiconductor die DI1 and the second semiconductor die DI2 and be electrically connected to the first semiconductor die DI1 and the second semiconductor die DI2. Therefore, the semiconductor device SD2 may not include the above bonding layer BL, and the second transparent conductive layer TL2 may be used to electrically connect the first semiconductor die DI1 and the second semiconductor die DI2. Although Figure 7 not shown, in some embodiments, the semiconductor device SD2 may include a bonding layer BL provided between the second semiconductor die DI2 and the second transparent conductive layer TL2. The material selection of the second transparent conductive layer TL2 may refer to the material of the above transparent conductive layer TL, but not limited thereto.

[0061] According to this embodiment, the second transparent conductive layer TL2 can be electrically connected to the substrate SB, or rather, can be electrically connected to a conductive element in the circuit layer of the substrate SB (i.e., Figure 7 the conductive element CE shown). Specifically, as Figure 7 shown, the semiconductor device SD2 may further include at least one opening OP4, where the opening OP4 can be formed, for example, by removing a part of the insulating layer IN1. The opening OP4 can expose the conductive element CE of the substrate SB, and the second transparent conductive layer TL2 can extend on the insulating layer IN1 and enter the opening OP4 to contact the conductive element CE, thereby being electrically connected to the conductive element CE. In this embodiment, the conductive element CE can include any suitable electronic component, or rather, the conductive element CE can be electrically connected to any suitable electronic component, depending on the design of the semiconductor device SD2. For example, in this embodiment, the conductive element CE can include a switching element, or rather, the conductive element CE can be electrically connected to a switching element, but not limited thereto. It should be noted that the second reflective layer RL2 is not electrically connected between the second transparent conductive layer TL2 and the first transparent conductive layer TL1. For example, in some embodiments, as Figure 7 shown, the second reflective layer RL2 can contact the second transparent conductive layer TL2 and the first transparent conductive layer TL1, and the second reflective layer RL2 may not include a conductive material. Or, in some embodiments, the second reflective layer RL2 does not contact at least one of the second transparent conductive layer TL2 and the first transparent conductive layer TL1. In addition, in this embodiment, the first reflective layer RL1 may not contact the second transparent conductive layer TL2.

[0062] According to this embodiment, by providing the second transparent conductive layer TL2, the semiconductor device SD2 can have different display modes. Specifically, in some embodiments, the second transparent conductive layer TL2 can be grounded, for example, grounded through the conductive element CE. At this time, the driving electrical signal of the semiconductor die can pass through the first electrode E1, the first semiconductor die DI1, and the second transparent conductive layer TL2. In this case, the semiconductor device SD2 can have a first display mode, in which in the first display mode, the first semiconductor die DI1 can emit light, while the second semiconductor die DI2 may not emit light. In the first display mode, since only the first semiconductor die DI1 in the die stack structure DIS emits light, the first display mode can be a narrow viewing angle display mode. For example, in the first display mode, the light emitted by the semiconductor device SD2 can be more concentrated, or the brightness of the light emitted by the semiconductor device SD2 at a small viewing angle can be increased. In some embodiments, the second transparent conductive layer TL2 can be floating. At this time, the driving electrical signal of the semiconductor die can pass through the first electrode E1, the first semiconductor die DI1, the second transparent conductive layer TL2, the second semiconductor die DI2, and the first transparent conductive layer TL1. In this case, the semiconductor device SD2 can have a second display mode, in which in the second display mode, both the first semiconductor die DI1 and the second semiconductor die DI2 can emit light. In the second display mode, since both the first semiconductor die DI1 and the second semiconductor die DI2 in the die stack structure DIS emit light, the second display mode can be a high brightness display mode. Specifically, the brightness of the semiconductor device SD2 in the second display mode (i.e., the brightness of the light emitted by the semiconductor device SD2 in the second display mode) can be greater than the brightness of the semiconductor device SD2 in the first display mode. In some embodiments, the second transparent conductive layer TL2 can supply current to the second semiconductor die DI2, for example, supply current through the conductive element CE and pass through the second transparent conductive layer TL2, the second semiconductor die DI2, and the first transparent conductive layer TL1. In this case, the semiconductor device SD2 can have a third display mode, in which in the third display mode, the second semiconductor die DI2 can emit light, while the first semiconductor die DI1 may not emit light. In the third display mode, since only the second semiconductor die DI2 in the die stack structure DIS emits light, the third display mode can be a wide viewing angle display mode. For example, the brightness of the large-angle light emitted by the semiconductor device SD2 in the third display mode can be greater than the brightness of the large-angle light emitted by the semiconductor device SD2 in the first display mode. In other words, through the circuit design of the second transparent conductive layer TL2, the first semiconductor die DI1 and the second semiconductor die DI2 in the die stack structure DIS can emit light independently, thereby enabling the semiconductor device SD2 to have multiple display modes.

[0063] Please refer to Figure 8 , Figure 8Schematic diagrams of the semiconductor device according to the fifth embodiment of the present invention in different operating modes. Specifically, Figure 8 Several examples of controlling the display mode of the semiconductor device SD2 through at least one switching element are shown. In detail, in some embodiments, as Figure 8 shown in circuit (I) of, the above-mentioned conductive element CE can be a switching element A1 whose two ends are respectively electrically connected to the p-pole and n-pole of the first semiconductor die DI1, or the conductive element CE can be electrically connected to the switching element A1. In this case, when the switching element A1 is turned off (or an open circuit is formed), both the first semiconductor die DI1 and the second semiconductor die DI2 can emit light, and at this time, the semiconductor device SD2 can have the above-mentioned second display mode; when the switching element A1 is connected (or a short circuit is formed), the second semiconductor die DI2 can emit light, and the first semiconductor die DI1 may not emit light, and at this time, the semiconductor device SD2 can have the above-mentioned third display mode. In some embodiments, as Figure 8 shown in circuit (II) of, the above-mentioned conductive element CE can be a switching element A2 whose two ends are respectively electrically connected to the p-pole and n-pole of the second semiconductor die DI2, or the conductive element CE can be electrically connected to the switching element A2. In this case, when the switching element A2 is turned off (or an open circuit is formed), both the first semiconductor die DI1 and the second semiconductor die DI2 can emit light, and at this time, the semiconductor device SD2 can have the above-mentioned second display mode; when the switching element A2 is connected (or a short circuit is formed), the first semiconductor die DI1 can emit light, and the second semiconductor die DI2 may not emit light, and at this time, the semiconductor device SD2 can have the above-mentioned first display mode. In some embodiments, as Figure 8 shown in circuit (III) of, the semiconductor device SD2 can include a switching element A1 whose two ends are respectively electrically connected to the p-pole and n-pole of the first semiconductor die DI1 and a switching element A2 whose two ends are respectively electrically connected to the p-pole and n-pole of the second semiconductor die DI2. Alternatively, the conductive element CE can include Figure 8 the switching element A1 and the switching element A2 shown in circuit (III) of. In this case, the turning off or connection of the switching element A1 and the switching element A2 can be controlled respectively, and then the light emission of the first semiconductor die DI1 and the second semiconductor die DI2 can be independently controlled, so that the semiconductor device SD2 has the above-mentioned first display mode, second display mode or third display mode. It should be noted that the semiconductor device SD2 of this embodiment can also exhibit different display modes through other suitable methods, and is not limited to the above methods.

[0064] In summary, the present invention provides a semiconductor wafer or a semiconductor device, wherein a pixel (or sub-pixel) of the semiconductor wafer or the semiconductor device may include a grain stack structure formed by stacking a plurality of semiconductor grains and connecting them in series with each other. In this way, the driving efficiency or the energy utilization efficiency of the semiconductor wafer or the semiconductor device can be improved.

[0065] The above are only the embodiments of the present invention and are not intended to limit the present invention. For those of ordinary skill in the art, the present invention may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor wafer, characterized in that: include: a first semiconductor crystal grain; a second semiconductor die disposed on the first semiconductor die and electrically connected to the first semiconductor die; a filling layer surrounding a side wall of the first semiconductor crystal grain and a side wall of the second semiconductor crystal grain; a transparent conductive layer, disposed on the second semiconductor grain and the filling layer and electrically connected to the second semiconductor grain; and A reflective layer is arranged on a side wall of the filling layer.

2. The semiconductor wafer according to claim 1, characterized in that The invention also includes a bonding layer disposed between the first semiconductor crystal grain and the second semiconductor crystal grain, wherein the bonding layer is used to electrically connect the first semiconductor crystal grain and the second semiconductor crystal grain.

3. The semiconductor wafer according to claim 1, wherein: It also includes a first electrode and a second electrode, wherein the first electrode is arranged under the first semiconductor grain and electrically connected to the first semiconductor grain, and the second electrode is arranged under the filling layer and electrically connected to the transparent conductive layer through the reflective layer.

4. The semiconductor wafer according to claim 3, characterized in that The reflective layer includes a metal material.

5. The semiconductor wafer according to claim 3, characterized in that The reflective layer includes a first sublayer and a second sublayer disposed on the first sublayer, wherein the reflectivity of the first sublayer to visible light is greater than the reflectivity of the second sublayer to visible light.

6. The semiconductor wafer according to claim 3, characterized in that The reflective layer includes a first sublayer and a second sublayer disposed on the first sublayer, wherein the conductivity of the second sublayer is greater than the conductivity of the first sublayer.

7. The semiconductor wafer according to claim 1, wherein: In a cross-sectional view of the semiconductor wafer, a maximum width of the second semiconductor grain is smaller than a maximum width of the first semiconductor grain.

8. The semiconductor wafer according to claim 1, wherein In a cross-sectional view of the semiconductor wafer, the sidewall of the first semiconductor grain is not flush with the sidewall of the second semiconductor grain.

9. The semiconductor wafer according to claim 1, wherein: In a cross-sectional view of the semiconductor wafer, the sidewall of the first semiconductor grain is flush with the sidewall of the second semiconductor grain.

10. A semiconductor device, characterized in that: include: a substrate; A first semiconductor crystal grain is disposed on the substrate; a second semiconductor die disposed on the first semiconductor die and electrically connected to the first semiconductor die; a first filling layer surrounding a side wall of the first semiconductor grain; a second filling layer surrounding a side wall of the second semiconductor grain; a first transparent conductive layer, disposed on the second semiconductor crystal grain and electrically connected to the second semiconductor crystal grain; a first reflective layer, disposed on a side wall of the first filling layer; and A second reflective layer is disposed on a side wall of the second filling layer.

11. The semiconductor device according to claim 10, wherein: In a cross-sectional view of the semiconductor device, a maximum width of the second filling layer is greater than a maximum width of the first filling layer.

12. The semiconductor device according to claim 10, wherein: The invention also includes a bonding layer disposed between the first semiconductor crystal grain and the second semiconductor crystal grain, wherein the bonding layer is used to electrically connect the first semiconductor crystal grain and the second semiconductor crystal grain.

13. The semiconductor device according to claim 10, wherein: The invention also includes a second transparent conductive layer, which is disposed between the first semiconductor crystal grain and the second semiconductor crystal grain and electrically connects the first semiconductor crystal grain and the second semiconductor crystal grain.

14. The semiconductor device according to claim 13, wherein: The semiconductor device has a first display mode and a second display mode. In the first display mode, the second transparent conductive layer is grounded, and in the second display mode, the second transparent conductive layer is floating.

15. The semiconductor device according to claim 14, wherein: The first display mode is a narrow viewing angle display mode, and the second display mode is a high brightness display mode.

16. The semiconductor device according to claim 14, wherein: The brightness of the semiconductor device in the second display mode is greater than the brightness of the semiconductor device in the first display mode.

17. The semiconductor device according to claim 13, wherein: The semiconductor device has a third display mode. In the third display mode, the second transparent conductive layer provides a current to the second semiconductor die.

18. The semiconductor device according to claim 17, wherein: The third display mode is a wide viewing angle display mode.

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