Nonvolatile oxide heterojunction synaptic transistor and preparation method thereof

Abstract

The present invention discloses a non-volatile oxide heterojunction synaptic transistor and its preparation method, belonging to the field of artificial synaptic technology. The transistor comprises a substrate, a high-K gate dielectric layer, a P-type / N-type oxide semiconductor layer, and a metal top electrode. Through the rational selection of P-type and N-type oxides and in-depth exploration of the device process, the P-type and N-type oxides can form a good built-in electric field after contact. Applying different pulse voltage modes to the gate can regulate the dynamic migration of oxygen vacancies and the P-N junction barrier width, thereby affecting the channel resistance and changing the source-drain current, achieving dynamic switching and stable maintenance of long-term potentiation and inhibition synaptic plasticity behavior. The preparation process of this synaptic transistor device is simple, the production process is complete, and it is highly compatible with existing CMOS processes, providing new ideas for the development of multi-level tunable dynamic neuromorphic computing systems based on the hardware level.

Description

Technical Field

[0001] The present invention belongs to the technical field of artificial synapses, and in particular relates to a non-volatile oxide heterojunction synaptic transistor, and discloses a specific preparation method thereof. Background Art

[0002] With the rapid development of artificial intelligence (AI), artificial synaptic devices, as core vehicles for simulating the dynamic connections between biological neurons, play a key role in enabling brain-like learning and memory. By emulating the short-term plasticity (STP) and long-term plasticity (LTP / LTD) characteristics of biological synapses, these devices dynamically adjust neural network connection weights, providing hardware support for emerging technologies such as neuromorphic computing chips and spiking neural networks. They represent a key breakthrough in overcoming the energy efficiency bottlenecks of traditional von Neumann computing architectures.

[0003] However, current mainstream artificial synaptic devices (such as memristors and ion-gate transistors) are generally limited by the dynamic properties of their materials and the efficiency of interfacial charge transfer. Most can only achieve short-term synaptic plasticity, while mimicking the long-term memory functions of biological synapses, such as long-term potentiation (LTP) and depression (LTD), remains a significant challenge. These limitations stem from two key factors: the ion migration or interfacial charge accumulation mechanisms relied upon by these conventional devices are susceptible to thermodynamic relaxation effects, leading to rapid decay of weight information; Furthermore, the nonlinear, sudden change in the conductance state makes it difficult to achieve high-precision, multi-level control, severely limiting the hardware mapping of complex learning rules.

[0004] To address these challenges, there is an urgent need to develop novel device systems that combine long-term memory retention, bidirectional plasticity control, and compatibility with CMOS (complementary metal oxide semiconductor) processes. While amorphous oxide semiconductors (AOSs) and their heterostructures show promise, current research primarily focuses on the interface state manipulation of N-type AOSs, with insufficient exploration of P-type amorphous oxide semiconductors for integrated applications in synaptic devices. Current research on transistors based on PN heterojunctions suffers from functional limitations: their operating mechanism relies on unidirectional modulation of the carrier concentration (holes / electrons) at the heterojunction interface by gate voltage, making them inherently volatile devices and unable to meet the non-volatile weight requirements of neural networks. Breakthroughs should focus on heterojunction material system design and process integration innovation, with a particular emphasis on mastering key mechanisms such as P / N-type oxide band matching and precise control of oxygen vacancy trap states. Such technological breakthroughs could not only overcome the challenges of simulating long-term plasticity but also facilitate the evolution of neuromorphic systems from short-term memory to adaptive long-term learning, laying the foundation for the construction of strong artificial intelligence hardware platforms with biological plausibility. Summary of the Invention

[0005] In response to the above-mentioned problems, the present invention aims to provide a non-volatile oxide heterojunction synaptic transistor and a method for preparing the same. This application utilizes specific P-type oxides and N-type oxides to form PN junctions and oxygen vacancy defects. Based on the coordinated regulation of the PN junction rectification mechanism and the distribution of oxygen vacancies, multi-level reversible switching and steady-state maintenance of synaptic long-term potentiation (LTP) and depression (LTD) states can be achieved.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a non-volatile oxide heterojunction synaptic transistor, comprising a substrate, a high-K gate dielectric layer, a P-type oxide semiconductor layer, an N-type oxide semiconductor layer and a metal top electrode arranged in sequence from bottom to top; the P-type oxide semiconductor is selected from a material with rich oxygen vacancies, high mobility and a narrow band gap; the N-type oxide semiconductor is selected from a material with high mobility and a high switching ratio; after the P-type and N-type oxides come into contact, a good built-in electric field is formed at the P / N interface; different pulse voltage patterns are applied to the gate to regulate the distribution of oxygen vacancies and the PN junction barrier width, which can affect the channel resistance, change the source-drain current, and achieve reversible switching and stable maintenance of synaptic weights between long-term potentiation and long-term depression.

[0007] Furthermore, the different pulse voltage modes include different pulse sizes, different pulse numbers and different pulse widths.

[0008] Furthermore, the high-K gate dielectric is a hafnium-based, zirconium-based, aluminum-based, tantalum-based or titanium-based material, which has strong gate control capability and low leakage current to ensure device stability. HfO2 is preferred, and the thickness of the high-K gate dielectric layer is 15~25 nm.

[0009] Furthermore, the P-type oxide semiconductor is selected from TeSeO x , NiO, SnO or Cu2O, preferably TeSeO x (Se content is 0% to 30%), the thickness of the P-type oxide semiconductor layer is 8 to 15 nm. Furthermore, the N-type oxide semiconductor is selected from any one of indium zinc oxide (IZO), ZnO, In2O3, or indium gallium zinc oxide (IGZO), and the thickness of the N-type oxide semiconductor layer is 10 to 15 nm.

[0010] Furthermore, the substrate material is P-type heavily doped silicon, the substrate thickness is 0.55~0.75 mm, and the metal top electrode thickness is 85~100 nm.

[0011] The method for preparing the non-volatile oxide heterojunction synaptic transistor is as follows:

[0012] 1) Pre-treating the substrate;

[0013] 2) After growing the high-K gate dielectric on the substrate, thermal annealing is performed;

[0014] 3) preparing a P-type oxide semiconductor front channel layer on the gate dielectric layer by high vacuum thermal evaporation;

[0015] 4) Using magnetron sputtering technology to sputter N-type oxide semiconductor on the front channel layer to prepare N-type back channel film, annealing, and forming a PN junction;

[0016] 5) Prepare the top electrode on the channel layer by vacuum thermal evaporation.

[0017] Furthermore, in step 2), the gate dielectric is grown on the substrate using atomic layer deposition technology. After the gate dielectric is grown, it is annealed at 300°C for 3 to 5 minutes to increase the HfO2 film capacitance and reduce leakage current, thereby improving device performance and reliability.

[0018] Furthermore, in step 3), the thermal evaporation process is carried out at 10 -5 The evaporation was carried out under a vacuum degree of 1.5 Pa, and the thermal steaming current was 60.48~90.85 A.

[0019] Furthermore, in step 4), the magnetron sputtering process is carried out in a 0.6 Pascal Ar atmosphere, the sputtering frequency is 70 W, and the sputtering time is 80-120 s; the annealing temperature is 200° C., and the annealing time is 60-80 min.

[0020] The beneficial effects of the present invention are:

[0021] 1. The oxide heterojunction synaptic transistor disclosed in this application includes a substrate, a high-K gate dielectric, a P-type oxide semiconductor layer, an N-type oxide semiconductor layer, and a top electrode. The two types of oxide semiconductors form a PN junction. The P-type oxide semiconductor used is a material with abundant oxygen vacancies, a narrow band gap, and high mobility. The oxygen vacancies act as charge traps, and the arrangement of oxygen vacancies changes the channel conductance. The N-type oxide semiconductor is a material with high mobility and a high on-off ratio, with few interface defects, excellent stability, and efficient electron injection. The P-type and N-type oxides form a good built-in electric field after contact, which can suppress spontaneous charge diffusion and ensure data non-volatility.

[0022] 2. The synaptic transistor based on the P / N-type oxide heterojunction disclosed in this application achieves non-volatile synaptic function through the following mechanisms: by changing the gate voltage polarity, on the one hand, dynamically changes the depletion layer width of the heterojunction PN region; on the other hand, by changing the distribution of oxygen vacancies in the oxide semiconductor, the formation state of the channel conduction path is modulated, and ultimately, information writing and retention are achieved through significant changes in source-drain current. In addition, by designing different gate pulse voltage patterns (such as pulse amplitude, number, width, etc.), the oxygen vacancy distribution and PN junction barrier width can be finely controlled, thereby achieving dynamic switching and stable maintenance of long-term synaptic energy efficiency between potentiation and inhibition.

[0023] 3. This application achieves the construction of oxide heterojunction transistors with non-volatile synaptic functionality through the specific selection of oxide semiconductor materials and the coordinated optimization of atomic-level interface engineering. This eliminates the need for multi-layer material stacking, such as tunneling layers and charge-trapping layers, found in traditional floating gate or semi-floating gate structures. Synaptic non-volatility is achieved solely through oxide interface defects (such as oxygen vacancies), significantly reducing process complexity. Furthermore, the fabrication technology for oxide heterojunction transistors is mature, the production process is sophisticated, and they can be fabricated on a large scale and are highly compatible with existing CMOS processes, further effectively reducing production costs and the difficulty of widespread adoption.

[0024] 4. The oxide heterojunction synaptic transistor disclosed in this application regulates the distribution of oxygen vacancy trap charges through gate pulses, and has the characteristics of low power consumption and good CMOS compatibility, making it more adaptable to future development trends. It provides new ideas for the development of neuromorphic synaptic devices and has broad application prospects in the fields of Internet of Things (IoT) devices, smart chips, and artificial intelligence. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a flow chart of preparing a non-volatile oxide heterojunction synaptic transistor according to Example 1;

[0026] Figure 2 Neutron image a is TeSeO prepared in Example 1 x Atomic force microscope (AFM) image of the semiconductor surface, sub-image b is an atomic force microscope (AFM) image of the IZO semiconductor surface prepared in Example 1;

[0027] Figure 3 Sub-figure a is a schematic diagram of the structure of the non-volatile oxide heterojunction synaptic transistor prepared in Example 1, and sub-figure b is a schematic diagram of the corresponding synapse, wherein 1-synaptic vesicle, 2-neurotransmitter, 3-receptor, 4-mitochondria, 5-presynaptic membrane, 6-synaptic cleft, 7-postsynaptic membrane;

[0028] Figure 4Figure 1 is a non-volatile memory level curve modulated by applying different pulse modes to the gate of the oxide heterojunction synaptic transistor prepared in Example 1. Figure a shows the non-volatile memory level curve modulated by applying positive pulse voltages of different magnitudes, Figure b shows the non-volatile memory level curve modulated by varying the voltage pulse width when the pulse voltage is 3 V, and Figure c shows the non-volatile memory level curve modulated by applying different voltage pulse times when the pulse voltage is 3 V.

[0029] Figure 5 Figure 1 is a non-volatile memory level curve modulated by applying different pulse modes to the gate of the oxide heterojunction synaptic transistor prepared in Example 1. Sub-figure a shows the non-volatile memory level curve modulated by applying negative pulse voltages of different magnitudes, sub-figure b shows the non-volatile memory level curve modulated by changing the voltage pulse width when the pulse voltage is -0.5 V, and sub-figure c shows the non-volatile memory level curve modulated by applying different voltage pulse numbers when the pulse voltage is -0.5 V.

[0030] Figure 6 Figure a shows the cyclic programming / erase characteristic curve of the device, which is triggered by 35 consecutive enhancement positive pulses (+4 V) and 35 suppression negative pulses (-0.8 V) with a pulse width of 400 ms. Figure b is an enlarged view of part A in Figure a.

[0031] Figure 7 1 is the energy band diagram of the PN junction barrier of the oxide heterojunction synaptic transistor prepared in Example 1, wherein sub-figure a is the energy band diagram when a positive gate voltage is applied to achieve writing, and sub-figure b is the energy band diagram when a negative gate voltage is applied to gradually restore the source-drain current. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0033] Example 1

[0034] This embodiment discloses a method for preparing a non-volatile oxide heterojunction synaptic transistor. The preparation process is as follows: Figure 1 , the specific preparation steps are as follows:

[0035] 1) Substrate pretreatment: P-type heavily doped silicon wafers were ultrasonically cleaned in anhydrous ethanol and deionized water for 10 min each, twice to ensure the surface was clean and free of impurities. After being blown dry with a nitrogen gun, the substrate was heated at 80°C for 5 min to ensure that it was dry. The substrate thickness was 0.55 mm.

[0036] 2) Preparation of the gate dielectric layer: The pretreated substrate was placed in an atomic layer deposition (ALD) apparatus. Tetrakis(dimethylamino)hafnium (TDMAH) and H2O were introduced to grow a 20 nm thick HfO2 gate dielectric on the substrate. The substrate was then rapidly annealed at 300°C for 5 minutes to improve the capacitance characteristics of the gate dielectric and reduce leakage current.

[0037] 3) Preparation of P-type oxide semiconductor layer: On the surface of the gate dielectric layer, a hard mask was used to perform patterning in a high vacuum thermal evaporator to obtain a rectangular channel layer with a length of 1300 μm and a width of 750 μm. A mixture of 93% TeO2 and 7% Se was used as the P-type semiconductor material. After thorough mixing and grinding, it was placed in a tungsten evaporation boat. -5 Pa vacuum degree, thermal evaporation was performed with a thermal evaporation current of 90.85 A to prepare 10 nm thick TeSeO x Front channel layer.

[0038] Figure 2 Neutron image a shows TeSeO x AFM image of a flat and smooth semiconductor surface.

[0039] 4) Preparation of the N-type oxide semiconductor layer: A layer of IZO (N-type semiconductor material) was deposited on the sample channel using a high-vacuum triple-target coating machine. A hard mask 1200 μm long and 550 μm wide was patterned to completely embed the P-type channel. RF magnetron sputtering was used in a 0.6 Pascal Ar atmosphere using a 99.99% pure IZO ceramic target. The RF power was adjusted to 70 W for 80 s, resulting in a thickness of approximately 15 nm. The sample was then annealed in air at 200°C for 60 min.

[0040] Figure 2 Neutron image b shows the AFM image of the flat and smooth surface of the IZO semiconductor.

[0041] 5) Vacuum thermal evaporation technology to manufacture source and drain electrodes: Place the metal Al particles and the device covered with the mask into the evaporation device, and -5 Under a vacuum degree of 1.5 Pa, the thermal evaporation current was 110.8 A to prepare 100 nm thick Al source and drain electrodes (1000 μm long and 150 μm wide). After the evaporation was completed, the power was slowly reduced to 0, and after the cavity was completely cooled, nitrogen was flushed in and the finished product was taken out.

[0042] The edge of the device was scraped, silver glue was applied, and the bottom electrode was brought out for testing.

[0043] The structural diagram of the oxide heterojunction synaptic transistor prepared according to the above method and the corresponding synaptic diagram are shown in FIG. Figure 3As shown in Figures a and b, the transistor device structure is P from bottom to top. + -Si substrate, HfO2 high-K gate dielectric layer, P-type oxide semiconductor (TeSeO x ) front channel layer, N-type oxide semiconductor (IZO) back channel layer and Al metal top electrode.

[0044] The oxide heterojunction synaptic transistor fabricated in this example was electrically tested using a Keysight B1500. The test circuit involved contacting the source, drain, and gate of the device with probes, with the source grounded. Different pulse voltages were applied to the gate, and a fixed read voltage was applied to the drain. Figure 4 and Figure 5 The experimental results of dynamically modulating the device's memory characteristics by regulating the gate voltage pulse pattern are presented. Figure 4 The effect of positive voltage pulses on the memory level was studied: by adjusting the positive pulse amplitude ( Figure 4 Neutron Figure a), changing the pulse width (400 ms to 5000 ms, Figure 4 Neutron Figure b) and the number of pulses applied ( Figure 4 Neutron image c), the device shows obvious long-term enhancement characteristics. Correspondingly, Figure 5 The control effect of negative voltage pulse was systematically explored: in adjusting the amplitude of negative pulse ( Figure 5 Neutron image a), extended pulse width range ( Figure 5 Neutron image b) and changing the number of pulses ( Figure 5 In the case of the neutron image (c), the device exhibits significant long-term inhibition. Experimental results demonstrate that by precisely controlling parameters such as the amplitude, width, and number of positive and negative pulses, dynamic and polymorphic control of the memory level can be effectively achieved, providing important experimental evidence for realizing reconfigurable synaptic function. This is primarily due to the fact that applying different gate biases affects the PN junction width and oxygen vacancy migration.

[0045] In addition, from Figure 6 As can be seen in the figure, applying 35 4 V positive pulses can achieve the memory process in the device, while applying 35 -0.8 V negative pulses gradually reduces the current to achieve the forgetting process. The pulse width of both positive and negative pulses is 400 ms. Together, the memory and forgetting processes simulate the synaptic energy efficiency process of the device, and the device exhibits stable and repeatable cycling performance.

[0046] For the transistor device prepared in this embodiment, the materials forming the PN junction are P-type oxide semiconductor TeSeO x and N-type oxide semiconductor IZO. TeSeO xIZO is a material with abundant oxygen vacancies, a narrow band gap, and high mobility. Oxygen vacancies act as charge traps, altering channel conductance through their arrangement. IZO is a material with high mobility and a high on-off ratio, with few interface defects and excellent stability, enabling efficient electron injection. Its high-mobility amorphous structure supports fast transport, and oxygen vacancies act as electron capture centers, enhancing non-volatility.

[0047] The PN junction barrier band diagram of this device can be found in Figure 7 ,from Figure 7 As shown in Figure a, when a positive gate pulse (+4V) is applied, the PN junction is in a positive bias state. The positive gate pulse not only weakens the potential of the built-in electric field, but also changes the distribution of oxygen vacancies. Driven by the positive gate voltage, the positively charged oxygen vacancies in the P-type oxide move closer to the PN junction, further weakening the potential of the built-in electric field. The electrons are driven to transfer from the N-type oxide across the potential barrier to the P-type oxide, and the amount of injected charge increases with the increase in the number of pulses, the increase in width, and the increase in pulse voltage. When the pulse disappears, the oxygen vacancies spontaneously return to their initial positions slowly, making it difficult for the built-in electric field to return to its initial state. Therefore, the channel conductance increases and the current increases. When a negative gate pulse of -0.8 V is applied ( Figure 7 Neutron Figure b), the external electric field will accelerate the oxygen vacancies remaining at the PN junction to be pulled away, causing the oxygen vacancies to be rearranged, restoring the built-in electric field, reducing the channel conductance, and achieving the inhibition function.

[0048] The above shows and describes the basic principles, main features, and advantages of the present invention. However, the above is only a specific embodiment of the present invention, and the technical features of the present invention are not limited thereto. Any other implementation methods derived by any person skilled in the art without departing from the technical solution of the present invention are intended to be within the scope of the present invention.

Claims

1. A nonvolatile oxide heterojunction synaptic transistor, characterized in that: It includes a substrate, a high-K gate dielectric layer, a P-type oxide semiconductor layer, an N-type oxide semiconductor layer and a metal top electrode which are arranged in sequence; The P-type oxide semiconductor is selected from materials having abundant oxygen vacancies, high mobility and narrow band gap; The N-type oxide semiconductor is selected from materials having high mobility and high on / off ratio; After the P-type and N-type oxide semiconductors come into contact, a good built-in electric field is formed at the P / N interface; Applying different pulse voltage patterns to the gate can regulate the distribution of oxygen vacancies and the width of the PN junction barrier, which can affect the channel resistance, change the source-drain current, and achieve reversible switching and stable maintenance of synaptic weights between long-term potentiation and long-term depression. The P-type oxide semiconductor is selected from TeSeO x , the thickness of the P-type oxide semiconductor layer is 8~15 nm; The N-type oxide semiconductor is selected from IZO, and the thickness of the N-type oxide semiconductor layer is 10-15 nm.

2. The nonvolatile oxide heterojunction synapse transistor according to claim 1, wherein: The different pulse voltage modes include different pulse sizes, different numbers of pulses and / or different pulse widths.

3. The nonvolatile oxide heterojunction synapse transistor according to claim 1, wherein: The high-K gate dielectric is a hafnium-based, zirconium-based, aluminum-based, tantalum-based or titanium-based material, and the thickness of the high-K gate dielectric layer is 15~25 nm.

4. The nonvolatile oxide heterojunction synapse transistor according to claim 1, wherein: TeSeO x It is prepared using a mixture of 93% TeO2 and 7% Se as raw materials.

5. The nonvolatile oxide heterojunction synapse transistor according to claim 1, wherein: The substrate material is P-type heavily doped silicon, the substrate thickness is 0.55~0.75 mm, and the metal top electrode thickness is 85~100 nm.

6. The method for preparing a non-volatile oxide heterojunction synapse transistor according to any one of claims 1 to 5, wherein: The specific steps are as follows: 1) Pre-treating the substrate; 2) After growing a high-K gate dielectric layer on the substrate, thermal annealing is performed; 3) preparing a P-type oxide semiconductor front channel layer on the gate dielectric layer by high vacuum thermal evaporation; 4) Using magnetron sputtering technology to sputter an N-type oxide semiconductor on the front channel layer to prepare an N-type back channel film, and annealing; 5) Prepare the top electrode on the N-type back channel film using vacuum thermal evaporation.

7. The method for preparing a non-volatile oxide heterojunction synapse transistor according to claim 6, wherein: In step 2), the gate dielectric layer is grown on the substrate using atomic layer deposition technology. After the gate dielectric layer is grown, it is annealed at 300° C. for 3 to 5 minutes.

8. The method for preparing a non-volatile oxide heterojunction synapse transistor according to claim 6, wherein: In step 3), the thermal evaporation process is carried out at 10 -5 The evaporation was carried out under a vacuum degree of 1.5 Pa, and the thermal steaming current was 60.48~90.85 A.

9. The method for preparing a non-volatile oxide heterojunction synapse transistor according to claim 6, wherein: In step 4), the magnetron sputtering process is carried out in a 0.6 Pa Ar atmosphere, the sputtering power is 70 W, and the sputtering time is 80-120 s; the annealing temperature is 200° C. and the annealing time is 60-80 min.

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