Three-dimensional capacitor, manufacturing method thereof and ferroelectric memory
By adopting a three-dimensional capacitor structure in ferroelectric memory and preventing metal diffusion and dielectric layer oxidation through an isolation layer that completely surrounds the capacitor, the problem of large-area planar capacitors affecting storage density and performance reduction in the prior art is solved, and higher storage density and better capacitor performance are achieved.
Patent Information
- Application Number
- CN202311744434.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-18
- Publication Date
- 2025-06-20
AI Technical Summary
The planar structure of existing capacitive ferroelectric random access memory causes the device to require large-area planar capacitors, affecting the storage density and chip integration. At the same time, the oxidation of the dielectric layer material leads to a decrease in conductivity and performance.
Using a three-dimensional capacitor structure, the capacitor is completely surrounded by the first isolation layer and the second isolation layer, preventing the diffusion of metal elements and oxidation of the dielectric layer, and improving the insulation and isolation effect.
Improves storage density and chip integration, prevents electrode material from oxidizing, and improves the overall performance of the capacitor.
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Figure CN120187281A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a three-dimensional capacitor, a manufacturing method thereof, and a ferroelectric memory. Background Art
[0002] Ferroelectric memories achieve the storage of "0" and "1" signals through the polarization reversal of ferroelectrics under the action of an external electric field, and the polarization state of the ferroelectrics can still be stably maintained after the external electric field is removed. Therefore, the memory has non-volatility. Ferroelectric memories have the advantages of fast operation speed, low power consumption, good durability, and high reliability, and are outstanding in non-volatile memories. Among them, emerging hafnium-based ferroelectric materials have great advantages in terms of CMOS process compatibility and device miniaturization, and thus have broad application prospects.
[0003] Currently, the mainstream capacitive ferroelectric random access memories are mostly planar structures. To ensure that the device has enough polarization charge to identify the stored information, it is necessary to fabricate large-area planar capacitors that occupy a large amount of space, thereby affecting the storage density and chip integration. In addition, the dielectric layer material is usually SiO2, and the upper and lower electrodes in contact with the dielectric layer are oxidized, resulting in a decrease in the conductivity and an increase in the resistance of the upper and lower electrodes, and further leading to a reduction in the overall performance of the capacitor. Summary of the Invention
[0004] In view of the above analysis, embodiments of the present invention aim to provide a three-dimensional capacitor, a manufacturing method thereof, and a ferroelectric memory to solve problems such as that large-area planar capacitors will affect the storage density and chip integration, and that the oxidation of capacitor electrodes will reduce the performance of the capacitor.
[0005] On the one hand, an embodiment of the present invention provides a three-dimensional capacitor, including: a metal layer located above a substrate; a first dielectric layer located above the metal layer; a trench penetrating the first dielectric layer and exposing the top surface of the metal layer at the bottom surface of the trench; a first isolation layer located on opposite sidewalls of the trench and above a raised portion of the first dielectric layer; a lower electrode conformally located in the trench and covering a portion of the first isolation layer outside the opposite sidewalls; a ferroelectric dielectric layer conformally covering the lower electrode layer; an upper electrode conformally covering the ferroelectric dielectric layer; and a second isolation layer conformally covering the first isolation layer and the upper electrode.
[0006] The beneficial effects of the above technical solution are as follows: being completely surrounded by the first isolation layer and the second isolation layer can not only provide an insulation isolation effect between devices, but also prevent the diffusion and contamination of metal elements when using different electrode materials or avoid the oxidation of the upper and lower electrodes of the capacitor by the silicon oxide material of the silicon oxide dielectric layer.
[0007] Based on further improvements to the above device, the material of the metal layer is W, Cu, Al, Au, Ag, Pt, Pd, Mo, or TiN; the materials of the first isolation layer and the second isolation layer are SiN; the material of the first dielectric layer is SiO2; the materials of the upper electrode and the lower electrode are W, Al, Au, Pt, Pd, Mo, Cu, Ru, Ta, Ir, Ti, TiN, TaN, RuO x , IrO x or heavily doped polysilicon; the material of the ferroelectric dielectric layer is doped HfO x , where the doping materials include but are not limited to Si, Al, Zr, Y, Gd, Sr, La, Ga, or In.
[0008] Based on further improvements to the above device, the top surface of the metal layer contacts and connects to the bottom surface of the lower electrode in the trench.
[0009] Based on further improvements to the above device, the opposite ends of the lower electrode, the ferroelectric dielectric layer, and the upper electrode are flush in the vertical direction.
[0010] Based on further improvements to the above device, the opposite side surfaces of the lower electrode above the first isolation layer contact the inner surface of the second isolation layer; the opposite side surfaces of the ferroelectric dielectric layer above the upper electrode contact the inner surface of the second isolation layer; and the opposite end surfaces of the upper electrode above the ferroelectric dielectric layer contact the inner surface of the second isolation layer.
[0011] Based on further improvements to the above device, the three-dimensional capacitor further includes a second dielectric layer, a via, and a metal interconnection layer, where the second dielectric layer conformally covers the second isolation layer; the via passes through the second dielectric layer and the second isolation layer in the trench and reaches the top surface of the upper electrode; and the metal interconnection layer is located above the top surface of the via and a part of the second dielectric layer to contact and connect to the top surface of the via.
[0012] On the other hand, an embodiment of the present invention provides a method for manufacturing a three-dimensional capacitor, including: sequentially forming a metal layer, a first dielectric layer, and a first sacrificial layer above a substrate; etching the first sacrificial layer and the first dielectric layer to form a trench exposing a partial top surface of the metal layer; conformally forming a second sacrificial layer above the trench and the first sacrificial layer; etching the second sacrificial layer until stopping at the top surface of the first sacrificial layer, such that the second sacrificial layer remaining on the opposite sidewalls of the trench and the first sacrificial layer above the first dielectric layer constitute a first isolation layer; conformally forming a lower electrode layer, an intermediate dielectric layer, and an upper electrode layer in sequence above the trench and the first isolation layer, and then partially etching the upper electrode layer, the intermediate dielectric layer, and the lower electrode layer outside the opposite sidewalls of the trench to form a sandwich-shaped ferroelectric capacitor; conformally forming a second isolation layer above the first isolation layer and the ferroelectric capacitor to completely surround the ferroelectric capacitor through the first isolation layer and the second isolation layer.
[0013] Based on a further improvement of the above method, partially etching the upper electrode layer, the intermediate dielectric layer, and the lower electrode layer outside the opposite sidewalls of the trench to form a sandwich-shaped ferroelectric capacitor includes: sequentially etching the two ends of the upper electrode layer, the intermediate dielectric layer, and the lower electrode layer outside the opposite sidewalls of the trench; stopping the etching at the top surface of the first isolation layer to form the lower electrode, the ferroelectric dielectric layer located above the lower electrode, and the upper electrode located above the ferroelectric dielectric layer of the ferroelectric capacitor with the upper electrode layer, the intermediate dielectric layer, and the lower electrode layer.
[0014] Based on a further improvement of the above method, after conformally forming a second isolation layer above the first isolation layer and the ferroelectric capacitor, it further includes: forming a second dielectric layer above the second isolation layer, and then performing a planarization process on the second dielectric layer using a chemical mechanical polishing (CMP) process; etching through holes in the second dielectric layer and the second isolation layer, wherein the through holes are connected to the upper electrode in the middle of the trench; covering the inner wall of the through holes with nitride and then filling the through holes with a metal material, or directly filling the through holes with a metal material; and forming a metal interconnection layer above the filled through holes.
[0015] On the other hand, an embodiment of the present invention provides a ferroelectric memory, including a plurality of memory cells, wherein each memory cell includes a transistor and the above-mentioned three-dimensional capacitor located above the transistor, wherein the gate of the transistor is connected to a word line; the drain of the transistor is connected to the lower electrode of the three-dimensional capacitor via a first interconnection layer and a second interconnection layer; the source of the transistor is connected to a bit line via a third interconnection layer and a fourth interconnection layer.
[0016] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0017] 1. Completely surrounding a single capacitor by the first isolation layer and the second isolation layer can not only provide an insulating isolation effect between devices, but also prevent the diffusion and contamination of metal elements when using different electrode materials or avoid the oxidation of the upper and lower electrodes of the capacitor by the silicon oxide material of the silicon oxide dielectric layer;
[0018] 2. It can effectively improve the storage density of the product and the integration degree of the chip, and the process manufacturing difficulty is not high.
[0019] In the present invention, the above technical solutions can also be combined with each other to achieve more preferred combination schemes. Other features and advantages of the present invention will be described in the subsequent specification, and some advantages can be made obvious from the specification or understood by implementing the present invention. The objectives and other advantages of the present invention can be realized and obtained from the content specifically pointed out in the specification and the drawings. Description of the Drawings
[0020] The drawings are only for the purpose of showing specific embodiments and are not considered as limiting the present invention. Throughout the drawings, the same reference signs denote the same components.
[0021] Figure 1 FIG. is an overall cross-sectional view of a three-dimensional capacitor according to an embodiment of the present invention;
[0022] Figure 2 FIG. is a cross-sectional view of forming a first sacrificial layer in the process of manufacturing a three-dimensional capacitor according to an embodiment of the present invention;
[0023] Figure 3 FIG. is a cross-sectional view of forming a trench in the process of manufacturing a three-dimensional capacitor according to an embodiment of the present invention;
[0024] Figure 4 FIG. is a cross-sectional view of forming a second sacrificial layer in the process of manufacturing a three-dimensional capacitor according to an embodiment of the present invention;
[0025] Figure 5 FIG. is a cross-sectional view of forming a first isolation layer in the process of manufacturing a three-dimensional capacitor according to an embodiment of the present invention;
[0026] Figure 6 FIG. is a cross-sectional view of forming a lower electrode layer, an intermediate dielectric layer, and an upper electrode layer of a capacitor in the process of manufacturing a three-dimensional capacitor according to an embodiment of the present invention;
[0027] Figure 7 FIG. is a cross-sectional view of forming a three-dimensional capacitor in the process of manufacturing a three-dimensional capacitor according to an embodiment of the present invention;
[0028] Figure 8 A cross-sectional view of forming a second isolation layer during the manufacturing process of a three-dimensional capacitor according to an embodiment of the present invention;
[0029] Figure 9 A cross-sectional view of forming a second dielectric layer during the manufacturing process of a three-dimensional capacitor according to an embodiment of the present invention;
[0030] Figure 10 A cross-sectional view of forming a via hole during the manufacturing process of a three-dimensional capacitor according to an embodiment of the present invention; and
[0031] Figure 11 A cross-sectional view of a ferroelectric memory according to an embodiment of the present invention.
[0032] Reference numerals:
[0033] 101 - Substrate; 102 - Metal layer; 103 - First dielectric layer; 104 - Trench; 105 - First isolation layer; 106 - Top surface of the metal layer; 107 - Lower electrode; 108 - Ferroelectric dielectric layer; 109 - Upper electrode; 110 - Second isolation layer; 111 - Second dielectric layer; 112 - Via hole; 113 - Metal interconnect layer; 115 - First sacrificial layer; 116 - Second sacrificial layer; 117 - Lower electrode layer; 118 - Intermediate dielectric layer; 119 - Upper electrode layer; 1101 - Gate; 1102 - Drain; 1103 - Source; 1104 - First interconnect layer; 1105 - Second interconnect layer; 1106 - Third interconnect layer; 1107 - Fourth interconnect layer. Detailed implementation manners
[0034] The following will specifically describe the preferred embodiments of the present invention with reference to the accompanying drawings. The accompanying drawings form a part of this application and are used together with the embodiments of the present invention to explain the principles of the present invention, rather than to limit the scope of the present invention.
[0035] Reference Figure 1 , a specific embodiment of the present invention discloses a three-dimensional capacitor 100, including: a metal layer 102 located above a substrate 101; a first dielectric layer 103 located above the metal layer 102; a trench 104 penetrating the first dielectric layer 103 above the metal layer 102 and exposing the top surface 106 of the metal layer at the bottom of the trench; a first isolation layer 105 located on the opposite sidewalls of the trench 104 and above the protrusion of the first dielectric layer 103; a lower electrode 107 conformally located in the trench 104 and covering a part of the first isolation layer 105 outside the opposite sidewalls; a ferroelectric dielectric layer 108 conformally covering the lower electrode 107; an upper electrode 109 conformally covering the ferroelectric dielectric layer 108; and a second isolation layer 110 conformally covering the first isolation layer 105 and the upper electrode 109.
[0036] Compared with the prior art, for the three-dimensional capacitor provided in this embodiment, the complete enclosure of a single capacitor by the first isolation layer and the second isolation layer can not only provide an insulating isolation effect between devices, but also prevent the diffusion contamination of metal elements when different electrode materials are used or avoid the oxidation of the upper and lower electrodes of the capacitor by the silicon oxide material of the silicon oxide dielectric layer.
[0037] In the following, with reference to Figure 1 , the three-dimensional capacitor according to the embodiment of the present invention will be described in detail. The three-dimensional capacitor 100 includes: a substrate 101, a metal layer 102, a first dielectric layer 103, a trench 104, a first isolation layer 105, the top surface 106 of the metal layer, a lower electrode 107, a ferroelectric dielectric layer 108, an upper electrode 109, a second isolation layer 110, a second dielectric layer 111, a via 112, and a metal interconnection layer 113.
[0038] The metal layer 102 is located above the substrate 101. The material of the substrate includes Si and / or SiO2. The material of the metal layer includes but is not limited to: tungsten W, copper Cu, aluminum Al, gold Au, silver Ag, platinum Pt, palladium Pd, molybdenum Mo, or titanium nitride TiN. The first dielectric layer 103 is located above the metal layer 102. The material of the first dielectric layer 103 is silicon nitride SiO2.
[0039] The trench 104 passes through the first dielectric layer 103 above the metal layer 102 and exposes the top surface 106 of the metal layer at the bottom surface of the trench 104. The top surface of the metal layer 102 is in contact connection with the bottom surface of the lower electrode in the trench 104. The trench 104 is a U-shaped or cylindrical deep groove structure.
[0040] The first isolation layer 105 is located on the opposite sidewalls of the trench 104 and above the protrusion of the first dielectric layer 103. The first isolation layer 105 includes a first part on the right sidewall of the trench 104, a second part above the protrusion of the first dielectric layer on the right side of the right sidewall, a third part on the left sidewall of the trench 104, and a fourth part above the protrusion of the first dielectric layer on the left side of the left sidewall. In addition, there is no first isolation layer 105 inside the opposite sidewalls of the first isolation layer in the trench. The material of the first isolation layer 105 is SiN.
[0041] The lower electrode 107 is conformally located in the trench 104 and covers a part of the first isolation layer 105 outside the opposite sidewalls. Specifically, the lower electrode 107 includes a first part located in the trench 104, a second part located on the right side of the right sidewall of the trench, and a third part located on the left side of the left sidewall of the trench. The bottom surface of the first part of the lower electrode is in contact connection with the top surface 106 of the metal layer. The left sidewall of the first part of the lower electrode is in contact with the third part of the first isolation layer, and the right sidewall of the first part of the lower electrode is in contact with the first part of the first isolation layer. The second part of the lower electrode does not extend to the end of the second part of the first isolation layer, that is, it does not cover the right end of the first isolation layer. The third part of the lower electrode does not extend to the end of the fourth part of the first isolation layer, that is, it does not cover the left end of the first isolation layer. The ferroelectric dielectric layer 108 conformally covers the lower electrode 107. The upper electrode 109 conformally covers the ferroelectric dielectric layer 108. The opposite ends of the lower electrode 107, the ferroelectric dielectric layer 108, and the upper electrode 109 are flush in the vertical direction. The materials of the upper electrode and the lower electrode include but are not limited to tungsten W, aluminum Al, gold Au, platinum Pt, palladium Pd, molybdenum Mo, copper Cu, ruthenium Ru, tantalum Ta, iridium Ir, titanium Ti, titanium nitride TiN, tantalum nitride TaN, ruthenium oxide RuO x 、iridium oxide IrO x or heavily doped polysilicon; the material of the ferroelectric dielectric layer is doped HfO x , wherein the doping materials include but are not limited to silicon Si, aluminum Al, zirconium Zr, yttrium Y, gadolinium Gd, strontium Sr, lanthanum La, gallium Ga, or indium In.
[0042] The second isolation layer 110 conformally covers the first isolation layer 105 and the upper electrode 109. The material of the second isolation layer is SiN. The opposite side surfaces of the lower electrode 107 located above the first isolation layer 105 are in contact with the inner surface of the second isolation layer; the opposite side surfaces of the ferroelectric dielectric layer 108 located above the upper electrode are in contact with the inner surface of the second isolation layer; and the opposite end surfaces of the upper electrode located above the ferroelectric dielectric layer are in contact with the inner surface of the second isolation layer.
[0043] The second dielectric layer 111 conformally covers the second isolation layer 110; the via 112 penetrates through the second dielectric layer 111 and the second isolation layer 110 in the trench 104 and reaches the top surface of the upper electrode 109; and the metal interconnect layer 113 is located above the top surface of the via 112 and a part of the second dielectric layer to be in contact connection with the top surface of the via.
[0044] Another specific embodiment of the present invention discloses a method for manufacturing a three-dimensional capacitor, including: referring to Figure 2 , sequentially forming a metal layer 102, a first dielectric layer 103, and a first sacrificial layer 115 above the substrate 101; referring to Figure 3, etch the first sacrificial layer 115 and the first dielectric layer 103 to form a trench exposing a partial top surface 106 of the metal layer 102, i.e., the top surface of the metal layer 102 corresponding to the trench; refer to Figure 4 , conformally form a second sacrificial layer 116 over the trench and the first sacrificial layer 115; refer to Figure 5 , etch the second sacrificial layer 116 until stopping at the top surface of the first sacrificial layer, such that the second sacrificial layer remaining on the opposite sidewalls of the trench and the first sacrificial layer over the first dielectric layer constitute a first isolation layer 105; refer to Figure 6 and Figure 7 , conformally form a lower electrode layer 117, an intermediate dielectric layer 118, and an upper electrode layer 119 in sequence over the trench 104 and the first isolation layer 105, and then partially etch the upper electrode layer 119, the intermediate dielectric layer 118, and the lower electrode layer 117 outside the opposite sidewalls of the trench to form a sandwich-shaped ferroelectric capacitor; refer to Figure 8 , conformally form a second isolation layer 110 over the first isolation layer 105 and the ferroelectric capacitor to completely surround the ferroelectric capacitor through the first isolation layer 105 and the second isolation layer 110, i.e., completely surround the lower electrode 107, the ferroelectric dielectric layer 108, and the upper electrode 109.
[0045] Refer to Figure 6 and Figure 7 Partially etching the upper electrode layer 119, the intermediate dielectric layer 118, and the lower electrode layer 117 outside the opposite sidewalls of the trench to form a sandwich-shaped ferroelectric capacitor includes: sequentially etching the two ends of the upper electrode layer 119, the intermediate dielectric layer 118, and the lower electrode layer 117 outside the opposite sidewalls of the trench; the etching stops at the top surface of the first isolation layer 105 to form the remaining upper electrode layer 119, the intermediate dielectric layer 118, and the lower electrode layer 117 into the lower electrode 107 of the ferroelectric capacitor, the ferroelectric dielectric layer 108 located above the lower electrode 107, and the upper electrode 109 located above the ferroelectric dielectric layer 108.
[0046] After conformally forming the second isolation layer 110 over the first isolation layer 105 and the ferroelectric capacitor, it further includes: refer to Figure 9 , form a second dielectric layer 111 over the second isolation layer 110, and then perform a planarization process on the second dielectric layer 111 using a chemical mechanical polishing (CMP) process; refer to Figure 10 , etch through holes 112 in the second dielectric layer 111 and the second isolation layer 110, wherein the through holes 112 are connected to the upper electrode 109 in the middle of the trench; refer to Figure 10 , cover the inner walls of the through holes with nitride and then fill the through holes with a metal material, or directly fill the through holes with a metal material; and refer to Figure 1 , form a metal interconnect layer 113 over the filled through holes 112.
[0047] During the manufacturing process of ferroelectric capacitors, complete surrounding of the capacitor by the isolation layer can be achieved. Through the method proposed by the present invention, the storage density of the product and the integration degree of the chip can be effectively improved, and the manufacturing difficulty of the process is not high; the complete surrounding of a single capacitor by the isolation layer can not only improve the insulation isolation effect between devices, but also prevent the diffusion pollution of metal elements or the failure of electrode oxidation when using different electrode materials, thus effectively improving the reliability of the product.
[0048] In the following, the manufacturing method of the three-dimensional capacitor according to the embodiment of the present invention will be described in detail by way of specific examples.
[0049] In step 1, a Si / SiO2 substrate;
[0050] In step 2, a metal layer on the substrate, and the materials include but are not limited to W, Cu, Al, Au, Ag, Pt, Pd, Mo, TiN, etc.;
[0051] In step 3, a first dielectric layer on the metal layer, and the dielectric material can be SiO2;
[0052] In step 4, a first sacrificial layer is formed on the first dielectric layer, and the sacrificial layer material can be SiN;
[0053] In step 5, the first sacrificial layer and the first dielectric layer are etched to form a U-shaped or columnar deep groove structure;
[0054] In step 6, a second sacrificial layer is formed on the deep groove, covering the surface and the side walls of the deep groove, and the second sacrificial layer material is the same as the first sacrificial layer;
[0055] In step 7, the second sacrificial layer is etched to the surface of the first sacrificial layer, and only the part covering the side walls of the deep groove remains of the second sacrificial layer;
[0056] In step 8, so far, the remaining parts of the first and second sacrificial layers form the first isolation layer;
[0057] In step 9, a sandwich-shaped ferroelectric capacitor structure is formed on the first isolation layer, including a lower electrode, a ferroelectric dielectric layer, and an upper electrode, and the three thin films cover the surface and the side walls of the deep groove. Among them, the materials that can be selected for the lower electrode and the upper electrode include but are not limited to W, Al, Au, Pt, Pd, Mo, Cu, Ru, Ta, Ir, Ti, TiN, TaN, RuOx, IrOx, heavily doped polysilicon, etc., and the ferroelectric dielectric layer is a doped HfOx thin film, and the doping materials that can be selected include but are not limited to Si, Al, Zr, Y, Gd, Sr, La, Ga, In, etc.;
[0058] In step 10, the ferroelectric capacitor is patterned by photolithography and etching, and the etching stops at the first isolation layer;
[0059] In step 11, a second isolation layer is formed on the patterned ferroelectric capacitor to completely surround the capacitor. The isolation layer material can be SiN;
[0060] In step 12, a second dielectric layer is formed on the second isolation layer, and planarization is performed using CMP (chemical mechanical polishing);
[0061] In step 13, vias are etched in the second dielectric layer. The vias penetrate the second dielectric layer and the second isolation layer and are connected to the upper electrode;
[0062] In step 14, the vias are filled with metal. The materials include but are not limited to W, Cu, Al, etc. When using metals such as Cu that are prone to diffusion, nitrides (such as SiN, TaN, etc.) can be first covered on the inner wall of the vias as isolation;
[0063] In step 15, a metal interconnection layer is formed on the filled vias.
[0064] Reference Figure 11 , yet another specific embodiment of the present invention discloses a ferroelectric memory including a plurality of memory cells. Each memory cell includes a transistor and a three-dimensional capacitor located above the transistor. The gate (S) 1101 of the transistor is connected to the word line; the drain (D) 1102 of the transistor is connected to the lower electrode 107 of the three-dimensional capacitor via the first interconnection layer 1104 and the second interconnection layer 1105; the source (S) 1103 of the transistor is connected to the bit line via the third interconnection layer 1106 and the fourth interconnection layer 1107. The three-dimensional capacitor 100 includes: a metal layer located above the substrate 101; a trench 104 that penetrates the first dielectric layer 103 above the metal layer 102 and exposes the top surface 106 of the metal layer at the bottom of the trench; a first isolation layer 105 located on the opposite sidewalls of the trench 104 and above the protrusion of the first dielectric layer 103; a lower electrode 107 conformally located in the trench 104 and covering a part of the first isolation layer 105 outside the opposite sidewalls; a ferroelectric dielectric layer 108 conformally covering the lower electrode 107; an upper electrode 109 conformally covering the ferroelectric dielectric layer 108; and a second isolation layer 110 conformally covering the first isolation layer 105 and the upper electrode 109. The second dielectric layer 111 conformally covers the second isolation layer 110; the via 112 penetrates the second dielectric layer 111 and the second isolation layer 110 in the trench 104 and reaches the top surface of the upper electrode 109; and the metal interconnection layer 113 is located above the top surface of the via 112 and a part of the second dielectric layer to make contact connection with the top surface of the via.
[0065] In addition, the ferroelectric memory includes 1T1C memory cells or nTnC memory cells.
[0066] Those skilled in the art can understand that all or part of the processes for implementing the methods of the above embodiments can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. Among them, the computer-readable storage medium is a magnetic disk, an optical disk, a read-only memory, a random access memory, etc.
[0067] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.
Claims
1. A three-dimensional capacitor, characterized in that, Comprising: A metal layer, located above the substrate; A first dielectric layer, located above the metal layer; A trench, penetrating the first dielectric layer and exposing the top surface of the metal layer at the bottom surface of the trench; A first isolation layer, located on the opposite sidewalls of the trench and above the raised portion of the first dielectric layer; A lower electrode, conformally located in the trench and covering a portion of the first isolation layer outside the opposite sidewalls; A ferroelectric dielectric layer, conformally covering the lower electrode layer; An upper electrode, conformally covering the ferroelectric dielectric layer; And A second isolation layer, conformally covering the first isolation layer and the upper electrode.
2. The three-dimensional capacitor according to claim 1, characterized in that, The material of the metal layer is W, Cu, Al, Au, Ag, Pt, Pd, Mo or TiN; The materials of the first isolation layer and the second isolation layer are SiN; The material of the first dielectric layer is SiO2; The materials of the upper electrode and the lower electrode are W, Al, Au, Pt, Pd, Mo, Cu, Ru, Ta, Ir, Ti, TiN, TaN, RuO x 、IrO x or heavily doped polysilicon; The material of the ferroelectric dielectric layer is doped HfO x , wherein the doping materials include but are not limited to Si, Al, Zr, Y, Gd, Sr, La, Ga or In.
3. The three-dimensional capacitor according to claim 1, characterized in that, The top surface of the metal layer is in contact connection with the bottom surface of the lower electrode in the trench.
4. The three-dimensional capacitor according to claim 1, characterized in that, The opposite ends of the lower electrode, the ferroelectric dielectric layer and the upper electrode are flush in the vertical direction.
5. The three-dimensional capacitor according to claim 1, characterized in that, The opposite side surfaces of the lower electrode located above the first isolation layer are in contact with the inner surface of the second isolation layer; The opposite side surfaces of the ferroelectric dielectric layer located above the upper electrode are in contact with the inner surface of the second isolation layer; and The opposite end surfaces of the upper electrode located above the ferroelectric dielectric layer are in contact with the inner surface of the second isolation layer.
6. The three-dimensional capacitor according to claim 5, characterized in that, It further comprises a second dielectric layer, a via hole and a metal interconnection layer, wherein, The second dielectric layer, conformally covering the second isolation layer; The via hole, passing through the second dielectric layer and the second isolation layer in the trench and reaching the top surface of the upper electrode; and The metal interconnection layer, located above the top surface of the via hole and a part of the second dielectric layer to be in contact connection with the top surface of the via hole.
7. A method for manufacturing a three-dimensional capacitor, characterized in that, Comprising: Sequentially forming a metal layer, a first dielectric layer and a first sacrificial layer above the substrate; Etching the first sacrificial layer and the first dielectric layer to form a trench exposing a part of the top surface of the metal layer; Conformally forming a second sacrificial layer above the trench and the first sacrificial layer; Etching the second sacrificial layer until stopping at the top surface of the first sacrificial layer, so that the second sacrificial layer remaining on the opposite sidewalls of the trench and the first sacrificial layer above the first dielectric layer constitute a first isolation layer; Sequentially and conformally forming a lower electrode layer, an intermediate dielectric layer and an upper electrode layer above the trench and the first isolation layer, and then partially etching the upper electrode layer, the intermediate dielectric layer and the lower electrode layer outside the opposite sidewalls of the trench to form a sandwich-shaped ferroelectric capacitor; Conformally forming a second isolation layer above the first isolation layer and the ferroelectric capacitor to completely surround the ferroelectric capacitor through the first isolation layer and the second isolation layer.
8. The manufacturing method of the three-dimensional capacitor according to claim 7, wherein, Partially etching the upper electrode layer, the intermediate dielectric layer and the lower electrode layer outside the opposite sidewalls of the trench to form a sandwich-shaped ferroelectric capacitor, including: Sequentially etching the two ends of the upper electrode layer, the intermediate dielectric layer and the lower electrode layer outside the opposite sidewalls of the trench; Etching is stopped at the top surface of the first isolation layer to form the upper electrode layer, the intermediate dielectric layer, and the lower electrode layer into the lower electrode of the ferroelectric capacitor, the ferroelectric dielectric layer above the lower electrode, and the upper electrode above the ferroelectric dielectric layer.
9. The manufacturing method of the three-dimensional capacitor according to claim 8, wherein, After a second isolation layer is conformally formed over the first isolation layer and the ferroelectric capacitor, it further includes: forming a second dielectric layer over the second isolation layer, and then planarizing the second dielectric layer using a chemical mechanical polishing (CMP) process; etching through holes in the second dielectric layer and the second isolation layer, wherein the through holes are connected to the upper electrode in the middle of the trench; covering the inner walls of the through holes with nitride and then filling the through holes with a metal material, or directly filling the through holes with a metal material; and forming a metal interconnect layer over the filled through holes.
10. A ferroelectric memory, wherein, It includes a plurality of memory cells, wherein each memory cell includes a transistor and a three-dimensional capacitor as described in any one of claims 1 to 6 above the transistor, wherein the gate of the transistor is connected to a word line; the drain of the transistor is connected to the lower electrode of the three-dimensional capacitor via a first interconnect layer and a second interconnect layer; the source of the transistor is connected to a bit line via a third interconnect layer and a fourth interconnect layer.