Display substrate, display panel and display device

Abstract

The invention discloses a display substrate, a display panel and a display device, and relates to the technical field of display. The display substrate comprises a first substrate, a plurality of scanning lines, a plurality of data lines and a plurality of pixel units, the scanning lines, the data lines and the pixel units are located on one side of the first substrate, the scanning lines extend in the row direction, the data lines extend in the column direction, and the pixel units are arranged in an array mode in the row direction and the column direction; each pixel unit comprises a plurality of sub-pixels arranged in the row direction, and the sub-pixels located in the same pixel unit are connected with the same data line and connected with different scanning lines respectively. The size of the sub-pixels in the column direction is larger than that of the sub-pixels in the row direction; m scanning lines are arranged between every two adjacent rows of pixel units, M is larger than or equal to 2 and smaller than or equal to the number N of sub-pixels contained in each pixel unit, under the condition that M is equal to N, the M scanning lines are connected with the same pixel unit, and under the condition that M is smaller than N, at least two scanning lines in the M scanning lines are connected with different pixel units.

Description

Display substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] With the development of driving methods and manufacturing processes, the production cost and picture quality of liquid crystal displays have been greatly improved.

[0003] Overview

[0004] The present disclosure provides a display substrate, comprising:

[0005] A first substrate, and a plurality of scan lines, a plurality of data lines, and a plurality of pixel units located on one side of the first substrate, wherein the scan lines extend in a row direction, the data lines extend in a column direction, and the plurality of pixel units are arranged in an array along the row direction and the column direction respectively;

[0006] The pixel unit includes: a plurality of sub-pixels arranged along a row direction, wherein the plurality of sub-pixels in the same pixel unit are connected to the same data line and are respectively connected to different scan lines;

[0007] wherein the size of the sub-pixel along the column direction is greater than the size of the sub-pixel along the row direction; and

[0008] M scan lines are arranged between two adjacent rows of pixel units, where M is greater than or equal to 2 and less than or equal to the number N of sub-pixels contained in one of the pixel units. When M is equal to N, the M scan lines are respectively connected to different sub-pixels of the same pixel unit. When M is less than N, at least two of the M scan lines are connected to sub-pixels of different pixel units.

[0009] In some embodiments, the plurality of pixel units include a first pixel unit, and the plurality of scan lines include:

[0010] A first scan line, a second scan line, and a third scan line are arranged in sequence along a column direction, wherein the first scan line, the second scan line, and the third scan line are respectively connected to different sub-pixels in the first pixel unit, and the first scan line, the second scan line, and the third scan line are located on the same side of the first pixel unit.

[0011] In some embodiments, the display substrate further comprises:

[0012] a first thin film transistor connected to the first scan line, a second thin film transistor connected to the second scan line, and a third thin film transistor connected to the third scan line;

[0013] The first thin film transistor, the second thin film transistor, and the third thin film transistor are all located between the first scan line and the third scan line.

[0014] In some embodiments, the first scan line is disposed close to the first pixel unit, and the first scan line has a first bending portion, which bends toward a side close to the first pixel unit.

[0015] In some embodiments, the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel sequentially arranged along a row direction;

[0016] The first bending portion completely passes through the second sub-pixel and partially passes through the first sub-pixel and the third sub-pixel in the row direction.

[0017] In some embodiments, the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel sequentially arranged along a row direction;

[0018] The second scanning line has a second bending portion, and the second bending portion bends toward a side close to the first scanning line.

[0019] In some embodiments, the plurality of pixel units include a second pixel unit, and the plurality of scan lines include:

[0020] The fourth scan line, the fifth scan line and the sixth scan line are respectively connected to different sub-pixels in the second pixel unit, and the fourth scan line and the fifth scan line are located on different sides of the second pixel unit.

[0021] In some embodiments, the sixth scan line runs through the second pixel unit.

[0022] In some embodiments, the plurality of scan lines include a seventh scan line and an eighth scan line that are adjacent to each other, and the seventh scan line and the eighth scan line are located between two adjacent rows of pixel units;

[0023] The display substrate further includes a fourth thin film transistor connected to the seventh scan line and a fifth thin film transistor connected to the eighth scan line, and the fourth thin film transistor and the fifth thin film transistor are both located between the seventh scan line and the eighth scan line.

[0024] In some embodiments, the seventh scanning line has a third bending portion, and the third bending portion bends toward a side close to the eighth scanning line;

[0025] The eighth scanning line has a fourth bending portion, the fourth bending portion is bent toward a side close to the seventh scanning line and is arranged opposite to the third bending portion;

[0026] Among them, the fourth thin film transistor is located on the first side of the third bending portion and the fourth bending portion, and the fifth thin film transistor is located on the second side of the third bending portion and the fourth bending portion, and the first side and the second side are the two opposite sides of the third bending portion and the fourth bending portion in the row direction.

[0027] In some embodiments, the third bending portion and the fourth bending portion are arranged axially symmetrically with respect to a symmetry axis extending along the row direction.

[0028] In some embodiments, the plurality of scan lines include a ninth scan line and a tenth scan line that are adjacent to each other, and the ninth scan line and the tenth scan line are located between two adjacent rows of pixel units;

[0029] The display substrate also includes: a sixth thin film transistor connected to the ninth scan line, and a seventh thin film transistor connected to the tenth scan line, and the sixth thin film transistor is located on the side of the ninth scan line away from the tenth scan line, and the seventh thin film transistor is located on the side of the tenth scan line away from the ninth scan line.

[0030] In some embodiments, at different positions in the row direction, the intervals between the ninth scan line and the tenth scan line are substantially the same.

[0031] In some embodiments, the plurality of data lines include a first data line, the sixth thin film transistor and the seventh thin film transistor are both connected to a first lead, and the first lead and the first data line are connected at an intersection through a first via.

[0032] In some embodiments, the first via hole is located between the ninth scan line and the tenth scan line; and

[0033] The ninth scanning line has a fifth bending portion, which bends toward a side away from the first via hole. The tenth scanning line has a sixth bending portion, which bends toward a side away from the first via hole.

[0034] In some embodiments, the fifth bent portion and the sixth bent portion are both in the shape of arcs, and the centers of the arcs are approximately located at the first via hole.

[0035] In some embodiments, the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel sequentially arranged along a row direction;

[0036] The plurality of pixel units include a plurality of second pixel units arranged along a column direction, and the plurality of second pixel units include a third pixel unit, a fourth pixel unit, and a fifth pixel unit that are adjacent to each other in sequence;

[0037] The sixth thin film transistor and the seventh thin film transistor located between the third pixel unit and the fourth pixel unit are respectively connected to different first sub-pixels located in the same column, and the sixth thin film transistor and the seventh thin film transistor located between the fourth pixel unit and the fifth pixel unit are respectively connected to different second sub-pixels located in the same column.

[0038] In some embodiments, the first data line is located between the first sub-pixel and the second sub-pixel;

[0039] The display substrate further includes: a first shielding line located between two adjacent columns of pixel units, and a second shielding line located between the second sub-pixel and the third sub-pixel;

[0040] In the orthographic projection on the first substrate, the thin film transistor connected to the first sub-pixel overlaps with the first shading line, the thin film transistor connected to the second sub-pixel overlaps with the second shading line, and the thin film transistor connected to the third sub-pixel overlaps with the second shading line.

[0041] In some embodiments, the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel sequentially arranged along a row direction;

[0042] The display substrate further includes at least one of the following:

[0043] The touch lines extend along the column direction and are arranged in the same layer as the data lines;

[0044] The shielding lines extend along the column direction and are respectively arranged in different layers from the data lines and the scan lines;

[0045] The touch line, the data line or the shielding line is respectively arranged between the first sub-pixel and the second sub-pixel, between the second sub-pixel and the third sub-pixel, and between two adjacent columns of pixel units.

[0046] In some embodiments, the display substrate further comprises:

[0047] a thin film transistor, wherein a gate electrode is connected to the scan line, a first electrode is connected to the data line via a lead, and a second electrode is connected to the sub-pixel;

[0048] The lead wire is provided in the same layer as the data line, or in the same layer as the active layer of the thin film transistor.

[0049] The present disclosure provides a display panel, comprising: a cell substrate, a liquid crystal layer, and a display substrate as described in any embodiment, wherein the liquid crystal layer is located between the cell substrate and the display substrate, and the plurality of pixel units are arranged close to the liquid crystal layer.

[0050] In some embodiments, the display substrate further includes a thin film transistor, and the thin film transistor is respectively connected to the scan line, the data line, and the sub-pixel;

[0051] The cell-matching substrate includes: a second substrate, and a light shielding layer provided on a side of the second substrate close to the liquid crystal layer, the light shielding layer including a plurality of openings separated from each other and arranged in an array, wherein the orthographic projections of the openings on the display substrate overlap with the sub-pixels;

[0052] The light shielding layer includes: a first light shielding pattern and a second light shielding pattern located between two adjacent rows of openings, wherein in an orthographic projection on the display substrate, the first light shielding pattern and the second light shielding pattern both cover the scan line located between the two adjacent rows of openings in a column direction, the first light shielding pattern also covers at least one thin film transistor, and the second light shielding pattern does not overlap with the thin film transistor;

[0053] The width of the first light-shielding pattern along the column direction is different from the width of the second light-shielding pattern along the column direction.

[0054] In some embodiments, the display substrate includes: a sixth scan line running through the pixel units, and two scan lines disposed between two adjacent rows of pixel units;

[0055] The light shielding layer further includes a third light shielding pattern and a fourth light shielding pattern, wherein in an orthographic projection on the display substrate, the third light shielding pattern covers the sixth scan line and the thin film transistor connected to the sixth scan line in a column direction, and the fourth light shielding pattern covers two scan lines and at least one thin film transistor located between two adjacent rows of pixel units in a column direction;

[0056] The width of the third light-shielding pattern along the column direction is different from the width of the fourth light-shielding pattern along the column direction.

[0057] In some embodiments, a ratio of a width of the third light-shielding pattern along the column direction to a width of the fourth light-shielding pattern along the column direction is greater than or equal to 0.5 and less than or equal to 0.8.

[0058] The present disclosure provides a display device, comprising:

[0059] The display panel according to any one of the embodiments; and

[0060] The source driver chip is bound and connected to the display substrate and is used for providing data signals to the data lines.

[0061] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

[0062] BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

[0064] FIG1 exemplarily shows a schematic planar structural diagram of a first display substrate provided by the present disclosure;

[0065] FIG2 exemplarily shows a schematic planar structural diagram of a second display substrate provided by the present disclosure;

[0066] FIG3 exemplarily shows a schematic planar structural diagram of a third display substrate provided by the present disclosure;

[0067] FIG4 exemplarily shows a schematic planar structural diagram of a fourth display substrate provided by the present disclosure;

[0068] 5 and 6 exemplarily show schematic planar structural views of a fifth display substrate provided by the present disclosure;

[0069] FIG7 exemplarily shows a schematic cross-sectional structure diagram of a display device provided by the present disclosure.

[0070] Detailed description

[0071] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0072] 1 to 5 , schematic diagrams of planar structures of several display substrates are exemplarily shown. As shown in any one of FIG1 to 5 , the display substrate includes a first substrate (not shown in the figure), and a plurality of scan lines SC, a plurality of data lines DT, and a plurality of pixel units P located on one side of the first substrate. The scan lines SC extend along the row direction f1, the data lines DT extend along the column direction f2, and the plurality of pixel units P are arranged in an array along the row direction f1 and the column direction f2, respectively.

[0073] As shown in any one of FIG. 1 to FIG. 5 , the pixel unit P includes: a plurality of sub-pixels PX arranged along the row direction f1 . The plurality of sub-pixels PX in the same pixel unit P are connected to the same data line DT and are respectively connected to different scan lines SC.

[0074] The size of the sub-pixel PX along the column direction f2 is larger than the size of the sub-pixel PX along the row direction f1.

[0075] By arranging multiple sub-pixels PX in the same pixel unit P to be connected to the same data line DT and to different scan lines SC, the number of data lines DT can be reduced, thereby reducing the number of source driver chips required, thereby reducing costs. The source driver chip is used to provide data signals to the data lines DT.

[0076] For example, as shown in any one of Figures 1 to 5, the pixel unit P includes three sub-pixels PX, and the three sub-pixels PX are connected to the same data line DT and are respectively connected to different scan lines SC. In this way, triple rate driving (TRD) can be achieved, and the number of source driver chips can be reduced by 2 / 3, thereby reducing costs.

[0077] In conventional TRD technology, since the size of the sub-pixel PX along the column direction f2 is smaller than that along the row direction f1 and this pixel arrangement is different from conventional pixel arrangement, the readability of clear characters is reduced by at least 30%.

[0078] The display substrate provided herein has a subpixel PX arrangement that is larger along the column direction f2 than along the row direction f1, similar to conventional pixel arrangements. Conventional pixel arrangements utilize a systematic optimization algorithm for font display in liquid crystal displays. Therefore, the display substrate provided herein can utilize this optimization algorithm for font display, ensuring legibility of crisp characters.

[0079] The display substrate provided by the present disclosure can, on the one hand, improve display clarity, and on the other hand, reduce the number of source driver chips and lower costs.

[0080] In some embodiments, M scan lines SC are disposed between two adjacent rows of pixel units P, where M is greater than or equal to 2 and less than or equal to the number N of sub-pixels PX included in one pixel unit P. When M is equal to N, the M scan lines SC are respectively connected to different sub-pixels PX in the same pixel unit P. When M is less than N, at least two of the M scan lines SC are connected to sub-pixels PX in different pixel units P.

[0081] For example, as shown in FIG1 or FIG2 , M=3 scan lines SC (such as scan lines SC1, SC2, and SC3 shown in FIG1 or FIG2 ) are provided between two adjacent rows of pixel units P, and the number of sub-pixels PX included in one pixel unit P is N=3 (such as sub-pixels PX1, PX2, and PX3 shown in FIG1 or FIG2 ). That is, the number M of scan lines SC provided between two adjacent rows of pixel units P is equal to the number N of sub-pixels PX included in one pixel unit P. In this case, the three scan lines SC provided between two adjacent rows of pixel units P respectively connect different sub-pixels PX located in the same pixel unit P.

[0082] For example, as shown in any one of Figures 3 to 5 , M=2 scan lines SC are provided between two adjacent rows of pixel units P (scan lines SC7 and SC8 shown in Figure 3 , and scan lines SC9 and SC10 shown in Figures 4 or 5 ), and the number of sub-pixels PX included in one pixel unit P is N=3 (sub-pixels PX1, PX2, and PX3 shown in Figures 3 to 5 ). That is, the number M of scan lines SC provided between two adjacent rows of pixel units P is less than the number N of sub-pixels PX included in one pixel unit P. In this case, the two scan lines SC provided between two adjacent rows of pixel units P respectively connect sub-pixels PX located in different pixel units P.

[0083] For example, in FIG. 3 to FIG. 5 , each scan line SC disposed between two adjacent rows of pixel units P is connected to a sub-pixel PX in the pixel unit P close to the scan line SC.

[0084] In some embodiments, as shown in any one of Figures 1 to 5, the pixel unit P includes a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3 arranged in sequence along a row direction f1. The first sub-pixel PX1 is, for example, a red sub-pixel, the second sub-pixel PX2 is, for example, a green sub-pixel, and the third sub-pixel PX3 is, for example, a blue sub-pixel.

[0085] In some embodiments, as shown in any one of FIG. 1 to FIG. 4 , the display substrate further includes: touch lines TC extending along the column direction f2 and disposed in the same layer as the data lines DT.

[0086] In some embodiments, as shown in any one of FIG. 1 to FIG. 5 , the display substrate further includes shielding lines SD extending along the column direction f2 and disposed in different layers from the data lines DT and the scan lines SC.

[0087] As shown in any one of Figures 1 to 5, a touch line TC, a data line DT or a shielding line SD is respectively provided between the first sub-pixel PX1 and the second sub-pixel PX2, between the second sub-pixel PX2 and the third sub-pixel PX3, and between two adjacent columns of pixel units P.

[0088] 1 , 2 or 4 , the touch line TC is located between two adjacent columns of pixel units P, the data line DT is located between the first sub-pixel PX1 and the second sub-pixel PX2 , and the shielding line SD is located between the second sub-pixel PX2 and the third sub-pixel PX3 .

[0089] 3 , the touch line TC is located between two adjacent columns of pixel units P, the shielding line SD is located between the first sub-pixel PX1 and the second sub-pixel PX2 , and the data line DT is located between the second sub-pixel PX2 and the third sub-pixel PX3 .

[0090] 5 , the data line DT is located between the first sub-pixel PX1 and the second sub-pixel PX2, and the shielding line SD includes: a first shielding line SD1 located between two adjacent columns of pixel units P, and a second shielding line SD2 located between the second sub-pixel PX2 and the third sub-pixel PX3.

[0091] Exemplarily, the scan line SC is located on a side of the data line DT away from the first substrate, and the second shielding line SD2 is located on a side of the scan line SC away from the first substrate.

[0092] In some embodiments, as shown in Figure 1 or Figure 2, the plurality of pixel units P include a first pixel unit P1, and the plurality of scan lines SC include: a first scan line SC1, a second scan line SC2, and a third scan line SC3 arranged in sequence along the column direction f2, the first scan line SC1, the second scan line SC2, and the third scan line SC3 are respectively connected to different sub-pixels PX in the first pixel unit P1, and the first scan line SC1, the second scan line SC2, and the third scan line SC3 are located on the same side of the first pixel unit P1.

[0093] Exemplarily, as shown in FIG. 1 or FIG. 2 , the first scan line SC1 is connected to the first sub-pixel PX1 , the second scan line SC2 is connected to the second sub-pixel PX2 , and the third scan line SC3 is connected to the third sub-pixel PX3 .

[0094] Exemplarily, as shown in FIG. 1 or FIG. 2 , the first scan line SC1 , the second scan line SC2 , and the third scan line SC3 are all located at the lower side of the first pixel unit P1 .

[0095] In some embodiments, as shown in FIG1 or FIG2 , the display substrate further includes: a first thin film transistor T1 connected to the first scan line SC1, a second thin film transistor T2 connected to the second scan line SC2, and a third thin film transistor T3 connected to the third scan line SC3. The first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are all located between the first scan line SC1 and the third scan line SC3.

[0096] Exemplarily, as shown in FIG. 1 or FIG. 2 , the first thin film transistor T1 is connected to the first sub-pixel PX1 , the second thin film transistor T2 is connected to the second sub-pixel PX2 , and the third thin film transistor T3 is connected to the third sub-pixel PX3 .

[0097] Exemplarily, as shown in FIG. 1 or FIG. 2 , the third scan line SC3 is disposed away from the first pixel unit P1 , and the third scan line SC3 is in the shape of a bar extending along the row direction f1 .

[0098] Exemplarily, as shown in FIG1 , the first scan line SC1 is disposed close to the first pixel unit P1 , and the first scan line SC1 is in the shape of a bar extending along a row direction f1 .

[0099] Exemplarily, as shown in FIG1 , the aperture ratios of the plurality of sub-pixels PX located in the first pixel unit P1 are the same.

[0100] In some embodiments, as shown in FIG. 2 , the first scan line SC1 is disposed close to the first pixel unit P1 . The first scan line SC1 has a first bending portion W1 . The first bending portion W1 bends toward a side close to the first pixel unit P1 .

[0101] For example, as shown in FIG2 , the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 can be arranged within a width range of the first bending portion W1 along the row direction f1, and then the area between the first scan line SC1 and the third scan line SC3 where no thin film transistors are arranged can be set as an opening area. In this way, the area of ​​the opening area can be further increased, the aperture ratio of the sub-pixel can be improved, the power consumption can be reduced, and the display effect can be improved.

[0102] 2 , the first scan line SC1 further includes a first extension portion 21 connected between two adjacent first bends W1. Within the first pixel unit P1, a dimension d1 of a sub-pixel PX adjacent to the first extension portion 21 along the column direction f2 is greater than a dimension d2 of a sub-pixel PX adjacent to the first bend W1 along the column direction f2.

[0103] Exemplarily, as shown in Figure 2, the sub-pixels PX adjacent to the first extension portion 21 are the first sub-pixel PX1 and the third sub-pixel PX3, and the sub-pixel PX adjacent to the first bending portion W1 is the second sub-pixel PX2. Therefore, the dimension d1 of the first sub-pixel PX1 along the column direction f2 is greater than the dimension d2 of the second sub-pixel PX2 along the column direction f2, and the dimension d1 of the third sub-pixel PX3 along the column direction f2 is greater than the dimension d2 of the second sub-pixel PX2 along the column direction f2.

[0104] Exemplarily, as shown in FIG. 2 , the first bending portion W1 completely passes through the second sub-pixel PX2 and partially passes through the first sub-pixel PX1 and the third sub-pixel PX3 in the row direction f1 .

[0105] 2 , the first bending portion W1 passes through a portion of the first subpixel PX1 close to the second subpixel PX2 in the row direction f1 , and the first bending portion W1 passes through a portion of the third subpixel PX3 close to the second subpixel PX2 in the row direction f1 .

[0106] 2 , the aperture ratio of the second subpixel PX2 is smaller than the aperture ratios of the first subpixel PX1 and the third subpixel PX3 . The aperture ratios of the first subpixel PX1 and the third subpixel PX3 may be the same or different.

[0107] In order to further improve the aperture ratio of the sub-pixel PX, the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3 can be compactly arranged in the row direction f1. For example, when preparing the film layers of the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3, the spacing between patterns on the same layer can be set to the minimum process limit value, thereby further increasing the area of ​​the opening region, improving the aperture ratio, and enhancing the display effect.

[0108] In some embodiments, as shown in FIG. 1 or FIG. 2 , the second scan line SC2 has a second bending portion W2 , and the second bending portion W2 bends toward a side close to the first scan line SC1 .

[0109] For example, as shown in FIG1 or FIG2 , the second bent portion W2 partially penetrates the second sub-pixel PX2 and the third sub-pixel PX3 in the row direction f1. For example, the second bent portion W2 penetrates a portion of the second sub-pixel PX2 close to the third sub-pixel PX3 in the row direction f1, and the second bent portion W2 penetrates a portion of the third sub-pixel PX3 close to the second sub-pixel PX2 in the row direction f1.

[0110] 2 , the second bend W2 is located within the width of the first bend W1 along the row direction f1. The first bend W1 and the second bend W2 do not intersect, and the width of the second bend W2 along the row direction f1 is smaller than the width of the first bend W1 along the row direction f1.

[0111] In some embodiments, as shown in any one of Figures 3 to 5, the plurality of pixel units P include a second pixel unit P2, and the plurality of scan lines SC include: a fourth scan line SC4, a fifth scan line SC5, and a sixth scan line SC6, the fourth scan line SC4, the fifth scan line SC5, and the sixth scan line SC6 are respectively connected to different sub-pixels PX in the second pixel unit P2, and the fourth scan line SC4 and the fifth scan line SC5 are located on different sides of the second pixel unit P2.

[0112] Exemplarily, as shown in FIG3 , the fourth scan line SC4 is connected to the first sub-pixel PX1 , the fifth scan line SC5 is connected to the third sub-pixel PX3 , and the sixth scan line SC6 is connected to the second sub-pixel PX2 .

[0113] Exemplarily, as shown in FIG4 , the fourth scan line SC4 is connected to the second sub-pixel PX2 , the fifth scan line SC5 is connected to the first sub-pixel PX1 , and the sixth scan line SC6 is connected to the third sub-pixel PX3 .

[0114] Exemplarily, as shown in FIG5 , the fourth scan line SC4 is connected to the first sub-pixel PX1 , the fifth scan line SC5 is connected to the second sub-pixel PX2 , and the sixth scan line SC6 is connected to the third sub-pixel PX3 .

[0115] Exemplarily, as shown in any one of FIG. 3 to FIG. 5 , the fourth scan line SC4 is located at the upper side of the second pixel unit P2 , and the fifth scan line SC5 is located at the lower side of the second pixel unit P2 .

[0116] When multiple scan lines SC are centrally arranged (as shown in FIG. 1 or FIG. 2 ), since the multiple scan lines SC are arranged on the same layer, a necessary spacing between the lines is required to prevent short circuits. In this embodiment, by dispersing the fourth scan line SC4 and the fifth scan line SC5, the reduction in aperture area caused by spacing between lines on the same layer is eliminated, thereby increasing the aperture ratio and improving the display quality.

[0117] In some embodiments, as shown in any one of FIG. 3 to FIG. 5 , the sixth scan line SC6 runs through the second pixel unit P2. Thus, by distributing the fourth scan line SC4, the fifth scan line SC5, and the sixth scan line SC6, the reduction in the opening area caused by the spacing between lines on the same layer can be further eliminated, thereby increasing the aperture ratio and improving the display effect.

[0118] Exemplarily, as shown in any one of FIG. 3 to FIG. 5 , in the column direction f2 , the sixth scan line SC6 is centrally disposed within the region of the second pixel unit P2 .

[0119] Exemplarily, as shown in any one of FIG. 3 to FIG. 5 , the sixth scan line SC6 is in a strip shape extending along the row direction f1 .

[0120] As shown in any one of FIG. 3 to FIG. 5 , each sub-pixel PX in the second pixel unit P2 is divided into two parts, an upper part and an lower part, by the sixth scan line SC6 , and the pixel electrodes of the two parts are connected to each other.

[0121] In some embodiments, as shown in FIG. 3 , the plurality of scan lines SC include a seventh scan line SC7 and an eighth scan line SC8 , which are adjacent to each other. The seventh scan line SC7 and the eighth scan line SC8 are located between two adjacent rows of pixel units P.

[0122] For example, for two adjacent pixel units P in the column direction, the seventh scan line SC7 may be the fifth scan line SC5 of the previous pixel unit P, and the eighth scan line SC8 may be the fourth scan line SC4 of the next pixel unit P, as shown in FIG3 . Alternatively, the seventh scan line SC7 may be the fourth scan line SC4 of the next pixel unit P, and the eighth scan line SC8 may be the fifth scan line SC5 of the previous pixel unit P, but this disclosure is not limited thereto.

[0123] As shown in FIG3 , the display substrate further includes: a fourth thin film transistor T4 connected to the seventh scan line SC7 , and a fifth thin film transistor T5 connected to the eighth scan line SC8 , and both the fourth thin film transistor T4 and the fifth thin film transistor T5 are located between the seventh scan line SC7 and the eighth scan line SC8 .

[0124] As shown in FIG3 , the fourth thin film transistor T4 is located on a side of the seventh scan line SC7 close to the eighth scan line SC8 , and the fifth thin film transistor T5 is located on a side of the eighth scan line SC8 close to the seventh scan line SC7 .

[0125] Exemplarily, as shown in FIG3 , the fourth thin film transistor T4 is connected to the third sub-pixel PX3 , and the fifth thin film transistor T5 is connected to the first sub-pixel PX1 .

[0126] In some embodiments, as shown in FIG. 3 , the seventh scan line SC7 has a third bending portion W3 , and the third bending portion W3 bends toward a side close to the eighth scan line SC8 .

[0127] By setting the third bent portion W3, the area between the seventh scan line SC7 and the eighth scan line SC8 and not covered by the fourth thin film transistor T4 and the fifth thin film transistor T5 can be set as an opening area. In this way, the area of ​​the opening area can be further increased, the aperture ratio of the sub-pixel PX can be improved, power consumption can be reduced, and the display effect can be improved.

[0128] In some embodiments, as shown in FIG. 3 , the eighth scan line SC8 has a fourth bending portion W4 . The fourth bending portion W4 bends toward a side close to the seventh scan line SC7 and is disposed opposite to the third bending portion W3 .

[0129] By setting the fourth bending portion W4, the area between the seventh scan line SC7 and the eighth scan line SC8 and not covered by the fourth thin film transistor T4 and the fifth thin film transistor T5 can be set as an opening area. In this way, the area of ​​the opening area can be further increased, the aperture ratio of the sub-pixel PX can be improved, power consumption can be reduced, and the display effect can be improved.

[0130] In some embodiments, as shown in Figure 3, the fourth thin film transistor T4 is located on the first side of the third bend portion W3 and the fourth bend portion W4, and the fifth thin film transistor T5 is located on the second side of the third bend portion W3 and the fourth bend portion W4, and the first side and the second side are the two opposite sides of the third bend portion W3 and the fourth bend portion W4 in the row direction f1.

[0131] Exemplarily, as shown in FIG3 , the fourth thin film transistor T4 is located on the right side of the third bending portion W3 and the fourth bending portion W4 , and the fifth thin film transistor T5 is located on the left side of the third bending portion W3 and the fourth bending portion W4 .

[0132] 3 , the third bend W3 and the fourth bend W4 partially penetrate the second sub-pixel PX2 in the row direction f1. That is, the third bend W3 and the fourth bend W4 are both located within the width of the second sub-pixel PX2 in the row direction f1.

[0133] Exemplarily, as shown in FIG3 , the third bending portion W3 and the fourth bending portion W4 have the same size in the row direction f1 .

[0134] Exemplarily, as shown in FIG3 , the third bending portion W3 and the fourth bending portion W4 have the same size in the column direction f2 .

[0135] In some embodiments, as shown in FIG. 3 , the third bending portion W3 and the fourth bending portion W4 are arranged axially symmetrically with respect to a symmetry axis extending along the row direction.

[0136] In some embodiments, as shown in FIG. 4 or FIG. 5 , the plurality of scan lines SC include a ninth scan line SC9 and a tenth scan line SC10 , which are adjacent to each other. The ninth scan line SC9 and the tenth scan line SC10 are located between two adjacent rows of pixel units P.

[0137] For example, for two adjacent pixel units P in the column direction, the ninth scan line SC9 may be the fifth scan line SC5 of the previous pixel unit P, and the tenth scan line SC10 may be the fourth scan line SC4 of the next pixel unit P, as shown in Figures 4 and 5. Alternatively, the ninth scan line SC9 may be the fourth scan line SC4 of the next pixel unit P, and the tenth scan line SC10 may be the fifth scan line SC5 of the previous pixel unit P, but this disclosure is not limited to this.

[0138] As shown in Figure 4 or Figure 5, the display substrate further includes: a sixth thin film transistor T6 connected to the ninth scan line SC9, and a seventh thin film transistor T7 connected to the tenth scan line SC10, and the sixth thin film transistor T6 is located on the side of the ninth scan line SC9 away from the tenth scan line SC10, and the seventh thin film transistor T7 is located on the side of the tenth scan line SC10 away from the ninth scan line SC9.

[0139] As shown in Figure 4 or Figure 5, by arranging the sixth thin film transistor T6 and the seventh thin film transistor T7 on the outside of the ninth scan line SC9 and the tenth scan line SC10, compared with the display substrate shown in Figure 3, the area between the ninth scan line SC9 and the tenth scan line SC10 and not covered by the thin film transistor T can be set as an opening area, thereby further increasing the area of ​​the opening area, improving the aperture ratio of the sub-pixel PX, reducing power consumption, and improving the display effect.

[0140] Exemplarily, as shown in FIG. 4 , the ninth scan line SC9 and the tenth scan line SC10 are in the shape of bars extending along the row direction f1 .

[0141] In some embodiments, as shown in FIG. 4 , at different positions in the row direction f1 , the intervals between the ninth scan line SC9 and the tenth scan line SC10 are substantially the same.

[0142] 4 , the spacing between the ninth scan line SC9 and the tenth scan line SC10 at position A is substantially equal to the spacing between the ninth scan line SC9 and the tenth scan line SC10 at position B. Position A and position B may be any two different positions in the row direction f1.

[0143] In some embodiments, as shown in FIG5 , the plurality of data lines DT include a first data line DT1 , the sixth thin film transistor T6 and the seventh thin film transistor T7 are both connected to the first lead Y1 , and the first lead Y1 and the first data line DT1 are connected at the intersection through a first via hole.

[0144] Since the sixth thin film transistor T6 and the seventh thin film transistor T7 are connected to the first data line DT1 through the same first via hole, the number of via holes can be reduced, the opening area can be further increased, and the aperture ratio can be improved.

[0145] Exemplarily, the first electrode of the sixth thin film transistor T6 and the first electrode of the seventh thin film transistor T7 are both connected to the first lead Y1 .

[0146] Exemplarily, as shown in FIG. 5 , the first lead line Y1 is located between the ninth scan line SC9 and the tenth scan line SC10 .

[0147] In some embodiments, as shown in FIG. 5 , the first via hole is located between the ninth scan line SC9 and the tenth scan line SC10 .

[0148] In some embodiments, as shown in FIG5 , the ninth scan line SC9 has a fifth bending portion W5 that bends away from the first via hole, and the tenth scan line SC10 has a sixth bending portion W6 that bends away from the first via hole.

[0149] The fifth bending portion W5 and the sixth bending portion W6 are used to form a avoiding area of ​​the first via hole, so as to prevent the ninth scan line SC9 or the tenth scan line SC10 from short-circuiting with the pattern at the first via hole.

[0150] In some embodiments, as shown in FIG5 , the fifth bend W5 and the sixth bend W6 are both arc-shaped, and the centers of the arcs are approximately located at the first via hole, thereby forming an escape zone and avoiding unnecessary occupation of the opening area.

[0151] In some embodiments, as shown in FIG. 6 , the plurality of pixel units P include a plurality of second pixel units P2 arranged along a column direction f2 , and the plurality of second pixel units P2 include sequentially adjacent third pixel units P3 , fourth pixel units P4 , and fifth pixel units P5 .

[0152] As shown in Figure 6, the sixth thin film transistor T6 and the seventh thin film transistor T7 located between the third pixel unit P3 and the fourth pixel unit P4 are respectively connected to the first sub-pixel PX1 located in the same column but different, and the sixth thin film transistor T6 and the seventh thin film transistor T7 located between the fourth pixel unit P4 and the fifth pixel unit P5 are respectively connected to the second sub-pixel PX2 located in the same column but different.

[0153] 6 , the first data line DT1 is located between the first subpixel PX1 and the second subpixel PX2 . The display substrate further includes a first shielding line SD1 located between two adjacent columns of pixel units P, and a second shielding line SD2 located between the second subpixel PX2 and the third subpixel PX3 .

[0154] For example, as shown in Figure 6, in an orthographic projection on the first substrate, the thin film transistor T connected to the first sub-pixel PX1 overlaps with the first shielding line SD1, the thin film transistor T connected to the second sub-pixel PX2 overlaps with the second shielding line SD2, and the thin film transistor T connected to the third sub-pixel PX3 overlaps with the second shielding line SD2. In this way, the occupation of the opening area by the thin film transistors T can be further reduced, further improving the aperture ratio.

[0155] For example, as shown in Figure 6, the thin film transistor T connected to the first sub-pixel PX1 includes a sixth thin film transistor T6 and a seventh thin film transistor T7 located between the third pixel unit P3 and the fourth pixel unit P4. As shown in Figure 6, in an orthographic projection on the first substrate, the sixth thin film transistor T6 and the seventh thin film transistor T7 located between the third pixel unit P3 and the fourth pixel unit P4 overlap with the first shielding line SD1.

[0156] For example, as shown in Figure 6, the thin film transistor T connected to the second sub-pixel PX2 includes a sixth thin film transistor T6 and a seventh thin film transistor T7 located between the fourth pixel unit P4 and the fifth pixel unit P5. As shown in Figure 6, in an orthographic projection on the first substrate, the sixth thin film transistor T6 and the seventh thin film transistor T7 located between the fourth pixel unit P4 and the fifth pixel unit P5 overlap with the second shielding line SD2.

[0157] Exemplarily, as shown in FIG6 , the thin film transistor T connected to the third sub-pixel PX3 includes an eighth thin film transistor T8 , and the eighth thin film transistor T8 overlaps with the second shielding line SD2 .

[0158] In some embodiments, as shown in any one of Figures 1 to 5, the display substrate further includes: a thin film transistor T, a gate of the thin film transistor T is connected to the scan line SC, a first electrode of the thin film transistor T is connected to the data line DT via a lead Y, and a second electrode of the thin film transistor T is connected to the sub-pixel PX.

[0159] 1 to 4 , the lead wire Y and the data line DT are provided in the same layer. In this example, the lead wire Y is directly connected to the data line DT, and the lead wire Y is connected to the first electrode of the thin film transistor T through a via.

[0160] Exemplarily, as shown in FIG5 , the lead Y is provided in the same layer as the active layer of the thin film transistor T. In this example, the lead Y is connected to the data line DT through a via, and the lead Y is directly connected to the first electrode of the thin film transistor T. The first electrode of the thin film transistor T is provided in the same layer as the active layer, and the first electrode of the thin film transistor T is connected to the channel region of the thin film transistor T. The lead Y, for example, includes a first lead Y1.

[0161] The present disclosure provides a display panel, as shown in Figure 7, which includes: a pairing substrate 71, a liquid crystal layer 72, and a display substrate 73 provided in any embodiment, the liquid crystal layer 72 is located between the pairing substrate 71 and the display substrate 73, and a plurality of pixel units are arranged close to the liquid crystal layer 72.

[0162] Those skilled in the art will appreciate that the display panel provided by the present disclosure has the advantages of the above-mentioned display substrate.

[0163] In some embodiments, as shown in FIG. 7 , the cell substrate 71 includes a second substrate 711 and a light shielding layer BM disposed on a side of the second substrate 711 close to the liquid crystal layer 72 .

[0164] As shown in any one of FIG. 1 to FIG. 5 , the light shielding layer BM includes a plurality of openings OP that are separated from each other and arranged in an array. The orthographic projections of the openings OP on the display substrate 73 overlap with the sub-pixels PX.

[0165] For example, in orthographic projection on the display substrate 73, a row of sub-pixels PX overlaps with one or more rows of openings OP. As shown in FIG1 or FIG2 , a row of sub-pixels PX overlaps with a row of openings OP. As shown in any of FIG3 to FIG5 , a row of sub-pixels PX overlaps with two rows of openings OP.

[0166] In some embodiments, as shown in any one of Figures 1 to 5, the light-shielding layer BM includes: a first light-shielding pattern BM1 and a second light-shielding pattern BM2 located between two adjacent rows of openings OP. In the orthographic projection on the display substrate 73, the first light-shielding pattern BM1 and the second light-shielding pattern BM2 both cover the scan line SC located between two adjacent rows of openings OP in the column direction f2. The first light-shielding pattern BM1 also covers at least one thin-film transistor T, and the second light-shielding pattern BM2 does not overlap with the thin-film transistor T.

[0167] For example, as shown in FIG1 , the first light-shielding pattern BM1 and the second light-shielding pattern BM2 both cover three scan lines SC (scan lines SC1, SC2, and SC3 shown in FIG1 ) located between two adjacent rows of openings OP in the column direction f2. The first light-shielding pattern BM1 also covers three thin-film transistors T (thin-film transistors T1, T2, and T3 shown in FIG1 ) connected to the three scan lines SC. The width of the first light-shielding pattern BM1 along the column direction f2 is the same as the width of the second light-shielding pattern BM2 along the column direction f2, for example, both are 27.4 microns.

[0168] For example, as shown in FIG2 , the first light-shielding pattern BM1 and the second light-shielding pattern BM2 both cover three scan lines SC (scan lines SC1, SC2, and SC3 shown in FIG2 ) located between two adjacent rows of openings OP in the column direction f2. The first light-shielding pattern BM1 also covers three thin-film transistors T (thin-film transistors T1, T2, and T3 shown in FIG2 ) connected to the three scan lines SC. The width of the first light-shielding pattern BM1 along the column direction f2 is different from the width of the second light-shielding pattern BM2 along the column direction f2. For example, the width of the first light-shielding pattern BM1 along the column direction f2 is greater than the width of the second light-shielding pattern BM2 along the column direction f2. For example, the width of the first light-shielding pattern BM1 along the column direction f2 is 27.4 microns, and the width of the second light-shielding pattern BM2 along the column direction f2 is 17.1 microns.

[0169] For example, as shown in any of Figures 3 to 5 , both the first light-shielding pattern BM1 and the second light-shielding pattern BM2 cover two scan lines SC (scan lines SC7 and SC8 shown in Figure 3 , or scan lines SC9 and SC10 shown in Figures 4 or 5 ) located between two adjacent rows of openings OP and between two adjacent rows of pixel units P in the column direction f2. The first light-shielding pattern BM1 also covers one thin-film transistor T (T4 or T5 shown in Figure 3 , or T6 or T7 shown in Figure 4 ) or two thin-film transistors T (T6 and T7 shown in Figure 5 ). The width of the first light-shielding pattern BM1 along the column direction f2 is different from the width of the second light-shielding pattern BM2 along the column direction f2. For example, the width of the first light-shielding pattern BM1 along the column direction f2 is greater than the width of the second light-shielding pattern BM2 along the column direction f2. For example, the width of the first light-shielding pattern BM1 along the column direction f2 is 20.6 microns, and the width of the second light-shielding pattern BM2 along the column direction f2 is 10.3 microns.

[0170] For example, as shown in any of Figures 3 to 5 , the first light-shielding pattern BM1 and the second light-shielding pattern BM2 each cover a scan line SC (such as scan line SC6 shown in Figures 3 to 5 ) located between two adjacent rows of openings OP and extending through the pixel unit P in the column direction f2. The first light-shielding pattern BM1 also covers a thin-film transistor T connected to the scan line SC. The width of the first light-shielding pattern BM1 along the column direction f2 is different from the width of the second light-shielding pattern BM2 along the column direction f2. For example, the width of the first light-shielding pattern BM1 along the column direction f2 is greater than the width of the second light-shielding pattern BM2 along the column direction f2. For example, the width of the first light-shielding pattern BM1 along the column direction f2 is 14 microns, and the width of the second light-shielding pattern BM2 along the column direction f2 is 3.5 microns.

[0171] In some embodiments, as shown in any of Figures 3 to 5 , the display substrate 73 includes: a sixth scan line SC6 that runs through the pixel cells P, and two scan lines SC disposed between two adjacent rows of pixel cells P (scan lines SC7 and SC8 shown in Figure 3 , or scan lines SC9 and SC10 shown in Figures 4 or 5 ). The light-shielding layer BM also includes a third light-shielding pattern BM3 and a fourth light-shielding pattern BM4. In an orthographic projection on the display substrate 73, the third light-shielding pattern BM3 covers the sixth scan line SC6 and the thin-film transistor T connected to the sixth scan line SC6 in the column direction f2. The fourth light-shielding pattern BM4 covers the two scan lines SC and at least one thin-film transistor T (T4 or T5 shown in Figure 3 , T6 or T7 shown in Figure 4 , or T6 and T7 shown in Figure 5 ) located between two adjacent rows of pixel cells P in the column direction. The width of the third light-shielding pattern BM3 along the column direction f2 is different from the width of the fourth light-shielding pattern BM4 along the column direction f2.

[0172] Exemplarily, as shown in any one of FIG. 3 to FIG. 5 , the width of the third light-shielding pattern BM3 along the column direction f2 is less than or equal to the width of the fourth light-shielding pattern BM4 along the column direction f2 .

[0173] In some embodiments, the ratio of the width of the third light-shielding pattern BM3 along the column direction f2 to the width of the fourth light-shielding pattern BM4 along the column direction f2 is greater than or equal to 0.5 and less than or equal to 0.8. Setting the ratio greater than or equal to 0.5 can prevent light leakage. Setting the ratio greater than or equal to 0.8 can help increase the aperture ratio.

[0174] For example, as shown in any one of FIG. 3 to FIG. 5 , the width of the third light-shielding pattern BM3 along the column direction f2 is 14 micrometers, the width of the fourth light-shielding pattern BM4 along the column direction f2 is 20.6 micrometers, and the ratio therebetween is approximately 0.68.

[0175] The present disclosure provides a display device, comprising: a display substrate or a display panel as provided in any embodiment; and a source driver chip bound and connected to the display substrate, for providing data signals to the data lines.

[0176] For example, the source driver chip may provide a data signal to the same data line in a time-division manner, so as to drive a plurality of sub-pixels connected to the same data line to display in sequence.

[0177] Those skilled in the art will appreciate that the display device provided by the present disclosure has the advantages of the above-mentioned display substrate or display panel.

[0178] Exemplarily, the display device further includes: a gate driving circuit, configured to sequentially provide scanning signals to the scanning lines, where the scanning signals are, for example, pulse signals.

[0179] The display device provided by the present disclosure can be: a display module, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a car display device, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function.

[0180] In the present disclosure, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0181] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the present disclosure.

[0182] As used herein, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus that includes the element.

[0183] References herein to "one embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "an example," "an example," "some examples," and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0184] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0185] When describing some embodiments, the expressions "coupled" and "connected" may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0186] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0187] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0188] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0189] The use of "for" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0190] The use of "based on" or "according to" in this document is intended to be open and inclusive. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values.

[0191] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0192] As used herein, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two being equal is less than or equal to 5% of either one. "Flush" includes absolute equality and approximate flushness, wherein the acceptable deviation range of approximate flushness can be, for example, the distance between the two being flush is less than or equal to 5% of either one's size.

[0193] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0194] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0195] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A display substrate, comprising: A first substrate, and a plurality of scan lines, a plurality of data lines, and a plurality of pixel units located on one side of the first substrate, wherein the scan lines extend along a row direction, the data lines extend along a column direction, and the plurality of pixel units are arranged in an array along the row direction and the column direction respectively; The pixel unit comprises: a plurality of sub-pixels arranged along a row direction, wherein the plurality of sub-pixels in the same pixel unit are connected to the same data line and are respectively connected to different scan lines; wherein the size of the sub-pixel along the column direction is greater than the size of the sub-pixel along the row direction; and M scan lines are arranged between two adjacent rows of pixel units, where M is greater than or equal to 2 and less than or equal to the number N of sub-pixels contained in one of the pixel units. When M is equal to N, the M scan lines are respectively connected to different sub-pixels of the same pixel unit. When M is less than N, at least two of the M scan lines are connected to sub-pixels of different pixel units.

2. The display substrate according to claim 1, wherein: The plurality of pixel units include a first pixel unit, and the plurality of scan lines include: A first scan line, a second scan line, and a third scan line are sequentially arranged along a column direction, wherein the first scan line, the second scan line, and the third scan line are respectively connected to different sub-pixels in the first pixel unit, and the first scan line, the second scan line, and the third scan line are located on the same side of the first pixel unit.

3. The display substrate according to claim 2, wherein: The display substrate further comprises: a first thin film transistor connected to the first scan line, a second thin film transistor connected to the second scan line, and a third thin film transistor connected to the third scan line; The first thin film transistor, the second thin film transistor and the third thin film transistor are all located between the first scan line and the third scan line.

4. The display substrate according to claim 3, wherein: The first scanning line is disposed close to the first pixel unit. The first scanning line has a first bending portion, and the first bending portion bends toward a side close to the first pixel unit.

5. The display substrate according to claim 4, wherein: The pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence along a row direction; The first bending portion completely penetrates the second sub-pixel and partially penetrates the first sub-pixel and the third sub-pixel in the row direction.

6. The display substrate according to any one of claims 3 to 5, wherein: The pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence along a row direction; The second scanning line has a second bending portion, and the second bending portion is bent toward a side close to the first scanning line.

7. The display substrate according to claim 1, wherein: The plurality of pixel units include a second pixel unit, and the plurality of scan lines include: The fourth scan line, the fifth scan line and the sixth scan line are respectively connected to different sub-pixels in the second pixel unit, and the fourth scan line and the fifth scan line are located at different sides of the second pixel unit.

8. The display substrate according to claim 7, wherein: The sixth scan line runs through the second pixel unit.

9. The display substrate according to claim 7 or 8, wherein: The plurality of scan lines include a seventh scan line and an eighth scan line that are adjacent to each other, and the seventh scan line and the eighth scan line are located between two adjacent rows of pixel units; The display substrate further includes: a fourth thin film transistor connected to the seventh scan line, and a fifth thin film transistor connected to the eighth scan line, and the fourth thin film transistor and the fifth thin film transistor are both located between the seventh scan line and the eighth scan line.

10. The display substrate according to claim 9, wherein: The seventh scanning line has a third bending portion, and the third bending portion is bent toward a side close to the eighth scanning line; The eighth scanning line has a fourth bending portion, the fourth bending portion is bent toward a side close to the seventh scanning line and is arranged opposite to the third bending portion; Among them, the fourth thin film transistor is located on the first side of the third bending portion and the fourth bending portion, and the fifth thin film transistor is located on the second side of the third bending portion and the fourth bending portion, and the first side and the second side are two opposite sides of the third bending portion and the fourth bending portion in the row direction.

11. The display substrate according to claim 10, wherein: The third bending portion and the fourth bending portion are arranged axially symmetrically with respect to a symmetry axis extending along the row direction.

12. The display substrate according to claim 7 or 8, wherein: The plurality of scan lines include a ninth scan line and a tenth scan line that are adjacent to each other, and the ninth scan line and the tenth scan line are located between two adjacent rows of pixel units; The display substrate also includes: a sixth thin film transistor connected to the ninth scan line, and a seventh thin film transistor connected to the tenth scan line, and the sixth thin film transistor is located on the side of the ninth scan line away from the tenth scan line, and the seventh thin film transistor is located on the side of the tenth scan line away from the ninth scan line.

13. The display substrate according to claim 12, wherein: At different positions in the row direction, the intervals between the ninth scanning line and the tenth scanning line are substantially the same.

14. The display substrate according to claim 12, wherein: The plurality of data lines include a first data line, the sixth thin film transistor and the seventh thin film transistor are both connected to a first lead line, and the first lead line and the first data line are connected at a crossing position through a first via hole.

15. The display substrate according to claim 14, wherein: The first via hole is located between the ninth scan line and the tenth scan line; and The ninth scanning line has a fifth bending portion, which is bent toward a side away from the first via hole. The tenth scanning line has a sixth bending portion, which is bent toward a side away from the first via hole.

16. The display substrate according to claim 15, wherein: The fifth bending portion and the sixth bending portion are both in the shape of arcs, and the centers of the arcs are substantially located at the first via hole.

17. The display substrate according to any one of claims 14 to 16, wherein: The pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence along a row direction; The plurality of pixel units include a plurality of second pixel units arranged along a column direction, and the plurality of second pixel units include a third pixel unit, a fourth pixel unit, and a fifth pixel unit that are adjacent to each other in sequence; The sixth thin film transistor and the seventh thin film transistor located between the third pixel unit and the fourth pixel unit are respectively connected to different first sub-pixels located in the same column, and the seventh thin film transistor located in the fourth pixel unit is respectively connected to different first sub-pixels located in the same column. The sixth thin film transistor and the seventh thin film transistor between the unit and the fifth pixel unit are respectively connected to different second sub-pixels located in the same column.

18. The display substrate according to claim 17, wherein: The first data line is located between the first sub-pixel and the second sub-pixel; The display substrate further includes: a first shielding line located between two adjacent columns of pixel units, and a second shielding line located between the second sub-pixel and the third sub-pixel; In the orthographic projection on the first substrate, the thin film transistor connected to the first sub-pixel overlaps with the first shielding line, the thin film transistor connected to the second sub-pixel overlaps with the second shielding line, and the thin film transistor connected to the third sub-pixel overlaps with the second shielding line.

19. The display substrate according to any one of claims 1 to 18, wherein: The pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence along a row direction; The display substrate further includes at least one of the following: A touch line extending along a column direction and arranged in the same layer as the data line; The shielding lines extend along the column direction and are respectively arranged in different layers from the data lines and the scanning lines; The touch control line, the data line or the shielding line is respectively arranged between the first sub-pixel and the second sub-pixel, between the second sub-pixel and the third sub-pixel, and between two adjacent columns of pixel units.

20. The display substrate according to any one of claims 1 to 19, wherein: The display substrate further comprises: A thin film transistor, wherein a gate electrode is connected to the scan line, a first electrode is connected to the data line via a lead wire, and a second electrode is connected to the sub-pixel; Wherein, the lead wire is arranged in the same layer as the data wire, or is arranged in the same layer as the active layer of the thin film transistor.

21. A display panel, comprising: A cell substrate, a liquid crystal layer, and a display substrate as claimed in any one of claims 1 to 20, wherein the liquid crystal layer is located between the cell substrate and the display substrate, and the plurality of pixel units are arranged close to the liquid crystal layer.

22. The display panel according to claim 21, wherein: The display substrate further comprises a thin film transistor, and the thin film transistor is respectively connected to the scan line, the data line and the sub-pixel; The cell-matching substrate comprises: a second substrate, and a light shielding layer arranged on a side of the second substrate close to the liquid crystal layer, the light shielding layer comprises a plurality of openings separated from each other and arranged in an array, and the orthographic projection of the openings on the display substrate overlaps with the sub-pixel; The light shielding layer comprises: a first light shielding pattern and a second light shielding pattern located between two adjacent rows of openings, wherein in an orthographic projection on the display substrate, the first light shielding pattern and the second light shielding pattern both cover the scan line located between the two adjacent rows of openings in a column direction, the first light shielding pattern also covers at least one thin film transistor, and the second light shielding pattern has no overlap with the thin film transistor; The width of the first light-shielding pattern along the column direction is different from the width of the second light-shielding pattern along the column direction.

23. The display panel according to claim 22, wherein: The display substrate comprises: a sixth scanning line running through the pixel unit, and two scanning lines arranged between two adjacent rows of pixel units; The light shielding layer further includes a third light shielding pattern and a fourth light shielding pattern, wherein in the orthographic projection on the display substrate, the third light shielding pattern covers the sixth scanning line and the thin film transistor connected to the sixth scanning line in the column direction, and the fourth light shielding pattern covers two scanning lines and at least one thin film transistor located between two adjacent rows of pixel units in the column direction; Wherein, the width of the third light-shielding pattern along the column direction is different from the width of the fourth light-shielding pattern along the column direction.

24. The display panel according to claim 23, wherein: A ratio between a width of the third light-shielding pattern along the column direction and a width of the fourth light-shielding pattern along the column direction is greater than or equal to 0.5 and less than or equal to 0.

8.

25. A display device comprising: The display panel according to any one of claims 21 to 24; as well as The source driver chip is bound and connected to the display substrate and is used to provide data signals to the data lines.

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