Pixel array, driving method thereof and display device

Abstract

The invention provides a pixel array, a driving method thereof and a display device, and the pixel array comprises a plurality of grid lines which extend in the row direction and are arranged in the column direction; the data lines extend in the column direction and are arranged in the row direction; each pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel which are arranged in the row direction, each column of pixel units is correspondingly provided with a data line, and the first sub-pixel and the second sub-pixel are directly and electrically connected with the data line of the corresponding column. The third sub-pixels are electrically connected with the data lines of the corresponding columns after being connected in series with the second sub-pixels; each row of pixel units is correspondingly provided with two grid lines, the two grid lines comprise a first grid line and a second grid line, the first sub-pixel and the third sub-pixel are connected to the first grid line of the corresponding row, and the second sub-pixel is connected to the second grid line of the corresponding row.

Description

Pixel array, driving method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel array, a driving method thereof, and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the advantages of small size, low power consumption, high image quality, no radiation and easy portability. It has developed rapidly in recent years and has gradually replaced traditional cathode ray tube display (CRT) and occupied a dominant position in the current flat panel display market.

[0003] Summary of the Invention

[0004] The present disclosure provides a pixel array, a driving method thereof, and a display device. The specific solutions are as follows:

[0005] An embodiment of the present disclosure provides a pixel array, comprising:

[0006] A plurality of gate lines extending in a row direction and arranged in a column direction;

[0007] a plurality of data lines extending along the column direction and arranged along the row direction;

[0008] Multiple rows and columns of pixel units, each of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel arranged along the row direction, wherein each column of the pixel units corresponds to a data line, the first sub-pixel and the second sub-pixel are directly electrically connected to the data line of the corresponding column, and the third sub-pixel is electrically connected to the data line of the corresponding column after being connected in series with the second sub-pixel; each row of the pixel units corresponds to two gate lines, the two gate lines include a first gate line and a second gate line, the first sub-pixel and the third sub-pixel are both connected to the first gate line of the corresponding row, and the second sub-pixel is connected to the second gate line of the corresponding row.

[0009] Optionally, in the above pixel array provided by the embodiment of the present disclosure, the first sub-pixel includes a first thin film transistor and a first pixel electrode, the second sub-pixel includes a second thin film transistor and a second pixel electrode, and the third sub-pixel includes a third thin film transistor and a third pixel electrode; wherein,

[0010] The gate of the first thin film transistor and the gate of the third thin film transistor are both connected to the first gate line, and the gate of the second thin film transistor is connected to the second gate line;

[0011] The first electrode of the first thin film transistor and the first electrode of the second thin film transistor are directly electrically connected to the data line of the corresponding column, the second electrode of the first thin film transistor is electrically connected to the first pixel electrode, the second electrode of the second thin film transistor is electrically connected to the second pixel electrode, the first electrode of the third thin film transistor is electrically connected to the second electrode of the second thin film transistor, and the second electrode of the third thin film transistor is electrically connected to the third pixel electrode.

[0012] Optionally, in the above-mentioned pixel array provided by the embodiment of the present disclosure, the first sub-pixel, the second sub-pixel and the third sub-pixel are arranged in sequence along the row direction, and the data line is set between the first sub-pixel and the second sub-pixel.

[0013] Optionally, in the above pixel array provided in an embodiment of the present disclosure, the light emitting color of the first sub-pixel is red, the light emitting color of the second sub-pixel is green, and the light emitting color of the third sub-pixel is blue;

[0014] Alternatively, the light emitting color of the first sub-pixel is blue, the light emitting color of the second sub-pixel is green, and the light emitting color of the third sub-pixel is red.

[0015] Optionally, in the above-mentioned pixel array provided by the embodiment of the present disclosure, the second sub-pixel, the first sub-pixel and the third sub-pixel are arranged sequentially along the row direction, and the data line is set on a side of the second sub-pixel away from the first sub-pixel.

[0016] Optionally, in the above pixel array provided in an embodiment of the present disclosure, the light emitting color of the second sub-pixel is red, the light emitting color of the first sub-pixel is green, and the light emitting color of the third sub-pixel is blue;

[0017] Alternatively, the light emitting color of the second sub-pixel is blue, the light emitting color of the first sub-pixel is green, and the light emitting color of the third sub-pixel is red.

[0018] Optionally, in the above-mentioned pixel array provided by an embodiment of the present disclosure, the two gate lines corresponding to the pixel units in each row are arranged on the same side of the pixel units in the corresponding row.

[0019] Optionally, in the above-mentioned pixel array provided by an embodiment of the present disclosure, the thin film transistors corresponding to the pixel units in each row are arranged between two gate lines of the pixel units in the corresponding row.

[0020] Correspondingly, an embodiment of the present disclosure further provides a display device, including a display panel, wherein the display panel includes any one of the above-mentioned pixel arrays provided by the embodiment of the present disclosure.

[0021] Accordingly, an embodiment of the present disclosure further provides a method for driving a pixel array, for driving any of the above pixel arrays provided by the embodiment of the present disclosure, the driving method comprising:

[0022] When displaying a frame of pixel images, the first gate line and the second gate line are controlled to be turned on at the same time, and a data voltage corresponding to the third sub-pixel is input to the first sub-pixel, the second sub-pixel and the third sub-pixel through the data line;

[0023] controlling the first gate line to be turned on, controlling the second gate line to be turned off, and inputting a data voltage corresponding to the first sub-pixel to the first sub-pixel through the data line;

[0024] The first gate line is controlled to be closed, the second gate line is controlled to be opened, and a data voltage corresponding to the second sub-pixel is input to the second sub-pixel through the data line.

[0025] Accordingly, an embodiment of the present disclosure further provides a method for driving a pixel array, for driving any of the above pixel arrays provided by the embodiment of the present disclosure, the driving method comprising:

[0026] When displaying a frame of pixel images, the first gate line and the second gate line are controlled to be turned on at the same time, and a data voltage corresponding to the third sub-pixel is input to the first sub-pixel, the second sub-pixel and the third sub-pixel through the data line;

[0027] controlling the first gate line to be closed, controlling the second gate line to be opened, and inputting a data voltage corresponding to the second sub-pixel to the second sub-pixel through the data line;

[0028] The first gate line is controlled to be turned on, the second gate line is controlled to be turned off, and a data voltage corresponding to the first sub-pixel is input to the first sub-pixel through the data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic structural diagram of a pixel array provided in the related art;

[0030] FIG2 is a schematic structural diagram of another pixel array provided in the related art;

[0031] FIG3 is a schematic structural diagram of another pixel array provided in the related art;

[0032] FIG4 is a schematic structural diagram of a pixel array provided by an embodiment of the present disclosure;

[0033] FIG5 is a schematic diagram of the layout corresponding to a pixel unit in FIG4 ;

[0034] FIG6 is a schematic structural diagram of another pixel array provided by an embodiment of the present disclosure;

[0035] FIG7 is a schematic diagram of the layout corresponding to a pixel unit in FIG6 ;

[0036] FIG8 is a schematic structural diagram of another pixel array provided by an embodiment of the present disclosure;

[0037] FIG9 is a schematic diagram of the layout corresponding to a pixel unit in FIG8 ;

[0038] FIG10 is a schematic structural diagram of another pixel array provided by an embodiment of the present disclosure;

[0039] FIG11 is a schematic diagram of the layout corresponding to a pixel unit in FIG10 ;

[0040] FIG12 is a schematic structural diagram of another pixel array provided by an embodiment of the present disclosure;

[0041] FIG13 is a schematic structural diagram of another pixel array provided by an embodiment of the present disclosure;

[0042] FIG14 is a schematic structural diagram of another pixel array provided by an embodiment of the present disclosure;

[0043] FIG15 is a schematic structural diagram of another pixel array provided by an embodiment of the present disclosure;

[0044] FIG16 is a schematic flow chart of a driving method for a pixel array provided in an embodiment of the present disclosure;

[0045] FIG17 is a schematic flow chart of a method for driving a pixel array according to an embodiment of the present disclosure;

[0046] FIG18 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words “include” or “comprise” and the like used in this disclosure mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0049] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0050] Currently, the commonly used pixel architectures include Single Gate (single gate, each row of pixel units is driven by a row of scan lines), Dual Gate (double gate, each row of pixel units is driven by two rows of scan lines), and Triple Gate (three gates, each row of pixel units is driven by three rows of scan lines), as shown in Figures 1-3. Figure 1 is a single-gate pixel architecture provided in the relevant technology, Figure 2 is a dual-gate pixel architecture provided in the relevant technology, and Figure 3 is a triple-gate pixel architecture provided in the relevant technology, where G1, G2... are scan lines, D1, D2... are data lines, and each pixel unit includes multiple sub-pixels of different luminous colors (for example, R, G, B). At the same display panel resolution, different pixel architectures require different numbers of source driver ICs (integrated circuits), which in turn affects the production cost of the display panel. Compared to the single-gate pixel architecture shown in FIG1 , the dual-gate pixel architecture shown in FIG2 can reduce the number of source driver ICs to 2 / 3 of that in FIG1 , and the triple-gate pixel architecture shown in FIG3 can reduce the number of source driver ICs to 1 / 3 of that in FIG1 . Thus, the triple-gate pixel architecture shown in FIG3 can significantly reduce the production cost of source driver ICs. However, since the triple-gate pixel architecture requires a large number of gate lines, the gate lines occupy a large area of ​​the display area, thereby reducing the aperture ratio of the display panel. Therefore, how to provide a method that can reduce the number of source driver ICs to 1 / 3 of that in FIG1 while also increasing the aperture ratio of the display area is a technical problem that those skilled in the art urgently need to solve.

[0051] In view of this, an embodiment of the present disclosure provides a pixel array, as shown in Figures 4 to 15. Figures 4, 6, 8, 10, and 12 to 15 are respectively schematic structural diagrams of the pixel array provided in the embodiment of the present disclosure. Figure 5 is a schematic layout diagram corresponding to a pixel unit in Figure 4, Figure 7 is a schematic layout diagram corresponding to a pixel unit in Figure 6, Figure 9 is a schematic layout diagram corresponding to a pixel unit in Figure 8, and Figure 11 is a schematic layout diagram corresponding to a pixel unit in Figure 10. The pixel array includes:

[0052] A plurality of gate lines (G1, G2, G1, G2, ...) extending along a row direction X and arranged along a column direction Y;

[0053] A plurality of data lines (D1, D2, D3, ...) extending along the column direction Y and arranged along the row direction X;

[0054] There are multiple rows and columns of pixel units P, each pixel unit P includes a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 arranged along a row direction X, wherein each column of pixel units P is correspondingly provided with a data line (for example, the first column of pixel units P from the left is correspondingly provided with a data line D1, the second column of pixel units P from the left is correspondingly provided with a data line D2, the third column of pixel units P from the left is correspondingly provided with a data line D3...), and the first sub-pixels P1 and the second sub-pixels P2 are directly electrically connected to the data lines of the corresponding columns (for example, each first sub-pixel P1 and each second sub-pixel P2 in the first column of pixel units P is directly electrically connected to the data line D1 corresponding to the first column of pixel units P, each first sub-pixel P1 and each second sub-pixel P2 in the second column of pixel units P is directly electrically connected to the data line D2 corresponding to the second column of pixel units P, and each first sub-pixel P1 and each second pixel P2 in the third column of pixel units P is directly electrically connected to the data line D1 corresponding to the third column of pixel units P). The corresponding data line D3 is electrically connected...), the third sub-pixel P3 is electrically connected to the data line of the corresponding column after being connected in series with the second sub-pixel P2 (for example, each third sub-pixel P3 in the first column of pixel units P is electrically connected to the data line D1 corresponding to the first column of pixel units P after being connected in series with the corresponding second sub-pixel P2, each third sub-pixel P3 in the second column of pixel units P is electrically connected to the data line D2 corresponding to the second column of pixel units P after being connected in series with the corresponding second sub-pixel P2, and each third sub-pixel P3 in the third column of pixel units P is electrically connected to the data line D3 corresponding to the third column of pixel units P after being connected in series with the corresponding second sub-pixel P2...); two gate lines are correspondingly arranged for each row of pixel units P, and the two gate lines include a first gate line G1 and a second gate line G2, the first sub-pixel P1 and the third sub-pixel P3 are both connected to the first gate line G1 of the corresponding row, and the second sub-pixel P2 is connected to the second gate line G2 of the corresponding row.

[0055] The above-mentioned pixel array provided by the embodiment of the present disclosure can realize display driving of different sub-pixels by using one data line and two gate lines for each pixel unit. Compared with the three-gate pixel architecture in the related art, the present disclosure can reduce the number of data lines to 1 / 3 of the single-gate pixel structure while also reducing the number of gate lines for each row of pixel units. This can increase the display area and improve the aperture ratio on the one hand; on the other hand, the reduction in the number of gate lines can also reduce the parasitic capacitance between the gate lines and other signal lines (such as data lines, power lines, etc.), thereby increasing the charging time of each row of pixel units, ensuring the charging rate, and improving the display effect.

[0056] In a specific implementation, in the above pixel array provided by the embodiment of the present disclosure, as shown in FIG4 to FIG15 , the first sub-pixel P1 includes a first thin film transistor T1 and a first pixel electrode 1, the second sub-pixel P2 includes a second thin film transistor T2 and a second pixel electrode 2, and the third sub-pixel P3 includes a third thin film transistor T3 and a third pixel electrode 3; wherein,

[0057] The gate G11 of the first thin film transistor T1 and the gate G13 of the third thin film transistor T3 are both connected to the first gate line G1, and the gate G12 of the second thin film transistor T2 is connected to the second gate line G2;

[0058] The first electrode S11 of the first thin-film transistor T1 and the first electrode S12 of the second thin-film transistor T2 are directly electrically connected to the data line of the corresponding column (for example, the first electrode S11 of each first thin-film transistor T1 and the first electrode S12 of each second thin-film transistor T2 in the first column of pixel units P are directly electrically connected to the data line D1 corresponding to the first column of pixel units P, the first electrode S11 of each first thin-film transistor T1 and the first electrode S12 of each second thin-film transistor T2 in the second column of pixel units P are directly electrically connected to the data line D2 corresponding to the second column of pixel units P, the first electrode S11 of each first thin-film transistor T1 and the first electrode S12 of each second thin-film transistor T2 in the third column of pixel units P are directly electrically connected to the data line D3 corresponding to the third column of pixel units P, etc.), the second electrode D11 of the first thin-film transistor T1 is electrically connected to the first pixel electrode 1, the second electrode D12 of the second thin-film transistor T2 is electrically connected to the second pixel electrode 2, the first electrode S13 of the third thin-film transistor T3 is electrically connected to the second electrode D12 of the second thin-film transistor T2, and the second electrode D13 of the third thin-film transistor T3 is electrically connected to the third pixel electrode 3.

[0059] In a specific implementation, in the pixel array provided in the embodiments of the present disclosure, as shown in Figures 5, 7, 9, and 11, the first thin-film transistor T1 further includes a first active layer Act1, the second thin-film transistor T2 further includes a second active layer Act2, and the third thin-film transistor T3 further includes a third active layer Act3. The first active layer Act1, the second active layer Act2, and the third active layer Act3 may be an integral structure. Except for the semiconductor region overlapping with each gate electrode, the remaining portions of the integral structure may be semiconductor-doped conductors. Thus, the first electrode S11 (e.g., source) of the first thin-film transistor T1 is fabricated using a source-drain metal layer, and the second electrode D11 (e.g., drain) of the first thin-film transistor T1 may be directly a conductor on one side of the first active layer Act1. Thus, the first pixel electrode 1 may be electrically connected to the conductor on one side of the first active layer Act1 via a first via V1 penetrating the passivation layer and a second via V2 penetrating the planar layer. The first via V1 and the second via V2 are sleeve holes. Specifically, the manufacturing process of the first electrode and the second electrode of the second thin film transistor T2 and the third thin film transistor T3 is similar to that of the first thin film transistor T1 , and will not be described in detail here.

[0060] In a specific implementation, in the pixel array provided in the embodiments of the present disclosure, as shown in Figures 5, 7, 9, and 11, when manufacturing thin-film transistors, a source-drain metal layer can be first manufactured on a substrate, followed by an active layer, and then a gate layer. In this way, the source-drain metal layer can be used to shield the active layer of the thin-film transistor to prevent light from damaging the performance of the thin-film transistor. For example, a first shielding portion 4, which is provided in the same layer as the source-drain metal layer, is provided below the first active layer Act1 of the first thin-film transistor T1; a second shielding portion 5, which is provided in the same layer as the source-drain metal layer, is provided below the second active layer Act2 of the second thin-film transistor T2; and a third shielding portion 6, which is provided in the same layer as the source-drain metal layer, is provided below the third active layer Act3 of the third thin-film transistor T3.

[0061] Specifically, as shown in Figures 4-15, subpixels in the same column emit the same color, and subpixels in the same row are arranged in red, green, and blue order. Each pixel unit achieves display drive by using one data line and two gate lines to drive three thin-film transistors, where the second and third thin-film transistors T2 and T3 are connected in series. The first gate line G1 drives the first and third thin-film transistors T1 and T3, while the second gate line G2 drives the second thin-film transistor T2. Charge data is written to the first subpixel P1 by switching the first thin-film transistor T1. Charge data is written to the second subpixel P2 by switching the second thin-film transistor T2. Charge data is written to the third subpixel P3 by switching the second and third thin-film transistors T2 and T3. Charge data is written to the third subpixel P3 only when both the second and third thin-film transistors T2 and T3 are turned on. If only one of the second and third thin-film transistors T2 and T3 is turned on, the third subpixel P3 cannot be charged. Therefore, by adopting the pixel array arrangement shown in Figures 4 to 15 provided in the embodiments of the present disclosure, and coordinating the switching of the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 with corresponding timing control, the display driving of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 can be realized.

[0062] In a specific implementation, in the above-mentioned pixel array provided by the embodiment of the present disclosure, as shown in Figures 4 to 11, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are arranged in sequence along the row direction X, and the data lines (D1, D2, D3 ...) are arranged between the first sub-pixel P1 and the second sub-pixel P2. Specifically, since the third sub-pixel P3 is connected in series with the second sub-pixel P2, that is, the third thin-film transistor T3 and the second thin-film transistor T2 are connected in series, by arranging the data lines (D1, D2, D3 ...) between the first sub-pixel P1 and the second sub-pixel P2, the first electrode S11 of the first thin-film transistor T1 and the first electrode S12 of the second thin-film transistor T2 can be electrically connected to the data lines between the two, thereby simplifying the layout difficulty of the pixel array. Of course, in a specific implementation, the data lines (D1, D2, D3 ...) are not limited to being arranged between the first sub-pixel P1 and the second sub-pixel P2, and can also be arranged at other locations, as long as the connection relationship between the thin-film transistors and between the thin-film transistors and the data lines in Figures 4 to 11 can be achieved.

[0063] In a specific implementation, in the above-mentioned pixel array provided in the embodiment of the present disclosure, as shown in Figures 4 to 7, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are arranged in sequence from left to right along the row direction X, the luminous color of the first sub-pixel P1 is red (R), the luminous color of the second sub-pixel P2 is green (G), and the luminous color of the third sub-pixel P3 is blue (B); in this way, the leftmost sub-pixel in each pixel unit P is the first sub-pixel P1, and the luminous color is red (R); the middle position in each pixel unit P is the second sub-pixel P2, and the luminous color is green (G); and the rightmost sub-pixel in each pixel unit P is the third sub-pixel P3, and the luminous color is blue (B).

[0064] In a specific implementation, in the above-mentioned pixel array provided by the embodiment of the present disclosure, as shown in Figures 4 and 5, each row of pixel units P corresponds to a first gate line G1 and a second gate line G2, wherein the first gate line G1 is farther away from the next row of pixel units P, and the second gate line G2 is closer to the next row of pixel units P.

[0065] In a specific implementation, in the above-mentioned pixel array provided by the embodiment of the present disclosure, as shown in Figures 6 and 7, each row of pixel units P corresponds to a first gate line G1 and a second gate line G2, wherein the second gate line G2 is farther away from the next row of pixel units P, and the first gate line G1 is closer to the next row of pixel units P.

[0066] In a specific implementation, when the pixel array shown in FIG. 4 to FIG. 7 displays a frame of pixel images, the specific driving method includes the following steps (taking the display of the first row of pixel units P as an example):

[0067] (1) The first gate line G1 and the second gate line G2 corresponding to the first row of pixel units P are controlled to be turned on at the same time, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are turned on at the same time. The data voltage b corresponding to the third sub-pixel P3 is input to the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 through the data lines (D1, D2, D3...). The pixel voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are all charged to the data voltage b. At this time, the data voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 from left to right along the row direction X are all b.

[0068] (2) The first gate line G1 is controlled to be turned on, and the second gate line G2 is controlled to be turned off. At this time, the first thin film transistor T1 and the third thin film transistor T3 are turned on at the same time, and the second thin film transistor T2 is turned off. The data voltage r corresponding to the first sub-pixel P1 is input to the first sub-pixel P1 through the data line (D1, D2, D3...). At this time, the pixel voltage of the first sub-pixel P1 is charged to r because the first thin film transistor T1 is turned on, and the pixel voltage of the second sub-pixel P2 continues to be the data voltage b because the second thin film transistor T2 is turned off. The pixel voltage of the third sub-pixel P3 continues to be the data voltage b because the third thin film transistor T3 is turned on and the second thin film transistor T2 is turned off. At this time, the data voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 from left to right along the row direction X are r, b, and b respectively.

[0069] (3) The first gate line G1 is controlled to be closed, and the second gate line G2 is controlled to be turned on. At this time, the first thin film transistor T1 and the third thin film transistor T3 are both turned off, and the second thin film transistor T2 is turned on. The data voltage g corresponding to the second sub-pixel P2 is input to the second sub-pixel P2 through the data line (D1, D2, D3...). At this time, the pixel voltage of the first sub-pixel P1 continues to be the data voltage r because the first thin film transistor T1 is turned off. The pixel voltage of the second sub-pixel P2 is charged to the data voltage g because the second thin film transistor T2 is turned on. The pixel voltage of the third sub-pixel P3 continues to be the data voltage b because the second thin film transistor T2 is turned on and the third thin film transistor T3 is turned off. At this time, the data voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 from left to right along the row direction X are r, g, and b respectively.

[0070] (4) The first gate line G1 and the second gate line G2 are both turned off, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are all turned off. From left to right along the row direction X, the first sub-pixel P1 maintains the data voltage r, the second sub-pixel P2 maintains the data voltage g, and the third sub-pixel P3 maintains the data voltage b. The first row of pixel unit arrays realizes normal light-emitting display.

[0071] Afterwards, the second row of pixel units P, the third row of pixel units P, etc. sequentially implement the light-emitting display of each row according to the above steps (1)-(4).

[0072] In a specific implementation, the pixel array shown in FIG. 4 to FIG. 7 may also adopt the following driving method when displaying a frame of pixel images (taking the display of the first row of pixel units P as an example):

[0073] (1) The first gate line G1 and the second gate line G2 corresponding to the first row of pixel units P are controlled to be turned on at the same time, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are turned on at the same time. The data voltage b corresponding to the third sub-pixel P3 is input to the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 through the data lines (D1, D2, D3...). The pixel voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are all charged to the data voltage b. At this time, the data voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 from left to right along the row direction X are all b.

[0074] (2) The first gate line G1 is controlled to be closed, and the second gate line G2 is controlled to be turned on. At this time, the first thin film transistor T1 and the third thin film transistor T3 are turned off at the same time, and the second thin film transistor T2 is turned on. The data voltage g corresponding to the second sub-pixel P2 is input to the second sub-pixel P2 through the data line (D1, D2, D3...). At this time, the pixel voltage of the second sub-pixel P2 is charged to g because the second thin film transistor T2 is turned on. The pixel voltage of the first sub-pixel P1 continues to be the data voltage b because the first thin film transistor T1 is turned off. The pixel voltage of the third sub-pixel P3 continues to be the data voltage b because the third thin film transistor T3 is turned off and the second thin film transistor T2 is turned on. At this time, the data voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 from left to right along the row direction X are b, g, and b respectively.

[0075] (3) The first gate line G1 is controlled to be turned on, and the second gate line G2 is controlled to be turned off. At this time, the first thin film transistor T1 and the third thin film transistor T3 are both turned on, and the second thin film transistor T2 is turned off. The data voltage r corresponding to the first sub-pixel P1 is input to the first sub-pixel P1 through the data line (D1, D2, D3...). At this time, the pixel voltage of the first sub-pixel P1 is charged to the data voltage r because the first thin film transistor T1 is turned on. The pixel voltage of the second sub-pixel P2 continues to be maintained at the data voltage g because the second thin film transistor T2 is turned off. The pixel voltage of the third sub-pixel P3 continues to be maintained at the data voltage b because the second thin film transistor T2 is turned off and the third thin film transistor T3 is turned on. At this time, the data voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 from left to right along the row direction X are r, g and b respectively.

[0076] (4) The first gate line G1 and the second gate line G2 are both turned off, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are all turned off. From left to right along the row direction X, the first sub-pixel P1 maintains the data voltage r, the second sub-pixel P2 maintains the data voltage g, and the third sub-pixel P3 maintains the data voltage b. The first row of pixel unit arrays realizes normal light-emitting display.

[0077] Afterwards, the second row of pixel units P, the third row of pixel units P, etc. sequentially implement the light-emitting display of each row according to the above steps (1)-(4).

[0078] In a specific implementation, in the above-mentioned pixel array provided in the embodiment of the present disclosure, as shown in Figures 8 to 11, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are arranged in sequence from right to left along the row direction X, the luminous color of the first sub-pixel P1 is blue (B), the luminous color of the second sub-pixel P2 is green (G), and the luminous color of the third sub-pixel P3 is red (R); in this way, the leftmost sub-pixel in each pixel unit P is the third sub-pixel P3, and the luminous color is red (R); the middle position in each pixel unit P is the second sub-pixel P2, and the luminous color is green (G); and the rightmost sub-pixel in each pixel unit P is the first sub-pixel P1, and the luminous color is blue (B).

[0079] In a specific implementation, in the above-mentioned pixel array provided by the embodiment of the present disclosure, as shown in Figures 8 and 9, each row of pixel units P corresponds to a first gate line G1 and a second gate line G2, wherein the second gate line G2 is farther away from the next row of pixel units P, and the first gate line G1 is closer to the next row of pixel units P.

[0080] In a specific implementation, in the above-mentioned pixel array provided in the embodiment of the present disclosure, as shown in Figures 10 and 11, each row of pixel units P corresponds to a first gate line G1 and a second gate line G2, wherein the first gate line G1 is farther away from the next row of pixel units P, and the second gate line G2 is closer to the next row of pixel units P.

[0081] In a specific implementation, when the pixel array shown in FIG8 to FIG11 displays a frame of pixel images, the specific driving method includes the following steps (taking the display of the first row of pixel units P as an example):

[0082] (1) The first gate line G1 and the second gate line G2 corresponding to the first row of pixel units P are controlled to be turned on at the same time, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are turned on at the same time. The data voltage r corresponding to the third sub-pixel P3 is input to the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 through the data lines (D1, D2, D3...). The pixel voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are all charged to the data voltage r. At this time, the data voltages of the third sub-pixel P3, the second sub-pixel P2 and the first pixel P1 from left to right along the row direction X are all r.

[0083] (2) The first gate line G1 is controlled to be turned on, and the second gate line G2 is controlled to be turned off. At this time, the first thin film transistor T1 and the third thin film transistor T3 are turned on at the same time, and the second thin film transistor T2 is turned off. The data voltage b corresponding to the first sub-pixel P1 is input to the first sub-pixel P1 through the data line (D1, D2, D3...). At this time, the pixel voltage of the third sub-pixel P3 continues to be the data voltage r because the second thin film transistor T2 is turned off and the third thin film transistor T3 is turned on. The pixel voltage of the second sub-pixel P2 continues to be the data voltage r because the second thin film transistor T2 is turned off. The pixel voltage of the first sub-pixel P1 is charged to b because the first thin film transistor T1 is turned on. At this time, the data voltages of the third sub-pixel P3, the second sub-pixel P2 and the first pixel P1 from left to right along the row direction X are r, r and b respectively.

[0084] (3) The first gate line G1 is controlled to be closed, and the second gate line G2 is controlled to be turned on. At this time, the second thin film transistor T2 is turned on, and the first thin film transistor T1 and the third thin film transistor T3 are both turned off. The data voltage g corresponding to the second sub-pixel P2 is input to the second sub-pixel P2 through the data line (D1, D2, D3...). At this time, the pixel voltage of the second sub-pixel P2 is charged to the data voltage g because the second thin film transistor T2 is turned on. The pixel voltage of the first sub-pixel P1 continues to be the data voltage b because the first thin film transistor T1 is turned off. The pixel voltage of the third sub-pixel P3 continues to be the data voltage r because the second thin film transistor T2 is turned on and the third thin film transistor T3 is turned off. At this time, the data voltages of the third sub-pixel P3, the second sub-pixel P2 and the first pixel P1 from left to right along the row direction X are r, g and b respectively.

[0085] (4) The first gate line G1 and the second gate line G2 are both turned off, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are all turned off. From left to right along the row direction X, the third sub-pixel P3 maintains the data voltage r, the second sub-pixel P2 maintains the data voltage g, and the first sub-pixel P1 maintains the data voltage b. The first row of pixel unit arrays realizes normal light-emitting display.

[0086] Afterwards, the second row of pixel units P, the third row of pixel units P, etc. sequentially implement the light-emitting display of each row according to the above steps (1)-(4).

[0087] In a specific implementation, the pixel array shown in FIG8 to FIG11 may also adopt the following driving method when displaying a frame of pixel images (taking the display of the first row of pixel units P as an example):

[0088] (1) The first gate line G1 and the second gate line G2 corresponding to the first row of pixel units P are controlled to be turned on at the same time, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are turned on at the same time. The data voltage r corresponding to the third sub-pixel P3 is input to the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 through the data lines (D1, D2, D3...). The pixel voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are all charged to the data voltage r. At this time, the data voltages of the third sub-pixel P3, the second sub-pixel P2 and the first pixel P1 from left to right along the row direction X are all r.

[0089] (2) The first gate line G1 is controlled to be closed, and the second gate line G2 is controlled to be turned on. At this time, the first thin film transistor T1 and the third thin film transistor T3 are turned off at the same time, and the second thin film transistor T2 is turned on. The data voltage g corresponding to the second sub-pixel P2 is input to the second sub-pixel P2 through the data line (D1, D2, D3...). At this time, the pixel voltage of the second sub-pixel P2 is charged to g due to the opening of the second thin film transistor T2. The pixel voltage of the first sub-pixel P1 continues to be the data voltage r due to the closing of the first thin film transistor T1. The pixel voltage of the third sub-pixel P3 continues to be the data voltage r due to the closing of the third thin film transistor T3 and the opening of the second thin film transistor T2. At this time, the data voltages of the third sub-pixel P3, the second sub-pixel P2 and the first pixel P1 from left to right along the row direction X are r, g, and r respectively.

[0090] (3) The first gate line G1 is controlled to be turned on, and the second gate line G2 is controlled to be turned off. At this time, the first thin film transistor T1 and the third thin film transistor T3 are both turned on, and the second thin film transistor T2 is turned off. The data voltage b corresponding to the first sub-pixel P1 is input to the first sub-pixel P1 through the data lines (D1, D2, D3...). At this time, the pixel voltage of the first sub-pixel P1 is charged to the data voltage b because the first thin film transistor T1 is turned on. The pixel voltage of the second sub-pixel P2 continues to be the data voltage g because the second thin film transistor T2 is turned off. The pixel voltage of the third sub-pixel P3 continues to be the data voltage r because the second thin film transistor T2 is turned off and the third thin film transistor T3 is turned on. At this time, the data voltages of the third sub-pixel P3, the second sub-pixel P2 and the first sub-pixel P1 from left to right along the row direction X are r, g and b respectively.

[0091] (4) The first gate line G1 and the second gate line G2 are both turned off, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are all turned off. From left to right along the row direction X, the third sub-pixel P3 maintains the data voltage r, the second sub-pixel P2 maintains the data voltage g, and the first sub-pixel P1 maintains the data voltage b. The first row of pixel unit arrays realizes normal light-emitting display.

[0092] Afterwards, the second row of pixel units P, the third row of pixel units P, etc. sequentially implement the light-emitting display of each row according to the above steps (1)-(4).

[0093] In a specific implementation, in the above-mentioned pixel array provided in the embodiment of the present disclosure, as shown in Figures 12 to 15, the second sub-pixel P2, the first sub-pixel P1, and the third sub-pixel P3 are arranged in sequence along the row direction X, and the data lines (D1, D2, D3, ...) are arranged on the side of the second sub-pixel P2 away from the first sub-pixel P1. Specifically, since the third sub-pixel P3 is connected in series with the second sub-pixel P2, that is, the third thin-film transistor T3 and the second thin-film transistor T2 are connected in series, by arranging the data lines (D1, D2, D3, ...) on the side of the second sub-pixel P2 away from the first sub-pixel P1, the first electrode S11 of the first thin-film transistor T1 and the first electrode S12 of the second thin-film transistor T2 can be electrically connected to the data line on the side of the second sub-pixel P2, thereby simplifying the layout difficulty of the pixel array. Of course, in a specific implementation, the data lines (D1, D2, D3...) are not limited to being set on the side of the second sub-pixel P2 away from the first sub-pixel P1, but can also be set at other positions, as long as the connection relationship between the thin film transistors and between the thin film transistors and the data lines in Figures 12-15 can be achieved.

[0094] In a specific implementation, in the above-mentioned pixel array provided in the embodiment of the present disclosure, as shown in Figures 12 and 13, the second sub-pixel P2, the first sub-pixel P1 and the third sub-pixel P3 are arranged in sequence from left to right along the row direction X, the luminous color of the second sub-pixel P2 is red (R), the luminous color of the first sub-pixel P1 is green (G), and the luminous color of the third sub-pixel P3 is blue (B); in this way, the leftmost sub-pixel in each pixel unit P is the second sub-pixel P2, and the luminous color is red (R); the middle position of each pixel unit P is the first sub-pixel P1, and the luminous color is green (G); and the rightmost sub-pixel in each pixel unit P is the third sub-pixel P3, and the luminous color is blue (B).

[0095] In a specific implementation, in the above-mentioned pixel array provided by the embodiment of the present disclosure, as shown in FIG12 , each row of pixel units P corresponds to a first gate line G1 and a second gate line G2 , wherein the second gate line G2 is farther away from the next row of pixel units P, and the first gate line G1 is closer to the next row of pixel units P.

[0096] In a specific implementation, in the above-mentioned pixel array provided by the embodiment of the present disclosure, as shown in FIG13 , each row of pixel units P corresponds to a first gate line G1 and a second gate line G2 , wherein the first gate line G1 is farther away from the next row of pixel units P, and the second gate line G2 is closer to the next row of pixel units P.

[0097] In a specific implementation, when the pixel array shown in FIG12 and FIG13 displays a frame of pixel images, the specific driving method includes the following steps (taking the display of the first row of pixel units P as an example):

[0098] (1) The first gate line G1 and the second gate line G2 corresponding to the first row of pixel units P are controlled to be turned on at the same time, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are turned on at the same time. The data voltage b corresponding to the third sub-pixel P3 is input to the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 through the data lines (D1, D2, D3...). The pixel voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are all charged to the data voltage b. At this time, the data voltages of the second sub-pixel P2, the first pixel P1 and the third pixel P3 from left to right along the row direction X are all b.

[0099] (2) The first gate line G1 is controlled to be turned on, and the second gate line G2 is controlled to be turned off. At this time, the first thin film transistor T1 and the third thin film transistor T3 are turned on at the same time, and the second thin film transistor T2 is turned off. The data voltage g corresponding to the first sub-pixel P1 is input to the first sub-pixel P1 through the data line (D1, D2, D3...). At this time, the pixel voltage of the first sub-pixel P1 is charged to g due to the opening of the first thin film transistor T1, and the pixel voltage of the second sub-pixel P2 continues to be maintained at the data voltage b due to the closing of the second thin film transistor T2. The pixel voltage of the third sub-pixel P3 continues to be maintained at the data voltage b because the third thin film transistor T3 is turned on and the second thin film transistor T2 is turned off. At this time, the data voltages of the second sub-pixel P2, the first pixel P1 and the third pixel P3 from left to right along the row direction X are b, g, and b respectively.

[0100] (3) The first gate line G1 is controlled to be closed, and the second gate line G2 is controlled to be turned on. At this time, the first thin film transistor T1 and the third thin film transistor T3 are both turned off, and the second thin film transistor T2 is turned on. The data voltage r corresponding to the second sub-pixel P2 is input to the second sub-pixel P2 through the data line (D1, D2, D3...). At this time, the pixel voltage of the second sub-pixel P2 is charged to the data voltage r because the second thin film transistor T2 is turned on. The pixel voltage of the first sub-pixel P1 continues to be the data voltage g because the first thin film transistor T1 is turned off. The pixel voltage of the third sub-pixel P3 continues to be the data voltage b because the second thin film transistor T2 is turned on and the third thin film transistor T3 is turned off. At this time, the data voltages of the second sub-pixel P2, the first pixel P1 and the third pixel P3 from left to right along the row direction X are r, g and b respectively.

[0101] (4) The first gate line G1 and the second gate line G2 are both turned off, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are all turned off. From left to right along the row direction X, the second sub-pixel P2 maintains the data voltage r, the first sub-pixel P1 maintains the data voltage g, and the third sub-pixel P3 maintains the data voltage b. The first row of pixel unit arrays realizes normal light-emitting display.

[0102] Afterwards, the second row of pixel units P, the third row of pixel units P, etc. sequentially implement the light-emitting display of each row according to the above steps (1)-(4).

[0103] In a specific implementation, the pixel arrays shown in FIG12 and FIG13 may also adopt the following driving method when displaying a frame of pixel images (taking the display of the first row of pixel units P as an example):

[0104] (1) The first gate line G1 and the second gate line G2 corresponding to the first row of pixel units P are controlled to be turned on at the same time, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are turned on at the same time. The data voltage b corresponding to the third sub-pixel P3 is input to the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 through the data lines (D1, D2, D3...). The pixel voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are all charged to the data voltage b. At this time, the data voltages of the second sub-pixel P2, the first pixel P1 and the third pixel P3 from left to right along the row direction X are all b.

[0105] (2) The first gate line G1 is controlled to be closed, and the second gate line G2 is controlled to be turned on. At this time, the first thin film transistor T1 and the third thin film transistor T3 are turned off at the same time, and the second thin film transistor T2 is turned on. The data voltage r corresponding to the second sub-pixel P2 is input to the second sub-pixel P2 through the data line (D1, D2, D3...). At this time, the pixel voltage of the second sub-pixel P2 is charged to r because the second thin film transistor T2 is turned on. The pixel voltage of the first sub-pixel P1 continues to be the data voltage b because the first thin film transistor T1 is turned off. The pixel voltage of the third sub-pixel P3 continues to be the data voltage b because the third thin film transistor T3 is turned off and the second thin film transistor T2 is turned on. At this time, the data voltages of the second sub-pixel P2, the first pixel P1 and the third pixel P3 from left to right along the row direction X are r, b, and b respectively.

[0106] (3) The first gate line G1 is controlled to be turned on, and the second gate line G2 is controlled to be turned off. At this time, the first thin film transistor T1 and the third thin film transistor T3 are both turned on, and the second thin film transistor T2 is turned off. The data voltage g corresponding to the first sub-pixel P1 is input to the first sub-pixel P1 through the data lines (D1, D2, D3...). At this time, the pixel voltage of the first sub-pixel P1 is charged to the data voltage g due to the opening of the first thin film transistor T1. The pixel voltage of the second sub-pixel P2 continues to be maintained at the data voltage r due to the closing of the second thin film transistor T2. The pixel voltage of the third sub-pixel P3 continues to be maintained at the data voltage b due to the closing of the second thin film transistor T2 and the opening of the third thin film transistor T3. At this time, the data voltages of the second sub-pixel P2, the first pixel P1 and the third pixel P3 from left to right along the row direction X are r, g and b respectively.

[0107] (4) The first gate line G1 and the second gate line G2 are both turned off, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are all turned off. From left to right along the row direction X, the second sub-pixel P2 maintains the data voltage r, the first sub-pixel P1 maintains the data voltage g, and the third sub-pixel P3 maintains the data voltage b. The first row of pixel unit arrays realizes normal light-emitting display.

[0108] Afterwards, the second row of pixel units P, the third row of pixel units P, etc. sequentially implement the light-emitting display of each row according to the above steps (1)-(4).

[0109] In a specific implementation, in the above-mentioned pixel array provided in the embodiment of the present disclosure, as shown in Figures 14 and 15, the second sub-pixel P2, the first sub-pixel P1 and the third sub-pixel P3 are arranged in sequence from right to left along the row direction X, the luminous color of the second sub-pixel P2 is blue (B), the luminous color of the first sub-pixel is green (G), and the luminous color of the third sub-pixel P3 is red (R); in this way, the leftmost sub-pixel in each pixel unit P is the third sub-pixel P3, and the luminous color is red (R); the middle position in each pixel unit P is the first sub-pixel P1, and the luminous color is green (G); and the rightmost sub-pixel in each pixel unit P is the second sub-pixel P2, and the luminous color is blue (B).

[0110] In a specific implementation, in the above-mentioned pixel array provided by the embodiment of the present disclosure, as shown in FIG14 , each row of pixel units P corresponds to a first gate line G1 and a second gate line G2 , wherein the first gate line G1 is farther away from the next row of pixel units P, and the second gate line G2 is closer to the next row of pixel units P.

[0111] In a specific implementation, in the above-mentioned pixel array provided by the embodiment of the present disclosure, as shown in FIG15 , each row of pixel units P corresponds to a first gate line G1 and a second gate line G2 , wherein the second gate line G2 is farther away from the next row of pixel units P, and the first gate line G1 is closer to the next row of pixel units P.

[0112] In a specific implementation, when the pixel array shown in FIG14 and FIG15 displays a frame of pixel images, the specific driving method includes the following steps (taking the display of the first row of pixel units P as an example):

[0113] (1) The first gate line G1 and the second gate line G2 corresponding to the first row of pixel units P are controlled to be turned on at the same time, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are turned on at the same time. The data voltage r corresponding to the third sub-pixel P3 is input to the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 through the data lines (D1, D2, D3...). The pixel voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are all charged to the data voltage r. At this time, the data voltages of the third sub-pixel P3, the first pixel P1 and the second pixel P2 from left to right along the row direction X are all r.

[0114] (2) The first gate line G1 is controlled to be turned on, and the second gate line G2 is controlled to be turned off. At this time, the first thin film transistor T1 and the third thin film transistor T3 are turned on at the same time, and the second thin film transistor T2 is turned off. The data voltage g corresponding to the first sub-pixel P1 is input to the first sub-pixel P1 through the data lines (D1, D2, D3...). At this time, the pixel voltage of the first sub-pixel P1 is charged to g due to the opening of the first thin film transistor T1, and the pixel voltage of the second sub-pixel P2 continues to be the data voltage r due to the closing of the second thin film transistor T2. The pixel voltage of the third sub-pixel P3 continues to be the data voltage r because the third thin film transistor T3 is turned on and the second thin film transistor T2 is turned off. At this time, the data voltages of the third sub-pixel P3, the first sub-pixel P1, and the second sub-pixel P2 from left to right along the row direction X are r, g, and r respectively.

[0115] (3) The first gate line G1 is controlled to be closed, and the second gate line G2 is controlled to be turned on. At this time, the first thin film transistor T1 and the third thin film transistor T3 are both turned off, and the second thin film transistor T2 is turned on. The data voltage b corresponding to the second sub-pixel P2 is input to the second sub-pixel P2 through the data line (D1, D2, D3...). At this time, the pixel voltage of the second sub-pixel P2 is charged to the data voltage b because the second thin film transistor T2 is turned on. The pixel voltage of the first sub-pixel P1 continues to be the data voltage g because the first thin film transistor T1 is turned off. The pixel voltage of the third sub-pixel P3 continues to be the data voltage r because the second thin film transistor T2 is turned on and the third thin film transistor T3 is turned off. At this time, the data voltages of the third sub-pixel P3, the first sub-pixel P1 and the second sub-pixel P2 from left to right along the row direction X are r, g, and b respectively.

[0116] (4) The first gate line G1 and the second gate line G2 are both turned off, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are all turned off. From left to right along the row direction X, the third sub-pixel P3 maintains the data voltage r, the first sub-pixel P1 maintains the data voltage g, and the second sub-pixel P2 maintains the data voltage b. The first row of pixel unit arrays realizes normal light-emitting display.

[0117] Afterwards, the second row of pixel units P, the third row of pixel units P, etc. sequentially implement the light-emitting display of each row according to the above steps (1)-(4).

[0118] In a specific implementation, the pixel arrays shown in FIG14 and FIG15 may also adopt the following driving method when displaying a frame of pixel images (taking the display of the first row of pixel units P as an example):

[0119] (1) The first gate line G1 and the second gate line G2 corresponding to the first row of pixel units P are controlled to be turned on at the same time, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are turned on at the same time. The data voltage r corresponding to the third sub-pixel P3 is input to the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 through the data lines (D1, D2, D3...). The pixel voltages of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are all charged to the data voltage r. At this time, the data voltages of the third sub-pixel P3, the first pixel P1 and the second pixel P2 from left to right along the row direction X are all r.

[0120] (2) The first gate line G1 is controlled to be closed, and the second gate line G2 is controlled to be turned on. At this time, the first thin film transistor T1 and the third thin film transistor T3 are turned off at the same time, and the second thin film transistor T2 is turned on. The data voltage b corresponding to the second sub-pixel P2 is input to the second sub-pixel P2 through the data line (D1, D2, D3...). At this time, the pixel voltage of the second sub-pixel P2 is charged to b because the second thin film transistor T2 is turned on. The pixel voltage of the first sub-pixel P1 continues to be the data voltage r because the first thin film transistor T1 is turned off. The pixel voltage of the third sub-pixel P3 continues to be the data voltage r because the third thin film transistor T3 is turned off and the second thin film transistor T2 is turned on. At this time, the data voltages of the third sub-pixel P3, the first sub-pixel P1, and the second sub-pixel P2 from left to right along the row direction X are r, r, and b respectively.

[0121] (3) The first gate line G1 is controlled to be turned on, and the second gate line G2 is controlled to be turned off. At this time, the first thin film transistor T1 and the third thin film transistor T3 are both turned on, and the second thin film transistor T2 is turned off. The data voltage g corresponding to the first sub-pixel P1 is input to the first sub-pixel P1 through the data lines (D1, D2, D3...). At this time, the pixel voltage of the first sub-pixel P1 is charged to the data voltage g because the first thin film transistor T1 is turned on. The pixel voltage of the second sub-pixel P2 continues to be maintained at the data voltage b because the second thin film transistor T2 is turned off. The pixel voltage of the third sub-pixel P3 continues to be maintained at the data voltage r because the second thin film transistor T2 is turned off and the third thin film transistor T3 is turned on. At this time, the data voltages of the third sub-pixel P3, the first sub-pixel P1 and the second sub-pixel P2 from left to right along the row direction X are r, g, and b respectively.

[0122] (4) The first gate line G1 and the second gate line G2 are both turned off, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are all turned off. From left to right along the row direction X, the third sub-pixel P3 maintains the data voltage r, the first sub-pixel P1 maintains the data voltage g, and the second sub-pixel P2 maintains the data voltage b. The first row of pixel unit arrays realizes normal light-emitting display.

[0123] Afterwards, the second row of pixel units P, the third row of pixel units P, etc. sequentially implement the light-emitting display of each row according to the above steps (1)-(4).

[0124] In a specific implementation, in the pixel array provided in the embodiments of the present disclosure, as shown in Figures 4 to 15 , the two gate lines (the first gate line G1 and the second gate line G2) corresponding to each row of pixel units P are arranged on the same side of the corresponding row of pixel units P. This helps to simplify the layout of the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3.

[0125] In a specific implementation, in the pixel array provided in the embodiments of the present disclosure, as shown in Figures 4 to 15 , the thin film transistors (T1, T2, T3) corresponding to each row of pixel units P are disposed between the two gate lines (G1 and G2) of the corresponding row of pixel units P. This facilitates simplification, with the first thin film transistor T1 and the third thin film transistor T3 being electrically connected to the first gate line G1 as close as possible, and the second thin film transistor T2 being electrically connected to the second gate line G2 as close as possible, thereby simplifying the layout.

[0126] In specific implementation, in the above-mentioned pixel array provided in the embodiment of the present disclosure, as shown in Figures 5, 7, 9 and 11, the pixel array of the embodiment of the present disclosure is generally used as a pixel array on the array substrate of a liquid crystal display panel, and a black matrix layer (BM) is generally provided on the opposite substrate (i.e., the color film substrate) of the liquid crystal display panel. The BM is generally provided in the gap between adjacent sub-pixels. On the one hand, it is used to define the sub-pixel area, and on the other hand, it is used to block metal signal lines, such as gate lines, data lines, etc., to prevent the metal signal lines from reflecting and reduce the reflectivity of the display area.

[0127] In specific implementation, the above-mentioned pixel array provided in the embodiment of the present disclosure further includes other functional film layers well known to those skilled in the art, such as a common electrode layer, and a storage capacitor is formed between the common electrode layer and each pixel electrode.

[0128] Based on the same inventive concept, an embodiment of the present disclosure further provides a method for driving a pixel array, which is used to drive the pixel arrays shown in FIG. 4 to FIG. 15 provided in the embodiment of the present disclosure. As shown in FIG. 16 , the driving method includes:

[0129] S1601, when displaying a frame of pixel images, controlling the first gate line and the second gate line to be turned on simultaneously, and inputting a data voltage corresponding to the third sub-pixel to the first sub-pixel, the second sub-pixel, and the third sub-pixel through the data line;

[0130] S1602, controlling the first gate line to be turned on, controlling the second gate line to be turned off, and inputting a data voltage corresponding to the first sub-pixel to the first sub-pixel through the data line;

[0131] S1603 , controlling the first gate line to be closed, controlling the second gate line to be opened, and inputting a data voltage corresponding to the second sub-pixel to the second sub-pixel through the data line.

[0132] Based on the same inventive concept, an embodiment of the present disclosure further provides a method for driving a pixel array, which is used to drive the pixel arrays shown in FIG. 4 to FIG. 15 provided in the embodiment of the present disclosure. As shown in FIG. 17 , the driving method includes:

[0133] S1701, when displaying a frame of pixel images, controlling the first gate line and the second gate line to be turned on simultaneously, and inputting a data voltage corresponding to the third sub-pixel to the first sub-pixel, the second sub-pixel, and the third sub-pixel through the data line;

[0134] S1702, controlling the first gate line to be closed, controlling the second gate line to be opened, and inputting a data voltage corresponding to the second sub-pixel to the second sub-pixel through the data line;

[0135] S1703 , controlling the first gate line to be turned on, controlling the second gate line to be turned off, and inputting a data voltage corresponding to the first sub-pixel to the first sub-pixel through the data line.

[0136] The driving method of the above-mentioned two pixel arrays provided in the embodiments of the present disclosure can realize display driving of different sub-pixels by using one data line and two gate lines for each pixel unit. Compared with the three-gate pixel architecture in the related art, the present disclosure can reduce the number of data lines to 1 / 3 of the single-gate pixel structure while also reducing the number of gate lines for each row of pixel units. This can increase the display area and improve the aperture ratio on the one hand; on the other hand, the reduction in the number of gate lines can also reduce the parasitic capacitance between the gate lines and other signal lines, thereby increasing the charging time of each row of pixel units, ensuring the charging rate, and improving the display effect.

[0137] In specific implementation, the driving principles of the driving methods of the above two pixel arrays provided in the embodiments of the present disclosure can refer to the driving principles of the above one pixel array, and will not be described in detail here.

[0138] Based on the same inventive concept, embodiments of the present disclosure further provide a display device, including a display panel including the aforementioned pixel array provided in embodiments of the present disclosure. The principles underlying the problem solved by this display device are similar to those of the aforementioned pixel array, and thus the implementation of this display device can be referenced to the implementation of the aforementioned pixel array, and any repetitions will not be repeated here.

[0139] In a specific implementation, the display device provided in the embodiment of the present invention is a liquid crystal display device.

[0140] In specific implementation, the display device provided in the embodiment of the present invention may be a full-screen display device, or may be a flexible display device, etc., which is not limited here.

[0141] In a specific implementation, the display device provided in the embodiment of the present invention may be a full-screen mobile phone as shown in FIG18 . Of course, the display device provided in the embodiment of the present invention may also be any product or component with a display function, such as a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limiting the present invention.

[0142] The embodiments of the present disclosure provide a pixel array, a driving method thereof, and a display device. By using one data line and two gate lines for each pixel unit, display driving of different sub-pixels can be achieved. Compared with the three-gate pixel architecture in the related art, the present disclosure reduces the number of data lines to 1 / 3 of the single-gate pixel structure while also reducing the number of gate lines per row of pixel units by one. This can increase the display area and improve the aperture ratio. On the other hand, the reduction in the number of gate lines can also reduce the parasitic capacitance between the gate lines and other signal lines, thereby increasing the charging time of each row of pixel units, ensuring the charging rate, and improving the display effect.

[0143] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A pixel array, wherein: include: A plurality of gate lines extending along the row direction and arranged along the column direction; A plurality of data lines extending along the column direction and arranged along the row direction; A plurality of rows and columns of pixel units, each of the pixel units comprising a first sub-pixel, a second sub-pixel and a third sub-pixel arranged along the row direction, wherein each column of the pixel units is provided with a corresponding data line, the first sub-pixel and the second sub-pixel are directly electrically connected to the data line of the corresponding column, and the third sub-pixel is electrically connected to the data line of the corresponding column after being connected in series with the second sub-pixel; and two gate lines are provided corresponding to each row of the pixel units, the two gate lines comprising a first gate line and a second gate line, the first sub-pixel and the third sub-pixel are both connected to the first gate line of the corresponding row, and the second sub-pixel is connected to the second gate line of the corresponding row.

2. The pixel array according to claim 1, wherein: The first sub-pixel includes a first thin film transistor and a first pixel electrode, the second sub-pixel includes a second thin film transistor and a second pixel electrode, and the third sub-pixel includes a third thin film transistor and a third pixel electrode; wherein, The gate of the first thin film transistor and the gate of the third thin film transistor are both connected to the first gate line, and the gate of the second thin film transistor is connected to the second gate line; The first electrode of the first thin film transistor and the first electrode of the second thin film transistor are directly electrically connected to the data line of the corresponding column, the second electrode of the first thin film transistor is electrically connected to the first pixel electrode, the second electrode of the second thin film transistor is electrically connected to the second pixel electrode, the first electrode of the third thin film transistor is electrically connected to the second electrode of the second thin film transistor, and the second electrode of the third thin film transistor is electrically connected to the third pixel electrode.

3. The pixel array according to claim 2, wherein: The first sub-pixel, the second sub-pixel and the third sub-pixel are arranged in sequence along the row direction, and the data line is arranged between the first sub-pixel and the second sub-pixel.

4. The pixel array according to claim 3, wherein: The light-emitting color of the first sub-pixel is red, the light-emitting color of the second sub-pixel is green, and the light-emitting color of the third sub-pixel is blue; Alternatively, the light emitting color of the first sub-pixel is blue, the light emitting color of the second sub-pixel is green, and the light emitting color of the third sub-pixel is red.

5. The pixel array according to claim 2, wherein: The second sub-pixel, the first sub-pixel and the third sub-pixel are arranged in sequence along the row direction, and the data line is arranged on a side of the second sub-pixel away from the first sub-pixel.

6. The pixel array according to claim 5, wherein: The light-emitting color of the second sub-pixel is red, the light-emitting color of the first sub-pixel is green, and the light-emitting color of the third sub-pixel is blue; Alternatively, the light emitting color of the second sub-pixel is blue, the light emitting color of the first sub-pixel is green, and the light emitting color of the third sub-pixel is red.

7. The pixel array according to any one of claims 2 to 6, wherein: The two gate lines corresponding to each row of the pixel units are arranged on the same side of the pixel units in the corresponding row.

8. The pixel array according to claim 7, wherein: The thin film transistors corresponding to each row of the pixel units are arranged between two gate lines of the corresponding row of the pixel units.

9. A display device, wherein: It comprises a display panel, wherein the display panel comprises the pixel array according to any one of claims 1 to 8.

10. A method for driving a pixel array, for driving the pixel array according to any one of claims 1 to 8, wherein: The driving method comprises: When displaying a frame of pixel images, the first gate line and the second gate line are controlled to be turned on at the same time, and a data voltage corresponding to the third sub-pixel is input to the first sub-pixel, the second sub-pixel and the third sub-pixel through the data line; Controlling the first gate line to be turned on, controlling the second gate line to be turned off, and inputting a data voltage corresponding to the first sub-pixel to the first sub-pixel through the data line; The first gate line is controlled to be closed, and the second gate line is controlled to be opened, and a data voltage corresponding to the second sub-pixel is input to the second sub-pixel through the data line.

11. A method for driving a pixel array, for driving the pixel array according to any one of claims 1 to 8, wherein: The driving method comprises: When displaying a frame of pixel images, the first gate line and the second gate line are controlled to be turned on at the same time, and a data voltage corresponding to the third sub-pixel is input to the first sub-pixel, the second sub-pixel and the third sub-pixel through the data line; Controlling the first gate line to be closed, controlling the second gate line to be opened, and inputting a data voltage corresponding to the second sub-pixel to the second sub-pixel through the data line; The first gate line is controlled to be turned on, and the second gate line is controlled to be turned off, and a data voltage corresponding to the first sub-pixel is input to the first sub-pixel through the data line.

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