Semiconductor device

Abstract

This semiconductor device is provided with: a first semiconductor region (21) of a first conductivity type, said first semiconductor region (21) having an active region (110) and a non-active region (120); a second semiconductor region (22) of a second conductivity type provided in the first semiconductor region in the active region; a third semiconductor region (25) of the second conductivity type provided in the first semiconductor region in the non-active region; and a fourth semiconductor region (26) of the second conductivity type provided in the first semiconductor region, the fourth semiconductor region being sandwiched by the third semiconductor region. The active region has a first width that separates and adjoins the second semiconductor region. The non-active region has a second width of a fourth semiconductor region sandwiched by the third semiconductor region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a structure for suppressing variations in breakdown voltage caused by external factors and improving stability. Background Art

[0002] In order to increase the breakdown voltage of a semiconductor device, a structure for increasing the breakdown voltage is formed in a peripheral region around an element region where semiconductor elements are formed. For example, a junction termination extension (JTE) or a field limiting ring (FLR) structure is used for the structure of a terminal portion.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent No. 5122810 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] However, the depletion layer extends in the peripheral region and reaches the surface of the semiconductor substrate, so that the semiconductor device is liable to be affected by external ions or the like. For example, due to the influence of ions invading from the outside, the shape of the depletion layer is deformed, which may cause variations and instability in the breakdown voltage.

[0008] In view of the above problems, an object of the present invention is to provide a semiconductor device that can suppress variations in breakdown voltage caused by external factors and stabilize characteristics.

[0009] Means for Solving the Problems

[0010] According to one aspect of the present invention, a semiconductor device includes: a first semiconductor region of a first conductivity type, which has an active region and a non-active region; a second semiconductor region of a second conductivity type, which is provided in the first semiconductor region in the active region; a third semiconductor region of the second conductivity type, which is provided in the first semiconductor region in the non-active region; and a fourth semiconductor region of the second conductivity type, which is sandwiched by the third semiconductor region and provided in the first semiconductor region. The active region has a first width that separates and adjoins the second semiconductor regions. The non-active region has a second width of the fourth semiconductor region sandwiched by the third semiconductor region.

[0011] Advantages of the Invention

[0012] According to the present invention, it is possible to provide a semiconductor device in which variations in breakdown voltage caused by external factors are suppressed. Brief Description of the Drawings

[0013] Figure 1 It is a cross-sectional view of the semiconductor device of the embodiment.

[0014] Figure 2 It is a top view of the semiconductor device of the embodiment.

[0015] Figure 3 It is a cross-sectional view of a comparative example of the semiconductor device of the embodiment.

[0016] Figure 4 It is a top view of a comparative example of the semiconductor device of the embodiment.

[0017] Figure 5 It is a cross-sectional view of the semiconductor device of a modified example of the embodiment.

[0018] Figure 6 It is a top view of the semiconductor device of a modified example of the embodiment. Detailed Embodiment

[0019] Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the lengths of the respective parts, etc. are different from the actual ones. Therefore, the specific dimensions should be judged with reference to the following description. In addition, of course, there are also parts where the dimensional relationships and ratios are different between the drawings.

[0020] In addition, the embodiments shown below illustrate devices and methods for embodying the technical concept of the present invention. The technical concept of the present invention does not limit the shape, structure, configuration, etc. of the structural components to the following content.

[0021] (Embodiment)

[0022] Figure 1 It is along Figure 2 The cross-sectional view taken along line A-A. In addition, Figure 2 It is a schematic top view of the semiconductor device 1 of the embodiment. In the following description, an XYZ coordinate system, which is an example of a rectangular coordinate system, is used. That is, the plane parallel to the surface of the substrate constituting the semiconductor device 1 is set as the XY plane, and the direction perpendicular to the XY plane is set as the Z direction. In addition, the X axis and the Y axis are two perpendicular directions in the XY plane.

[0023] As Figure 1As shown, the semiconductor device 1 of the first embodiment has a first semiconductor region 21 of the first conductivity type, a second semiconductor region 22 of the second conductivity type, a third semiconductor region 25 of the second conductivity type, and a fourth semiconductor region 26 of the second conductivity type. In addition, the semiconductor device 1 may further have a fifth semiconductor region 23 of the first conductivity type, a sixth semiconductor region 24 of the first conductivity type, a trench 30, and an interlayer insulating film 60. In the following description, the first semiconductor region 21 is also referred to as the drift region 21, the second semiconductor region 22 is also referred to as the deep region 22, the third semiconductor region 25 is also referred to as the guard ring region 25, the fourth semiconductor region 26 is also referred to as the clearance region 26, the fifth semiconductor region 23 is also referred to as the source region 23, and the sixth semiconductor region 24 is also referred to as the drain region 24.

[0024] The first conductivity type and the second conductivity type are opposite conductivity types to each other. That is, if the first conductivity type is n-type, the second conductivity type is p-type. If the first conductivity type is p-type, the second conductivity type is n-type. Here, the case where the first conductivity type is n-type and the second conductivity type is p-type is illustratively described.

[0025] The semiconductor device 1 has a semiconductor substrate 10. As the material of the semiconductor substrate 10, for example, silicon (Si), silicon carbide (SiC), nitride semiconductor, oxide semiconductor, etc. can be applied. Specifically, for the nitride semiconductor, for example, gallium nitride (GaN), aluminum nitride (AlN), boron nitride (BN), indium nitride (InN), and their mixed crystal semiconductors, etc. can be applied. In addition, for the oxide semiconductor, for example, gallium oxide (Ga2O3), zinc oxide (ZnO), magnesium oxide (MgO), and their mixed crystal semiconductors, etc. can be applied. In particular, since SiC, GaN, and Ga2O3 can perform high-voltage withstand operation, the structure in which the clearance region 26 is provided for the guard ring region 25 of the present embodiment can be effectively applied.

[0026] The semiconductor substrate 10 has one main surface 10a and another main surface 10b. The semiconductor substrate 10 has a drift region 21, a deep region 22, a source region 23, a drain region 24, a guard ring region 25, and a clearance region 26.

[0027] The drift region 21 has an active region 110 and a non-active region 120. That is, the drift region 21 is continuously disposed commonly for the active region 110 and the non-active region 120.

[0028] The active region 110 is, for example, a region where semiconductor elements are disposed. Figure 1Among them, an example of a trench-type MOS (metal-oxide semiconductor) configured with trenches will be described. The active region 110 has a first width WDP of the separated and adjacent deep regions 22. In addition, the semiconductor element is not limited to the trench-type MOS. In the following description, the active region 110 is also referred to as the active cell region 110.

[0029] The non-active region 120 is, for example, a region having a breakdown voltage structure. The non-active region 120 has a second width WGAP of the gap region 26 sandwiched by the guard ring regions 25. In the following description, the non-active region 120 is also referred to as the junction termination region 120.

[0030] The deep regions 22 are provided in the drift region 21 in the active cell region 110. In addition, in the active cell region 110, the position where avalanche breakdown occurs near the deep regions 22 is also referred to as the first generation position PA1.

[0031] The trenches 30 are provided in the drift region 21 in the active cell region 110. Regarding the trenches 30, a first insulating film 40 and a conductor 50 are provided in the trenches 30. In addition, the first insulating film 40 may also be a gate insulating film. Furthermore, the conductor 50 may also be a gate electrode.

[0032] The source region 23 is provided in the deep regions 22 in the active cell region 110.

[0033] The drain region 24 is provided in the drift region 21 on the other main surface 10b side. In addition, the drain region 24 is continuously arranged in common for the active cell region 110 and the junction termination region 120.

[0034] The guard ring regions 25 are provided in the drift region 21 in the junction termination region 120. Specifically, in the case of an SiC substrate, the impurity concentration of the guard ring regions 25 is, for example, formed to be about 1×10 15 cm -3 ~1×10 19 cm -3 or so. In addition, the junction depth X j 1 of the guard ring regions 25 is, for example, about 0.5 μm to 3 μm. In the following description, in the junction termination region 120, the position where avalanche breakdown occurs near the guard ring regions 25 is also referred to as the second generation position PB1.

[0035] The gap region 26 is sandwiched by the guard ring regions 25 and provided in the drift region 21 in the junction termination region 120. Specifically, in the case of an SiC substrate, the impurity concentration of the gap region 26 is, for example, 1×10 19 cm -3 ~1×10 22cm -3 or so. That is, the impurity concentration in the gap region 26 is higher than that in the guard ring region 25. In addition, the impurity concentration in the gap region 26 is such that it is not depleted within the gap region 26. Furthermore, the junction depth X j 2 of the gap region 26 is about 0.1 μm to 2 μm, for example. In addition, the junction depth X j 2 of the gap region 26 is shallower than the junction depth X j 1 of the guard ring region 25. In the following description, in the junction termination region 120, the position where avalanche breakdown occurs near the guard ring region 25 adjacent to the gap region 26 is also referred to as the third generation position PC1.

[0036] When viewed from above, Figure 1 and Figure 2 the width of the second width WGAP shown is wider than the first width WDP. Specifically, the upper limit value of the second width WGAP is determined, for example, by expanding to a width at which the depletion layer between the second widths WGAP does not break down.

[0037] The value of the second width WGAP / the first width WDP is defined by the following formula (1). That is,

[0038] 1 < (second width WGAP / first width WDP) < (second width WGAP / first width WDP at which the depletion layer extending to the second width WGAP does not break down) (1)

[0039] In addition, the upper limit value of (second width WGAP / first width WDP) can be 2 or less, for example. Here, the width at which the depletion layer extending between the second widths WGAP does not break down is determined by the breakdown voltage and the impurity concentration in each region of the pn junction.

[0040] Next, the positions where avalanche breakdown occurs in the semiconductor device 1 of the embodiment and the positions where avalanche breakdown occurs in the comparative example shown Figure 3 are described. In the following description, the breakdown voltage is also referred to as the breakdown strength.

[0041] In the semiconductor device 1, as Figure 1 shown, the positions where avalanche breakdown occurs are at least any one of the first generation position PA1, the second generation position PB1, and the third generation position PC1.

[0042] The breakdown voltage of the semiconductor device 1 is designed to cause avalanche breakdown at the third generation position PC1. That is, the breakdown voltage is determined by the avalanche breakdown generated near the guard ring region adjacent to the gap region. Specifically, the withstand voltage generated by the avalanche breakdown at the third generation position PC1 is, for example, smaller than the withstand voltage generated by the avalanche breakdown at the first generation position PA1. That is, the withstand voltage of the avalanche breakdown generated near the guard ring region 25 adjacent to the gap region 26 is smaller than the withstand voltage of the avalanche breakdown generated near the deep region 22. In addition, the withstand voltage generated by the avalanche breakdown at the third generation position PC1 is, for example, smaller than the withstand voltage generated by the avalanche breakdown at the second generation position PB1. That is, the withstand voltage of the avalanche breakdown generated near the guard ring region 25 adjacent to the gap region 26 is smaller than the withstand voltage of the avalanche breakdown generated near the terminal portion of the guard ring region 25. Additionally, the withstand voltages generated by the avalanche breakdowns at the first generation position PA1 and the second generation position can be equal (PC1 withstand voltage < PB1 withstand voltage ≤ PA1 withstand voltage). Additionally, the withstand voltage relationship of the semiconductor device 1 can also be PC1 withstand voltage < PA1 withstand voltage ≤ PB1 withstand voltage. That is, since the breakdown voltage of the semiconductor device 1 is determined by the third generation position PC1, even if the generation of the avalanche breakdown at the second generation position PB1 as the terminal portion varies due to external factors, the withstand voltage characteristics are stabilized.

[0043] As a comparative example is Figure 3 the cross-sectional view shown. In the comparative example, the semiconductor device of the embodiment does not have the gap region 26. Figure 4 is a top view of the comparative example. As Figure 4 shown, in the comparative example, in the junction termination region 120, the guard ring regions are provided in the same manner. Figure 3 is a cross-sectional view along the Figure 4 B-B line in

[0044] As Figure 3 shown, in the structure of the comparative example, the positions where avalanche breakdown occurs are at least either the first generation position PA2 or the second generation position PB2.

[0045] In the case of improving the withstand voltage, the position where avalanche breakdown occurs in the structure of the comparative example is the second generation position PB2.

[0046] In the comparative example, when the generation of the avalanche breakdown at the second generation position PB1 as the terminal portion varies due to external factors, the breakdown voltage of the structure of the comparative example also easily varies.

[0047] As described above, in the semiconductor device of the embodiment, by providing a gap region in the junction termination region, variations in the withstand voltage due to external factors can be suppressed, and the characteristics can be stabilized.

[0048] (Modification example of the embodiment)

[0049] Figure 5 This is a cross-sectional view of the junction termination region 120A of the semiconductor device 1A which is a modification of the embodiment. In addition, Figure 6 This is a top view of the junction termination region 120A of the semiconductor device 1A which is a modification of the embodiment. Figure 5 This is Figure 6 a cross-sectional view along the C-C line of

[0050] The semiconductor device 1A has a plurality of gap regions 26 with respect to the junction termination region 120 of the semiconductor device 1 of the embodiment. Regarding other structures, they are the same as those of Figure 1 the embodiment shown.

[0051] The junction termination region 120 has a plurality of second widths WGAP of the gap regions 26 sandwiched by the guard ring regions 25.

[0052] As described above, in the modification of the semiconductor device of the embodiment, by providing a plurality of gap regions in the junction termination region, the variation in breakdown voltage due to external factors can be suppressed, and the characteristics can be stabilized.

[0053] (Other Embodiments)

[0054] Although the present invention has been described by the embodiment as above, the discussions and drawings forming a part of this disclosure should not be construed as limiting the present invention. Based on this disclosure, various alternative embodiments, examples, and application techniques are obvious to those skilled in the art.

[0055] Thus, of course, the present invention includes various embodiments and the like not described herein.

[0056] For example, it may be the case where the first conductivity type is p-type and the second conductivity type is n-type.

[0057] In addition, the semiconductor devices (1, 1A) of the embodiment may have a heterojunction structure in which p-type and n-type are formed of different materials in one semiconductor device (1, 1A).

[0058] For example, the semiconductor element disposed in the active region 110 is not limited to a MOSFET, and may also be a diode.

[0059] Industrial Applicability

[0060] The semiconductor device of the present invention can be used in the electronic device industry including the manufacturing industry of semiconductor devices in which the variation in breakdown voltage due to external factors is suppressed.

[0061] Reference Numeral Explanation

[0062] 1: Semiconductor device; 10: Semiconductor substrate; 21: First semiconductor region, drift region; 22: Second semiconductor region, deep region; 23: Fifth semiconductor region, source region; 24: Sixth semiconductor region, drain region; 25: Third semiconductor region, guard ring region; 26: Fourth semiconductor region, clearance region; 30: Trench; 40: First insulating film; 50: Conductor; 60: Interlayer insulating film; 110: Active region, active cell region; 120: Non-active region, junction termination region.

Claims

1. A semiconductor device, the semiconductor device having: A first semiconductor region of a first conductivity type, having an active region and a non-active region; A second semiconductor region of a second conductivity type, disposed in the first semiconductor region in the active region; A third semiconductor region of a second conductivity type, disposed in the first semiconductor region in the non-active region; and A fourth semiconductor region of a second conductivity type, sandwiched by the third semiconductor region and disposed in the first semiconductor region, The active region has a first width separating and adjacent to the second semiconductor regions, The non-active region has a second width of a fourth semiconductor region sandwiched by the third semiconductor region.

2. The semiconductor device according to claim 1, wherein, The impurity concentration of the fourth semiconductor region is higher than that of the third semiconductor region.

3. The semiconductor device according to claim 2, wherein, The impurity concentration of the third semiconductor region is 1×10 15 cm -3 ~1×10 19 cm -3 。 4. The semiconductor device according to claim 2, wherein, The impurity concentration of the fourth semiconductor region is 1×10 19 cm -3 ~1×10 22 cm -3 .

5. The semiconductor device according to claim 1, wherein, The junction depth of the fourth semiconductor region is shallower than that of the third semiconductor region.

6. The semiconductor device according to claim 5, wherein, The junction depth of the fourth semiconductor region is 0.1 μm to 2 μm.

7. The semiconductor device according to claim 5, wherein, The junction depth of the third semiconductor region is 0.5 μm to 3 μm.

8. The semiconductor device according to claim 1, wherein, The second width is wider than the first width.

9. The semiconductor device according to claim 1, wherein, The upper limit value of the second width is the width at which the depletion layer extending to the second width does not break down.

10. The semiconductor device according to claim 1, wherein, The value of the second width WGAP / the first width WDP is defined by the following formula (1). 1 < (second width WGAP / first width WDP) < (second width WGAP / first width WDP at which the depletion layer extending to the second width WGAP does not break down) (1).

11. The semiconductor device according to claim 10, wherein, The value of (second width WGAP / first width WDP at which the depletion layer extending to the second width WGAP does not break down) is 2 or less.

12. The semiconductor device according to claim 1, wherein, The non-active region has a plurality of the fourth semiconductor regions sandwiched by the third semiconductor region.

13. The semiconductor device according to claim 1, wherein, The semiconductor device has a semiconductor substrate, and the semiconductor substrate has the first semiconductor region, the second semiconductor region, the third semiconductor region, and the fourth semiconductor region. The material of the semiconductor substrate includes at least one material selected from the group consisting of silicon, silicon carbide, nitride semiconductors, and oxide semiconductors.

14. The semiconductor device according to claim 1, wherein, The breakdown voltage is determined by avalanche breakdown generated near the third semiconductor region in contact with the fourth semiconductor region.

15. The semiconductor device according to claim 1, wherein, The breakdown voltage of the avalanche breakdown generated in the third semiconductor region in contact with the fourth semiconductor region is smaller than the breakdown voltage of the avalanche breakdown generated near the second semiconductor region.

16. The semiconductor device according to claim 1, wherein, The breakdown voltage of the avalanche breakdown generated in the third semiconductor region in contact with the fourth semiconductor region is smaller than the breakdown voltage of the avalanche breakdown generated near the terminal portion of the third semiconductor region.

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