Solid-state imaging element, manufacturing method, and electronic apparatus

Abstract

The present invention relates to a solid-state imaging element capable of achieving higher performance, a manufacturing method, and an electronic device. The solid-state imaging element includes: a first transistor provided with a side wall surrounding a side surface; and a second transistor connected in series with the first transistor and provided with a side wall surrounding a side surface. In addition, an impurity concentration of a first high-concentration diffusion layer provided in a semiconductor substrate below a sidewall of a drain side of the first transistor is higher than an impurity concentration of a third layer provided between the first transistor and the second transistor and provided in the semiconductor substrate until below a sidewall of a source side of the first transistor The impurity concentration of the concentration diffusion layer is low. The present technology can be applied, for example, to a smaller solid-state imaging element.

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device, a manufacturing method, and an electronic device, and particularly, to a solid-state imaging device, a manufacturing method, and an electronic device capable of further improving performance. Background Art

[0002] Heretofore, various techniques have been developed for improving the performance of transistors included in semiconductor devices such as solid-state imaging devices.

[0003] For example, Patent Document 1 discloses a semiconductor device including MOS-type transistors, wherein the source of each MOS-type transistor contains an impurity of a different type from the drain of the transistor and has a higher impurity diffusion coefficient than the drain, thereby having higher reliability. Citation List Patent Documents

[0004] Patent Document 1: Japanese Patent Laid-Open No. 5-343672 Summary of the Invention Technical Problem to be Solved by the Invention

[0005] However, the manufacturing method disclosed in Patent Document 1 is difficult to be applied to the miniaturization of solid-state imaging devices promoted in recent years. In addition, with such miniaturization of solid-state imaging devices, the sidewall width tends to become narrow. Therefore, there is a concern that the performance of the transistors may be degraded due to aging deterioration caused by hot carriers, deterioration of source follower characteristics, or other reasons.

[0006] The present invention developed in view of the above circumstances further improves performance. Solution to the Technical Problem

[0007] A solid-state imaging device according to an aspect of the present invention includes: a first transistor provided with sidewalls surrounding sides of the first transistor; a second transistor connected in series with the first transistor and provided with sidewalls surrounding sides of the second transistor; a first high-concentration diffusion layer provided in a semiconductor substrate and reaching below the sidewalls on the drain side of the first transistor; and a third high-concentration diffusion layer provided in the semiconductor substrate between the first transistor and the second transistor and reaching below the sidewalls on the source side of the first transistor. The impurity concentration of the first high-concentration diffusion layer is lower than the impurity concentration of the third high-concentration diffusion layer.

[0008] A manufacturing method according to one aspect of the present invention is a method for manufacturing a solid-state imaging device, the solid-state imaging device including a first transistor provided with sidewalls that surround side surfaces of the first transistor; and a second transistor that is connected in series with the first transistor and is provided with sidewalls, the sidewalls of the second transistor surrounding side surfaces of the second transistor. The manufacturing method includes: forming a first high-concentration diffusion layer provided on a semiconductor substrate and below the sidewalls up to a drain side of the first transistor; and forming a third high-concentration diffusion layer that is provided on the semiconductor substrate between the first transistor and the second transistor and below the sidewalls up to a source side of the first transistor. An impurity concentration of the first high-concentration diffusion layer is lower than an impurity concentration of the third high-concentration diffusion layer.

[0009] An electronic device according to one aspect of the present invention includes a solid-state imaging device, the solid-state imaging device including a first transistor provided with sidewalls that surround side surfaces of the first transistor; a second transistor that is connected in series with the first transistor and is provided with sidewalls, the sidewalls of the second transistor surrounding side surfaces of the second transistor; a first high-concentration diffusion layer provided on a semiconductor substrate and below the sidewalls up to a drain side of the first transistor; and a third high-concentration diffusion layer that is provided on the semiconductor substrate between the first transistor and the second transistor and below the sidewalls up to a source side of the first transistor. An impurity concentration of the first high-concentration diffusion layer is lower than an impurity concentration of the third high-concentration diffusion layer.

[0010] According to one aspect of the present invention, the solid-state imaging device has a first transistor provided with sidewalls that surround side surfaces of the first transistor; a second transistor that is connected in series with the first transistor and is provided with sidewalls, the sidewalls of the second transistor surrounding side surfaces of the second transistor. An impurity concentration of a first high-concentration diffusion layer is lower than an impurity concentration of a third high-concentration diffusion layer. The first high-concentration diffusion layer is provided on a semiconductor substrate and below the sidewalls up to a drain side of the first transistor, and the third high-concentration diffusion layer is provided on the semiconductor substrate between the first transistor and the second transistor and below the sidewalls up to a source side of the first transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Figure 1 is a cross-sectional view showing a configuration example of an imaging device according to a first embodiment to which the present technology is applied. Figure 2 Figure 2 is for explaining Figure 1 a manufacturing method of the imaging device in​​​​ Figure 3 Figure 3 is a diagram for explaining Figure 1 the manufacturing method of the imaging element in Figure 4 Figure 4 is a cross-sectional view showing an example of the structure of an imaging element according to a second embodiment to which this technology is applied. Figure 5 Figure 5 is a diagram for explaining Figure 4 the manufacturing method of the imaging element in Figure 6 Figure 6 is a cross-sectional view showing an example of the structure of an imaging element according to a third embodiment to which this technology is applied. Figure 7 Figure 7 is a diagram for explaining Figure 6 the manufacturing method of the imaging element in Figure 8 Figure 8 is a cross-sectional view showing an example of the structure of an imaging element according to a fourth embodiment to which this technology is applied. Figure 9 Figure 9 is a diagram for explaining Figure 8 the manufacturing method of the imaging element in Figure 10 Figure 10 is a diagram for explaining Figure 8 the manufacturing method of the imaging element in Figure 11 Figure 11 is a diagram showing Figure 1 an example of the planar layout of the imaging element in Figure 12 Figure 12 is a diagram showing Figure 1 another example of the planar layout of the imaging element in Figure 13 Figure 13 is a diagram showing Figure 6 an example of the planar layout of the imaging element in Figure 14 Figure 14 is a diagram showing an explanation of the fin structure of a transistor. Figure 15 Figure 15 is a diagram showing an example of a structure including two fins. Figure 16 Figure 16 is a diagram for explaining the cutting of a gate electrode. ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​Figure 17 Figure 17 It is a diagram showing another example of the gate insulating film. Figure 18 Figure 18 It is a diagram showing an example of explaining a wide contact electrode. Figure 19 Figure 19 It is a diagram showing an example of a structure including a wide contact electrode provided on two fins. Figure 20 Figure 20 It is a diagram showing an example of a pixel circuit diagram. Figure 21 Figure 21 It is a block diagram showing an example of the structure of an imaging device. Figure 22 Figure 22 It is a diagram showing an example of the usage of an image sensor. Figure 23 Figure 23 It is a block diagram showing an example of the schematic structure of a vehicle control system. Figure 24 Figure 24 It is a diagram assisting in explaining an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. Figure 25 Figure 25 It is a diagram showing an example of the schematic structure of an endoscope system. Figure 26 Figure 26 It is a diagram showing Figure 25 an example of the functional structure of the camera and the camera control unit (CCU) shown. Figure 27 Figure 27 It is a diagram showing an example of the schematic structure of a microsurgery system. DETAILED DESCRIPTION

[0012] Hereinafter, specific embodiments applying the present technology will be described in detail with reference to the drawings.

[0013] <First Structural Example of Imaging Element> Figure 1 It is a cross-sectional view showing an example of the structure of an imaging element according to a first embodiment applying the present technology.

[0014] As Figure 1 shown, the imaging element 11 includes a semiconductor substrate 21 and a wiring layer 22 laminated on the semiconductor substrate 21. In addition, among the plurality of transistors provided for each pixel included in the imaging element 11, Figure 1 ​​​​​​​​​​​​​​​​​​​​​An example of the cross-sectional structure of the amplification transistor 23 and the selection transistor 24 connected in series is particularly shown. For example, according to the imaging element 11, the amplification transistor 23 amplifies the charge photoelectrically converted by the photodiode, converts the charge into a pixel signal, and then outputs the pixel signal to the vertical signal line via the selection transistor 24.

[0015] The gate electrode 31 of the amplification transistor 23 and the gate electrode 33 of the selection transistor 24 are provided on the surface of the semiconductor substrate 21, and a predetermined gap is left between the gate electrode 31 and the gate electrode 33. Note that the gate insulating film 25 is formed on the surface of the semiconductor substrate 21. The gate insulating film 25 is configured to insulate the gate electrode 31 and the gate electrode 33 from the semiconductor substrate 21. For example, the gate insulating film 25 can be formed by oxidizing the surface of the semiconductor substrate 21, or by forming a SiO film or a high-dielectric insulating film on the surface of the semiconductor substrate 21, etc.

[0016] In addition, sidewalls 32 are provided to surround the side surfaces of the gate electrode 31, and sidewalls 34 are provided to surround the side surfaces of the gate electrode 33. In addition, an oxide film (SiO) 35 constituting a buffer layer is provided to cover the gate electrode 31 and the sidewalls 32, and also to cover the gate electrode 33 and the sidewalls 34. A nitride film (SiN) 36 is further stacked on the oxide film 35, which serves as a barrier layer for etching the interlayer film 37 of the wiring layer 22 when forming the contact electrode 38 connected to the second high-concentration diffusion layer 54-1, the contact electrode 39 connected to the gate electrode 31, the contact electrode 40 connected to the gate electrode 33, and the contact electrode 41 connected to the second high-concentration diffusion layer 54-2.

[0017] The wiring layer 22 includes the contact electrodes 38 to 41 and the wirings 42 to 45 in the interlayer film 37 stacked on the oxide film 35 and the nitride film 36. The wiring 42 is connected to the drain of the amplification transistor 23 via the contact electrode 38 to supply the drain power supply VDD to the amplification transistor 23. The wiring 43 is connected to the gate electrode 31 via the contact electrode 39 to supply a potential corresponding to the level of the charge transmitted from the photodiode and accumulated in the floating diffusion portion to the amplification transistor 23. The wiring 44 is connected to the gate electrode 33 via the contact electrode 40 to supply a selection signal for controlling the on and off states of the selection transistor 24. The wiring 45 is connected to the source of the selection transistor 24 via the contact electrode 41 to output the pixel signal to the vertical signal line.

[0018] For example, a low-concentration diffusion layer 52, a first high-concentration diffusion layer 53, a second high-concentration diffusion layer 54, and a third high-concentration diffusion layer 55 are provided on a semiconductor substrate 21, and they are all formed by implanting N-type impurity ions into a P-type well layer 51. The low-concentration diffusion layer 52 is formed in the surface region of the semiconductor substrate 21. The first high-concentration diffusion layer 53 is formed to reach the deep region of the semiconductor substrate 21. Each of the second high-concentration diffusion layer 54 and the third high-concentration diffusion layer 55 is formed to reach a deeper region of the semiconductor substrate 21 than the first high-concentration diffusion layer 53.

[0019] On the drain side of the amplifying transistor 23, a low-concentration diffusion layer 52-1, a first high-concentration diffusion layer 53-1, and a second high-concentration diffusion layer 54-1 are sequentially provided starting from near the gate electrode 31. On the source side of the selection transistor 24, a low-concentration diffusion layer 52-2, a first high-concentration diffusion layer 53-2, and a second high-concentration diffusion layer 54-2 are sequentially provided starting from near the gate electrode 33. The third high-concentration diffusion layer 55 is provided between the amplifying transistor 23 and the selection transistor 24. A low-concentration diffusion layer 52a-3 and a first high-concentration diffusion layer 53a-3 are sequentially provided from the gate electrode 31 toward the third high-concentration diffusion layer 55, and at the same time, a low-concentration diffusion layer 52b-3 and a first high-concentration diffusion layer 53b-3 are sequentially provided from the gate electrode 33 to the third high-concentration diffusion layer 55.

[0020] The low-concentration diffusion layers 52-1 to 52-3 are LDD (lightly doped drain) layers provided at the ends of the gate electrode 31 and the gate electrode 33, and are used to suppress an increase in the electric field strength near the ends of the gate electrode 31 and the gate electrode 33 associated with the miniaturization of the amplifying transistor 23 and the selection transistor 24.

[0021] The first high-concentration diffusion layer 53-1 is provided to reduce the electric field strength between the low-concentration diffusion layer 52-1 and the second high-concentration diffusion layer 54-1 so that its impurity concentration is lower than that of the second high-concentration diffusion layer 54-1. In addition, as shown in the figure, the first high-concentration diffusion layer 53-1 is also formed under the sidewall 32 on the drain side of the amplifying transistor 23. In addition, for example, it is preferable to set the width "a" of the first high-concentration diffusion layer 53-1, that is, the distance between the low-concentration diffusion layer 52-1 and the second high-concentration diffusion layer 54-1, to at least 10 nm.

[0022] The first high-concentration diffusion layer 53-2 is provided to reduce the electric field strength between the low-concentration diffusion layer 52-2 and the second high-concentration diffusion layer 54-2 so that its impurity concentration is lower than that of the second high-concentration diffusion layer 54-2.

[0023] Each of the first high-concentration diffusion layers 53a-3 and 53b-3 is set to have an impurity concentration lower than that of the third high-concentration diffusion layer 55. Alternatively, a configuration in which the first high-concentration diffusion layers 53a-3 and 53b-3 are not provided may be employed, that is, a configuration in which the third high-concentration diffusion layer 55 is formed to extend to the regions where the first high-concentration diffusion layers 53a-3 and 53b-3 are to be formed. In this case, the resistance value on the source side of the amplifying transistor 23 is reduced. Therefore, the gain characteristics of the amplifying transistor 23 can be improved.

[0024] The second high-concentration diffusion layer 54-1 is set to have a high impurity concentration necessary for forming a contact formation region provided for connection to the contact electrode 38. Similarly, the second high-concentration diffusion layer 54-2 is set to have a high impurity concentration necessary for forming a contact formation region provided for connection to the contact electrode 41.

[0025] The third high-concentration diffusion layer 55 is set to have a high impurity concentration necessary for appropriately reducing the resistance of each of the gate electrode 31 of the amplifying transistor 23 and the gate electrode 33 of the selection transistor 24. In addition, as shown in the figure, the third high-concentration diffusion layer 55 is also formed under the sidewall 32 on the source side of the amplifying transistor 23.

[0026] For example, in the imaging element 11, an opening 61 is provided in the nitride film 36 to open an opening between the gate electrode 31 of the amplifying transistor 23 and the gate electrode 33 of the selection transistor 24. The nitride film 36 is formed such that the distance between the end face 62 and the end face 63 of the opening 61 is wider than the distance between the gate electrode 31 of the amplifying transistor 23 and the gate electrode 33 of the selection transistor 24.

[0027] In addition, in the process for manufacturing the imaging element 11, in a step different from the process for implementing the ion implantation for forming the second high-concentration diffusion layer 54-1, the ion implantation process for forming the third high-concentration diffusion layer 55 is performed using the nitride film 36 including the above-mentioned opening 61 as a mask. In this way, while determining the impurity concentration, distribution, etc. of the second high-concentration diffusion layer 54-1 provided on the drain side of the amplifying transistor 23 according to the desired design, it is possible to determine, for example, the impurity concentration, distribution, etc. of the third high-concentration diffusion layer 55 formed between the amplifying transistor 23 and the selection transistor 24 according to the desired design.

[0028] Specifically, the second highest concentration diffusion layer 54-1 is designed to have an impurity concentration necessary for forming a contact formation region provided for connection to the contact electrode 38, and the first highest concentration diffusion layer 53-1 reaching below the side wall 32 on the drain side of the amplifying transistor 23 has a width of at least 10 nm. In addition, the third highest concentration diffusion layer 55 is designed to have a high impurity concentration necessary for appropriately reducing the resistance of each of the gate electrode 31 of the amplifying transistor 23 and the gate electrode 33 of the selection transistor 24, and reaches below the side wall 32 on the source side of the amplifying transistor 23.

[0029] In this way, the imaging element 11 can be configured such that the first highest concentration diffusion layer 53-1 is provided below the side wall 32 on the drain side of the amplifying transistor 23, and the third highest concentration diffusion layer 55 is provided below the side wall 32 on the source side of the amplifying transistor 23. In addition, the first highest concentration diffusion layer 53-1 is designed to have an impurity concentration lower than that of the third highest concentration diffusion layer 55. Therefore, the imaging element 11 can provide advantageous effects of appropriately reducing the drain-side electric field and contact resistance of the amplifying transistor 23 and reducing the diffusion layer resistance between the amplifying transistor 23 and the selection transistor 24. Therefore, the imaging element 11 can improve the aging attenuation of the amplifying transistor 23 caused by hot carriers without reducing the mutual conductance gm of the amplifying transistor 23 and the on-resistance Ron of the amplifying transistor 23.

[0030] In addition, even when the width of the side wall 32 becomes narrow with the miniaturization of the source follower, the imaging element 11 can reduce the increase in the electric field intensity at the drain end of the amplifying transistor 23. In this case, the source follower characteristics can be improved.

[0031] Therefore, the imaging element 11 can further achieve high performance by improving the aging attenuation of the amplifying transistor 23 caused by hot carriers, improving the source follower characteristics, and the like.

[0032] will be described with reference to Figure 2 and Figure 3 the steps performed to form the amplifying transistor 23 and the selection transistor 24 in the manufacturing method of the imaging element 11.

[0033] In the first step, as shown in the first stage of Figure 2 , for example, gate electrodes 31 and 33 are formed by laminating polysilicon as an electrode material on the surface of the semiconductor substrate 21, with a predetermined interval left therebetween.

[0034] In the second step, as shown in Figure 2As shown in the second stage of , ion implantation is performed on the surface region of the semiconductor substrate 21 (for example, dose: 1E14 to 1E15). In this way, a low-concentration diffusion layer 52-1 is formed on the drain side of the amplification transistor 23, a low-concentration diffusion layer 52-2 is formed on the source side of the selection transistor 24, and a low-concentration diffusion layer 52-3 is formed between the amplification transistor 23 and the selection transistor 24.

[0035] In the third step, as Figure 2 shown in the third stage of , sidewalls 32 are formed so as to surround the sides of the gate electrode 31, and sidewalls 34 are formed so as to surround the sides of the gate electrode 33. An oxide film 35 is further formed to cover the corresponding sidewalls 32 and 34. Then, ion implantation is performed on the deep region of the semiconductor substrate 21 (for example, dose: 1E14 to 1E15). In this way, a first high-concentration diffusion layer 53-1 is formed on the drain side of the amplification transistor 23, a first high-concentration diffusion layer 53-2 is formed on the source side of the selection transistor 24, and a first high-concentration diffusion layer 53-3 is formed between the amplification transistor 23 and the selection transistor 24. At this time, the ion implantation needs to be performed such that the first high-concentration diffusion layer 53-1 reaches below the sidewall 32 on the drain side of the amplification transistor 23.

[0036] In the fourth step, as Figure 3 shown in the first stage of , a nitride film 36 is laminated on the oxide film 35. Then, ion implantation (for example, dose: 2E15 to 8E15) is performed on the drain side of the gate electrode 31 and the source side of the gate electrode 33 to reach the deep region of the semiconductor substrate 21. In this way, a second high-concentration diffusion layer 54-1 is formed on the drain side of the amplification transistor 23, and a second high-concentration diffusion layer 54-2 is formed on the source side of the selection transistor 24. At this time, the ion implantation for forming the second high-concentration diffusion layer 54-1 needs to be performed such that the width "a" of the first high-concentration diffusion layer 53-1 is at least 10 nm.

[0037] In the fifth step, as Figure 3 shown in the second stage of , a resist film 71 patterned to open corresponding to the opening 61 is formed on the nitride film 36. Then, the nitride film 36 formed between the amplification transistor 23 and the selection transistor 24 is removed by etching the nitride film 36 using the resist film 71 as a mask to form an opening 61 in the nitride film 36.

[0038] In the sixth step, as Figure 3As shown in the third stage of , by using the nitride film 36 as a mask, ion implantation (e.g., dose: 2E15 to 8E15) is performed until reaching the deep region of the semiconductor substrate 21 between the gate electrode 31 and the gate electrode 33 to form the third high-concentration diffusion layer 55. At this time, the ion implantation needs to be performed such that the third high-concentration diffusion layer 55 reaches below the sidewall 32 on the source side of the amplifying transistor 23.

[0039] Then, a process for removing the resist film 71 is performed, an interlayer film 37 is laminated, and a process for forming the contact electrodes 38 to 41 and the wirings 42 to 45 within the interlayer film 37 is also performed to form the wiring layer 22. In this way, the Figure 1 shown amplifying transistor 23 and selection transistor 24 are completed.

[0040] As described above, forming the second high-concentration diffusion layers 54-1 and 24-2 and the third high-concentration diffusion layer 55 in different steps enables ion implantation to be performed under different conditions. In this way, it is possible to design the second high-concentration diffusion layers 54-1 and 24-2 and the third high-concentration diffusion layer 55 using different impurities. For example, each of the second high-concentration diffusion layers 54-1 and 24-2 is allowed to maintain the impurity concentration necessary for forming the contact formation region, while the third high-concentration diffusion layer 55 is allowed to have an impurity concentration for reducing the electric field strength in the region formed between the amplifying transistor 23 and the selection transistor 24. In this way, the imaging element 11 can improve the source follower characteristics of the amplifying transistor 23 and the selection transistor 24.

[0041] <Second Structural Example of Imaging Element> Figure 4 is a cross-sectional view showing a structural example of an imaging element according to a second embodiment to which the present technology is applied. Note that Figure 4 the imaging element 11A included in and the corresponding constituent elements of the imaging element 11 in Figure 1 are given the same reference numerals, and detailed descriptions thereof will not be repeated.

[0042] As Figure 4 shown, similar to the imaging element 11 in Figure 1 the imaging element 11A includes an amplifying transistor 23A and a selection transistor 24A.

[0043] However, the structure of the imaging element 11A is different from that of the imaging element 11 in Figure 1 in that the amplifying transistor 23A does not have the second high-concentration diffusion layer 54-1 provided on the drain side of the amplifying transistor 23 in Figure 1 and the amplifying transistor 23A does not have the one provided in Figure 1The second highest concentration diffusion layer 54-2 on the source side of the selection transistor 24 in []. Thus, in the case of the imaging element 11A, the first highest concentration diffusion layer 53-1 serves as a contact formation region for connection to the contact electrode 38, and the first highest concentration diffusion layer 53-2 serves as a contact formation region for connection to the contact electrode 41.

[0044] In other words, the imaging element 11A has a structure in which the impurity concentration of the contact formation region for connection to the contact electrode 38 on the drain side of the amplification transistor 23A is lower than Figure 1 the impurity concentration of this contact formation region of the imaging element 11 in [].

[0045] Similar to Figure 1 the imaging element 11 in [], the imaging element 11A constructed as above can further improve performance by improving the aging attenuation of the amplification transistor 23A caused by hot carriers, enhancing the source follower characteristics, and the like.

[0046] Reference will be made to Figure 5 to describe the steps for forming the amplification transistor 23A and the selection transistor 24A in the manufacturing method of the imaging element 11A.

[0047] First, perform processing similar to the first to third steps described above with reference to Figure 2 and then perform the 11th step.

[0048] In the 11th step, as shown in the first stage of Figure 5 [], a nitride film 36 is laminated on the oxide film 35. In this case, although the second highest concentration diffusion layers 54-1 and 54-2 are formed in the fourth step described above with reference to Figure 3 [], the second highest concentration diffusion layers 54-1 and 54-2 are not formed in the 11th step.

[0049] Next, in the 12th and 13th steps, similar to the fifth and sixth steps described above with reference to Figure 3 [], perform the process of forming the opening 61 in the nitride film 36 and the process of forming the third highest concentration diffusion layer 55 using the nitride film 36 as a mask. Then, perform the process of removing the resist film 71, laminate the interlayer film 37, and also perform the process of forming the contact electrodes 38 to 41 and the wirings 42 to 45 in the interlayer film 37 to form the wiring layer 22. In this way, the Figure 4 shown amplification transistor 23A and selection transistor 24A are completed.

[0050] <Third Configuration Example of Imaging Element> Figure 6 is a cross-sectional view showing a configuration example of an imaging element according to a third embodiment to which the present technology is applied. Note thatFigure 6 The imaging element 11B included therein and having the same constituent elements as the corresponding constituent elements of the imaging element 11 in Figure 1 are given the same reference numerals, and a detailed description thereof will not be repeated.

[0051] As Figure 6 shown, similar to the imaging element 11 in Figure 1 , the imaging element 11B includes an amplifying transistor 23B and a selection transistor 24B.

[0052] However, the structure of the imaging element 11B is different from that of the imaging element 11 in Figure 1 in that a nitride film 36B is not formed on the drain side of the amplifying transistor 23B and the source side of the selection transistor 24B. Specifically, in the case of the structure of the imaging element 11B, an opening 61 is formed in the nitride film 36B located between the amplifying transistor 23B and the selection transistor 24B. Further, the nitride film 36B is formed up to the side surface of the side wall 32 on the drain side of the amplifying transistor 23B, and the nitride film 36B is formed up to the side surface of the side wall 34 on the source side of the selection transistor 24B.

[0053] Similar to the imaging element 11 in Figure 1 , the imaging element 11B configured as above can further improve performance by improving the aging attenuation of the amplifying transistor 23B caused by hot carriers, enhancing the source follower characteristics, and the like.

[0054] Steps for forming the amplifying transistor 23B and the selection transistor 24B in the manufacturing method of the imaging element 11B will be described with reference to Figure 7 .

[0055] First, processing similar to the first to third steps described above with reference to Figure 2 is performed, and then the 21st step is performed.

[0056] In the 21st step, as shown in the first stage of Figure 7 , a nitride film 36B is stacked on the oxide film 35, and then the nitride film 36B formed on the surface of the semiconductor substrate 21 is etched back on the drain side of the amplifying transistor 23B and the source side of the selection transistor 24B. In this way, the nitride film 36B on the drain side of the amplifying transistor 23B and the nitride film 36B on the source side of the selection transistor 24B are removed. Then, ion implantation (for example, dose: 2E15 to 8E15) is performed on the semiconductor substrate 21 on the drain side of the gate electrode 31 and the source side of the gate electrode 33 until a deep region is reached to form second high-concentration diffusion layers 54-1 and 54-2.

[0057] Next, in the 22nd and 23rd steps, similar to the fifth and sixth steps described above with reference to Figure 3 a process of forming an opening 61 in the nitride film 36 and a process of forming a third high-concentration diffusion layer 55 by using the nitride film 36 as a mask are performed. Then, a process of removing the resist film 71 is performed, an interlayer film 37 is laminated, and a process of forming contact electrodes 38 to 41 and wirings 42 to 45 in the interlayer film 37 is also performed. In this way, the Figure 6 amplifying transistor 23B and the selection transistor 24B shown are completed.

[0058] <Fourth Structural Example of Image Sensor> Figure 8 is a cross-sectional view showing a structural example of an image sensor according to a fourth embodiment to which the present technology is applied. Note that Figure 8 the components included in the image sensor 11C and the corresponding components of the image sensor 11 in Figure 1 are given the same reference numerals and will not be described in detail again.

[0059] As Figure 8 shown, similar to the image sensor 11 in Figure 1 the image sensor 11C includes an amplifying transistor 23C and a selection transistor 24C.

[0060] However, the structure of the image sensor 11C is different from that of the image sensor 11 in Figure 1 that no opening 61 is formed in the nitride film 36C ( Figure 1 ), and a dummy contact electrode 81 is provided between the amplifying transistor 23C and the selection transistor 24C. Specifically, the image sensor 11C has a structure including a through hole 93 (refer to Figure 9 ) in the interlayer film 37 as a hole for forming the third high-concentration diffusion layer 55. According to this structure, the third high-concentration diffusion layer 55 is formed by ion implantation using the through hole 93. After forming the third high-concentration diffusion layer 55, for example, in the step of forming the contact electrodes 38 to 41, a metal material such as tungsten is buried in the through hole 93 to produce the dummy contact electrode 81.

[0061] In addition, the dummy contact electrode 81 is configured such that one end is connected to the semiconductor substrate 21 and the other end is not connected (different from the contact electrodes 38 to 41, not connected to the wirings 42 to 45). In this case, the dummy contact electrode 81 is in an electrically floating state. Therefore, the parasitic capacitance does not increase due to the presence of the electrically floating dummy contact electrode 81.

[0062] In addition, in the case of the imaging element 11C, by adjusting the interval A between the contact electrode 38 and the nitride film 36C, the width "a" of the first high-concentration diffusion layer 53-1 can be adjusted, that is, the distance between the low-concentration diffusion layer 52-1 and the second high-concentration diffusion layer 54-1. As described above, for example, it is preferable to set the width "a" of the first high-concentration diffusion layer 53-1 to at least 10 nm.

[0063] In addition, in the case of the imaging element 11C, the interval B between the dummy contact electrode 81 and the nitride film 36C on the side of the amplifying transistor 23C can be made equal to the interval C between the dummy contact electrode 81 and the nitride film 36C on the side of the selection transistor 24C (B = C). For example, when the interval B and the interval C are equal, each of the interval B and the interval C is controlled by the radius of the dummy contact electrode 81.

[0064] Alternatively, the interval B between the dummy contact electrode 81 and the nitride film 36C on the side of the amplifying transistor 23C can be smaller than the interval C between the dummy contact electrode 81 and the nitride film 36C on the side of the selection transistor 24C (B < C). For example, when the interval B is smaller than the interval C, each of the interval B and the interval C is controlled by the radius and the arrangement position of the dummy contact electrode 81.

[0065] In addition, when the interval B is greater than or equal to the interval C (B ≥ C) (this is not preferable), the resistance on the source side of the amplifying transistor 23C increases, and the electric field on the drain side of the selection transistor 24C increases.

[0066] Similar to Figure 1 the imaging element 11, the imaging element 11C configured as described above can further improve the performance by improving the aging attenuation of the amplifying transistor 23C caused by hot carriers, enhancing the source follower characteristics, and the like.

[0067] Reference will be made to Figure 9 and Figure 10 to describe the steps for forming the amplifying transistor 23C and the selection transistor 24C in the manufacturing method of the imaging element 11C.

[0068] First, processing similar to the first to third steps described above with reference to Figure 2 is performed, and then the 31st step is performed.

[0069] In the 31st step, as shown in the first stage of Figure 9 , the nitride film 36C is laminated on the oxide film 35.

[0070] In the 32nd step, as shown in the second stage of Figure 9 , the interlayer film 37 is laminated on the nitride film 36C with a thickness corresponding to the respective lengths of the contact electrodes 38 and 41 and the dummy contact electrode 81.

[0071] In step 33, as shown in the third stage of Figure 9 , through holes 91 to 93 are formed to penetrate the interlayer film 37. The through hole 91 is formed to have an opening in the first high-concentration diffusion layer 53-1, the through hole 92 is formed to have an opening in the first high-concentration diffusion layer 53-2, and the through hole 93 is formed to have an opening in the first high-concentration diffusion layer 53-3.

[0072] In the step of FIG. 34, as shown in the first stage of Figure 10 , ion implantation (for example, dose: 2E15 to 8E15) is performed using the through holes 91 to 93 until a region deep in the semiconductor substrate 21 is reached to form the second high-concentration diffusion layers 54-1 and 54-2 and the third high-concentration diffusion layer 55.

[0073] In the step of FIG. 35, as shown in the second stage of Figure 10 , a metal material such as tungsten is buried in the through holes 91 to 93 to form the contact electrodes 38 and 41 and the dummy contact electrode 81. In addition, wirings 42 connected to the contact electrode 38 and wirings 45 connected to the contact electrode 41 are formed.

[0074] Then, a process for forming the contact electrodes 39 and 40 and the wirings 43 and 44 and further laminating the interlayer film 37 is performed to form the wiring layer 22. In this way, the magnified transistor 23C and the selection transistor 24C shown in Figure 8 are completed.

[0075] Note that instead of the structure including the dummy contact electrode 81, the imaging element 11C may have a structure generated by burying a material same as the material of the interlayer film 37 in the through hole 92 after forming the third high-concentration diffusion layer 55.

[0076] <Planar layout of the imaging element> The planar layout of the imaging element 11 will be described with reference to Figures 11 to 13 .

[0077] Figure 11 A of Figure 11 shows an example of the planar layout of the imaging element 11, while Figure 1 B of

[0078] As shown in Figure 11As shown in A of FIG. , the imaging element 11 may adopt such a planar layout that includes an amplifying transistor 23 and a selection transistor 24 that are linearly arranged respectively in a plan view. Specifically, as shown by the dotted line in the figure, the amplifying transistor 23 and the selection transistor 24 are arranged such that the line connecting the source and drain of the amplifying transistor 23 and the line connecting the source and drain of the selection transistor 24 form a straight line.

[0079] In addition, for example, Figure 11 The interval A shown in is the distance from the side of the oxide film 35 covering the sidewall 32 of the amplifying transistor 23 facing the selection transistor 24 to the side 39a of the contact electrode 39 connected to the gate electrode 31 of the amplifying transistor 23 facing the selection transistor 24. In addition, for example, Figure 11 The interval B shown in is the distance from the side 35a of the oxide film 35 covering the sidewall 32 of the amplifying transistor 23 facing the selection transistor 24 to the end face 62 of the opening 61 of the nitride film 36 covering the amplifying transistor 23.

[0080] For example, the imaging element 11 needs to have the nitride film 36 in the region where the contact electrode 39 is connected to the gate electrode 31, so as to reduce the amount of excavation of the gate electrode 31 during the processing of the contact electrode 39, that is, to provide a countermeasure against the plasma-induced damage (PID) of the gate electrode 31. Therefore, in the case of the imaging element 11, the interval A between the side 39a of the contact electrode 39 and the side 35a of the oxide film 35 used as a reference must be greater than or equal to the interval B between the end face 62 of the opening 61 and the side 35a of the oxide film 35 used as a reference (A≥B).

[0081] In addition, as Figure 11 As shown in B of FIG. , the imaging element 11 includes a first high-concentration diffusion layer 53-1 under the sidewall 32 on the drain side of the amplifying transistor 23 and a third high-concentration diffusion layer 55 under the sidewall 32 on the source side of the amplifying transistor 23. In addition, as described above, the first high-concentration diffusion layer 53-1 is formed with a lower impurity concentration than the third high-concentration diffusion layer 55. Specifically, the imaging element 11 is configured such that the impurity concentration under the sidewall 32 on the drain side of the amplifying transistor 23 is lower than the impurity concentration under the sidewall 32 on the source side of the amplifying transistor 23.

[0082] Figure 12 Another example of the planar layout of the imaging element 11 is shown.

[0083] As Figure 12As shown, the imaging element 11 may adopt such a planar layout that includes a magnifying transistor 23 and a selection transistor 24 which cross each other at substantially right angles and form an L shape in a plan view. Specifically, as shown by the dashed line in the figure, the magnifying transistor 23 and the selection transistor 24 are arranged such that the line extending from the gate electrode 31 to the source of the magnifying transistor 23 and the line extending from the gate electrode 31 to the drain of the magnifying transistor 23 and connecting the source and drain of the selection transistor 24 cross each other at substantially right angles.

[0084] Same as the structure described with reference to Figure 11 In the case where the imaging element 11 has the above planar layout, the interval A between the side surface 39a of the contact electrode 39 and the side surface 35a of the reference oxide film 35 must be greater than or equal to the interval B between the end surface 62 of the opening 61 and the side surface 35a of the reference oxide film 35 (A≥B).

[0085] Figure 13 A in shows an example of the planar layout of the imaging element 11B, while Figure 13 B in shows Figure 6 a cross-sectional view of an example of the structure of the imaging element 11B similar to the structure shown.

[0086] As Figure 13 shown in A of, the imaging element 11B may adopt such a planar layout that includes a magnifying transistor 23B and a selection transistor 24B arranged in a straight line.

[0087] In addition, in the case of the imaging element 11B, same as the structure described with reference to Figure 11 the interval A between the side surface 39a of the contact electrode 39 and the side surface 35a of the reference oxide film 35 must be greater than or equal to the interval B between the end surface 62 of the opening 61 and the side surface 35a of the reference oxide film 35 (A≥B).

[0088] <Fin structure of the transistor> Reference will be made to Figure 14 describe the magnifying transistor 23a and the selection transistor 24a both of which adopt a fin structure.

[0089] Figure 14 A in shows an example of the planar layout of the magnifying transistor 23a and the selection transistor 24a both of which adopt a fin structure, while Figure 14 B in shows the cross-sectional structure of the magnifying transistor 23a observed along the direction of arrow A-A shown in A of Figure 14 . Note that the selection transistor 24a has a cross-sectional structure similar to that of the magnifying transistor 23a.

[0090] For example, the imaging element 11 may have a configuration including an amplification transistor 23a and a selection transistor 24a, each transistor having a three-dimensional fin structure provided with fins 101 arranged from the drain side of the amplification transistor 23a to the source side of the selection transistor 24a, and the shape of each fin protrudes with respect to the semiconductor substrate 21. As shown in Figure 14 B of Figure 14 , each fin 101 is configured such that a part of the semiconductor substrate 21 is formed in a convex shape protruding toward the wiring layer 22 and is insulated from the gate electrode 31a by a gate insulating film 26, and the gate insulating film 26 covers the portion of the fin 101 protruding from the gate insulating film 25 formed flat on the surface of the semiconductor substrate 21.

[0091] Each of the amplification transistor 23a and the selection transistor 24a having such a fin structure exhibits characteristics such as shorter switching times and higher current densities. Although Figure 14 shows an example configuration including one fin 101, a configuration including a plurality of fins 101 may also be employed to further improve the characteristics of the amplification transistor 23a and the selection transistor 24a.

[0092] Reference will be made to Figure 15 describe an example configuration including two fins 101-1 and 101-2.

[0093] Figure 15 A of shows an example configuration including an amplification transistor 23b having a gate electrode 31b and a selection transistor 24b having a gate electrode 33b. The gate electrode 31b and the gate electrode 33b are provided to straddle the fin 101-1 and the fin 101-2. Each of the amplification transistor 23b and the selection transistor 24b having such a configuration exhibits characteristics such as shorter switching times and higher current densities than those of the amplification transistor 23a and the selection transistor 24a in Figure 14 Figure 14 .

[0094] At the same time, as shown by the dashed lines in the figure, the parasitic capacitance generated between the gate electrode 31b and the contact electrodes 38-1 and 38-2 in the amplification transistor 23b increases as the side area of the gate electrode 31b increases. Similarly, as shown by the dashed lines in the figure, the parasitic capacitance generated between the gate electrode 33b and the contact electrodes 41-1 and 41-2 in the selection transistor 24b increases as the side area of the gate electrode 33b increases. Therefore, it is considered preferable to adopt a configuration capable of reducing the parasitic capacitance.

[0095] Figure 15FIG. B shows such a configuration that includes an amplification transistor 23c having gate electrodes 31c-1 and 31c-2 respectively disposed on fins 101-1 and 101-2 and a selection transistor 24c having gate electrodes 33c-1 and 33c-2 respectively disposed on fins 101-l and 101-2. Therefore, a slit 102 is provided between gate electrode 31c-1 and gate electrode 31c-2, while a slit 103 is provided between gate electrode 33c-1 and gate electrode 33c-2. In other words, in the case of the amplification transistor 23c and the selection transistor 24c, gate electrode 31c-1 and gate electrode 33c-1 are provided for fin 101-1, while gate electrode 31c-2 and gate electrode 33c-2 are provided for fin 101-2.

[0096] The amplification transistor 23c and the selection transistor 24c configured as above have a smaller side area than the amplification transistor 23b and the selection transistor 24b, and thus can reduce the parasitic capacitance.

[0097] For example, as Figure 16 shown, the gate electrode 31c-1 and the gate electrode 31c-2 of the amplification transistor 23c can be formed by forming a gate electrode 31c that spans fins 101-1 and 101-2 and then cutting the gate electrode 31c along the cutting position between fins 101-1 and 101-2. Similarly, although not shown in the figure, the gate electrode 33c-1 and the gate electrode 33c-2 of the selection transistor 24c can also be formed by forming a gate electrode 33c that spans fins 101-1 and 101-2 and then cutting the gate electrode 33c along the cutting position between fins 101-1 and 101-2. Note that the gate electrode 31c and the gate electrode 33c can be cut when forming the respective gate electrodes 31c, 33c or after laminating the interlayer film 37.

[0098] As described above, by forming a slit 102 between the gate electrode 31c-1 and the gate electrode 31c-2 (similarly, by forming a slit 103 between the gate electrode 33c-1 and the gate electrode 33c-2), a tensile stress can be applied to the channel, as Figure 16 shown by the thick arrows in. Therefore, this configuration of the amplification transistor 23c and the selection transistor 24c is expected to improve the electron mobility.

[0099] Note that Figure 16 shows a configuration example of forming the gate insulating film 26 by oxidizing the surfaces of fins 101-1 and 101-2 at the portions protruding from the gate insulating film 25 that is planarized on the surface of the semiconductor substrate 21. Meanwhile, Figure 17An exemplary configuration is shown in which a gate insulating film 26 is formed by forming an SiO film, a high-dielectric insulating film, etc. on the surfaces of fins 101-1 and 101-2 at portions protruding from a gate insulating film 25 formed flat on the surface of a semiconductor substrate 21.

[0100] Figure 15 C shows an exemplary configuration of an amplification transistor 23d including a gate electrode 31d having a notch 104 and a selection transistor 24d including a gate electrode 33d having a notch 105. The gate electrode 31d and the gate electrode 33d are provided to straddle the fins 101-1 and 101-2.

[0101] For example, the notch 104 is formed in both side surfaces of the gate electrode 31d of the amplification transistor 23d located between the fins 101-1 and 101-2, and the contact electrode 39-1 and the contact electrode 39-2 are connected to the gate electrode 31d corresponding to the fins 101-1 and 101-2, respectively. Similarly, the notch 105 is formed in both side surfaces of the gate electrode 33d of the selection transistor 24d located between the fins 101-1 and 101-2, and the contact electrode 40-1 and the contact electrode 40-2 are connected to the gate electrode 33d corresponding to the fins 101-1 and 101-2, respectively.

[0102] The amplification transistor 23d and the selection transistor 24d configured as above have a smaller side area than the amplification transistor 23b and the selection transistor 24b, and thus can reduce the parasitic capacitance.

[0103] Figure 15 D shows an exemplary configuration of an amplification transistor 23e including a gate electrode 31e having a notch 104 and a selection transistor 24e including a gate electrode 33e having a notch 105. The gate electrode 31e and the gate electrode 33e are provided to straddle the fins 101-1 and 101-2.

[0104] For example, the notch 104 is formed in both side surfaces of the gate electrode 31e of the amplification transistor 23e located between the fins 101-1 and 101-2, and the contact electrode 39 is connected to the center of the gate electrode 31e. Similarly, the notch 105 is formed in both side surfaces of the gate electrode 33e of the selection transistor 24e located between the fins 101-1 and 101-2, and the contact electrode 40 is connected to the center of the gate electrode 33e.

[0105] The amplification transistor 23e and the selection transistor 24e configured as above have a smaller side area than the amplification transistor 23b and the selection transistor 24b, and thus can reduce the parasitic capacitance.

[0106] Although Figure 15An example configuration including two fins 101-1 and 101-2 is shown, but a configuration including more than two fins 101 may also be employed.

[0107] <Structure of wide contact electrodes> will be described with reference to Figure 18 amplifying transistor 23f and selection transistor 24f each employing a wide contact electrode. Note that each of amplifying transistor 23f and selection transistor 24f has a fin structure similar to that of amplifying transistor 23a and selection transistor 24a described above with reference to Figure 14 Figure A of shows an example of a planar layout of amplifying transistor 23f employing wide contact electrode 38f and selection transistor 24f employing wide contact electrode 41f.

[0108] Figure 18 Figure B of shows a cross-sectional structure of wide contact electrode 38f as viewed in the direction of arrow A-A in Figure A of. Note that wide contact electrode 41f has a cross-sectional structure similar to that of wide contact electrode 38f. Figure 18 Figure B of shows that, for example, amplifying transistor 23f is formed such that contact electrode 38f has a wide shape sufficient to produce a structure in which wide contact electrode 38f and fin 101 are in contact with each other not only on the upper surface of fin 101 but also on the side surface of fin 101. Accordingly, as the contact area between wide contact electrode 38f and fin 101 increases, amplifying transistor 23f can reduce resistance. Similarly, as the contact area between wide contact electrode 41f and fin 101 increases, selection transistor 24f can reduce resistance. Figure 18 will be described with reference to

[0109] For example, as shown in Figure 18 Figure B of, amplifying transistor 23f is formed such that contact electrode 38f has a wide shape sufficient to produce a structure in which wide contact electrode 38f and fin 101 are in contact with each other not only on the upper surface of fin 101 but also on the side surface of fin 101. Accordingly, as the contact area between wide contact electrode 38f and fin 101 increases, amplifying transistor 23f can reduce resistance. Similarly, as the contact area between wide contact electrode 41f and fin 101 increases, selection transistor 24f can reduce resistance.

[0110] will be described with reference to Figure 19 an example configuration including wide contact electrodes respectively provided on two fins 101-1 and 101-2.

[0111] Figure 19 Figure A of shows an example configuration including amplifying transistor 23g having wide contact electrode 38g and gate electrode 31g provided to span fin 101-1 and fin 101-2 and selection transistor 24g having wide contact electrode 41g and gate electrode 33g provided to span fin 101-1 and fin 101-2. Amplifying transistor 23g and selection transistor 24g configured as above can reduce resistance as the contact area increases.

[0112] Figure 19B shows a structural example including an amplification transistor 23h having a wide contact electrode 38h set to straddle fins 101-1 and 101-2 and having gate electrodes 31h-1 and 31h-2 on fins 101-1 and 101-2 respectively, and a selection transistor 24h having a wide contact transistor 41h set to straddle fins 101-1 and 101-2 and having gate electrodes 33h-1 and 33h-2 on fins 101-1 and 101-2 respectively. The amplification transistor 23h and the selection transistor 24h configured as above can reduce the parasitic capacitance by reducing the side area, and can reduce the resistance as the contact area increases.

[0113] Figure 19 C shows a structural example including an amplification transistor 23i having a wide contact electrode 38i set to straddle fins 101-1 and 101-2 and having a gate electrode 31i including a notch 104, and a selection transistor 24i having a wide contact electrode 41i set to straddle fins 101-1 and 101-2 and having a gate electrode 33i including a notch 105. The amplification transistor 23i and the selection transistor 24i configured as above can reduce the parasitic capacitance by reducing the side area, and can reduce the resistance as the contact area increases.

[0114] Figure 19 D shows a structural example including an amplification transistor 23j having a wide contact electrode 38j set to straddle fins 101-1 and 101-2 and having a gate electrode 31j including a notch 104, and a selection transistor 24j having a wide contact electrode 41j set to straddle fins 101-1 and 101-2 and having a gate electrode 33j including a notch 105. The amplification transistor 23j and the selection transistor 24j configured as above can reduce the parasitic capacitance by reducing the side area, and can reduce the resistance as the contact area increases.

[0115] Although Figure 19 shows a structural example including two fins 101-1 and 101-2, a structure including more than two fins 101 can also be adopted.

[0116] Although the amplification transistor 23 and the selection transistor 24 connected in series are illustrated in this embodiment, the present technology is also applicable to transistors having other functions as long as these transistors are two transistors connected in series.

[0117] <Pixel circuit diagram> Figure 20 is a diagram showing an example of a circuit diagram of a pixel 151 including an amplification transistor 23 and a selection transistor 24.

[0118] As Figure 20As shown, in addition to the amplification transistor 23 and the selection transistor 24, the pixel 151 includes a photodiode 152, a transfer transistor 153, a floating diffusion portion 154, and a reset transistor 155.

[0119] The photodiode 152 performs photoelectric conversion on the light applied to the pixel 151 and generates charges. The transfer transistor 153 is turned on or off according to the transfer signal TRG. When the transfer transistor 153 is turned on, the charges generated by the photodiode 152 are transferred to the floating diffusion portion 154. The floating diffusion portion 154 is connected to the gate electrode of the amplification transistor 23. The charges accumulated in the floating diffusion portion 154 are amplified by the amplification transistor 23 and converted into pixel signals. The selection transistor 24 is turned on or off according to the selection signal SEL. When the selection transistor 24 is turned on, the pixel signals converted by the amplification transistor 23 are output to the vertical signal line VSL. The reset transistor 155 is turned on or off according to the reset signal RST. When the reset transistor 155 is turned on, the charges accumulated in the floating diffusion portion 154 are discharged to the power supply Vdd. Therefore, the floating diffusion portion 154 is reset.

[0120] <Example of the Structure of an Electronic Device> For example, the above-described imaging element 11 is applicable to various types of electronic devices, including imaging systems such as digital cameras and digital video cameras, cellular phones having an imaging function, and other types of devices having an imaging function.

[0121] Figure 21 is a block diagram showing an example of the structure of an imaging device mounted on an electronic device.

[0122] As Figure 21 shown, the imaging device 201 includes an optical system 202, an imaging element 203, a signal processing circuit 204, a monitor 205, and a memory 206, and is configured to capture still images and moving images.

[0123] The optical system 202 including one or more lenses introduces image light (incident light) from a subject into the imaging element 203 and forms an image of the light on the light receiving surface (sensor unit) of the imaging element 203.

[0124] The above-described imaging element 11 is applied to the imaging element 203. According to the image formed on the light receiving surface by the optical system 202, electrons are accumulated on the imaging element 203 for a fixed period of time. Then, signals corresponding to the electrons accumulated on the imaging element 203 are supplied to the signal processing circuit 204.

[0125] The signal processing circuit 204 performs various types of signal processing on the pixel signals output from the imaging element 203. The image (image data) formed as a result of the signal processing performed by the signal processing circuit 204 is supplied to the monitor 205 and displayed on the monitor 205, or is supplied to the memory 206 and stored (recorded) in the memory 206.

[0126] For example, by adopting the above-described imaging element 11, the imaging device 201 configured as described above can capture higher-quality images.

[0127] <Examples of Use of Image Sensors> Figure 22 It is a diagram showing examples of use of the above-described image sensor (imaging element).

[0128] As described below, for example, the above-described image sensor can be used to sense various situations of light such as visible light, infrared light, ultraviolet light, and X-rays.

[0129] - Devices for capturing images for appreciation, such as digital cameras and mobile devices with camera functions; - Devices for transportation, such as in-vehicle sensors that capture the front, rear, surrounding, interior, or other areas related to the vehicle for purposes such as safe driving (e.g., automatic parking) or identifying the driver's state, surveillance cameras that monitor moving vehicles or roads, and distance measurement sensors that measure the distance between vehicles; - Devices for household appliances, such as televisions, refrigerators, and air conditioners that capture images of the user's gestures and operate the appliances based on these gestures; - Devices for medical and health care, such as endoscopes and devices for angiography using received infrared light; - Devices for security, such as surveillance cameras for crime prevention and cameras for personal identification; - Devices for beauty, such as skin measurement devices for capturing skin images and microscopes for capturing scalp images; - Devices for sports, such as action cameras for sports and wearable cameras; - Devices for agriculture, such as cameras for monitoring fields and crop conditions.

[0130] <Examples of Applications for Mobile Bodies> The technology according to the present invention (this technology) is applicable to various products. For example, the technology according to the present invention can be implemented as a device installed on any type of mobile body selected from, for example, automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0131] Figure 23 is a block diagram showing an example of a schematic configuration of a vehicle control system that is an example of a mobile body control system to which the technology according to the embodiments of the present invention can be applied.

[0132] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 23 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and a vehicle-mounted network interface (I / F) 12053 are shown.

[0133] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various types of programs. For example, the drive system control unit 12010 serves as a control device for devices such as a driving force generation device for generating the driving force of the vehicle, such as an internal combustion engine or a drive motor, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating the braking force of the vehicle.

[0134] The body system control unit 12020 controls the operation of various types of devices provided on the vehicle body according to various types of programs. For example, the body system control unit 12020 serves as a control device for a keyless entry system, a smart key system, an electric window device, or various lights such as headlights, reverse lights, brake lights, turn signal lights, or fog lights. In this case, radio waves or signals from a mobile device substituting for a key can be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, electric window device, or lights of the vehicle.

[0135] The outside vehicle information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the outside vehicle information detection unit 12030 is connected to a camera unit 12031. The outside vehicle information detection unit 12030 causes the camera unit 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the outside vehicle information detection unit 12030 can perform detection processing of objects such as people, vehicles, obstacles, signs, or characters on the road surface, or can perform detection processing of the distance to the above objects.

[0136] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging unit 12031 can output the electrical signal as an image or can output the electrical signal as ranging information. In addition, the light received by the imaging unit 12031 can be visible light or can be invisible light such as infrared light.

[0137] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the degree of driver fatigue or the degree of driver concentration, or can determine whether the driver is dozing off.

[0138] The microcomputer 12051 can calculate control target values for the driving force generating device, the steering mechanism, or the braking device based on information outside or inside the vehicle obtained by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at implementing advanced driver assistance system (ADAS) functions, which include collision avoidance or impact mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle speed holding driving, vehicle collision warning, or vehicle lane departure warning, etc.

[0139] In addition, by controlling the driving force generating device, the steering mechanism, the braking device, etc. based on information outside or inside the vehicle obtained by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, the microcomputer 12051 can perform cooperative control aimed at implementing autonomous driving, etc., which enables the vehicle to autonomously drive without relying on the driver's operation.

[0140] In addition, based on the information outside the vehicle obtained by the out-vehicle information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlamp to change from high beam to low beam, for example, according to the positions of the vehicle ahead or the oncoming vehicle detected by the out-vehicle information detection unit 12030.

[0141] The sound and image output unit 12052 sends an output signal of at least one of sound and image to an output device that can notify information visually or auditorily to the passengers in the vehicle or outside the vehicle. Figure 23In the example, as output devices, the audio speaker 12061, the display unit 12062, and the instrument panel 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0142] Figure 24 It is a diagram showing an example of the installation position of the imaging unit 12031.

[0143] In Figure 24 it, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0144] The imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, arranged at positions on the front nose, rearview mirror, rear bumper, and rear door of the vehicle 12100 and at a position above the windshield inside the passenger compartment. The imaging unit 12101 arranged on the front nose and the imaging unit 12105 arranged above the windshield inside the passenger compartment mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged on the rearview mirror mainly acquire images on both sides of the vehicle 12100. The imaging unit 12104 arranged on the rear bumper or rear door mainly acquires images behind the vehicle 12100. The imaging unit 12105 arranged above the windshield inside the passenger compartment is mainly used to detect a vehicle ahead, a pedestrian, an obstacle, a traffic signal, a traffic sign, or a lane, etc.

[0145] Incidentally, Figure 24 It shows an example of the imaging ranges of the imaging units 12101 to 12104. The imaging range 12111 represents the imaging range of the imaging unit 12101 arranged on the front nose. The imaging ranges 12112 and 12113 represent the imaging ranges of the imaging units 12102 and 12103 arranged on the rearview mirror, respectively. The imaging range 12114 represents the imaging range of the imaging unit 12104 arranged on the rear bumper or rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as viewed from above is obtained.

[0146] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0147] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can determine the distance of each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change of the distance (relative speed with respect to the vehicle 12100), and thus extract the nearest three-dimensional object as the preceding vehicle. In particular, this three-dimensional object exists on the travel path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or greater than 0 km / h). In addition, the microcomputer 12051 can preset the inter-vehicle distance to be maintained with the preceding vehicle and perform automatic braking control (including following-stop control) or automatic acceleration control (including following-start control), etc. Therefore, cooperative control such as autonomous driving aimed at enabling the vehicle to travel autonomously without relying on the driver's operation can be executed.

[0148] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12501 can classify the three-dimensional object data of the three-dimensional objects into the three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies the obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually recognize and obstacles that the driver of the vehicle 12100 has difficulty visually recognizing. Then, the microcomputer 12051 determines the collision risk indicating the degree of risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering via the drive system control unit 12010. Therefore, the microcomputer 12051 can assist driving to avoid collisions.

[0149] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can identify a pedestrian, for example, by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. For example, such identification of a pedestrian is performed through the following steps: a step of extracting feature points in the captured images of the imaging units 12101 to 12104 that are infrared cameras; and a step of performing pattern matching processing on a series of feature points representing the object contour to determine whether it is a pedestrian. If the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the audio-video output unit 12052 controls the display unit 12062 so that a square contour line for emphasis is displayed in a manner of being superimposed on the identified pedestrian. The audio-video output unit 12052 may also control the display unit 12062 to display an icon or the like representing a pedestrian at a desired position.

[0150] An example of a vehicle control system to which the technology according to the present invention can be applied has been described above. For example, the technology according to the present invention is applicable to the imaging unit 12031 and the like in the above configuration. For example, applying the technology according to the present invention to the imaging unit 12031 and the like can improve the reliability by enhancing the performance.

[0151] <Application Example> The technology according to the present invention is applicable to a medical imaging system. A medical imaging system is a medical system such as an endoscope system and a microscope system that uses imaging technology.

[0152] [Endoscope System] An example of an endoscope system will be described using Figure 25 and 26 FIG. 5000 is a diagram showing an example of a schematic configuration of an endoscope system 5000 to which the technology according to the present invention can be applied. Figure 25 FIG. 5001 is a diagram showing an example of a configuration of an endoscope 5001 and a camera control unit (CCU) 5039. Figure 26 FIG. 5002 shows a situation where an operator (e.g., a doctor) 5067 as a surgical participant uses the endoscope system 5000 to perform a surgery on a patient 5071 on a hospital bed 5069. As Figure 25 shown, the endoscope system 5000 includes an endoscope 5001 as a medical imaging element, a CCU 5039, a light source device 5043, a recording device 5053, an output device 5055, and a support device 5027 for supporting the endoscope 5001. Figure 25

[0153] ​In endoscopic surgery, an insertion aid called a trocar 5025 is punctured into a patient 5071. Then, through the trocar 5025, a scope 5003 connected to an endoscope 5001 and a surgical instrument 5021 are inserted into the body of the patient 5071. For example, the surgical instrument 5021 includes: an energy device such as an electrosurgical knife and forceps.

[0154] A surgical image, which is a medical image of the interior of the patient 5071's body taken by the endoscope 5001, is displayed on a display device 5041. While viewing the surgical image displayed on the display device 5041, an operator 5067 performs surgery on a surgical target using the surgical instrument 5021. The medical image is not limited to a surgical image and may be a diagnostic image taken during diagnosis.

[0155] [Endoscope] The endoscope 5001 is an imaging unit for imaging the interior of the patient 5071's body, and for example, as Figure 26As shown, a camera 5005 includes a condenser optical system 50051 for condensing incident light, a zoom optical system 50052 capable of performing optical zoom by changing the focal length of an imaging unit, a focusing optical system 50053 capable of performing focus adjustment by changing the focal length of the imaging unit, and a light receiving sensor 50054. The endoscope 5001 condenses the light passing through the connected mirror 5003 onto the light receiving sensor 50054 to generate pixel signals, and outputs the pixel signals to the CCU 5039 through a transmission system. The mirror 5003 is an insertion section that includes an objective lens at its distal end and guides the light from the connected light source device 5043 into the body of the patient 5071. The mirror 5003 is, for example, a rigid mirror for a rigid endoscope and a flexible mirror for a flexible endoscope. The mirror 5003 can be a direct-view mirror or an oblique-view mirror. The pixel signal only needs to be a signal based on the signal output from the pixel, and is, for example, a raw (RAW) signal or an image signal. The transmission system connecting the endoscope 5001 to the CCU 5039 can include a memory, and the memory can store parameters related to the endoscope 5001 and the CCU 5039. The memory can be provided at the connection section or the cable of the transmission system. For example, the memory of the transmission system can store the parameters before the endoscope 5001 is shipped or the parameters changed when current is applied, and can change the operation of the endoscope based on the parameters read from the memory. A set of a camera and a transmission system can be referred to as an endoscope. The light receiving sensor 50054 is a sensor for converting the received light into pixel signals, and is, for example, a complementary metal oxide semiconductor (CMOS) imaging sensor. The light receiving sensor 50054 is preferably an imaging sensor having a Bayer array capable of performing color imaging. The light receiving sensor 50054 is also preferably an imaging sensor having the number of pixels corresponding to a resolution such as 4K (3840 horizontal pixels × 2160 vertical pixels), 8K (7680 horizontal pixels × 4320 vertical pixels), or square 4K (3840 or more horizontal pixels × 3840 or more vertical pixels). The light receiving sensor 50054 can be one sensor chip or multiple sensor chips. For example, a prism can be provided to separate the incident light into predetermined wavelength bands, and these wavelength bands can be imaged by different light receiving sensors. Multiple light receiving sensors can be provided for stereoscopic viewing. The light receiving sensor 50054 can be a sensor having a chip structure including an arithmetic processing circuit for image processing, or can be a sensor for time-of-flight (ToF). The transmission system is, for example, an optical fiber cable system or a wireless transmission system. The wireless transmission only needs to be able to transmit the pixel signals generated by the endoscope 5001, and, for example, the endoscope 5001 can be wirelessly connected to the CCU 5039, or the endoscope 5001 can be connected to the CCU 5039 via a base station in the operating room.At this time, the endoscope 5001 can not only transmit pixel signals, but also transmit information related to the pixel signals (for example, the processing priority of the pixel signals and / or synchronization signals) at the same time. In the endoscope, the mirror can be integrated with the camera, and the light receiving sensor can be provided at the distal end of the mirror.

[0156] [Camera Control Unit (CCU)] The CCU 5039 is a control device for integrally controlling the endoscope 5001 and the light source device 5043 connected to the CCU 5039. For example, as Figure 26 shown, it is an image processing device including a field programmable gate array (FPGA) 50391, a central processing unit (CPU) 50392, a random access memory 50393, a read only memory (ROM) 50394, a graphics processing unit (GPU) 50395, and an interface (I / F) 50396. The CCU 5039 can integrally control the display device 5041, the recording device 5053, and the output device 5055 connected to the CCU 5039. The CCU 5039 controls, for example, the irradiation timing, the irradiation intensity, and the type of the irradiation light source of the light source device 5043. The CCU 5039 also performs image processing such as development processing (for example, demosaicing processing) and correction processing on the pixel signals output from the endoscope 5001, and outputs the processed image signals (for example, images) to external devices such as the display device 5041. The CCU 5039 also sends control signals to the endoscope 5001 to control the drive of the endoscope 5001. The control signals are information about imaging conditions such as the magnification or focal length of the imaging unit. The CCU 5039 can have the function of down-converting images, and can be configured to be able to output high-resolution (for example, 4K) images to the display device 5041 and low-resolution (for example, high definition (HD)) images to the recording device 5053 at the same time.

[0157] The CCU 5039 can be connected to external devices (such as recording devices, display devices, output devices, and support devices) via an IP converter for converting signals into a predetermined communication protocol (such as Internet Protocol (IP), etc.). The connection between the IP converter and the external devices can be established using a wired network, or part or all of the network can be established using a wireless network. For example, the IP converter on the CCU 5039 side can have a wireless communication function, and can transmit the received images to the IP switch or the output-side IP converter via a wireless communication network (such as the fifth generation mobile communication system (5G) or the sixth generation mobile communication system (6G), etc.).

[0158] [Light Source Device] The light source device 5043 is a device capable of emitting light having a predetermined wavelength band, and includes, for example, a plurality of light sources and a light source optical system for guiding the light of the light sources. The light sources are, for example, xenon lamps, light emitting diode (LED) light sources, or laser diode (LD) light sources. The light source device 5043 includes, for example, LED light sources corresponding to the three respective primary colors of red (R), green (G), and blue (B), and controls the output intensity and output timing of each light source to emit white light. In addition to the light sources for emitting ordinary light for ordinary light observation, the light source device 5043 may also include a light source capable of emitting special light for special light observation. The special light is light having a predetermined wavelength band different from the ordinary light used for ordinary light observation, and is, for example, near-infrared light (light having a wavelength of 760 nm or longer), infrared light, blue light, or ultraviolet light. For example, normal light is white light or green light. In narrow-band imaging, which is a type of special light observation, blue light and green light are alternately emitted, so that narrow-band imaging can use the wavelength dependence of light absorption in body tissues to image a predetermined tissue (such as blood vessels, etc.) on the mucosal surface with high contrast. In fluorescence observation, which is a type of special light observation, excitation light is emitted to excite a reagent injected into the body tissue, and the fluorescence emitted by the body tissue or the reagent used as a marker is received to obtain a fluorescence image. Therefore, fluorescence observation can facilitate an operator to observe body tissues that are difficult to observe with normal light, for example. For example, in fluorescence observation using infrared light, infrared light having an excitation band is emitted to a reagent (such as indocyanine green (ICG)) injected into the body tissue, and the fluorescence from the reagent is received, so that fluorescence observation can easily observe the structure and affected parts of the body tissue. In fluorescence observation, a reagent (such as 5-aminolevulinic acid (5-ALA)) that emits fluorescence in the red wavelength band when excited by special light in the blue wavelength band can be used. The type of irradiation light of the light source device 5043 is set by the control of the CCU 5039. The CCU 5039 may have a mode of controlling the light source device 5043 and the endoscope 5001 to alternately perform ordinary light observation and special light observation. At this time, preferably, information based on the pixel signal obtained by special light observation is superimposed on the pixel signal obtained by ordinary light observation. The special light observation may be infrared light observation for observing a part inside the surface of an organ and hyperspectral observation using hyperspectral spectroscopy. In addition, photodynamic therapy can be combined.

[0159] [Recording device] The recording device 5053 is a device for recording pixel signals (e.g., images) obtained from the CCU 5039, and is, for example, a recorder. The recording device 5053 records the images obtained from the CCU 5039 in a hard disk drive (HDD), a solid state drive (SDD), and / or an optical disk. The recording device 5053 can be connected to a network in a hospital to be accessed from devices outside the operating room. The recording device 5053 may have a down-conversion function or an up-conversion function.

[0160] [Display device] The display device 5041 is a device capable of displaying images, and is, for example, a display monitor. The display device 5041 displays a display image based on the pixel signals obtained from the CCU 5039. The display device 5041 may include a camera and a microphone to be used as an input device allowing instruction input by sight recognition, voice recognition, and gestures.

[0161] [Output device] The output device 5055 is a device for outputting the information obtained from the CCU 5039, and is, for example, a printer. The output device 5055 prints a print image based on, for example, the pixel signals obtained from the CCU 5039 on paper.

[0162] [Support device] The support device 5027 is an articulated arm including a base 5029 incorporating an arm control device 5045, an arm 5031 extending from the base 5029, and a holding portion 5032 mounted at the distal end of the arm 5031. The arm control device 5045 includes a processor such as a CPU and operates according to a predetermined computer program to control the driving of the arm 5031. The support device 5027 uses the arm control device 5045 to control parameters including, for example, the length of a link 5035 forming the arm 5031 and the rotation angle and torque of a joint 5033, so as to control the position and posture of, for example, an endoscope 5001 held by the holding portion 5032. This control can change the position or posture of the endoscope 5001 to a desired position or posture, enabling the insertion of the scope 5003 into the patient 5071 and enabling the change of the observation area inside the body. The support device 5027 serves as an endoscope support arm for supporting the endoscope 5001 during an operation. Therefore, the support device 5027 can act as an endoscopist who is an assistant for holding the endoscope 5001. The support device 5027 can be a device for holding a microscope device 5301 described later and can be called a medical support arm. The support device 5027 can be controlled by the arm control device 5045 using an autonomous control method, or can be controlled using a control method in which the arm control device 5045 performs control based on a user input. The control method can be, for example, a master-slave method, in which the support device 5027, which serves as a slave device (duplication device) of a patient cart, is controlled based on the movement of a master device (main control device) that is an operator console in the user's hand. The control of the support device 5027 can also be remotely controlled from outside the operating room.

[0163] An example of an endoscope system 5000 to which the technology according to the present invention can be applied has been described above. For example, the technology according to the present invention can be applied to a microscope system.

[0164] [Microscope System] Figure 27 FIG. is an example showing a schematic configuration of a microscope surgical system to which the technology according to the present invention can be applied. In the following description, components identical to those of the endoscope system 5000 will be denoted by the same reference numerals and their description will not be repeated.

[0165] Figure 27 Schematically shows a situation where an operator 5067 performs surgery on a patient 5071 on a hospital bed 5069 using a microscope surgical system 5300. For simplicity, Figure 27The cart 5037 among the components of the microsurgical system 5300 is not shown, and the microscope device 5301 is shown in a simplified manner instead of the endoscope 5001. The microscope device 5301 may refer to the microscope 5303 provided at the distal end of the link 5035, or may refer to the overall structure including the microscope 5303 and the support device 5027.

[0166] As Figure 27 shown, during the operation, the microsurgical system 5300 is used to display an image of the surgical site captured by the microscope device 5301 in an enlarged manner on the display device 5041 installed in the operating room. The display device 5041 is installed at a position facing the operator 5067, and while observing the state of the surgical site using the image displayed on the display device 5042, the operator 5067 performs various operations such as excising the affected area at the surgical site. The microsurgical system is used for, for example, ophthalmic surgery and neurosurgery.

[0167] The respective examples of the endoscope system 5000 and the microsurgical system 5300 to which the technology according to the present invention can be applied have been described above. The systems to which the technology according to the present invention can be applied are not limited to such examples. For example, the support device 5027 may support other observation devices or other surgical instruments at its distal end, instead of the endoscope 5001 or the microscope 5303. Examples of other applicable observation devices include: surgical forceps, tweezers, a pneumoperitoneum tube for pneumoperitoneum, and an energy treatment tool for cutting tissue or sealing blood vessels by cauterization. By using the support device to support the above-mentioned observation devices or surgical instruments, their positions can be fixed more stably, and the load on the medical staff can be lower than in the case where the medical staff manually supports the observation devices or surgical instruments. The technology according to the present invention can also be applied to a support device for supporting such components other than the microscope.

[0168] As a suitable use example, the technology according to the present invention is applicable to the endoscope 5001 and the like in the above-mentioned configuration. For example, the technology according to the present invention applied to the endoscope 5001 and the like can improve reliability by improving performance.

[0169] <Combined example of the structure> Note that the present technology can also adopt the following structure. (1) A solid-state imaging element, comprising: A first transistor, which includes sidewalls surrounding the sides of the first transistor; A second transistor, which is connected in series with the first transistor and includes sidewalls surrounding the sides of the second transistor; A first high-concentration diffusion layer, which is disposed on a semiconductor substrate and extends below the sidewall on the drain side of the first transistor; and A third high-concentration diffusion layer, which is disposed on the semiconductor substrate between the first transistor and the second transistor and extends below the sidewall on the source side of the first transistor, wherein, The impurity concentration of the first high-concentration diffusion layer is lower than that of the third high-concentration diffusion layer. (2) The solid-state imaging device according to the above (1), further comprising: A second high-concentration diffusion layer, which is disposed on the drain side of the first transistor and serves as a contact formation region for connecting to a contact electrode for supplying a drain power supply to the first transistor, wherein, The impurity concentration of the second high-concentration diffusion layer is higher than that of the first high-concentration diffusion layer, and The first high-concentration diffusion layer has a width equal to or greater than a predetermined width. (3) The solid-state imaging device according to the above (1) or (2), further comprising: A low-concentration diffusion layer, which is disposed at the ends of the gate electrode of the first transistor and the ends of the second transistor. (4) The solid-state imaging device according to any one of the above (1) to (3), further comprising: A first film, which covers the gate electrode and the sidewall of the first transistor and the gate electrode and the sidewall of the second transistor; and A second film laminated on the first film, wherein, The second film has an opening that opens between the first transistor and the second transistor. (5) The solid-state imaging device according to the above (4), wherein the distance between the end faces of the opening formed in the second film is greater than the distance between the gate electrode of the first transistor and the gate electrode of the second transistor. (6) The solid-state imaging device according to the above (4) or (5), wherein the third high-concentration diffusion layer is formed by ion implantation using the second film having the opening as a mask. (7) The solid-state imaging device according to the above (6), wherein the third high-concentration diffusion layer and the second high-concentration diffusion layer are formed by different steps. (8) The solid-state imaging device according to any one of (4) to (7) above, wherein the second film is formed at least between the opening and the side surface of the side wall on the drain side of the first transistor. (9) The solid-state imaging device according to any one of (4) to (8) above, wherein the second film is provided such that the distance between the side surface of the first film covering the gate electrode of the first transistor and the side surface of the contact electrode connected to the gate electrode of the first transistor is greater than or equal to the distance between the reference and the end surface of the opening. (10) The solid-state imaging device according to any one of (4) to (9) above, wherein the first film is an oxide film, and the second film is a nitride film. (11) The solid-state imaging device according to any one of (1) to (10) above, wherein the contact electrode for supplying the drain power supply to the first transistor is connected to the first high-concentration diffusion layer. (12) The solid-state imaging device according to any one of (1) to (11) above, further comprising: a dummy contact electrode provided between the gate electrode of the first transistor and the gate electrode of the second transistor, and having one end connected to the semiconductor substrate and the other end not connected. (13) The solid-state imaging device according to (12) above, wherein when forming the dummy contact electrode, the third high-concentration diffusion layer is formed by ion implantation using a through hole formed in the interlayer film. (14) The solid-state imaging device according to any one of (1) to (13) above, wherein the first transistor and the second transistor are arranged linearly in a plan view, or cross each other at substantially a right angle in a plan view. (15) The solid-state imaging device according to any one of (1) to (14) above, wherein each of the first transistor and the second transistor has a fin structure having fins protruding from the semiconductor substrate and extending from the drain side of the first transistor to the source side of the second transistor. (16) The solid-state imaging device according to (15) above, wherein each of the first transistor and the second transistor has a plurality of the fins. (17) The solid-state imaging device according to (15) or (16) above, wherein each of the contact electrodes connected to the drain side of the first transistor and the contact electrodes connected to the source side of the second transistor has a wide shape that contacts the upper surface and the side surface of the fin. (18) The solid-state imaging device according to any one of (1) to (11) above, wherein the first transistor is an amplifying transistor, and the second transistor is a selection transistor. (19) A method of manufacturing a solid-state imaging device, the solid-state imaging device including a first transistor including sidewalls surrounding the surface of the first transistor; and a second transistor connected in series with the first transistor and including sidewalls surrounding the side surfaces of the second transistor, the manufacturing method including: forming a first high-concentration diffusion layer provided on a semiconductor substrate and extending below the sidewalls up to the drain side of the first transistor; and forming a third high-concentration diffusion layer provided on the semiconductor substrate between the first transistor and the second transistor and extending below the sidewalls up to the source side of the first transistor, wherein the impurity concentration of the first high-concentration diffusion layer is lower than the impurity concentration of the third high-concentration diffusion layer. (20) An electronic device, comprising: a solid-state imaging device, the solid-state imaging device including: a first transistor including sidewalls surrounding the side surfaces of the first transistor; a second transistor connected in series with the first transistor and including sidewalls surrounding the side surfaces of the second transistor; a first high-concentration diffusion layer provided on a semiconductor substrate and extending below the sidewalls up to the drain side of the first transistor; and a third high-concentration diffusion layer provided on the semiconductor substrate between the first transistor and the second transistor and extending below the sidewalls up to the source side of the first transistor, wherein the impurity concentration of the first high-concentration diffusion layer is lower than the impurity concentration of the third high-concentration diffusion layer.

[0170] Note that the present embodiment is not limited to the above embodiment, and can be modified in various ways without departing from the scope of the subject matter of the present invention. In addition, the advantageous effects to be provided are not limited to the advantageous effects illustrated in the present specification only by way of example. Other advantageous effects can also be provided. [List of Reference Numerals]

[0171] 11: Imaging element 21: Semiconductor substrate 22: Wiring layer 23: Amplifying transistor 24: Selecting transistor 25 and 26: Gate insulating film 31: Gate electrode 32: Sidewall 33: Gate electrode 34: Sidewall 35: Oxide film 36: Nitride film 37: Interlayer film 38 to 41: Contact electrode 42 to 45: Wiring 51: P-type well layer 52: Low-concentration diffusion layer 53: First high-concentration diffusion layer 54: Second high-concentration diffusion layer 55: Third high-concentration diffusion layer 61: Opening 62 and 63: End face 81: Pseudo-contact electrode 101: Fin 102 and 103: Slit 104 and 105: Notch

Claims

1. A solid-state imaging device, comprising: A first transistor, which includes sidewalls surrounding the sides of the first transistor; A second transistor, which is connected in series with the first transistor and includes sidewalls surrounding the sides of the second transistor; A first high-concentration diffusion layer, which is provided on a semiconductor substrate and extends below the sidewall on the drain side of the first transistor; And A third high-concentration diffusion layer, which is provided on the semiconductor substrate between the first transistor and the second transistor and extends below the sidewall on the source side of the first transistor, wherein, The impurity concentration of the first high-concentration diffusion layer is lower than the impurity concentration of the third high-concentration diffusion layer.

2. The solid-state imaging device according to claim 1, further comprising: A second high-concentration diffusion layer, which is provided on the drain side of the first transistor and serves as a contact formation region for connecting to a contact electrode for supplying a drain power supply to the first transistor, wherein, The impurity concentration of the second high-concentration diffusion layer is higher than the impurity concentration of the first high-concentration diffusion layer, and The first high-concentration diffusion layer has a width greater than a predetermined width.

3. The solid-state imaging device according to claim 1, further comprising: A low-concentration diffusion layer, which is provided at the ends of the gate electrode of the first transistor and the ends of the second transistor.

4. The solid-state imaging device according to claim 2, further comprising: A first film, which covers the gate electrode and the sidewalls of the first transistor and the gate electrode and the sidewalls of the second transistor; And A second film laminated on the first film, Wherein, The second film has an opening that opens between the first transistor and the second transistor.

5. The solid-state imaging device according to claim 4, wherein The distance between the end faces of the opening formed in the second film is greater than the distance between the gate electrode of the first transistor and the gate electrode of the second transistor.

6. The solid-state imaging device according to claim 5, wherein The third high-concentration diffusion layer is formed by ion implantation using the second film having the opening as a mask.

7. The solid-state imaging device according to claim 6, wherein The third high-concentration diffusion layer and the second high-concentration diffusion layer are formed by different steps.

8. The solid-state imaging device according to claim 4, wherein The second film is formed at least between the opening and the side surface of the sidewall on the drain side of the first transistor.

9. The solid-state imaging device according to claim 4, wherein The second film is arranged such that the distance between the side surface of the first film covering the gate electrode of the first transistor taken as a reference and the side surface of the contact electrode connected to the gate electrode of the first transistor is greater than or equal to the distance between the reference and the end face of the opening.

10. The solid-state imaging device according to claim 4, wherein The first film is an oxide film, and The second film is a nitride film.

11. The solid-state imaging device according to claim 1, wherein The contact electrode for supplying a drain power supply to the first transistor is connected to the first high-concentration diffusion layer.

12. The solid-state imaging device according to claim 1, further comprising: A dummy contact electrode, which is provided between the gate electrode of the first transistor and the gate electrode of the second transistor, and one end is connected to the semiconductor substrate and the other end is not connected.

13. The solid-state imaging device according to claim 12, wherein When forming the dummy contact electrode, the third high-concentration diffusion layer is formed by ion implantation using a through hole formed in an interlayer film.

14. The solid-state imaging device according to claim 1, wherein, The first transistor and the second transistor are arranged linearly in a plan view, or cross each other at a substantially right angle in a plan view.

15. The solid-state imaging device according to claim 1, wherein, Each of the first transistor and the second transistor has a fin structure having fins protruding with respect to the semiconductor substrate and extending from the drain side of the first transistor to the source side of the second transistor.

16. The solid-state imaging device according to claim 15, wherein, Each of the first transistor and the second transistor has a plurality of the fins.

17. The solid-state imaging device according to claim 16, wherein, Each of the contact electrode connected to the drain side of the first transistor and the contact electrode connected to the source side of the second transistor has a wide shape in contact with the upper surface and side surfaces of the fins.

18. The solid-state imaging device according to claim 1, wherein, The first transistor is an amplification transistor, and The second transistor is a selection transistor.

19. A method of manufacturing a solid-state imaging device, the solid-state imaging device including a first transistor that includes sidewalls surrounding a surface of the first transistor; and a second transistor, which is connected in series with the first transistor and includes sidewalls surrounding the side surfaces of the second transistor, the manufacturing method includes: forming a first high-concentration diffusion layer provided on the semiconductor substrate and under the sidewalls up to the drain side of the first transistor; and forming a third high-concentration diffusion layer provided on the semiconductor substrate between the first transistor and the second transistor and under the sidewalls up to the source side of the first transistor, wherein, the impurity concentration of the first high-concentration diffusion layer is lower than the impurity concentration of the third high-concentration diffusion layer.

20. An electronic device, comprising: Solid-state imaging device, The solid-state imaging device includes: a first transistor including sidewalls surrounding the side surfaces of the first transistor; a second transistor connected in series with the first transistor and including sidewalls surrounding the side surfaces of the second transistor; a first high-concentration diffusion layer provided on the semiconductor substrate and under the sidewalls up to the drain side of the first transistor; and a third high-concentration diffusion layer provided on the semiconductor substrate between the first transistor and the second transistor and under the sidewalls up to the source side of the first transistor, wherein, the impurity concentration of the first high-concentration diffusion layer is lower than the impurity concentration of the third high-concentration diffusion layer.

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