Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device.The array substrate comprises a substrate, an active layer, a first conducting layer and a second conducting layer, and a first conducting part in the second conducting layer is arranged to be of a laminated structure composed of a first sub-conducting part and a second sub-conducting part; the active layer is made to be connected with the source electrode or the drain electrode at least through the first conductive part, due to the fact that the light transmittance of the first conductive layer is smaller than that of the second conductive layer, the second conductive layer with the higher light transmittance is used for connecting the active layer with the source electrode or the drain electrode in a lap joint mode, the arrangement area of the first conductive layer can be reduced, and therefore the light transmittance of the whole display panel is improved; the conductivity of the first sub-conductive part is greater than that of the second sub-conductive part, so that the contact impedance of the first conductive part and the active layer can be reduced, the problem of current limiting is avoided, and the stability of the array substrate and the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device. Background Art

[0002] Liquid crystal display panels are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptop computers, and desktop computers due to their advantages of high image quality, power saving, thin body, and wide application range, and have become the mainstream in display devices. There are two types of liquid crystal display panels: amorphous silicon and low-temperature polycrystalline silicon. Low-temperature polycrystalline silicon liquid crystal display panels are widely used in high-specification liquid crystal display panels due to their high mobility.

[0003] Currently, the source and drain of a display panel are made of metal. The contact impedance between the metal and the active layer is small, but the light transmittance of the metal is low, which affects the overall light transmittance of the display panel. Transparent conductive materials have good electrical conductivity and light transmittance, but the sheet resistance of transparent conductive materials is higher than that of metal, resulting in a relatively high contact impedance between the transparent conductive material and the active layer, and a mismatch in the work function between the active layer and the transparent conductive material. If transparent conductive materials are used to replace metal to prepare the source and drain, current limiting problems will occur in thin film transistor devices.

[0004] Therefore, it is necessary to provide an array substrate, a display panel, and a display device to improve this defect. Summary of the Invention

[0005] Embodiments of the present application provide an array substrate, a display panel, and a display device, which can improve the light transmittance and stability of the display panel.

[0006] To achieve the above object, according to a first aspect of the present application, there is provided an array substrate, including:

[0007] A substrate;

[0008] An active layer disposed on one side of the substrate;

[0009] A first conductive layer disposed on the side of the active layer away from the substrate, the first conductive layer including at least one of a source electrode and a drain electrode;

[0010] A second conductive layer disposed on the side of the active layer away from the substrate, the light transmittance of the first conductive layer being less than the light transmittance of the second conductive layer;

[0011] Among them, the second conductive layer includes a first conductive portion, the first conductive portion includes a first sub-conductive portion and a second sub-conductive portion, the second sub-conductive portion is disposed on a surface of the first sub-conductive portion away from the substrate, a conductivity of the first sub-conductive portion is greater than a conductivity of the second sub-conductive portion, and the active layer is connected to the source electrode or the drain electrode through the first conductive portion.

[0012] Optionally, the array substrate further includes a third conductive layer, and the third conductive layer is disposed in a different layer from the second conductive layer;

[0013] Among them, the second conductive layer includes a first electrode, the third conductive layer includes a second electrode, the first electrode is one of a common electrode and a pixel electrode, and the second electrode is the other of the common electrode and the pixel electrode.

[0014] Optionally, the first electrode includes a first sub-electrode portion and a second sub-electrode portion, the second sub-electrode portion is disposed on a surface of the first sub-electrode portion away from the substrate, a material of the first sub-electrode portion is the same as a material of the first sub-conductive portion, and a material of the second sub-electrode portion is the same as a material of the second sub-conductive portion.

[0015] Optionally, the second conductive layer is disposed on a side of the first conductive layer away from the substrate, a first hole is provided between the second conductive layer and the active layer, and the first sub-conductive portion of the first conductive portion is connected to the active layer through the first hole; a second hole is provided between the second conductive layer and the first conductive layer, the second hole is spaced apart from the first hole, and the first sub-conductive portion of the first conductive portion is connected to the source electrode or the drain electrode through the second hole.

[0016] Optionally, the array substrate further includes:

[0017] A gate insulating layer, disposed on a surface of the active layer away from the substrate;

[0018] An interlayer dielectric layer, disposed on a surface of the gate insulating layer away from the substrate, at least a part of the first conductive layer is disposed on a surface of the interlayer dielectric layer away from the substrate, and at least a part of the third conductive layer is disposed on a surface of the interlayer dielectric layer away from the substrate; and

[0019] A passivation layer, disposed on surfaces of the interlayer dielectric layer and the first conductive layer away from the substrate, and the second conductive layer is disposed on a surface of the passivation layer away from the substrate;

[0020] Among them, the first hole penetrates through the passivation layer, the interlayer dielectric layer, and the gate insulating layer, and the second hole penetrates through the passivation layer.

[0021] Optionally, the first conductive layer includes a second conductive portion, and the second conductive portion is connected to the second electrode;

[0022] Wherein, the second conductive portion is partially disposed on a surface of the second electrode away from the substrate.

[0023] Optionally, the first conductive layer includes a second conductive portion, and the second conductive portion is connected to the second electrode;

[0024] Wherein, the second electrode is partially disposed on a surface of the second conductive portion away from the substrate.

[0025] Optionally, the second conductive layer is disposed on a side of the first conductive layer close to the substrate, the third conductive layer is disposed on a side of the first conductive layer away from the substrate, and the active layer is sequentially connected to the source electrode or the drain electrode through the first sub-conductive portion and the second sub-conductive portion of the first conductive portion.

[0026] Optionally, the first conductive layer is disposed on a surface of the second sub-conductive portion away from the substrate.

[0027] Optionally, a positive projection of the first conductive layer on the second conductive layer is located within the second conductive layer.

[0028] Optionally, the array substrate further includes:

[0029] A gate insulating layer disposed on a surface of the active layer away from the substrate;

[0030] An interlayer dielectric layer disposed on a surface of the gate insulating layer away from the substrate, and the second conductive layer is disposed on a surface of the interlayer dielectric layer away from the substrate; and

[0031] A passivation layer disposed on surfaces of the interlayer dielectric layer, the first conductive layer, and the second conductive layer away from the substrate, and the third conductive layer is disposed on a surface of the passivation layer away from the substrate;

[0032] Wherein, a first hole is provided between the second conductive layer and the active layer, the first hole penetrates through the passivation layer and the interlayer dielectric layer, and the first sub-conductive portion of the first conductive portion is connected to the active layer through the first hole.

[0033] Optionally, the light transmittance of the first sub-conductive portion is less than that of the second sub-conductive portion.

[0034] Optionally, the thickness of the first sub-conductive portion is less than that of the second sub-conductive portion.

[0035] Optionally, the thickness of the first sub-conductive portion is less than or equal to 300 Å, and the thickness of the second sub-conductive portion is greater than or equal to 300 Å and less than or equal to 1000 Å.

[0036] Optionally, the thickness of the first sub-conductive portion is greater than or equal to 30 Å and less than or equal to 80 Å.

[0037] Optionally, the material of the first sub-conductive portion includes a metal or a mixture of a metal and a metal oxide, and the material of the second sub-conductive portion includes a transparent conductive oxide.

[0038] Optionally, the diffusion coefficient of the material of the first sub-conductive portion is less than the diffusion coefficient of the material of the second sub-conductive portion, and the diffusion coefficient of the material of the second sub-conductive portion is less than the diffusion coefficient of the material of the first conductive layer.

[0039] According to a second aspect of the present application, a display panel is provided, including the array substrate as described above.

[0040] According to a third aspect of the present application, a display device is provided, including the display panel as described above.

[0041] In the array substrate of the embodiment of the present application, by providing the first conductive portion in the second conductive layer as a stacked structure composed of a first sub-conductive portion and a second sub-conductive portion, and connecting the active layer to the source electrode or the drain electrode through the first conductive portion, since the light transmittance of the first conductive layer is less than the light transmittance of the second conductive layer, the active layer is overlapped with the source electrode or the drain electrode by using the second conductive layer with a higher light transmittance, so that the layout area of the first conductive layer can be reduced, thereby improving the overall light transmittance of the array substrate. Since the conductivity of the first sub-conductive portion is greater than the conductivity of the second sub-conductive portion, the contact impedance between the first conductive portion and the active layer can be reduced, avoiding the problem of current limiting, and thus the stability of the display panel can be improved.

[0042] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. Description of the Drawings

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings without creative efforts based on these drawings.

[0044] In order to more fully understand the present application and its beneficial effects, the following description will be made in conjunction with the drawings, where the same reference numerals represent the same parts in the following description.

[0045] Figure 1Schematic structural diagram of the first array substrate provided by the embodiment of the present application;

[0046] Figures 2a to 2d Schematic process flow diagram of the first array substrate provided by the embodiment of the present application;

[0047] Figure 3 Schematic structural diagram of the second array substrate provided by the embodiment of the present application;

[0048] Figure 4 Schematic structural diagram of the third array substrate provided by the embodiment of the present application;

[0049] Figures 5a to 5e Schematic process flow diagram of the third array substrate provided by the embodiment of the present application;

[0050] Figure 6 Schematic structural diagram of the display panel provided by the embodiment of the present application;

[0051] Figure 7 Schematic diagram of the display device provided by the embodiment of the present application. Detailed implementation manners

[0052] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.

[0053] The embodiment of the present application provides an array substrate. The array substrate includes a substrate, an active layer, a first conductive layer, and a second conductive layer. The active layer is disposed on one side of the substrate. The first conductive layer is disposed on the side of the active layer away from the substrate. The first conductive layer includes at least one of a source electrode and a drain electrode. The second conductive layer is disposed on the side of the active layer away from the substrate. The light transmittance of the first conductive layer is less than that of the second conductive layer. The second conductive layer includes a first conductive portion. The first conductive portion includes a first sub-conductive portion and a second sub-conductive portion. The second sub-conductive portion is disposed on the surface of the first sub-conductive portion away from the substrate. The conductivity of the first sub-conductive portion is greater than that of the second sub-conductive portion. The active layer is connected to the source electrode or the drain electrode through the first conductive portion.

[0054] In an embodiment of the present application, by setting the first conductive portion in the second conductive layer as a stacked structure composed of a first sub-conductive portion and a second sub-conductive portion, and enabling the active layer to be connected to the source electrode or the drain electrode at least through the first sub-conductive portion of the first conductive portion, since the light transmittance of the first conductive layer is less than that of the second conductive layer, the active layer is overlapped with the source electrode or the drain electrode by using the second conductive layer with a higher light transmittance, which can reduce the arrangement area of the first conductive layer, thereby improving the overall light transmittance of the array substrate. Since the conductivity of the first sub-conductive portion is greater than that of the second sub-conductive portion, the contact impedance between the first conductive portion and the active layer can be reduced, avoiding the problem of current limiting, and thus the stability of the thin film transistor device in the array substrate can be improved.

[0055] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic structural diagram of a first array substrate provided by an embodiment of the present application. The array substrate 10 includes a substrate 1, an active layer 2, a first conductive layer 3, and a second conductive layer 4. The active layer 2 is disposed on one side of the substrate 1. The first conductive layer 3 is disposed on the side of the active layer 2 away from the substrate 1. The first conductive layer 3 includes at least one of a source electrode 31 and a drain electrode 32. The second conductive layer 4 is disposed on the side of the active layer 2 away from the substrate 1. The light transmittance of the first conductive layer 3 is less than that of the second conductive layer 4. The second conductive layer 4 includes a first conductive portion 41. The first conductive portion 41 includes a first sub-conductive portion 411 and a second sub-conductive portion 412. The conductivity of the first sub-conductive portion 411 is greater than that of the second sub-conductive portion 412. The active layer 2 is connected to the source electrode 31 or the drain electrode 32 at least through the first sub-conductive portion 411 of the first conductive portion 41.

[0056] In an embodiment of the present application, by setting the first conductive portion 41 in the second conductive layer 4 as a stacked structure composed of a first sub-conductive portion 411 and a second sub-conductive portion 412, and enabling the active layer 2 to be connected to the source electrode 31 or the drain electrode 32 at least through the first sub-conductive portion 411 of the first conductive portion 41, since the light transmittance of the first conductive layer 3 is less than that of the second conductive layer 4, the active layer 2 is overlapped with the source electrode 31 or the drain electrode 32 by using the second conductive layer 4 with a higher light transmittance, which can reduce the arrangement area of the first conductive layer 3, thereby improving the overall light transmittance of the array substrate. Since the conductivity of the first sub-conductive portion 411 is greater than that of the second sub-conductive portion 412, the contact impedance between the first conductive portion 41 and the active layer 2 can be reduced, avoiding the problem of current limiting, and thus the stability of the thin film transistor device in the array substrate can be improved.

[0057] In some embodiments, please refer to Figure 1, the array substrate 10 further includes a third conductive layer 5, which is disposed in a different layer from the second conductive layer 4. The second conductive layer 4 includes a first electrode 42, and the third conductive layer 5 includes a second electrode 51. The first electrode 42 is one of the common electrode and the pixel electrode, and the second electrode is the other of the common electrode and the pixel electrode. The first electrode 42 and the second electrode 51 jointly form an electric field for driving the rotation of liquid crystal molecules.

[0058] Please refer to Figure 1 , the first conductive portion 41 and the first electrode 42 are disposed in the same layer, and the materials of the first conductive portion 41 and the first electrode 42 are the same. By using the manufacturing process of the first electrode 42, the first conductive portion 41 can be simultaneously formed, so that the film layer structure and related processes of the display panel can be avoided from increasing. Connecting the active layer 2 to the source electrode 31 or the drain electrode 32 by using the first conductive portion 41 with a higher light transmittance can not only reduce the arrangement area of the first conductive layer 3 with a lower light transmittance, thereby improving the overall light transmittance of the array substrate, but also avoid opening holes in the insulating layer between the first conductive layer 3 and the active layer 2. Therefore, one photomask can be saved, and the production cost can be reduced.

[0059] In some embodiments, please refer to Figure 1 , the first electrode 42 is a pixel electrode, and the second electrode 51 is a common electrode. In some other embodiments, the first electrode 42 is a common electrode, and the second electrode 51 is a pixel electrode.

[0060] In some embodiments, please refer to Figure 1 , the light transmittance of the first sub-conductive portion 411 is less than that of the second sub-conductive portion 412. By making the light transmittance of the first sub-conductive portion 411 less than that of the second sub-conductive portion 412, the overall light transmittance of the first conductive portion 41 can be improved, so that while preventing the problem of current limiting in the thin film transistor devices in the array substrate and improving the stability of the thin film transistor devices, the overall light transmittance of the array substrate can be improved.

[0061] In some embodiments, please refer to Figure 1 , the thickness of the first sub-conductive portion 411 is less than that of the second sub-conductive portion 412. It should be noted that if the thickness of the first sub-conductive portion 411 is too large, it will affect the overall light transmittance of the second conductive layer 4, resulting in a decrease in the overall light transmittance of the array substrate. By making the thickness of the first sub-conductive portion 411 less than that of the second sub-conductive portion 412, it is ensured that the light transmittance of the second conductive layer 4 is greater than that of the first conductive layer 3, thereby increasing the overall light transmittance of the array substrate.

[0062] In some embodiments, please refer to Figure 1, the thickness of the first sub-conductive part 411 is less than or equal to 300 Å, and the thickness of the second sub-conductive part 412 is greater than or equal to 300 Å and less than or equal to 1000 Å. For example, the thickness of the first sub-conductive part 411 is 10 Å, 20 Å, 30 Å, 60 Å, 100 Å, 150 Å, 200 Å, 250 Å, or 300 Å, etc. The thickness of the second sub-conductive part 412 is 300 Å, 500 Å, 700 Å, 900 Å, or 1000 Å, etc.

[0063] It should be noted that since the light transmittance of the first sub-conductive part 411 is less than that of the second sub-conductive part 412, when the thickness of the first sub-conductive part 411 is greater than 300 Å, the sacrifice of the light transmittance of the first conductive part 41 is relatively large, affecting the overall light transmittance of the array substrate. When the thickness of the second sub-conductive part 412 is less than 300 Å, the impedance of the second sub-conductive part 412 is too large. When the thickness of the second sub-conductive part 412 exceeds 1000 Å, the light transmittance of the second sub-conductive part 412 will be reduced, resulting in a reduction in the overall light transmittance of the array substrate. Therefore, limiting the thickness of the first sub-conductive part 411 within 300 Å and limiting the thickness of the second sub-conductive part 412 between 300 Å and 1000 Å can not only make the first conductive part 41 have a lower impedance, thereby improving the stability of the thin-film transistor devices in the array substrate, but also enhance the overall light transmittance of the array substrate.

[0064] In some embodiments, the thickness of the first sub-conductive part 411 is greater than or equal to 30 Å and less than or equal to 80 Å. It should be noted that when the thickness of the first sub-conductive part 411 is less than 30 Å, the film formation uniformity of the first sub-conductive part 411 is poor, and the contact impedance between the first sub-conductive part 411 and the active layer 2 is large. Therefore, by limiting the thickness of the first sub-conductive part 411 between 30 Å and 80 Å, not only can the contact impedance between the first sub-conductive part 411 and the active layer 2 be reduced, but also the thickness of the first sub-conductive part 411 can be thinned to further enhance the overall light transmittance of the array substrate.

[0065] In some embodiments, the material of the first sub-conductive part 411 includes a metal or a mixture of a metal and a metal oxide.

[0066] In some embodiments, the material of the first sub-conductive part 411 includes a metal. Specifically, the material of the first sub-conductive part 411 may include any one of pure metal materials such as molybdenum, titanium, and tungsten, or may also include a titanium-tungsten alloy or other alloy materials.

[0067] In some embodiments, the material of the first sub-conductive portion 411 may be a mixture of a metal and a metal oxide. For example, the material of the first sub-conductive portion 411 may be a mixture of molybdenum and molybdenum oxide, a mixture of titanium and titanium oxide, or a mixture of tungsten and tungsten oxide. It should be noted that since metal materials such as molybdenum, titanium, and tungsten are prone to oxidation during the preparation process, a small amount of metal oxide will be formed in the finally formed first sub-conductive portion 411.

[0068] In some embodiments, the material of the second sub-conductive portion 412 includes a transparent conductive oxide, and the material of the second sub-conductive portion 412 may specifically include any one of transparent conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, and indium tin zinc oxide.

[0069] In some embodiments, the diffusion coefficient of the material of the first sub-conductive portion 411 is less than the diffusion coefficient of the material of the second sub-conductive portion 412, and the diffusion coefficient of the material of the second sub-conductive portion 412 is less than the diffusion coefficient of the material of the first conductive layer 3. It should be noted that since the first sub-conductive portion 411 is in direct contact with the active layer 2, the greater the diffusion coefficient of the first sub-conductive portion 411, the weaker the ion barrier ability of the first sub-conductive portion 411, and ions are more likely to enter the active layer 2 from the first sub-conductive portion 411, resulting in a problem that the thin film transistor device is prone to failure. In this embodiment, by making the diffusion coefficient of the material of the first sub-conductive portion 411 less than the diffusion coefficient of the material of the second sub-conductive portion 412, ions in the first sub-conductive portion 411 and the second sub-conductive portion 412 can be prevented from diffusing into the active layer 2, thereby reducing the risk of failure of the thin film transistor device.

[0070] In some embodiments, please refer to Figure 1 , the first electrode 42 includes a first sub-electrode portion 421 and a second sub-electrode portion 422. The second sub-electrode portion 422 is disposed on the surface of the first sub-electrode portion 421 away from the substrate 1, that is, the first electrode 42 is a double-layer conductive structure formed by stacking the first sub-electrode portion 421 and the second sub-electrode portion 422.

[0071] In some embodiments, please refer to Figure 1, the material of the first sub - electrode portion 421 is the same as that of the first sub - conductive portion 411, and the thickness of the first sub - electrode portion 421 is the same as that of the first sub - conductive portion 411. The material of the second sub - electrode portion 422 is the same as that of the second sub - conductive portion 412, and the thickness of the second sub - electrode portion 422 is the same as that of the second sub - conductive portion 412. By using the manufacturing process of the first electrode 42, the first conductive portion 41 can be simultaneously fabricated, thus avoiding the addition of the film layer structure and related processes of the display panel. Connecting the active layer 2 to the source electrode 31 or the drain electrode 32 with the first conductive portion 41 having a higher light transmittance can not only reduce the arrangement area of the first conductive layer 3 with a lower light transmittance, thereby improving the overall light transmittance of the array substrate, but also avoid opening holes in the insulating layer between the first conductive layer 3 and the active layer 2. Therefore, one photomask can be saved, and the production cost can be reduced.

[0072] In some embodiments, the first electrode 42 can be a single - layer conductive structure formed of a transparent conductive oxide material, so as to further improve the overall light transmittance of the array substrate.

[0073] In some embodiments, please refer to Figure 1 , the second conductive layer 4 is disposed on the side of the first conductive layer 3 away from the substrate 1. There is a first hole V1 between the second conductive layer 4 and the active layer 2, and the first sub - conductive portion 411 of the first conductive portion 41 is connected to the active layer 2 through the first hole V1. There is a second hole V2 between the second conductive layer 4 and the first conductive layer 3, and the second hole V2 is spaced from the first hole V1. The first sub - conductive portion 411 of the first conductive portion 41 is connected to the source electrode 31 or the drain electrode 32 through the second hole V2.

[0074] In some embodiments, please refer to Figure 1 , the array substrate 10 further includes a gate insulating layer 6, an interlayer dielectric layer 7, and a passivation layer 8. The gate insulating layer 6 is disposed on the surface of the active layer 2 away from the substrate 1. The interlayer dielectric layer 7 is disposed on the surface of the gate insulating layer 6 away from the substrate 1. At least a part of the first conductive layer 3 is disposed on the surface of the interlayer dielectric layer 7 away from the substrate 1. At least a part of the third conductive layer 5 is disposed on the surface of the interlayer dielectric layer 7 away from the substrate 1. The passivation layer 8 is disposed on the surfaces of the interlayer dielectric layer 7 and the first conductive layer 3 away from the substrate 1. The second conductive layer 4 is disposed on the surface of the passivation layer 8 away from the substrate 1. Along the thickness direction of the array substrate 10, the first hole V1 penetrates through the passivation layer 8, the interlayer dielectric layer 7, and the gate insulating layer 6, and the second hole V2 penetrates through the passivation layer 8.

[0075] In some embodiments, please refer to Figure 1, the active layer 2 includes a channel portion 21, a first doped portion 22, and a second doped portion 23. The first doped portion 22 is disposed between the second doped portion 23 and the channel portion 21, and the doping concentration of the first doped portion 22 is less than that of the second doped portion 23. Along the thickness direction of the array substrate 10, the first via V1 penetrates through the passivation layer 8, the interlayer dielectric layer 7, and the gate insulating layer 6, and exposes the surface of the second doped portion 23 away from the substrate 1. The second via V2 penetrates through the passivation layer 8 and exposes the surface of the source electrode 31 or the drain electrode 32 away from the substrate 1. The first sub-conductive portion 411 of the first conductive portion 41 is connected to the second doped portion 23 of the active layer 2 through the first via V1, and the first sub-conductive portion 411 is connected to the source electrode 31 or the drain electrode 32 through the second via V2.

[0076] In some embodiments, please refer to Figure 1 , the second conductive layer 4 has a plurality of first conductive portions 41, and the source electrode 31 and the drain electrode 32 are respectively connected to the active layer 2 through the corresponding first conductive portions 41.

[0077] In some embodiments, please refer to Figure 1 , the array substrate 10 further includes a buffer layer 9 and a gate layer 11. The buffer layer 9 is disposed on the surface of the substrate 1, the active layer 2 is disposed on the surface of the buffer layer 9 away from the substrate 1, the gate layer 11 is disposed on the surface of the gate insulating layer 6 away from the substrate 1, and the interlayer dielectric layer 7 covers the gate layer 11.

[0078] In some embodiments, please refer to Figure 1 , the first conductive layer 3 includes a second conductive portion 33. The second conductive portion 33 is connected to the second electrode 51. A part of the second conductive portion 33 is disposed on the surface of the second electrode 51 away from the substrate 1, and another part of the second conductive portion 33 is disposed on the surface of the interlayer dielectric layer 7 away from the substrate 1. When the second electrode 51 is a common electrode, the second conductive portion 33 can be regarded as a common voltage signal line, and the second conductive portion 33 can transmit the common voltage signal to the second electrode 51 so that the second electrode 51 and the first electrode 42 form an electric field for controlling the rotation of liquid crystal molecules.

[0079] Please refer to Figures 2a to 2d , Figures 2a to 2d is a schematic diagram of the manufacturing process of the first array substrate provided by the embodiments of the present application. The manufacturing method of the array substrate includes the following steps:

[0080] Step S1: Sequentially form a buffer layer 9, an active layer 2, a gate insulating layer 6, a gate layer 11, an interlayer dielectric layer 7, a third conductive layer 5, and a first conductive layer 3 on the substrate 1;

[0081] Step S2: A passivation layer 8 is formed on the interlayer dielectric layer 7, the third conductive layer 5, and the first conductive layer 3, and the passivation layer 8, the interlayer dielectric layer 7, and the gate insulating layer 6 are etched to form a first via V1 and a second via V2;

[0082] Step S3: A first sub-conductive material 401 is deposited on the surface of the passivation layer 8 away from the substrate 1, a second sub-conductive material 402 is deposited on the first sub-conductive material 401, and the first sub-conductive material 401 and the second sub-conductive material 402 are etched to form a plurality of first conductive portions 41 and a first electrode 42.

[0083] In some embodiments, referring to Figure 2a , step S1 includes: forming a third conductive layer 5 on the interlayer dielectric layer 7, patterning the third conductive layer 5 to form a second electrode 51; forming a first conductive layer 3 on the interlayer dielectric layer 7 and the third conductive layer 5, and patterning the first conductive layer 3 to form a source electrode 31, a drain electrode 32, and a second conductive portion 33.

[0084] Please refer to Figure 2a , the second conductive portion 33 is connected to the second electrode 51, a part of the second conductive portion 33 is formed on the surface of the second electrode 51 away from the substrate 1, and a part of the second conductive portion 33 is formed on the surface of the interlayer dielectric layer 7 away from the substrate 1.

[0085] It should be noted that Figures 2a to 2d only the manufacturing process of some film layer structures of the array substrate is schematically shown. The manufacturing processes of the remaining film layer structures in the array substrate can be replaced with the manufacturing processes of existing array substrates to achieve the same or similar effects, which will not be elaborated here.

[0086] In some embodiments, referring to Figure 3 , Figure 3 is a schematic structural diagram of a second array substrate provided by an embodiment of the present application, and its structure is substantially the same as that of Figure 1 the first array substrate shown, the difference being that: a part of the second electrode 51 is disposed on the surface of the second conductive portion 33 away from the substrate 1.

[0087] The preparation of the first conductive layer 3 is before the third conductive layer 5, that is, first deposit the first conductive layer 3 on the interlayer dielectric layer 7, pattern the first conductive layer 3 to form the source electrode 31, the drain electrode 32, and the second conductive portion 33; then deposit the third conductive layer 5 on the interlayer dielectric layer 7 and the first conductive layer 3, pattern the third conductive layer 5 to form the second electrode 51, a part of the second electrode 51 is formed on the surface of the second conductive portion 33 away from the substrate 1, and another part of the second electrode 51 is formed on the surface of the interlayer dielectric layer 7 away from the substrate 1. In this way, the same as Figure 1The same technical effects as those of the embodiments shown are not described herein for brevity.

[0088] In some embodiments, please refer to Figure 4 , Figure 4 FIG. 3 is a schematic structural diagram of a third array substrate provided by an embodiment of the present application. Its structure is substantially the same as that of the first array substrate shown in Figure 1 FIG. 1, except that: the second conductive layer 4 is disposed on the side of the first conductive layer 3 close to the substrate 1, the third conductive layer 5 is disposed on the side of the first conductive layer 3 away from the substrate 1, and the active layer 2 is sequentially connected to the source electrode 31 or the drain electrode 32 through the first sub-conductive part 411 and the second sub-conductive part 412 of the first conductive part 41.

[0089] Please refer to Figure 4 FIG. 4. The second conductive layer 4 is disposed on the surface of the interlayer dielectric layer 7 away from the substrate 1, the first conductive layer 3 is disposed on the surface of the second sub-conductive part 412 away from the substrate 1. The first sub-conductive part 411 of the first conductive part 41 is connected to the second doped part 23 of the active layer 2, and the source electrode 31 is connected to the second sub-conductive part 412 of the first conductive part 41. Since the conductivity of the first sub-conductive part 411 is higher than that of the second sub-conductive part 412, the contact impedance between the first conductive part 41 and the active layer 2 can be reduced, thereby preventing the thin-film transistor device in the array substrate from being current-limited, and thus the stability of the array substrate can be improved.

[0090] In some embodiments, please refer to Figure 4 FIG. 5. The orthographic projection of the first conductive layer 3 on the second conductive layer 4 is located within the second conductive layer 4. By using the second conductive layer 4 with a higher light transmittance to connect the first conductive layer 3 and the active layer 2, the arrangement area of the first conductive layer 3 with a lower light transmittance can be reduced, thereby improving the overall light transmittance of the array substrate.

[0091] In some embodiments, please refer to Figure 4 FIG. 6. A plurality of third holes V3 are provided between the second conductive layer 4 and the active layer 2. Along the thickness direction of the array substrate, the third holes V3 penetrate through the interlayer dielectric layer 7 and the gate insulating layer 6, and expose the surface of the second doped part 23 of the active layer 2 away from the substrate 1. The first sub-conductive part 411 of the first conductive part 41 is connected to the active layer 2 through the third holes V3, and the source electrode 31 or the drain electrode 32 is connected to the second sub-conductive part 412 of the first conductive part 41.

[0092] In some embodiments, please refer to Figure 4, the third conductive layer 5 is disposed on the surface of the passivation layer 8 away from the substrate 1. The third conductive layer 5 includes a second electrode 51. The second electrode 51 is a common electrode, and the first electrode 42 is a pixel electrode. The first sub-electrode portion 421 of the first electrode 42 is directly connected to the second doped portion 23 of the active layer 2 through the third via V3, so that the source electrode 31 or the drain electrode 32 in the first conductive layer 3 can be omitted, thereby further reducing the layout area of the first conductive layer 3, and thus further improving the light transmittance of the entire array substrate.

[0093] In some embodiments, please refer to Figures 5a to 5e , Figures 5a to 5e FIG. 3 is a schematic flow chart of the manufacturing process of the third array substrate provided by the embodiment of the present application. The manufacturing method of the array substrate includes the following steps:

[0094] Step S1: Sequentially form a buffer layer 9, an active layer 2, a gate insulating layer 6, a gate layer 11, and an interlayer dielectric layer 7 on the substrate 1;

[0095] Step S2: Etch the interlayer dielectric layer 7 and the gate insulating layer 6 to form a third via V3 that penetrates the interlayer dielectric layer 7 and the gate insulating layer 6;

[0096] Step S3: Sequentially deposit a second conductive layer 4 and a first conductive layer 3 on the interlayer dielectric layer 7, coat a photoresist on the first conductive layer 3, and perform exposure and development processing on the photoresist using a halftone mask plate to form a plurality of photoresist patterns 13;

[0097] Step S4: Perform a first patterning process on the first conductive layer 3 and the second conductive layer 4 simultaneously to form a first conductive portion 41 and a first electrode 42;

[0098] Step S5: Remove the photoresist pattern 13 above the first electrode 42, and remove the first conductive layer 3 not covered by the photoresist pattern 13 to form a source electrode 31 above the first conductive portion 41;

[0099] Step S5: Form a passivation layer 8 on the first conductive layer 3 and the second conductive layer 4, form a third conductive layer 5 on the passivation layer 8, and perform a patterning process on the third conductive layer 5 to form a second electrode 51.

[0100] According to the array substrate provided by the above embodiment of the present application, the embodiment of the present application also provides a display panel. Please refer to Figure 6 , Figure 6Schematic structural diagram of a display panel provided by an embodiment of the present application. The display panel 100 includes an array substrate 10, a counter substrate 20, and a liquid crystal layer 30. The array substrate 10 and the counter substrate 20 are disposed opposite to each other, and the liquid crystal layer 30 is disposed between the array substrate 10 and the counter substrate 20. The array substrate 10 can be replaced with the array substrate provided by any of the above embodiments to achieve the same technical effects in the display panel provided by this embodiment.

[0101] According to the display panel provided by the above embodiments of the present application, an embodiment of the present application further provides a display device. Please refer to Figure 7 , Figure 7 Schematic diagram of a display device provided by an embodiment of the present application. The display device 1000 includes a display panel 100 and a housing 200. The display panel 100 is disposed on the housing 200. The display panel 100 can be the display panel provided by any of the above embodiments. The display device provided by the embodiments of the present application can achieve the same technical effects as the display panel provided by any of the above embodiments, which will not be elaborated herein.

[0102] Beneficial effects of the embodiments of the present application: The embodiments of the present application provide an array substrate, a display panel, and a display device. The array substrate includes a substrate, an active layer, a first conductive layer, and a second conductive layer. By setting the first conductive portion in the second conductive layer as a stacked structure composed of a first sub-conductive portion and a second sub-conductive portion, and connecting the active layer to the source or drain through the first conductive portion, since the light transmittance of the first conductive layer is less than that of the second conductive layer, the second conductive layer with a higher light transmittance is used to lap the active layer and the source or drain, which can reduce the layout area of the first conductive layer, thereby improving the overall light transmittance of the array substrate. Since the conductivity of the first sub-conductive portion is greater than that of the second sub-conductive portion, the contact impedance between the first conductive portion and the active layer can be reduced, avoiding the problem of current limiting, and thus the stability of the array substrate and the display panel can be improved.

[0103] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0104] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0105] The embodiments, implementation manners, and related technical features of the present application can be combined and replaced with each other without conflict.

[0106] The above are only the preferred embodiments of the present application and do not impose any formal restrictions on the present application. However, any simple modifications, equivalent changes, and decorations made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; An active layer, disposed on one side of the substrate; A first conductive layer, disposed on a side of the active layer away from the substrate, the first conductive layer comprising at least one of a source electrode and a drain electrode; A second conductive layer is disposed on a side of the active layer away from the substrate, and the light transmittance of the first conductive layer is less than the light transmittance of the second conductive layer; Among them, the second conductive layer includes a first conductive part, the first conductive part includes a first sub-conductive part and a second sub-conductive part, the second sub-conductive part is arranged on the surface of the first sub-conductive part away from the substrate, the conductivity of the first sub-conductive part is greater than the conductivity of the second sub-conductive part, and the active layer is connected to the source or the drain through the first conductive part.

2. The array substrate according to claim 1, characterized in that: The array substrate further comprises a third conductive layer, and the third conductive layer is arranged in a different layer from the second conductive layer; The second conductive layer includes a first electrode, the third conductive layer includes a second electrode, the first electrode is one of a common electrode and a pixel electrode, and the second electrode is the other of the common electrode and the pixel electrode.

3. The array substrate according to claim 2, characterized in that: The first electrode includes a first sub-electrode portion and a second sub-electrode portion. The second sub-electrode portion is arranged on a surface of the first sub-electrode portion away from the substrate. The first sub-electrode portion is made of the same material as the first sub-conductive portion, and the second sub-electrode portion is made of the same material as the second sub-conductive portion.

4. The array substrate according to claim 2, characterized in that: The second conductive layer is arranged on a side of the first conductive layer away from the substrate, a first hole is arranged between the second conductive layer and the active layer, and the first sub-conductive portion of the first conductive portion is connected to the active layer through the first hole; a second hole is arranged between the second conductive layer and the first conductive layer, the second hole is arranged at intervals from the first hole, and the first sub-conductive portion of the first conductive portion is connected to the source or the drain through the second hole.

5. The array substrate according to claim 4, characterized in that: The array substrate further includes: A gate insulating layer, disposed on a surface of the active layer away from the substrate; an interlayer dielectric layer disposed on a surface of the gate insulating layer away from the substrate, the first conductive layer is at least partially disposed on a surface of the interlayer dielectric layer away from the substrate, and the third conductive layer is at least partially disposed on a surface of the interlayer dielectric layer away from the substrate; and A passivation layer is arranged on the surface of the interlayer dielectric layer and the first conductive layer away from the substrate, and the second conductive layer is arranged on the surface of the passivation layer away from the substrate; The first hole penetrates the passivation layer, the interlayer dielectric layer and the gate insulating layer, and the second hole penetrates the passivation layer.

6. The array substrate according to claim 5, characterized in that: The first conductive layer includes a second conductive portion, and the second conductive portion is connected to the second electrode; The second conductive portion is partially disposed on a surface of the second electrode away from the substrate.

7. The array substrate according to claim 5, characterized in that: The first conductive layer includes a second conductive portion, and the second conductive portion is connected to the second electrode; The second electrode portion is disposed on a surface of the second conductive portion away from the substrate.

8. The array substrate according to claim 2, wherein: The second conductive layer is arranged on a side of the first conductive layer close to the substrate, the third conductive layer is arranged on a side of the first conductive layer away from the substrate, and the active layer is connected to the source or the drain in sequence through the first sub-conductive portion and the second sub-conductive portion of the first conductive portion.

9. The array substrate according to claim 8, characterized in that: The first conductive layer is disposed on a surface of the second sub-conductive portion away from the substrate.

10. The array substrate according to claim 8, characterized in that: The orthographic projection of the first conductive layer on the second conductive layer is located in the second conductive layer.

11. The array substrate according to claim 8, characterized in that: The array substrate also includes: A gate insulating layer, disposed on a surface of the active layer away from the substrate; an interlayer dielectric layer, disposed on a surface of the gate insulating layer away from the substrate, and the second conductive layer is disposed on a surface of the interlayer dielectric layer away from the substrate; and a passivation layer, arranged on the surfaces of the interlayer dielectric layer, the first conductive layer and the second conductive layer away from the substrate, and the third conductive layer is arranged on the surface of the passivation layer away from the substrate; A first hole is provided between the second conductive layer and the active layer, the first hole penetrates the passivation layer and the interlayer dielectric layer, and the first sub-conductive portion of the first conductive portion is connected to the active layer through the first hole.

12. The array substrate according to claim 1, wherein: The light transmittance of the first sub-conductive portion is lower than the light transmittance of the second sub-conductive portion.

13. The array substrate according to claim 12, characterized in that: The thickness of the first sub-conductive portion is smaller than the thickness of the second sub-conductive portion.

14. The array substrate according to claim 1, characterized in that: The thickness of the first sub-conductive portion is less than or equal to 300 angstroms, and the thickness of the second sub-conductive portion is greater than or equal to 300 angstroms and less than or equal to 1000 angstroms.

15. The array substrate according to claim 14, characterized in that: The thickness of the first sub-conductive portion is greater than or equal to 30 angstroms and less than or equal to 80 angstroms.

16. The array substrate according to claim 1, wherein: The material of the first sub-conductive part includes metal or a mixture of metal and metal oxide, and the material of the second sub-conductive part includes transparent conductive oxide.

17. The array substrate according to claim 1, wherein: The diffusion coefficient of the material of the first sub-conductive portion is smaller than the diffusion coefficient of the material of the second sub-conductive portion, and the diffusion coefficient of the material of the second sub-conductive portion is smaller than the diffusion coefficient of the material of the first conductive layer.

18. A display panel, characterized in that: It comprises the array substrate, the opposite substrate and the liquid crystal layer as described in any one of claims 1 to 17, wherein the array substrate and the opposite substrate are arranged opposite to each other, and the liquid crystal layer is arranged between the array substrate and the opposite substrate.

19. A display device, characterized in that: Comprising the display panel as claimed in claim 18.

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