A flexible real-time high-precision radar echo simulation system

Abstract

This invention discloses a flexibly configurable real-time high-precision radar echo simulation system, relating to the field of signal transceiver and processing technology. The system includes N... M The extended interconnected computing matrix and control computer, on the one hand, can construct computing arrays of different topologies and sizes through the connection relationships between the upper and lower levels of the extended interconnected computing matrix, between the extended interconnected computing matrix and the interconnected computing matrix, and between the computing units within the interconnected computing matrix. The more array elements of the interconnected computing matrix and the more levels of the extended interconnection, the larger the scale of the computing matrix, the greater the total computing power and storage space, which can meet the needs of larger-scale radar echo simulation and adapt to different channel scales and computational complexities. On the other hand, by designing the working methods of the control computer and computing units, large-scale parallel echo computing can be realized, achieving high-precision radar echo simulation of multiple channels, and reducing the overall cost.

Description

Technical Field

[0001] This invention belongs to the field of signal transceiver and processing technology, specifically relating to a flexibly configurable real-time high-precision radar echo simulation system. Background Technology

[0002] When conducting indoor testing of radar systems, a common user requirement is to simulate radar echoes in typical scenarios (the electromagnetic waves emitted by the radar system to detect targets, reflected from the surface of an object, and returned to the radar antenna). These radar echoes include echoes from targets the radar wants to detect, as well as echoes from environmental objects the radar does not want to detect; the latter is often referred to as ambient clutter. When evaluating radar detection capabilities, the accuracy and sensitivity of target detection are almost always examined in the presence of significant ambient clutter. Users generally desire to conduct radar performance tests indoors, which necessitates high-precision simulation equipment for radar target echoes and ambient clutter.

[0003] Currently, there are many mature commercial applications of radar target simulators on the market, but environmental clutter simulators are still rare. Furthermore, both of these existing radar echo simulators generally suffer from the following problems:

[0004] (1) Insufficient target echo simulation capability. Existing radar echo simulators are generally designed to simulate a single channel, a single reflection characteristic, and a single radar echo propagation path. However, new radars use polarization, MIMO (Multiple-in Multiple-out), and multistatic radar technology to detect targets. This results in a radar target generating echoes from radar transmission waveforms from one or more azimuths, one or more antennas in each azimuth, and one or more polarization directions in each antenna. The radar echoes from different azimuths, different antennas, and different polarizations are different, resulting in many different combinations and variations. Currently, most radar echo simulators do not have such simulation capability.

[0005] (2) Insufficient environmental clutter simulation capability. All environmental objects will generate radar echoes. Compared with radar targets, environmental objects are far more complex, so the accurate simulation of environmental clutter is also more complex. Accurate radar clutter simulation usually involves first performing a high-precision model of the environment, and then dividing the environmental model into a large number of small environmental grids. At this time, approximate echo calculations can be performed on each grid based on the radar point target simulation method. Then, the radar echoes of all grids are vector summed at the receiving antenna, and the final sum is the radar clutter. However, there is currently a lack of real-time and accurate radar clutter simulators on the market that can achieve large-scale grid subdivision and simulation.

[0006] (3) Insufficient channel and computing power expansion capability. For complex simulation scenarios, the number of channels required for target echo or environmental clutter simulation may be as high as dozens, and there may be mutual coupling between channels. That is, the echo or clutter simulation of a certain channel is related to the transmitted wave of other channels. This leads to the need to expand the number of channels and computing power of the simulator multiple times according to the demand. However, the radar echo simulators on the market do not have such capabilities.

[0007] (4) The overall system construction cost is high. The radar echo simulator usually interacts through the radio frequency link, which is generally expensive. Therefore, the cost of the radar echo simulator is increased accordingly, especially for applications with a large number of channels.

[0008] In summary, current radar target echo simulators and radar environmental clutter simulators on the market suffer from problems such as insufficient target echo simulation capabilities, insufficient environmental clutter simulation capabilities, insufficient channel and computing power expansion capabilities, and high overall system construction costs. Summary of the Invention

[0009] The purpose of this invention is to provide a flexibly configurable real-time high-precision radar echo simulation system to solve the problems of insufficient target echo simulation capability, insufficient environmental clutter simulation capability, insufficient channel and computing power expansion capability, and high overall system construction cost in existing radar echo simulation schemes.

[0010] To achieve the above objectives, the present invention adopts the following technical solution:

[0011] This invention provides a flexibly configurable real-time high-precision radar echo simulation system, including: Meta-extended interconnect computing matrix and control computer, wherein, the The meta-extended interconnect computing matrix includes N M indivual Meta-extended interconnect computing matrix, the The meta-extended interconnect computing matrix includes N M-1 indivual Meta-extended interconnect computing matrix, and so on. The meta-extended interconnect computing matrix includes N M-m indivual Meta-extended interconnect computation matrix, until The meta-extended interconnect computing matrix comprises N² N1-ary interconnect computing matrices, and each N1-ary interconnect computing matrix includes N1 computing units. For N M ×N M-1 ×…×N M-m The abbreviation of ×…×N2×N1, NM N M-1 N M-m N2 and N1 represent integers greater than or equal to 2, M represents integers greater than or equal to 2, m exists when M is greater than or equal to 3, and represents an integer greater than or equal to 0 and less than M-2;

[0012] Any two of the N1 computing units are communicatively connected;

[0013] For each computational unit in any N1-ary interconnected computation matrix, the corresponding unit is communicatively connected to the computational unit in the corresponding position in N2-1 other N1-ary interconnected computation matrices, wherein the any N1-ary interconnected computation matrix and the N2-1 other N1-ary interconnected computation matrices constitute the... Meta-extended interconnect computation matrix;

[0014] For any one Each of the computational units in the meta-extended interconnection computation matrix is ​​such that the corresponding unit is connected to N. M-m -1 other The computing units located at corresponding positions in the meta-extended interconnect computing matrix are communicatively connected, wherein any one of them Meta-extended interconnect computation matrix and the N M-m -1 other The meta-extended interconnect computing matrix constitutes the above. Meta-extended interconnect computation matrix;

[0015] The control computer is respectively communicatively connected to the The controlled ends of each computing unit in the meta-extended interconnect computing matrix;

[0016] When the computing unit has a signal receiving channel and is configured as a receiving computing unit, it is used to transmit the radar transmitted waveform signal received through the signal receiving channel to the computing unit. Each of the computing units configured as participating computing units in the meta-extended interconnect computing matrix;

[0017] The control computer is used to calculate mesh parameters and transmit the calculated mesh parameters to the control computer. Each of the computing units configured as participating computing units in the meta-extended interconnect computing matrix;

[0018] When configured as a participating calculation unit, the computing unit performs electromagnetic reflection calculation, vector synthesis calculation, and / or electromagnetic propagation calculation on all received radar transmitted waveform signals based on the received grid parameters, and transmits the calculated radar echo signal to the [unclear - likely a specific location or system]. The computing unit in the meta-extended interconnect computing matrix that has a signal transmission channel and is configured as a transmission computing unit;

[0019] When the computing unit has a signal transmission channel and is configured as a transmission computing unit, it is used to perform vector synthesis on all the received radar echo signals to obtain the final radar echo signal, and then transmit it through the signal transmission channel.

[0020] Based on the above-described invention, a flexibly configurable real-time high-precision radar echo simulation system is provided, which includes N M The system utilizes an extended interconnected computing matrix and a control computer. On one hand, by connecting the upper and lower levels of the extended interconnected computing matrix, between extended interconnected computing matrices and interconnected computing matrices, and between computing units within the interconnected computing matrix, it can construct computing arrays of different topologies and scales. The more array elements in the interconnected computing matrix and the more levels of the extended interconnection, the larger the scale of the computing matrix, resulting in greater total computing power and storage space. This allows for larger-scale radar echo simulation requirements and adapts to different channel scales and computational complexities. On the other hand, by designing the working methods of the control computer and the computing units within the matrix, large-scale parallel echo computation can be achieved, enabling high-precision multi-channel radar echo simulation. Furthermore, by designing decoupled computing units, signal transceiver units can be removed from echo simulation nodes where radio frequency signal transmission and reception are not required, thereby reducing overall costs. This addresses the problems of insufficient target echo simulation capability, insufficient environmental clutter simulation capability, insufficient channel and computing power expansion capability, and high overall system construction cost in existing radar echo simulation schemes, facilitating practical application and promotion.

[0021] In one possible design, the calculation of the mesh parameters includes:

[0022] Divide radar targets and / or environmental objects into multiple grids;

[0023] For each of the multiple grids, multiple electromagnetic reflection parameters are calculated based on the corresponding electromagnetic wave incident angle, electromagnetic wave exit angle, and the geometry and surface characteristics of the object within the grid. These multiple electromagnetic reflection parameters include radar cross section, RCS fluctuation model parameters, backscattering coefficient, clutter distribution model parameters, and / or polarization scattering coefficient.

[0024] In one possible design, the calculated mesh parameters are transferred to the... Each of the computational units configured as participating computational units in the meta-extended interconnect computation matrix includes:

[0025] In the In the meta-extended interconnect computing matrix, the computing unit with a signal transmission channel and configured as a transmission computing unit is the central computing unit. The meta-extended interconnect computing matrix is ​​decomposed layer by layer outward into multi-order computing resources as follows: the computing resources within the central computing unit are classified as zero-order computing resources; the computing resources within all other computing units in the meta-interconnect computing matrix containing the central computing unit are classified as first-order computing resources; and the computing resources within the N1-level meta-interconnect computing matrix containing the central computing unit are classified as first-order computing resources. The computational resources within all other N1-ary interconnected computational matrices in the meta-extended interconnected computational matrix are classified as second-order computational resources, and so on, to determine Mm-order, M-1-order, and M-order computational resources.

[0026] The calculated mesh parameters corresponding to the near-end mesh are transferred to the... In the meta-extended interconnect computing matrix, each computing unit is configured as a participating computing unit, and the computing resources within the unit are divided into low-order computing resources. The calculated mesh parameters corresponding to the remote mesh are then transmitted to the [unclear - likely a specific location or network]. The computational units configured as participating computational units in the meta-extended interconnected computational matrix, and whose computational resources are divided into high-order computational resources, are as follows: the near-end grid refers to the grid that is close to the radar in the radar echo simulation scenario, and the far-end grid refers to the grid that is far from the radar in the radar echo simulation scenario. Both the near-end grid and the far-end grid belong to multiple grids obtained by dividing the radar target and / or environmental objects. Both the low-order computational resources and the high-order computational resources belong to the multi-order computational resources.

[0027] In one possible design, when the intra-unit computing resources of the computing unit are partitioned into non-zero-order computing resources and configured as participating computing units, the calculated radar echo signal is transmitted to the computing unit. The computing unit in the meta-extended interconnect computing matrix, which has a signal transmission channel and is configured as a transmission computing unit, includes:

[0028] If the local computing unit is directly connected to the first computing unit, then the radar echo signal calculated by the local computing unit and the radar echo signals calculated by all the second computing units are vector-synthesized to obtain a new radar echo signal. This new radar echo signal is then transmitted to the first computing unit. Otherwise, the radar echo signal calculated by the local computing unit is transmitted to the third computing unit, so that it can be transmitted back to the first computing unit via the third computing unit. The first computing unit refers to the... The computing unit in the N1-ary interconnect computing matrix that has a signal transmission channel and is configured as a transmission computing unit; the second computing unit refers to other computing units in the N1-ary interconnect computing matrix where the local computing unit is located that are configured as participating computing units and whose computing resources are of the same level as the computing resources in the local computing unit; the third computing unit refers to other computing units in the N1-ary interconnect computing matrix where the local computing unit is located that are directly connected to the first computing unit and whose computing resources are of the same level as the computing resources in the local computing unit.

[0029] In one possible design, the electromagnetic reflection calculation includes:

[0030] Based on the received grid parameters and the attribute parameters of the radar transmitted waveform signal, electromagnetic reflection simulation of the radar transmitted waveform signal is performed according to the following formula:

[0031] F r (t,n)=F t (t)·A(n)·σ(λ,n)·g(t,n)·f(θ,φ,pol)

[0032] In the formula, n represents the grid number and is a positive integer, t represents time, and F r (t,n) represents the reflected electromagnetic wave from the nth grid, F t (t) represents the incident electromagnetic wave, A(n) represents the area of ​​the nth grid, σ(λ,n) represents the reference radar cross section or backscattering coefficient of the nth grid related to the shape and material properties of the radar target and the wavelength λ of the incident electromagnetic wave, g(t,n) represents the RCS fluctuation model or clutter distribution model of the nth grid, and f(θ,φ,pol) represents the influence function of the incident angle θ, reflection angle φ and polarization state pol on the radar cross section.

[0033] In one possible design, the vector synthesis calculation includes:

[0034] Vector synthesis of reflected electromagnetic waves from adjacent grid groups containing at least two grids is performed according to the following formula:

[0035] F r (t)=ΣΔ(F r (t,n'),n')·Φ(f,n')

[0036] In the formula, t represents time, and F r (t) represents the vector synthesis result of the reflected electromagnetic waves of the adjacent grid group, n' represents the grid number in the adjacent grid group and is a positive integer, F r(t,n') represents the reflected electromagnetic wave of the n'th grid in the adjacent grid group, Δ(x,n') represents the time delay caused by the difference in radial distance between the n'th grid and the first grid in the adjacent grid group due to the direction of the radar receiving antenna, Φ(f,n') represents the Doppler frequency shift caused by the relative motion between the n'th grid and the first grid, and x represents the input variable of the function.

[0037] In one possible design, the electromagnetic propagation calculation includes:

[0038] Electromagnetic propagation is performed on the vector synthesis result of the reflected electromagnetic waves from the grid group according to the following formula:

[0039]

[0040] In the formula, t represents time, and F a (t) represents the reflected electromagnetic wave received by the radar receiving antenna, F r (t) represents the vector synthesis result of the reflected electromagnetic waves of the grid group, G t G represents the gain of the radar transmitting antenna. r Let R represent the gain of the radar receiving antenna, H(x) represent the radial distance in the direction of the radar receiving antenna, H(x) represent the multipath effect response function, Δ(x,R) represent the time delay caused by the radial distance R in the direction of the radar receiving antenna, Φ(f) represent the Doppler frequency shift caused by the motion relative to the radar receiving antenna, and x represent the input variable of the function.

[0041] In one possible design, the computing unit is communicatively connected to K signal transceiver units, where K represents a positive integer, and the signal transceiver units are used to provide the signal receiving channel and / or the signal transmitting channel.

[0042] In one possible design, when the signal transceiver unit includes a second FPGA module and a second storage module and a second high-speed serial interface respectively communicatively connected to the second FPGA module, the signal transceiver unit is also used as an extended computing unit relative to the computing unit, so as to share the computing tasks of the computing unit.

[0043] In one possible design, the computing unit includes a first FPGA module, a first storage module, and a first high-speed serial interface, wherein the number of the first high-speed serial interfaces is at least one and is used for communication connection to a signal transceiver unit or other computing units.

[0044] The first FPGA module is communicatively connected to the first storage module and the first high-speed serial interface.

[0045] In one possible design, the first storage module uses dynamic random access memory, and the first high-speed serial interface uses a Nano-Pitch interface, a MiniSAS HD interface, an SFP interface, an SFP+ interface, a QSFP interface, a QSFP+ interface, a QSFP28 interface, or a QSFP56 interface.

[0046] The beneficial effects of the above scheme are:

[0047] (1) This invention provides a flexibly configurable real-time high-precision radar echo simulation system, which includes N M The system utilizes an extended interconnected computing matrix and a control computer. On one hand, by connecting the upper and lower levels of the extended interconnected computing matrix, between the extended interconnected computing matrix and the interconnected computing matrix, and between the computing units within the interconnected computing matrix, it can construct computing arrays of different topologies and sizes. The more array elements in the interconnected computing matrix and the more levels of the extended interconnection, the larger the scale of the computing matrix, the greater the total computing power and storage space, which can meet the needs of larger-scale radar echo simulation and adapt to different channel sizes and computational complexities. On the other hand, by designing the working methods of the control computer and the computing units in the matrix, it can realize large-scale parallel echo computing, achieving high-precision radar echo simulation across multiple channels. Furthermore, by designing decoupled computing units, signal transceiver units can be removed from echo simulation nodes that do not require RF signal transmission and reception, thereby reducing the overall cost. This can solve the problems of insufficient target echo simulation capability, insufficient environmental clutter simulation capability, insufficient channel and computing power expansion capability, and high overall system construction cost in existing radar echo simulation schemes, making it convenient for practical application and promotion.

[0048] (2) Flexible expansion and splitting: The computational topology designed in this invention is suitable for radar echo simulation systems with a few channels to hundreds of channels. It can easily expand a small-scale radar echo simulation system into a large-scale system, and can also easily split a large-scale system into several small-scale systems.

[0049] (3) High-precision radar echo simulation: The accuracy of radar echo simulation system mainly depends on the number of grids divided for radar targets and environmental objects. The more grids there are, the higher the accuracy of the simulation. The corresponding computing power, data throughput and storage capabilities of the computing system required are also higher. The computing topology designed in this invention can flexibly expand the number of computing units, communication interfaces and storage units for each radar echo, thereby improving the ability of high-precision echo simulation.

[0050] (4) Low computational latency: The hardware circuit characteristics of FPGA itself have the characteristics of low computational latency. At the same time, the computational matrix topology designed in this invention makes data interaction between any two computational units only require a very short data exchange path. Therefore, the entire computational matrix has the advantage of low computational latency. This topology retains the low latency characteristics of low-order computational units when expanding step by step, and also has the characteristics of a significant increase in computing power of high-order computational units. This is exactly in line with the characteristics of low echo delay and small radar illumination area at near distance and large echo delay and large illumination area at far distance in radar clutter simulation.

[0051] (5) Low cost: Due to the standardization of computing units and interconnected computing matrices, the construction and expansion of large-scale radar echo simulation systems no longer need to be customized, thus achieving low cost;

[0052] (6) Easy to configure: Since the computational topology designed in this invention is a completely symmetric structure, the algorithm and program design of the entire computational matrix can be completed by designing the algorithm and program for a single computational unit.

[0053] (7) Customizable: The signal transceiver unit provides extended computing capabilities, and the implementation of this computing power is completely decoupled from the computing matrix, so it is easy to provide customized signal processing capabilities for radar echo simulation port equipment. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 This is a schematic diagram of the specific structure of the computing unit in the real-time high-precision radar echo simulation system provided in an embodiment of the present invention.

[0056] Figure 2 This is a schematic diagram of the specific structure of the binary interconnection computation matrix provided in an embodiment of the present invention.

[0057] Figure 3 This is a schematic diagram of the structure of an N-ary interconnection computation matrix provided in an embodiment of the present invention, wherein, Figure 3 Figure (a) shows a schematic diagram of the structure of the 3-element interconnection computation matrix. Figure 3 Figure (b) shows a schematic diagram of the structure of the 4-element interconnected computation matrix. Figure 3 Figure (c) shows a schematic diagram of the structure of the 5-element interconnected computation matrix.

[0058] Figure 4This is a schematic diagram of the structure of a 3×3 extended interconnection computation matrix provided in an embodiment of the present invention.

[0059] Figure 5 This is a schematic diagram of the structure of a 4×3-element extended interconnection computation matrix provided in an embodiment of the present invention.

[0060] Figure 6 This is a schematic diagram of the structure of a 4×4-element extended interconnection computation matrix provided in an embodiment of the present invention.

[0061] Figure 7 This is a schematic diagram of the specific structure of the signal transceiver unit in the real-time high-precision radar echo simulation system provided in an embodiment of the present invention.

[0062] Figure 8 This is an example diagram illustrating the connection relationship between the 4×4 interconnection computing matrix and the signal transceiver unit provided in an embodiment of the present invention.

[0063] Figure 9 This is an example diagram of the topological structure after the calculation and extension of the 4×4 interconnection computation matrix provided in the embodiment of the present invention.

[0064] Figure 10 This is an example diagram illustrating the connection relationship between the 4×3 interconnection computing matrix and the signal transceiver unit provided in an embodiment of the present invention.

[0065] Figure 11 This is an example diagram illustrating the implementation of the first radar echo simulation calculation logic based on a 4×3-element extended interconnection calculation matrix, as provided in an embodiment of the present invention.

[0066] Figure 12 This is an example diagram illustrating the second type of radar echo simulation calculation logic based on a 4×3-element extended interconnection calculation matrix, provided for embodiments of the present invention. Detailed Implementation

[0067] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in conjunction with the accompanying drawings and descriptions of the embodiments or the prior art. Obviously, the following description of the structure of the accompanying drawings is only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these embodiments without creative effort. It should be noted that the description of these embodiments is for the purpose of helping to understand the present invention, but does not constitute a limitation of the present invention.

[0068] It should be understood that although the terms "first" and "second", etc., may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another. For example, the first object may be referred to as the second object, and similarly, the second object may be referred to as the first object, without departing from the scope of the exemplary embodiments of the invention.

[0069] It should be understood that the term "and / or" that may appear in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, or A and B exist simultaneously. Another example is A, B and / or C, which can mean that any one of A, B, and C or any combination thereof exists. The term " / and" that may appear in this document describes another relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone or A and B exist simultaneously. In addition, the character " / " that may appear in this document generally indicates that the related objects before and after it are in an "or" relationship.

[0070] Example

[0071] like Figures 1-12 As shown, the real-time high-precision radar echo simulation system provided in this embodiment, which is flexibly configurable, includes, but is not limited to, [missing information - likely related to radar echo simulation]. Meta-extended interconnect computing matrix and control computer, etc., wherein, the The meta-extended interconnect computing matrix includes N M indivual Meta-extended interconnect computing matrix, the The meta-extended interconnect computing matrix includes N M-1 indivual Meta-extended interconnect computing matrix, and so on. The meta-extended interconnect computing matrix includes N M-m indivual Meta-extended interconnect computation matrix, until The meta-extended interconnect computing matrix comprises N² N1-ary interconnect computing matrices, and each N1-ary interconnect computing matrix includes N1 computing units. For N M ×N M-1 ×…×N M-m The abbreviation of ×…×N2×N1, N M N M-1 N M-mN1, N2, and N1 represent integers greater than or equal to 2, M represents an integer greater than or equal to 2, m exists when M is greater than or equal to 3, and represents an integer greater than or equal to 0 and less than M-2; any two computing units in the N1 computing units are communicatively connected; for each computing unit in any N1-element interconnected computing matrix, the corresponding unit is communicatively connected to the computing unit in the corresponding position in the N2-1 other N1-element interconnected computing matrices, wherein the any N1-element interconnected computing matrix and the N2-1 other N1-element interconnected computing matrices constitute the... Meta-extended interconnect computation matrix; for any one Each of the computational units in the meta-extended interconnection computation matrix is ​​such that the corresponding unit is connected to N. M-m -1 other The computing units located at corresponding positions in the meta-extended interconnect computing matrix are communicatively connected, wherein any one of them Meta-extended interconnect computation matrix and the N M-m -1 other The meta-extended interconnect computing matrix constitutes the above. Meta-extended interconnect computation matrix.

[0072] like Figures 1-11 As shown, in the specific structure of the real-time high-precision radar echo simulation system, the... The meta-extended interconnected computation matrix is ​​the main body for radar echo simulation calculations, and can be based on N M N M-1 N M-m The scale of the computing unit can be arbitrarily expanded by taking different values ​​of N2, N1, and M, so as to change product characteristics, expand product functions, and adjust channel scale according to different user needs. This solves the problems of insufficient channel and computing power expansion capabilities and high overall system construction costs of existing radar target echo simulators and radar environment clutter simulators on the market. In addition, since the construction of the aforementioned computing matrix is ​​completely symmetrical, when performing radar echo simulation calculations, by designing an embedded computing program for a certain computing unit, the embedded computing program for the entire computing matrix can be completed.

[0073] like Figure 1As shown, specifically, the computing unit includes, but is not limited to, a first FPGA module, a first storage module, and a first high-speed serial interface, wherein there are multiple first high-speed serial interfaces used for communication connections to the signal transceiver unit or other computing units; the first FPGA module is respectively communication-connected to the first storage module and the first high-speed serial interface. The first FPGA (Field Programmable Gate Array) module is used for radar echo simulation calculations, and can be implemented using existing device products; the number of first FPGA modules can be one or multiple, and when there are multiple, the multiple first FPGA modules can be interconnected through high-speed communication interfaces, thereby sharing the data required for calculation among the FPGA modules (at this time, the computing unit composed of multiple first FPGA modules is still logically regarded as a whole computing unit, which can enhance the computing power, storage capacity, and number of high-speed serial interfaces of a single computing unit, and improve the overall computing power and scalability of the interconnected computing matrix). The first storage module (i.e. Figure 1 The first high-speed serial interface (represented by DRAM) is used to temporarily store data in the computing unit, and can be implemented using Dynamic Random Access Memory (DRAM). When there are multiple first FPGA modules, each first FPGA module can be independently connected to the first storage module (i.e., there are also multiple first storage modules). Figure 1The D in the diagram is mainly used for the following four purposes: (a) high-speed interconnection with other computing units on the same circuit board; (b) high-speed interconnection with computing units on other circuit boards through high-speed serial interface connectors (such as QSFP28 or QSFP56 high-speed connectors); (c) connection with the high-speed serial interface of the signal transceiver unit; and (d) connection with the high-speed serial interface of other peripherals. More specifically, the first high-speed serial interface may, but is not limited to, adopt a Nano-Pitch interface, a MiniSAS HD (Serial Attached Small Computer System Interface, HD being an abbreviation for High Definition) interface, an SFP (Small Form Pluggable) interface, an SFP+ interface, a QSFP (Quad Small Form-factor Pluggable) interface, a QSFP+ interface, a QSFP28 interface, or a QSFP56 interface, etc. Preferably, a Nano-Pitch standard 42-pin connector (not limited to this standard) is used as a compact and high-speed connection interface. Each connector can provide up to 6 bidirectional data transmission links with a unidirectional rate of up to 16Gbps, totaling 96Gbps (12GB / s).

[0074] like Figure 2 As shown, the two computing units can communicate with each other via a high-speed serial interface to form a binary interconnect computing matrix. This binary interconnect computing matrix can be connected via a high-speed serial cable or implemented on the same circuit board. The latter eliminates the need for high-speed serial connectors and cables, simplifying the connection, reducing interconnection costs, and increasing the interconnection data rate. The two computing units, through high-speed interconnection, can exchange and share data at high speed, and simultaneously perform parallel calculations on different data, increasing computing power. Furthermore, the two binary interconnect computing matrices can be further extended through a high-speed serial interface to form a 2... 2 A binary-coded extended interconnection computation matrix (its extended interconnection method is: each computational unit of one binary-coded interconnection computation matrix is ​​paired with the corresponding computational unit of another binary-coded interconnection computation matrix). The 2 2 In the meta-extended interconnect matrix, each computing unit can exchange data with any other computing unit at most through an intermediate computing unit, thus ensuring that each computing unit can efficiently obtain the required computing data from other computing units.

[0075] Based on the above-described construction method of the 2-element interconnected computing matrix, further: N1 computing units are fully interconnected (here, full interconnection means that any computing unit is directly connected to the other N1-1 computing units through a high-speed serial connection) to form an N1-element interconnected computing matrix; for example, a 3-element interconnected computing matrix is ​​as follows: Figure 3 As shown in (a) above, the 4-element interconnection computation matrix is ​​as follows: Figure 3 As shown in (b) above, the 5-element interconnection computation matrix is ​​as follows: Figure 3 As shown in (c) in the figure, and so on.

[0076] Based on the above 2 2 Further, the construction method of the extended interconnect computing matrix is ​​as follows: an N1-element interconnect computing matrix can be extended and interconnected with up to N2-1 other N1-element interconnect computing matrices through a high-speed serial interface, constructing an extended interconnect computing matrix of maximum size N2×N1 (the extension interconnection method is that each computing unit of the N1-element interconnect computing matrix is ​​connected pairwise to the corresponding computing units of other N1-element interconnect computing matrices). For example, such as... Figure 4 As shown: the three ternary interconnection computation matrices are expanded into a 3×3 ternary extended interconnection computation matrix; as... Figure 5 As shown: the four ternary interconnection computation matrices are expanded into a 4×3 ternary extended interconnection computation matrix; as... Figure 6 As shown: four 4-ary interconnection computation matrices are expanded into 4×4-ary extended interconnection computation matrices, and so on.

[0077] Based on the above Figures 4-6It can be seen that the topology of the N2×N1 extended interconnect computing matrix is ​​completely symmetrical; that is, the position and connection of each computing unit in the matrix are completely consistent and symmetrical with respect to other computing units. Therefore, each computing unit in the extended interconnect computing matrix is ​​equivalent, which makes the computing matrix very suitable for performing highly parallel and symmetrical computations. In addition to the symmetry of the topology, each computing unit in the N2×N1 extended interconnect computing matrix only needs to go through at most one intermediate computing unit to complete data exchange with any other computing unit. This ensures that each computing unit can easily establish low-latency communication with other computing units, and thus obtain all the data in the entire computing matrix with low latency. Meanwhile, the calculation of radar echo simulation meets these characteristics: (1) the calculation of each echo may be related to all input signals; (2) the calculation of each echo uses the same algorithm and needs to be expanded according to requirements; (3) the calculation of echo needs to meet the requirements of real-time and low latency (specifically because the radar detection range is usually as close as 1km, and the time for electromagnetic waves to be reflected back after being emitted from the antenna to a target 1km away is only 6.6us, so in real-time simulation, the total time for the calculation and transmission of radar echo needs to be completed within this time limit, so the calculation system needs to have low latency characteristics). Thus, an N2×N1 element extended interconnection calculation matrix can be extended and interconnected with up to N3-1 other N2×N1 element interconnection calculation matrices based on the same extension method (where N3 represents an integer greater than or equal to 2) to construct a maximum of N3×N2×N1 element extended interconnection calculation matrix (i.e. Meta-interconnected computation matrix), and can be further extended to N by analogy. M ×N M-1 ×…×N M-m ×…×N2×N1 element-extended interconnection computation matrix (i.e., the aforementioned) Meta-extended interconnect computing matrix). Each computing unit within the meta-extended interconnected computing matrix is ​​also equivalent, and it can exchange data at high speed with any other computing unit by passing through at most M-1 intermediate computing units. This ensures that each computing unit can obtain the required computing data from other computing units efficiently and with low latency.

[0078] Based on the aforementioned expansion methods of the interconnected computing matrix, computing arrays of different topologies and sizes can be constructed. The more array elements in the interconnected computing matrix and the more layers of extended interconnection, the larger the scale of the computing matrix, the greater the total computing power and storage space, and the more adaptable it is to the needs of larger-scale radar echo simulation.

[0079] The control computer is respectively communicatively connected to the The controlled ends of each computing unit in the meta-extended interconnect computing matrix. For example... Figure 1 and Figure 2 As shown, the controlled end of the computing unit is specifically a control bus interface (i.e., Figure 1 (represented by C in Chinese), it preferably uses a PCIe bus or a PCIe-based instrument expansion bus (such as PXIe, CPCIe, VPX, etc.) as the communication and control bus to connect with the bus interface circuit. The PCIe bus and PCIe-based instrument expansion buses have a mature and complete hardware and software ecosystem, allowing users to easily add various I / O modules based on such bus platforms and use mature system and data management software to control and manage the system. These bus platforms also provide a modular architecture, allowing users to easily expand the system's functionality and capabilities using different types and numbers of modules. To enable the computing unit to have a signal receiving channel and / or a signal transmitting channel, specifically, the computing unit is communicatively connected to K signal transceiver units, where K represents a positive integer (i.e., it can be a positive integer such as 1, 2, or 3; additionally, under certain conditions, the computing unit may not be connected to any of the signal transceiver units). The signal transceiver units are used to provide the signal receiving channel and / or the signal transmitting channel. The signal receiving channel is used to receive an input digital signal obtained based on the conversion of an input radio frequency signal, or to receive an input radio frequency signal and convert it into an input digital signal. The signal transmitting channel is used to send an output digital signal that is converted into an output radio frequency signal, or to directly convert the output digital signal into an output radio frequency signal and send it out.

[0080] Since the computational input of the aforementioned interconnected computing matrix typically comes from external radio frequency signals, and the computational output usually also needs to be sent externally, the signal transceiver unit is required for acquisition or generation and transmission. In addition to handling high-speed transmission and reception of digital or analog signals, the signal transceiver unit can also perform signal processing according to specific needs, and is mainly composed of an FPGA module and a high-speed serial interface. Specifically, when the signal transceiver unit is used to provide a signal receiving channel and a signal transmitting channel, and the signal receiving channel is used to receive the input radio frequency signal and convert it into an input digital signal, and the signal transmitting channel is used to directly convert the output digital signal into an output radio frequency signal and transmit it, the signal transceiver unit includes, but is not limited to, an analog receiving front-end module, an analog transmitting front-end module, an ADC module, a DAC module, a second FPGA module, a second storage module, and a second high-speed serial interface, etc., wherein the analog receiving front-end module is used to receive the input radio frequency signal, the analog transmitting front-end module is used to transmit the output radio frequency signal, and the second high-speed serial interface is used to communicate with the computing unit; the output end of the analog receiving front-end module is communicatively connected to the input end of the ADC module, the output end of the ADC module is communicatively connected to the input end of the second FPGA module, the input end of the analog transmitting front-end module is communicatively connected to the output end of the DAC module, the input end of the DAC module is communicatively connected to the output end of the second FPGA module, and the second FPGA module is also communicatively connected to the second storage module and the second high-speed serial interface respectively.

[0081] like Figure 7As shown, in the specific structure of the signal transceiver unit, the analog receiving front-end module and the analog transmitting front-end module correspond one-to-one with the ADC module and the DAC module, respectively, for frequency conversion, amplification, conditioning, filtering, receiving and transmitting analog signals, and realizing the conversion between analog and digital signals. The second FPGA module has high-speed data throughput capability and is a key device connecting the ADC / DAC and the analog front-end. With its suitability for high-speed parallel fixed-point computation, it can provide the system with real-time signal preprocessing capabilities, performing some signal processing work on one hand, and extracting and compressing effective data on the other, reducing the amount of data transmitted between the system and the back-end signal processor. The second FPGA module can also have signal processing latency as low as nanoseconds and achieve low-latency signal transmission and reception through the ADC module and the DAC module. The second storage module specifically includes, but is not limited to, DRAM and FLASH, where the former is used for local caching and temporary storage of high-speed signal data, and the latter is used to store firmware programs. The second high-speed serial interface can be implemented as a high-speed serial bus interface using the Aurora communication protocol, preferably using the Aurora 16Gbps x6 or higher high-speed serial transmission protocol, which has a peak data throughput of 11GB / s and a transmission latency as short as microseconds. This can provide sufficient transmission bandwidth and sufficiently short transmission latency for most real-time signal processing applications, ensuring the continuity and timeliness of data transmission and providing the basic conditions for real-time signal processing. The second high-speed serial interface is further preferably made of the Nano-Pitch series connectors manufactured by Molex, which can provide a data transmission capability of up to 25Gbps x8, which is sufficient to meet the full-duplex transmission requirements of two 2GHz instantaneous bandwidth signals.

[0082] More preferably, the signal transceiver unit further includes, but is not limited to, a clock and trigger signal interface, an onboard OCXO module, and a clock generation and distribution circuit module based on a phase-locked loop mechanism, wherein the clock and trigger signal interface ( Figure 7 The onboard OCXO module (represented by DIO) is used, but is not limited to, receiving external sampling clock signals, reference clock signals, GPS second pulse signals, and trigger signals. Figure 7 The clock and trigger signal interface (represented by OCXO) is used to generate a time base signal; the trigger signal output terminal of the clock and trigger signal interface is communicatively connected to the second FPGA module, and the non-trigger signal output terminal of the clock and trigger signal interface and the time base signal output terminal of the onboard OCXO module are respectively communicatively connected to the input terminal of the clock generation and distribution circuit module. Figure 7The clock signal output terminal (represented by a PLL) is communicatively connected to the analog receiving front-end module, the analog transmitting front-end module, the ADC module, the DAC module, and the second FPGA module. The connectors for the clock and trigger signal interfaces can be selected according to the specific signal frequency and quantity. The sampling clock signal, the reference clock signal, the GPS second pulse signal, and the time base signal are used to provide clock signals to the analog receiving front-end module, the analog transmitting front-end module, the ADC module, the DAC module, and the second FPGA module respectively through the clock generation and distribution circuit module based on a phase-locked loop. The trigger signal is connected to the second FPGA module and is used for internal processing logic triggered by external events. In this way, through the aforementioned clock and trigger mechanism, multiple parallel or distributed signal transceiver units can work synchronously to achieve the reception or transmission of coherent signals.

[0083] The interconnection calculation matrix can connect the signal transceiver units according to the echo simulation requirements. The number of signal receiving channels and signal transmitting channels provided by each signal transceiver unit can be different and can also be set according to the echo simulation requirements. Since the complete interconnection calculation matrix and the connection of the signal transceiver units also have perfect symmetry, therefore, for the... Meta-extended interconnection computation matrix, if all N M ×N M-1 ×…×N M-m Each of the ×…×N2×N1 computational units is connected to…×N1 ( Let J represent a positive integer number of signal transceiver units, and each signal transceiver unit has J pairs of transceiver channels. Then the real-time high-precision radar echo simulation system has a total of J pairs of transceiver channels. For the transceiver channel, an H-receive / H-transmit radar echo simulation system is formed. Furthermore, based on the structure of the signal transceiver unit, it can be seen that the signal transceiver unit also includes a computing unit structure, namely a combination of FPGA, DRAM, and high-speed serial port. Therefore, when the signal transceiver unit is connected to the interconnect computing matrix, it is essentially equivalent to connecting new computing units to each node of the interconnect computing matrix. For example... Figure 8 As shown, in the 4-element interconnect computing matrix, each computing unit is connected to two signal transceiver units, which receive and transmit radio frequency signals. Since the signal transceiver units contain computing unit structures, this interconnect computing matrix is ​​effectively expanded to resemble... Figure 9The extended interconnect computing matrix topology is shown. Although each computing unit of the extended interconnect computing matrix does not have as many interconnected computing units as an interconnect computing matrix or an extended interconnect computing matrix (i.e., each computing unit is interconnected with other computing units through multiple high-speed serial interfaces), the computing power of each computing unit of the original extended interconnect computing matrix is ​​enhanced. This allows the extended interconnect computing matrix to not only perform fully symmetrical channel simulation calculations, but also to complete further signal processing related to devices connected to each channel simulation port. More preferably, when the signal transceiver unit includes a second FPGA module and a second storage module and a second high-speed serial interface respectively communicatively connected to the second FPGA module, the signal transceiver unit is also used as a... The extended computing unit is used to share the computational tasks of the main computing unit. Furthermore, the extended computing unit can also perform any one or any combination of the following extended computing tasks (A) to (I): (A) increasing the instantaneous bandwidth of the signal using interpolation; (B) reducing the instantaneous bandwidth of the signal using decimation; (C) changing the center frequency of the signal using digital frequency conversion; (D) calculating the signal spectrum in real time; (E) calculating target echoes or clutter in real time; (F) simulating the phase shift of signals arriving at each port of the multi-channel direction-finding receiver; (G) simulating the signal amplitude and phase of each channel in the radar sum and difference channels and auxiliary channels; (H) transmitting and receiving data via a high-speed serial bus; (I) performing amplitude and phase calibration of the transmitted and received signals. This extended computing capability significantly increases the functions that the real-time high-precision radar echo simulation system can simulate. Figure 9 This illustrates the topological structure after computationally extending the 4-element interconnect computation matrix; similarly, all... All extended interconnect computing matrices can be formed by connecting the signal transceiver units to any number of computing units, such as... Figure 10 As shown, 3 2 The interconnected computing matrix is ​​extended, and each computing unit is connected to one signal transceiver unit. Furthermore, the computational input to the aforementioned interconnected computing matrix can also be injected as a digital signal via a high-speed serial interface, and its computational output can also be output as a digital signal via a high-speed serial interface. In this case, the relevant computing unit may not be connected to the signal transceiver unit.

[0084] Since the radar echo simulation system needs to calculate and generate echoes for each radar receiving antenna and output them to the corresponding radar receiving channel via radio frequency or digital channels, and each output echo signal is generated by the simulation system after performing electromagnetic reflection, vector synthesis, and / or electromagnetic propagation simulation calculations based on one or more received incident radar transmitted wave signals, in the real-time high-precision radar echo simulation system, when the calculation unit has a signal receiving channel and is configured as a receiving calculation unit, it is used to transmit the radar transmitted waveform signal received through the signal receiving channel to the corresponding radar receiving channel. The various computing units configured as participating computing units in the meta-extended interconnect computing matrix; the control computer, used to perform mesh parameter calculations and transmit the calculated mesh parameters to the... Each of the computing units configured as participating computing units in the meta-extended interconnect computing matrix; when configured as participating computing units, the computing units are used to perform electromagnetic reflection calculation, vector synthesis calculation, and / or electromagnetic propagation calculation on all received radar transmitted waveform signals according to the received grid parameters, and transmit the calculated radar echo signals to the... The computational unit in the meta-extended interconnected computational matrix has a signal transmission channel and is configured as a transmission computational unit. When configured as a transmission computational unit with a signal transmission channel, the computational unit performs vector synthesis on all received radar echo signals to obtain the final radar echo signal, and then transmits it through the signal transmission channel. Furthermore, before performing high-precision calculations for radar echo simulation, it is necessary to determine the specific participating computational units (and corresponding environmental modeling parameters) based on the total number of grid computing resources required, and determine the receiving computational unit for the radar transmitted waveform signal and the transmitting computational unit for the radar echo signal based on the hardware connection of the signal transceiver unit. Then, based on the aforementioned determination results, the participating computational units, receiving computational units, and transmitting computational units are manually configured.

[0085] Specifically, the calculation of the grid parameters includes, but is not limited to: dividing the radar target and / or environmental objects into multiple grids; for each grid, calculating multiple electromagnetic reflection parameters based on the corresponding electromagnetic wave incident angle, electromagnetic wave exit angle, and the geometry and surface characteristics of the object within the grid. These multiple electromagnetic reflection parameters include, but are not limited to, radar cross section (RCS), RCS (Radar Cross Section) fluctuation model parameters, backscattering coefficient, clutter distribution model parameters, and / or polarization scattering coefficient. The aforementioned specific calculation process is existing technology and will not be elaborated further here. Furthermore, the electromagnetic reflection parameters can be pre-calculated or obtained directly from external model parameters.

[0086] Since the position and connection relationship of each computing unit in the extended interconnection computing matrix are completely consistent and symmetrical, the... The meta-extended interconnect computing matrix is ​​decomposed layer by layer outward from any one computing unit into multi-order computing resources: the computing resources within the arbitrary computing unit are classified as zero-order computing resources; the computing resources within all other computing units in the N1-meta-interconnect computing matrix containing the arbitrary computing unit are classified as first-order computing resources; and the computing resources within the N1-meta-interconnect computing matrix containing the arbitrary computing unit are classified as first-order computing resources. The computational resources within all other N1-ary interconnected computational matrices in the extended interconnected computational matrix are classified as second-order computational resources, and so on, determining Mm-order, M-1-order, and M-order computational resources. Since the aforementioned second-order computational resources require at most one computational unit to establish a one-to-one high-speed serial connection with the central computational unit, their access speed is slower than the first-order computational resources, and their computational latency is also lower; and so on. This computational resource topology is well-suited for the simulation calculation of radar environmental clutter, because radar environmental clutter also has the following characteristics: small near-field illumination area with smaller echo delay and fewer grid cells; large far-field illumination area with larger echo delay and more grid cells. This allows low-order computational resources to be allocated to near-field grids and high-order computational resources to far-field grids during simulation calculations. Preferably, the calculated grid parameters are transmitted to the central computational unit. Each of the computing units configured as participating computing units in the meta-extended interconnect computing matrix includes, but is not limited to, those configured to: The computing unit in the meta-extended interconnect computing matrix that has a signal transmission channel and is configured as a transmission computing unit is the central computing unit, and is configured as follows: The meta-extended interconnect computing matrix is ​​decomposed layer by layer outward into multi-order computing resources: the computing resources within the central computing unit are classified as zero-order computing resources; the computing resources within all other computing units in the N1-meta-interconnect computing matrix containing the central computing unit are classified as first-order computing resources; and the computing resources within the N1-meta-interconnect computing matrix containing the central computing unit are classified as first-order computing resources. The computational resources within all other N1-ary interconnection computation matrices in the meta-extended interconnection computation matrix are classified as second-order computational resources, and so on, determining Mm-order, M-1-order, and M-order computational resources; the calculated mesh parameters corresponding to the near-end mesh are transferred to the... In the meta-extended interconnect computing matrix, each computing unit is configured as a participating computing unit, and the computing resources within the unit are divided into low-order computing resources. The calculated mesh parameters corresponding to the remote mesh are then transmitted to the [unclear - likely a specific location or network]. In the meta-extended interconnected computing matrix, each computing unit is configured as a participating computing unit, and its computing resources are divided into high-order computing resources. Here, the near-end grid refers to the grid closer to the radar in the radar echo simulation scenario, and the far-end grid refers to the grid farther from the radar in the radar echo simulation scenario. Both the near-end and far-end grids belong to multiple grids obtained by dividing radar targets and / or environmental objects. The low-order and high-order computing resources both belong to the multi-order computing resources. The near-end and far-end grids are relative terms, and any grid can be determined as either a near-end or far-end grid based on a conventional threshold comparison method. Furthermore, assuming each computing unit has L-way grid computing resources, then... The meta-extended interconnected computing matrix has a total of: L zero-order grid computing resources, (N1-1)×L first-order grid computing resources, (N2-1)×N1×L second-order grid computing resources, and so on, for a total of N M ×N M-1 ×…×N M-m ×…×N2×N1×L road grid computing resources.

[0087] Specifically, the electromagnetic reflection calculation includes, but is not limited to: performing electromagnetic reflection simulation on the radar transmitted waveform signal according to the received grid parameters and the attribute parameters of the radar transmitted waveform signal, using the following formula:

[0088] F r (t,n)=F t (t)·A(n)·σ(λ,n)·g(t,n)·f(θ,φ,pol)

[0089] In the formula, n represents the grid number and is a positive integer, t represents time, and F r (t,n) represents the reflected electromagnetic wave from the nth grid, F t (t) represents the incident electromagnetic wave, A(n) represents the area of ​​the nth grid, σ(λ,n) represents the reference radar cross section or backscattering coefficient of the nth grid related to the shape and material properties of the radar target and the wavelength λ of the incident electromagnetic wave, g(t,n) represents the RCS fluctuation model or clutter distribution model of the nth grid, and f(θ,φ,pol) represents the influence function of the incident angle θ, reflection angle φ, and polarization state pol on the radar cross section. The aforementioned RCS fluctuation model or clutter distribution model is used to describe the change of scattering characteristics of the radar target over time t. Specifically, these fluctuations can be represented by Swerling models (such as the existing Swerling 1 model or Swerling 2 model, etc.) or clutter statistical distribution models.

[0090] Specifically, the vector synthesis calculation includes, but is not limited to, performing vector synthesis on reflected electromagnetic waves from adjacent grid groups containing at least two grids according to the following formula:

[0091] F r (t)=ΣΔ(F r (t,n'),n')·Φ(f,n')

[0092] In the formula, t represents time, and F r (t) represents the vector synthesis result of the reflected electromagnetic waves of the adjacent grid group, n' represents the grid number in the adjacent grid group and is a positive integer, F r (t,n') represents the reflected electromagnetic wave of the n'th grid in the adjacent grid group, Δ(x,n') represents the time delay caused by the difference in radial distance between the n'th grid and the first grid in the adjacent grid group due to the direction of the radar receiving antenna, Φ(f,n') represents the Doppler frequency shift caused by the relative motion between the n'th grid and the first grid, and x represents the input variable of the function.

[0093] Specifically, the electromagnetic propagation calculation includes, but is not limited to, performing electromagnetic propagation on the vector synthesis results of the reflected electromagnetic waves from the grid group according to the following formula:

[0094]

[0095] In the formula, t represents time, and F a (t) represents the reflected electromagnetic wave received by the radar receiving antenna, F r (t) represents the vector synthesis result of the reflected electromagnetic waves of the grid group, G t G represents the gain of the radar transmitting antenna. r Let R represent the gain of the radar receiving antenna, H(x) represent the radial distance in the direction of the radar receiving antenna, H(x) represent the multipath effect response function, Δ(x,R) represent the time delay caused by the radial distance R in the direction of the radar receiving antenna, Φ(f) represent the Doppler frequency shift caused by the motion relative to the radar receiving antenna, and x represent the input variable of the function.

[0096] Specifically, when the computing resources within the computing unit are allocated as non-zero-order computing resources and configured as participating computing units, the calculated radar echo signal is transmitted to the computing unit. The computing units in the meta-extended interconnect computing matrix that have signal transmission channels and are configured as transmission computing units include, but are not limited to: if the local computing unit is directly connected to the first computing unit, then the radar echo signal calculated by the local computing unit and the radar echo signals calculated by all the second computing units are vector-synthesized to obtain a new radar echo signal, and then the new radar echo signal is transmitted to the first computing unit; otherwise, the radar echo signal calculated by the local computing unit is transmitted to the third computing unit, so that it can be transmitted to the first computing unit through the third computing unit. The first computing unit refers to the... The computing unit in the N1-ary interconnect computing matrix that has a signal transmission channel and is configured as a transmission computing unit; the second computing unit refers to other computing units in the N1-ary interconnect computing matrix where the local computing unit is located that are configured as participating computing units and whose computing resources are of the same level as the computing resources in the local computing unit; the third computing unit refers to other computing units in the N1-ary interconnect computing matrix where the local computing unit is located that are directly connected to the first computing unit and whose computing resources are of the same level as the computing resources in the local computing unit.

[0097] This embodiment takes a 4×3 extended interconnect computing matrix as an example, and numbers each computing unit and signal transceiver channel group: In the computing unit numbering rule U(N2,N1), N1 is the position of each computing unit in each interconnect computing matrix, N2 is the position of each interconnect computing matrix in the extended interconnect computing matrix, the value of N1 is from 0 to 2, and the value of N2 is from 0 to 3; if the computing unit is connected to the signal transceiver unit, the signal transceiver channels connected to the signal transceiver unit are numbered as R(N2,N1,J) and T(N2,N1,J) respectively, where J is the Jth signal transceiver channel connected to this computing unit (the value starts from 0), N1 is the position of each computing unit in each interconnect computing matrix, and N2 is the position of each interconnect computing matrix in the extended interconnect computing matrix.

[0098] Implementation Example 1:

[0099] like Figure 11As shown in the example diagram (the lines connecting the computing units and signal transceiver units: solid lines represent high-speed connections used, dashed lines represent unused high-speed connections, and dotted lines represent high-speed connections between computing units and signal transceiver units), computing unit U(0,0) is connected to one set of signal transceiver channels, namely the R(0,0,0) receiving channel and the T(0,0,0) transmitting channel, requiring a total of 9 computing units for high-precision echo calculation; computing units U(1,0), U(1,1), and U(1,2) are each connected to one set of signal transceiver channels, requiring one computing unit of their own for lower-precision echo calculation.

[0100] Taking the T(0,0,0) transmission channel on the U(0,0) computing unit as an example, the calculation of its radar echo simulation is divided into the following four steps:

[0101] (A1) The radar transmitted waveform signal received by the U(0,0) calculation unit from the R(0,0,0) receiving channel is sent to the calculation units configured to participate in the calculation through the high-speed serial connection between the calculation units, including the U(0,X) calculation unit, the U(2,X) calculation unit and the U(3,X) calculation unit, for a total of 8 calculation units;

[0102] (B1) Control the computer to calculate the mesh parameters and send the calculated mesh parameters to each computing unit through the control bus interface;

[0103] (C1) Each computing unit performs electromagnetic reflection, vector synthesis, and electromagnetic propagation calculations, and sends the results to the U(0,0) computing unit through the high-speed serial connection between computing units. Among them, the U(2,X) computing unit and the U(3,X) computing unit need to first perform vector synthesis of the echo calculation results in their respective interconnected computing matrix, and then send the synthesized echo to the U(0,0) computing unit through the high-speed serial connection between the U(2,0) computing unit and the U(3,0) computing unit and the U(0,0) computing unit.

[0104] The (D1)U(0,0) calculation unit performs the final vector synthesis of all echo calculation results and then transmits them through the T(0,0,0) transmission channel.

[0105] Taking the T(1,0,0) transmit channel and R(1,0,0) receive channel on the U(1,0) computing unit as an example, the calculation of its radar echo simulation is divided into the following two steps:

[0106] (E1) controls the computer to calculate the mesh parameters and sends the calculated mesh parameters to the U(1,0) calculation unit through the control bus interface;

[0107] The (F1)U(1,0) computational unit performs electromagnetic reflection, vector synthesis, and electromagnetic propagation calculations, and sends the calculated results out through the T(0,0,0) transmission channel.

[0108] Implementation Example 2:

[0109] like Figure 12 As shown in the example diagram (where solid lines represent high-speed connections used, dashed lines represent unused high-speed connections, and dotted lines represent high-speed connections between computing units and signal transceiver units), each of the four U(X,0) computing units is connected to one signal receiving channel and two signal transmitting channels, i.e., the R(X,0,0) receiving channel and the T(X,0,Y) transmitting channel shown in the diagram, utilizing a total of nine computing units; based on the radar transmission waveforms received by these four signal receiving channels, high-precision echo calculations are performed for all eight signal transmitting channels.

[0110] Taking the T(0,0,0) and T(0,0,1) transmission channels on the U(0,0) computing unit as examples, the calculation of its radar echo simulation is divided into the following four steps:

[0111] (A2) The radar transmission waveform signals received from the R(0,0,0) receiving channel, R(1,0,0) receiving channel, R(2,0,0) receiving channel, and R(3,0,0) receiving channel on the U(0,0) computing unit, U(1,0) computing unit, U(2,0) computing unit, and U(3,0) computing unit are sent to the U(0,0) computing unit through the high-speed serial connection between the computing units, and then sent by the U(0,0) computing unit to the U(0,1) computing unit and the U(0,2) computing unit;

[0112] (B2) Control the computer to calculate the mesh parameters and send the calculated mesh parameters to each computing unit through the control bus interface;

[0113] (C2) The U(0,0) calculation unit, the U(0,1) calculation unit and the U(0,2) calculation unit perform electromagnetic reflection, vector synthesis and electromagnetic propagation calculations respectively, and the U(0,1) calculation unit and the U(0,2) calculation unit send the calculated results to the U(0,0) calculation unit through the high-speed serial connection between the calculation units;

[0114] (D2) The U(0,0) calculation unit performs the final vector synthesis of the echo calculation results from the U(0,0) calculation unit, the U(0,1) calculation unit, and the U(0,2) calculation unit, and then transmits them through the T(0,0,0) transmission channel and the T(0,0,1) transmission channel.

[0115] The echo calculation and transmission process of the U(1,0) calculation unit, the U(2,0) calculation unit, and the U(3,0) calculation unit can be deduced by analogy.

[0116] In summary, the real-time high-precision radar echo simulation system provided in this embodiment has the following technical effects:

[0117] (1) This embodiment provides a flexibly configurable real-time high-precision radar echo simulation system, which includes N M The system utilizes an extended interconnected computing matrix and a control computer. On one hand, by connecting the upper and lower levels of the extended interconnected computing matrix, between the extended interconnected computing matrix and the interconnected computing matrix, and between the computing units within the interconnected computing matrix, it can construct computing arrays of different topologies and sizes. The more array elements in the interconnected computing matrix and the more levels of the extended interconnection, the larger the scale of the computing matrix, the greater the total computing power and storage space, which can meet the needs of larger-scale radar echo simulation and adapt to different channel sizes and computational complexities. On the other hand, by designing the working methods of the control computer and the computing units in the matrix, it can realize large-scale parallel echo computing, achieving high-precision radar echo simulation across multiple channels. Furthermore, by designing decoupled computing units, signal transceiver units can be removed from echo simulation nodes that do not require RF signal transmission and reception, thereby reducing the overall cost. This can solve the problems of insufficient target echo simulation capability, insufficient environmental clutter simulation capability, insufficient channel and computing power expansion capability, and high overall system construction cost in existing radar echo simulation schemes, making it convenient for practical application and promotion.

[0118] (2) Flexible expansion and splitting: The computational topology designed in this embodiment is suitable for radar echo simulation systems with a few channels to hundreds of channels. It can easily expand a small-scale radar echo simulation system into a large-scale system, and can also easily split a large-scale system into several small-scale systems.

[0119] (3) High-precision radar echo simulation: The accuracy of the radar echo simulation system depends mainly on the number of grids used to divide the radar target and environmental objects. The more grids there are, the higher the accuracy of the simulation. The corresponding computing power, data throughput and storage capabilities of the computing system are also higher. The computing topology designed in this embodiment can flexibly expand the number of computing units, communication interfaces and storage units for each radar echo, thereby improving the ability of high-precision echo simulation.

[0120] (4) Low computational latency: The hardware circuit characteristics of FPGA itself have the characteristics of low computational latency. At the same time, the computational matrix topology designed in this embodiment makes data interaction between any two computational units only require a very short data exchange path. Therefore, the entire computational matrix has the advantage of low computational latency. This topology retains the low latency characteristics of low-order computational units when expanding step by step, and also has the characteristics of a significant increase in computing power of high-order computational units. This is exactly in line with the characteristics of low echo delay and small radar illumination area at near distance and large echo delay and large illumination area at far distance in radar clutter simulation.

[0121] (5) Low cost: Due to the standardization of computing units and interconnected computing matrices, the construction and expansion of large-scale radar echo simulation systems no longer need to be customized, thus achieving low cost;

[0122] (6) Easy to configure: Since the computational topology designed in this embodiment is a completely symmetrical structure, the algorithm and program design of the entire computational matrix can be completed by designing the algorithm and program for a single computational unit.

[0123] (7) Customizable: The signal transceiver unit provides extended computing capabilities, and the implementation of this computing power is completely decoupled from the computing matrix, so it is easy to provide customized signal processing capabilities for radar echo simulation port equipment.

[0124] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A flexibly configurable real-time high-precision radar echo simulation system, characterized in that, Including Meta-extended interconnect computing matrix and control computer, wherein, the The meta-extended interconnect computing matrix includes N M indivual Meta-extended interconnect computing matrix, the The meta-extended interconnect computing matrix includes N M-1 indivual Meta-extended interconnect computing matrix, and so on. The meta-extended interconnect computing matrix includes N M-m indivual Meta-extended interconnect computation matrix, until The meta-extended interconnect computing matrix comprises N² N1-ary interconnect computing matrices, and each N1-ary interconnect computing matrix includes N1 computing units. For N M ×N M-1 ×…×N M-m The abbreviation of ×…×N2×N1, N M N M-1 N M-m N2 and N1 represent integers greater than or equal to 2, M represents integers greater than or equal to 2, m exists when M is greater than or equal to 3, and represents an integer greater than or equal to 0 and less than M-2; Any two of the N1 computing units are communicatively connected; For each computational unit in any N1-ary interconnected computation matrix, the corresponding unit is communicatively connected to the computational unit in the corresponding position in N2-1 other N1-ary interconnected computation matrices, wherein the any N1-ary interconnected computation matrix and the N2-1 other N1-ary interconnected computation matrices constitute the... Meta-extended interconnect computation matrix; For any one Each of the computational units in the meta-extended interconnection computation matrix is ​​such that the corresponding unit is connected to N. M-m -1 other The computing units located at corresponding positions in the meta-extended interconnect computing matrix are communicatively connected, wherein any one of them Meta-extended interconnect computation matrix and the N M-m -1 other The meta-extended interconnect computing matrix constitutes the above. Meta-extended interconnect computation matrix; The control computer is respectively communicatively connected to the The controlled ends of each computing unit in the meta-extended interconnect computing matrix; When the computing unit has a signal receiving channel and is configured as a receiving computing unit, it is used to transmit the radar transmitted waveform signal received through the signal receiving channel to the computing unit. Each of the computing units configured as participating computing units in the meta-extended interconnect computing matrix; The control computer is used to calculate mesh parameters and transmit the calculated mesh parameters to the control computer. Each of the computing units configured as participating computing units in the meta-extended interconnect computing matrix; When configured as a participating calculation unit, the computing unit performs electromagnetic reflection calculation, vector synthesis calculation, and / or electromagnetic propagation calculation on all received radar transmitted waveform signals based on the received grid parameters, and transmits the calculated radar echo signal to the [unclear - likely a specific location or system]. The computing unit in the meta-extended interconnect computing matrix that has a signal transmission channel and is configured as a transmission computing unit; When the computing unit has a signal transmission channel and is configured as a transmission computing unit, it is used to perform vector synthesis on all the received radar echo signals to obtain the final radar echo signal, and then transmit it through the signal transmission channel.

2. The real-time high-precision radar echo simulation system as described in claim 1, characterized in that, The calculation of the grid parameters includes: Divide radar targets and / or environmental objects into multiple grids; For each of the multiple grids, multiple electromagnetic reflection parameters are calculated based on the corresponding electromagnetic wave incident angle, electromagnetic wave exit angle, and the geometry and surface characteristics of the object within the grid. These multiple electromagnetic reflection parameters include radar cross section, RCS fluctuation model parameters, backscattering coefficient, clutter distribution model parameters, and / or polarization scattering coefficient.

3. The real-time high-precision radar echo simulation system as described in claim 1, characterized in that, The calculated mesh parameters are transmitted to the... Each of the computing units configured as participating computing units in the meta-extended interconnect computing matrix includes: In the The computing unit in the meta-extended interconnect computing matrix that has a signal transmission channel and is configured as a transmission computing unit is the central computing unit, and is configured as follows: The meta-extended interconnect computing matrix is ​​decomposed layer by layer outward into multi-order computing resources: the computing resources within the central computing unit are classified as zero-order computing resources; the computing resources within all other computing units in the N1-meta-interconnect computing matrix containing the central computing unit are classified as first-order computing resources; and the computing resources within the N1-meta-interconnect computing matrix containing the central computing unit are classified as first-order computing resources. The computational resources within all other N1-ary interconnected computational matrices in the meta-extended interconnected computational matrix are classified as second-order computational resources, and so on, to determine Mm-order, M-1-order, and M-order computational resources. The calculated mesh parameters corresponding to the near-end mesh are transferred to the... In the meta-extended interconnect computing matrix, each computing unit is configured as a participating computing unit, and the computing resources within the unit are divided into low-order computing resources. The calculated mesh parameters corresponding to the remote mesh are then transmitted to the [unclear - likely a specific location or network]. The computational units configured as participating computational units in the meta-extended interconnected computational matrix, and whose computational resources are divided into high-order computational resources, are as follows: the near-end grid refers to the grid that is close to the radar in the radar echo simulation scenario, and the far-end grid refers to the grid that is far from the radar in the radar echo simulation scenario. Both the near-end grid and the far-end grid belong to multiple grids obtained by dividing the radar target and / or environmental objects. Both the low-order computational resources and the high-order computational resources belong to the multi-order computational resources.

4. The real-time high-precision radar echo simulation system as described in claim 3, characterized in that, When the computing resources within the computing unit are allocated as non-zero-order computing resources and configured as participating computing units, the calculated radar echo signal is transmitted to the computing unit. The computing unit in the meta-extended interconnect computing matrix, which has a signal transmission channel and is configured as a transmission computing unit, includes: If the local computing unit is directly connected to the first computing unit, then the radar echo signal calculated by the local computing unit and the radar echo signals calculated by all the second computing units are vector-synthesized to obtain a new radar echo signal. This new radar echo signal is then transmitted to the first computing unit. Otherwise, the radar echo signal calculated by the local computing unit is transmitted to the third computing unit, so that it can be transmitted back to the first computing unit via the third computing unit. The first computing unit refers to the... The computing unit in the N1-ary interconnect computing matrix that has a signal transmission channel and is configured as a transmission computing unit; the second computing unit refers to other computing units in the N1-ary interconnect computing matrix where the local computing unit is located that are configured as participating computing units and whose computing resources are of the same level as the computing resources in the local computing unit; the third computing unit refers to other computing units in the N1-ary interconnect computing matrix where the local computing unit is located that are directly connected to the first computing unit and whose computing resources are of the same level as the computing resources in the local computing unit.

5. The real-time high-precision radar echo simulation system as described in claim 1, characterized in that, The electromagnetic reflection calculation includes: Based on the received grid parameters and the attribute parameters of the radar transmitted waveform signal, electromagnetic reflection simulation of the radar transmitted waveform signal is performed according to the following formula: F r (t,n)=F t (t)·A(n)·σ(λ,n)·g(t,n)·f(θ,φ,pol) In the formula, n represents the grid number and is a positive integer, t represents time, and F r (t,n) represents the reflected electromagnetic wave from the nth grid, F t (t) represents the incident electromagnetic wave, A(n) represents the area of ​​the nth grid, σ(λ,n) represents the reference radar cross section or backscattering coefficient of the nth grid related to the shape and material properties of the radar target and the wavelength λ of the incident electromagnetic wave, g(t,n) represents the RCS fluctuation model or clutter distribution model of the nth grid, and f(θ,φ,pol) represents the influence function of the incident angle θ, reflection angle φ and polarization state pol on the radar cross section.

6. The real-time high-precision radar echo simulation system as described in claim 1, characterized in that, The vector synthesis calculation includes: Vector synthesis of reflected electromagnetic waves from adjacent grid groups containing at least two grids is performed according to the following formula: F r (t)=ΣΔ(F r (t,n'),n')·Φ(f,n') In the formula, t represents time, and F r (t) represents the vector synthesis result of the reflected electromagnetic waves of the adjacent grid group, n' represents the grid number in the adjacent grid group and is a positive integer, F r (t,n') represents the reflected electromagnetic wave of the n'th grid in the adjacent grid group, Δ(x,n') represents the time delay caused by the difference in radial distance between the n'th grid and the first grid in the adjacent grid group due to the direction of the radar receiving antenna, Φ(f,n') represents the Doppler frequency shift caused by the relative motion between the n'th grid and the first grid, and x represents the input variable of the function.

7. The real-time high-precision radar echo simulation system as described in claim 1, characterized in that, The electromagnetic propagation calculation includes: Electromagnetic propagation is performed on the vector synthesis result of the reflected electromagnetic waves from the grid group according to the following formula: In the formula, t represents time, and F a (t) represents the reflected electromagnetic wave received by the radar receiving antenna, F r (t) represents the vector synthesis result of the reflected electromagnetic waves of the grid group, G t G represents the gain of the radar transmitting antenna. r Let R represent the gain of the radar receiving antenna, H(x) represent the radial distance in the direction of the radar receiving antenna, H(x) represent the multipath effect response function, Δ(x,R) represent the time delay caused by the radial distance R in the direction of the radar receiving antenna, Φ(f) represent the Doppler frequency shift caused by the motion relative to the radar receiving antenna, and x represent the input variable of the function.

8. The real-time high-precision radar echo simulation system as described in claim 1, characterized in that, The computing unit is communicatively connected to K signal transceiver units, where K represents a positive integer. The signal transceiver units are used to provide the signal receiving channel and / or the signal transmitting channel.

9. The real-time high-precision radar echo simulation system as described in claim 8, characterized in that, When the signal transceiver unit includes a second FPGA module and a second storage module and a second high-speed serial interface respectively connected to the second FPGA module, the signal transceiver unit is also used as an extended computing unit relative to the computing unit, so as to share the computing tasks of the computing unit.

10. The real-time high-precision radar echo simulation system as described in claim 1, characterized in that, The computing unit includes a first FPGA module, a first storage module, and a first high-speed serial interface, wherein the number of the first high-speed serial interfaces is at least one and is used for communication connection to a signal transceiver unit or other computing units. The first FPGA module is communicatively connected to the first storage module and the first high-speed serial interface.

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