Page table data distribution method and device, equipment and medium

Abstract

The invention discloses a page table data distribution method and device, equipment and a medium. The page table data distribution method comprises the following steps: based on a test request of an MMU circuit, reading non-required parameter interface input data and required parameter interface input data; inputting data based on the non-necessary parameter interface, and creating a target page table tree; and managing an address allocation space of the target page table tree according to the necessary parameter interface input data and the double linked list structure, and allocating page table data to the address allocation space of the target page table tree while traversing the target page table tree. According to the technical scheme provided by the embodiment of the invention, the page table data generation efficiency can be improved, the data dependence of page table data distribution is broken, and the requirement of MMU IP level large-scale random testing can be met.

Description

Technical Field

[0001] The present invention relates to the technical field of memory management unit verification and simulation, and particularly to a page table data allocation method, device, equipment and medium. Background Art

[0002] In the verification of the MMU IP Level (Intellectual Property Core Level of the Memory Management Unit), page table data allocation is a key link in the verification process. The following problems exist in the actual project verification: 1) The process of randomizing page table data consumes a large amount of simulation time, and it is difficult to accurately match the page table type and quantity, which affects the final verification effect. 2) It is necessary to calculate the storage location of page table data through virtual addresses, which has strong data dependence. Summary of the Invention

[0003] The present invention provides a page table data allocation method, device, equipment and medium to solve the problems of strong data dependence and low efficiency of page table data generation existing in the existing page table data allocation, which cannot meet the requirements of large-scale random testing at the MMU IP level.

[0004] According to one aspect of the present invention, a page table data allocation method is provided, including:

[0005] Based on the test request of the MMU circuit, read the input data of the non-essential parameter interface and the input data of the essential parameter interface;

[0006] Based on the input data of the non-essential parameter interface, create a target page table tree;

[0007] According to the input data of the essential parameter interface and the double-linked list structure, manage the address allocation space of the target page table tree, and while traversing the target page table tree, allocate the address allocation space of the target page table tree and allocate page table data.

[0008] According to another aspect of the present invention, a page table data allocation device is provided, including:

[0009] A data acquisition module, configured to read the input data of the non-essential parameter interface and the input data of the essential parameter interface based on the test request of the MMU circuit;

[0010] A page table tree establishment module, configured to create a target page table tree based on the input data of the non-essential parameter interface;

[0011] A page table data allocation module, configured to manage the address allocation space of the target page table tree according to the input data of the essential parameter interface and the double-linked list structure, and while traversing the target page table tree, allocate the address allocation space of the target page table tree and allocate page table data.

[0012] According to another aspect of the present invention, there is provided an electronic device, which includes:

[0013] at least one processor; and

[0014] a memory communicatively connected to the at least one processor; wherein,

[0015] the memory stores a computer program executable by the at least one processor, and when the computer program is executed by the at least one processor, the at least one processor is enabled to execute the page table data allocation method according to any embodiment of the present invention.

[0016] According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the page table data allocation method according to any embodiment of the present invention when executed.

[0017] The technical solution of the embodiment of the present invention reads the input data of the non-essential parameter interface and the input data of the essential parameter interface through a test request based on the MMU circuit, thereby creates a target page table tree based on the input data of the non-essential parameter interface, and then manages the address allocation space of the target page table tree according to the input data of the essential parameter interface and the doubly linked list structure, and allocates page table data to the address allocation space of the target page table tree while traversing the target page table tree. This solution is applicable to the MMU circuit verification and simulation scenario, can obtain the input data of the non-essential parameter interface and the input data of the essential parameter interface flexibly configured by the user according to the test needs, automatically generates a target page table tree that meets the test requirements based on the input data of the non-essential parameter interface, and manages the address allocation space of the target page table tree through the doubly linked list structure, optimizing the memory allocation efficiency and avoiding fragmentation problems, realizing the optimized allocation of page table data, solving the problems of strong data dependence and low page table data generation efficiency in the existing page table data allocation, and being unable to meet the large-scale random test requirements of the MMU IP level, capable of improving the page table data generation efficiency, breaking the data dependence of page table data allocation, and meeting the large-scale random test requirements of the MMU IP level.

[0018] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0020] Figure 1 It is a flowchart of a page table data allocation method provided in Embodiment 1 of the present invention;

[0021] Figure 2 It is a flowchart of a page table data allocation method provided in Embodiment 2 of the present invention;

[0022] Figure 3 It is a schematic diagram of functional layering during page table data allocation provided in Embodiment 3 of the present invention;

[0023] Figure 4 It is a schematic diagram of the shape of a target page table tree provided in Embodiment 3 of the present invention;

[0024] Figure 5 It is a schematic diagram of the structure of a page table data allocation device provided in Embodiment 4 of the present invention;

[0025] Figure 6 It shows a schematic diagram of the structure of an electronic device that can be used to implement the embodiments of the present invention. Detailed implementation manners

[0026] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above accompanying drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily need to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0028] Example 1

[0029] Figure 1 As shown in the flowchart of a page table data allocation method provided in Example 1 of the present invention, this example is applicable to the situation of efficient data allocation for page table data. This method can be executed by a page table data allocation device, which can be implemented in the form of hardware and / or software, and the page table data allocation device can be configured in an electronic device. The electronic device can include, but is not limited to, a computer or a server, etc. As Figure 1 shown, the method includes:

[0030] Step 110: Read the input data of the non-essential parameter interface and the input data of the essential parameter interface based on the test request of the MMU circuit.

[0031] Among them, the input data of the non-essential parameter interface can be data describing the page table structure. Optionally, the page table structure can be a tree structure. The input data of the essential parameter interface can be data describing the physical address space mapping of the page table data.

[0032] In the embodiment of the present invention, when detecting the test request of the MMU circuit, the input data of the non-essential parameter interface in the non-essential data input interface can be read, as well as the input data of the essential parameter interface written by the user based on the essential data input interface.

[0033] Step 120: Create a target page table tree based on the input data of the non-essential parameter interface.

[0034] Among them, the target page table tree can be a tree structure generated based on the input data of the non-essential parameter interface.

[0035] In the embodiment of the present invention, the input data of the non-essential parameter interface read can be parsed to determine the randomness requirement for generating the page table tree, and a target page table tree can be created based on the randomness requirement. Among them, the randomness requirement includes, but is not limited to, the randomness of the page table tree shape and the randomness of the node storing the page table information, etc.

[0036] Optionally, a tree structure can be created based on the data parsing result of the input data of the non-essential parameter interface, and the page table information required to be stored in each node of the tree structure can be determined to obtain the target page table tree. Among them, the page table information includes, but is not limited to, the page table type, the number of page tables, and the address offset, etc.

[0037] Step 130: Manage the address allocation space of the target page table tree according to the input data of the essential parameter interface and the double-linked list structure, and while traversing the target page table tree, allocate page table data for the address allocation space of the target page table tree.

[0038] Among them, the address allocation space can be an address space specified by the user by inputting data through the mandatory parameter interface, and is used to record page table related data determined based on the page table information stored in the nodes of the target page table tree. The page table data can be page table related data written in the address allocation space.

[0039] In an embodiment of the present invention, the address allocation space can be parsed from the input data of the mandatory parameter interface, and the parsed address allocation space is managed through a doubly linked list structure. Furthermore, when traversing the target page table tree, according to the page table information stored in each node of the target page table tree, page table data is allocated to the address allocation space corresponding to the target page table tree.

[0040] By introducing a tree structure and a doubly linked list structure, this solution can decompose the complex operations in the traditional page table allocation method into two logically independent and easy-to-manage processes (generating the target page table tree and traversing the nodes of the page table tree to generate the page table data to be allocated, that is, performing function layering). This decomposition method has the following advantages: 1) Simplify logic: Split the complex page table allocation task into two clear steps, reducing the implementation complexity. Each process focuses on a single task, facilitating understanding and maintenance. 2) Improve efficiency: The generation process of the node information in the target page table tree can be completed in advance, reducing the computational overhead during real-time allocation. When traversing and allocating the page table data, it can quickly locate and allocate based on the pre-generated node information, improving the overall performance. 3) Enhance flexibility: The two processes are independent of each other and can be optimized or extended separately according to requirements. For example, the process of generating node information can support multiple page table structures, while the allocation process can adapt to different memory management strategies. 4) Facilitate debugging and testing: Each process can be tested separately, making it easier to locate and solve problems. The process of generating node information can generate intermediate results, facilitating the verification of its correctness. 5) Reduce resource occupancy: By pre-generating node information, the memory and computational resource consumption during real-time allocation can be reduced. It has been verified that when dealing with a 4-level page table structure and allocating more page table data, the simulation performance has increased by about 7 times.

[0041] The technical solution of the embodiment of the present invention reads the input data of the non-essential parameter interface and the input data of the essential parameter interface through a test request based on the MMU circuit, thereby creating a target page table tree based on the input data of the non-essential parameter interface, and then managing the address allocation space of the target page table tree according to the input data of the essential parameter interface and the doubly linked list structure, and while traversing the target page table tree, allocating the address allocation space of the target page table tree and allocating page table data. This solution is applicable to the MMU circuit verification and simulation scenario, can obtain the input data of the non-essential parameter interface and the input data of the essential parameter interface flexibly configured by the user according to the test needs, and automatically generate a target page table tree that meets the test requirements based on the input data of the non-essential parameter interface, and manages the address allocation space of the target page table tree through the doubly linked list structure, optimizing the memory allocation efficiency and avoiding the fragmentation problem, realizing the optimized allocation of page table data, solving the problems of strong data dependence and low page table data generation efficiency existing in the existing page table data allocation, and being unable to meet the large-scale random test requirements of the MMU IP level, being able to improve the page table data generation efficiency, break the data dependence of page table data allocation, and meet the large-scale random test requirements of the MMU IP level.

[0042] Embodiment 2

[0043] Figure 2 The flowchart of a page table data allocation method provided by the second embodiment of the present invention. This embodiment is specific based on the above embodiment, and gives a specific and optional implementation manner for creating a target page table tree based on the input data of the non-essential parameter interface. As Figure 2 shown, the method includes:

[0044] Step 210: Read the input data of the non-essential parameter interface and the input data of the essential parameter interface based on the test request of the MMU circuit.

[0045] Step 220: Create a target page table tree based on the input data of the non-essential parameter interface.

[0046] In an optional embodiment of the present invention, creating a target page table tree based on the input data of the non-essential parameter interface may include: when the first non-essential parameter interface input data in the input data of the non-essential parameter interface is not empty, creating a target page table tree with a fixed shape according to the first non-essential parameter interface input data; when both the first non-essential parameter interface input data and the second non-essential parameter interface input data in the input data of the non-essential parameter interface are empty, generating a completely random target page table tree; when the first non-essential parameter interface input data in the input data of the non-essential parameter interface is empty and the second non-essential parameter interface input data is not empty, generating a non-completely random target page table tree.

[0047] Among them, the input data of the first non-mandatory parameter interface can be used to describe the tree shape characteristics of the target page table tree. The input data of the second non-mandatory parameter interface can constrain the page table information stored in the nodes in the target page table tree. In a specific example, the input data of the second non-mandatory parameter interface can be that the depth of the page table tree is 2, there are only page table entries of the regular PTE type, and the total number does not exceed 200.

[0048] In the embodiments of the present invention, if the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is valid or specified, it indicates that the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is not empty. If the second non-mandatory parameter interface input data is not specified, it indicates that the second non-mandatory parameter interface input data is empty. If the second non-mandatory parameter interface input data is specified, it indicates that the second non-mandatory parameter interface input data is not empty. The logical rules for creating the target page table tree based on the non-mandatory parameter interface input data are as follows:

[0049] When the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is not empty, create a target page table tree with a fixed shape according to the non-mandatory parameter interface input data, that is, a target page table tree with a fixed node depth and the number of branches. At this time, the nodes in the target page table tree store random page table information.

[0050] When both the first non-mandatory parameter interface input data and the second non-mandatory parameter interface input data in the non-mandatory parameter interface input data are empty, generate a target page table tree with a randomly shaped tree and randomly stored page table information in the nodes, that is, a fully random target page table tree.

[0051] When the first non-mandatory parameter interface input data in the non-mandatory parameter interface input data is empty and the second non-mandatory parameter interface input data is not empty, generate a target page table tree with a randomly shaped tree but controllable page table information stored in the nodes in the target page table tree, that is, a non-fully random target page table tree.

[0052] Exemplarily, the logical rules for creating the target page table tree based on the non-mandatory parameter interface input data can be seen in Table 1:

[0053] Table 1 Creation Logic Rule Table of Target Page Table Tree

[0054] Step 230: Manage the address allocation space of the target page table tree according to the mandatory parameter interface input data and the doubly linked list structure, and while traversing the target page table tree, allocate the address allocation space for the target page table tree and allocate page table data.

[0055] In an alternative embodiment of the present invention, the address allocation space of the target page table tree may include a page table data storage address space and a page table data mapped physical address space; managing the address allocation space of the target page table tree according to the input data of the mandatory parameter interface and the doubly linked list structure may include: parsing the input data of the mandatory parameter interface to determine the page table data storage address space and the page table data mapped physical address space; managing the page table data storage address space based on the first doubly linked list structure, and managing the page table data mapped physical address space based on the second doubly linked list structure.

[0056] Among them, the page table data mapped physical address space may be the physical address space specified by the input data of the mandatory parameter interface. The page table data storage address space may be the address space other than the page table data mapped physical address space specified by the input data of the mandatory parameter interface. The page table data mapped physical address space and the page table data storage address space may be used to store page table data of different page table types. The first doubly linked list structure and the second doubly linked list structure are doubly linked list structures that respectively manage different address spaces.

[0057] In the embodiment of the present invention, the input data of the mandatory parameter interface may be parsed to obtain the address space specified by the user for storing page table data, that is, the page table data storage address space and the page table data mapped physical address space, and then the page table data storage address space may be managed through the first doubly linked list structure, and the page table data mapped physical address space may be managed through the second doubly linked list structure.

[0058] In an alternative embodiment of the present invention, allocating page table data to the address allocation space of the target page table tree may include: when the current page table entry in the target page table tree is traversed to be a page directory entry, determining the free space of the page table data storage address managed by the first doubly linked list structure; allocating page table data to the free space of the page table data storage address managed by the first doubly linked list structure.

[0059] Among them, the free space of the page table data storage address may be the unallocated space in the page table data storage address space.

[0060] In the embodiment of the present invention, when traversing the current page table entry stored in the node of the target page table tree, if the current page table entry is a page directory entry, the unallocated space in the page table data storage address space is determined based on the first doubly linked list structure, that is, the free space of the page table data storage address is obtained, and then the page table data corresponding to the current page table entry is allocated to the free space of the page table data storage address managed by the first doubly linked list structure.

[0061] In an alternative embodiment of the present invention, space is allocated for the address of the target page table tree, and page table data is allocated, which may include: when it is traversed that the current page table entry in the target page table tree is a page table entry, determining the free space of the physical address mapped by the page table data managed by the second doubly linked list structure; allocating the page table data to the free space of the physical address mapped by the page table data managed by the second doubly linked list structure.

[0062] Among them, the free space of the physical address mapped by the page table data may be the unallocated space in the physical address space mapped by the page table data.

[0063] In the embodiment of the present invention, when traversing the current page table entry stored in the node of the target page table tree, if the current page table entry is a page table entry, the unallocated space in the physical address space mapped by the page table data is determined based on the second doubly linked list structure, that is, the free space of the physical address mapped by the page table data is obtained, and then the page table data corresponding to the current page table entry is allocated to the free space of the physical address mapped by the page table data managed by the second doubly linked list structure.

[0064] It should be noted that as the depth of the page table hierarchy increases, the page table storage addresses and the number of physical pages to be allocated will increase significantly. The traditional page table data address allocation method is difficult to efficiently handle large-scale and frequent address allocation tasks, resulting in a significant extension of the simulation time. This is because the more address subspaces need to be allocated, the longer the constraint solving process is, and each random solving process will bring all the previously generated address spaces into the overall solution. The complexity of this algorithm is exponential and the efficiency is extremely low. This solution abstracts the entire memory space into a linked list structure, and all allocated and unallocated address spaces are associated by a doubly linked list. Through the doubly linked list, the available spaces adjacent before and after can be quickly found, and addresses can be directly allocated within the available spaces. The operation complexity implemented by the doubly linked list structure is O(n), where n is the number of address spaces already stored in the linked list, that is, the complexity of the doubly linked list structure increases linearly, and the address allocation efficiency can be significantly improved compared with the prior art. Among them, the unallocated address spaces can form an independent chain to ensure fast allocation and insertion of new address spaces. Multiple levels of sub-address spaces can be further allocated within the same address space, which is convenient for finer-grained memory segmentation and management, and effectively addresses the fragmentation problem. The use of the doubly linked list further optimizes the memory allocation efficiency and avoids the fragmentation problem.

[0065] Step 240, obtain a page table tree refill instruction.

[0066] Among them, the page table tree refill instruction can be an instruction for updating the page table information stored in the nodes of the target page table tree. The page table tree refill instruction can include at least one of a specific level refill instruction, a specific branch refill instruction, and a specific node refill instruction. The specific level refill instruction can be an instruction for refilling the node information at a specified level in the target page table tree. The specific branch refill instruction can be an instruction for refilling the node information in a specified branch of the target page table tree. The specific node refill instruction can be an instruction for filling the node information of a specified node in the target page table tree. Assuming that the specific branch refill instruction is to fill in empty data, it is equivalent to pruning the target page table tree. When the specific node refill instruction is to fill in empty data, it is equivalent to removing the node in the target node tree.

[0067] In an embodiment of the present invention, a page table tree refill instruction that needs to be written by a user based on the simulation verification of the MMU circuit can be obtained, and the node information can be quickly updated when the page table level changes dynamically, and the allocation process can be efficiently allocated based on the latest information.

[0068] Step 250: Determine the nodes with data to be updated in the target page table tree that has completed page table data allocation according to the page table tree refill instruction, and re-allocate page table data to the nodes with data to be updated.

[0069] Among them, the nodes with data to be updated can be the nodes in the target page table tree where the page table data is updated based on the page table tree refill instruction.

[0070] In an embodiment of the present invention, the page table tree refill instruction can be parsed to determine the nodes with data to be updated in the target page table tree that needs to update the page table data, so as to allocate new page table data to the nodes with data to be updated in the target page table tree that has completed page table data allocation.

[0071] In an optional embodiment of the present invention, after allocating space for the address of the target page table tree and allocating page table data, it may include: converting the target page table tree that has completed page table data allocation into a data format in JSON format to obtain simulation analysis associated data; wherein, at least two child nodes branch out backward from the root node in the target page table tree, and at least two child nodes branch out backward from the non-leaf nodes in the target page table tree.

[0072] Among them, the simulation analysis associated data can be text data in JSON format converted from the data stream corresponding to the target page table tree. The JSON (JavaScript Object Notation) format is a lightweight data exchange format.

[0073] In an embodiment of the present invention, the target page table tree with allocated page table data can be converted into the JSON format to obtain simulation analysis correlation data, which is convenient for reuse and verification between different levels, such as quickly exchanging address configuration information between the SOC Level (system-on-chip level) and the IP Level.

[0074] The technical solution of the embodiment of the present invention reads the input data of the non-essential parameter interface and the input data of the essential parameter interface through a test request based on the memory management unit (MMU) circuit, thereby creating a target page table tree based on the input data of the non-essential parameter interface, and then managing the address allocation space of the target page table tree according to the input data of the essential parameter interface and the doubly linked list structure. While traversing the target page table tree, page table data is allocated to the address allocation space of the target page table tree. After obtaining the page table tree re-population instruction, the data nodes to be updated of the target page table tree with allocated page table data are determined according to the page table tree re-population instruction, and page table data is re-allocated to the data nodes to be updated. This solution is applicable to the MMU circuit verification and simulation scenario, can obtain the input data of the non-essential parameter interface and the input data of the essential parameter interface flexibly configured by the user according to the test needs, automatically generate a target page table tree that meets the test requirements based on the input data of the non-essential parameter interface, and manage the address allocation space of the target page table tree through the doubly linked list structure, optimizing the memory allocation efficiency and avoiding fragmentation problems, realizing the optimized allocation of page table data, solving the problems of strong data dependence and low page table data generation efficiency in the existing page table data allocation, which cannot meet the large-scale random test requirements of the MMU IP level, improving the page table data generation efficiency, breaking the data dependence of page table data allocation, and meeting the large-scale random test requirements of the MMU IP level.

[0075] Embodiment Three

[0076] An optional embodiment of a page table data allocation method is provided in Embodiment Three of the present invention, and its specific implementation can be referred to the following embodiments. Among them, the same or corresponding technical terms as those in the above embodiments will not be elaborated here.

[0077] Figure 3 It is a schematic diagram of functional layering during page table data allocation provided in Embodiment Three of the present invention. The page table data allocation method can be configured in an application programming interface, such as Figure 3As shown in the figure, the application programming interface can be specifically divided into a node layer and a data layer. The node layer is used to generate the required page table tree structure, and each branch and leaf node in the tree structure stores the corresponding page table information. The data layer is used to traverse the nodes of the target page table tree and generate specific page table data based on the page table information. The node layer includes a page table tree component and a page table node solver. The data layer includes a page table allocator, a first page table storage area, and a second page table storage area. The main purpose of implementing the hierarchical structure in this solution is to decouple functions, make it more modular, and make the production and storage of data streams clearer and more efficient, facilitating future maintenance and function expansion. The page table tree component is used to generate the page table tree structure. The page table node solver is used to parse the constraints (the input data of the second non-required parameter interface) and generate page table nodes. The page table allocator is used to dynamically allocate page table data. The first page table storage area is used to manage the storage of page table data corresponding to the page table directory. The second page table storage area is used to manage the storage of page table data corresponding to the page table entries.

[0078] The foregoing application programming interface provides three configuration interfaces to the user (an optional page table tree node configuration interface, an optional page table node constraint configuration interface, and a physical address space mapping configuration interface; the optional page table tree node configuration interface is used to receive the input data of the first non-required parameter interface; the optional page table node constraint configuration interface is used to receive the input data of the second non-required parameter interface; the physical address space mapping configuration interface is used to receive the input data of the required parameter interface), which are used to control the current page table generation method.

[0079] Figure 4 This is a schematic diagram of the shape of a target page table tree provided in Embodiment 3 of the present invention. As Figure 4 shown, starting from the root node, each branch generated backward by the root node horizontally represents a group of independent physical processes pid (mapped to software system virtual processes). Vertically, the depth of the tree structure (the length of the branch) is 4, indicating that it can be divided into a maximum of 4-level page table structures. Among them, pid_0 represents the physical process numbered 0, and pid_1 represents the physical process numbered 1.

[0080] Exemplarily, the size of a single page table data is 8 Byte, and it is stored in the memory unit in a manner aligned with 8 Byte. The storage location of each page table data is mapped to each sub-node of the tree structure. Taking a virtual address with a 48-bit width as an example, the virtual page number is fixed at 9 bit, Figure 4 and the target page table tree shown can represent a maximum of 512 storage locations.

[0081] Figure 4Each square in it represents a node, and each node can store 512 page table entries (PDE or PTE, with the maximum addressable virtual page number per level up to 512). The node depth is 4 levels, corresponding to a four-level page table structure: L0 node → L1 node → L2 node → L3 node. The root node can fork out up to 16 L0 nodes backward, corresponding to 16 physical threads PID in the system. L0 / L1 / L2 / L3 nodes can each fork out up to 512 child nodes backward. Therefore, the maximum number of valid storage locations that can be represented in the entire page table tree is 16 x 512 x 512 x 512 x 512.

[0082] In each simulation, the depth of the nodes in the target page table tree, the types of page table entries (PDE or PTE) stored in the leaf nodes at each level, and the number of page tables are all randomly generated. This randomness aims to maximize the diversity of the combination relationship between page table storage locations and the types and quantities of page tables, so as to cover a wider verification space and improve the test coverage rate.

[0083] The target page table tree generated by the node layer is directly input into the data layer as a data stream. At the same time, the application interface will also print the generated data stream to a text file and record it in the general JSON format for subsequent simulation data analysis. The data stream completely records the page table information on each node. For example, the second-level page table node is marked with 1 PDE, 131 Norm PTEs, and 32 Frag PTEs, and their respective storage locations are identified by the address offset array.

[0084] The input data of the mandatory parameter interface acts on the data layer and will affect the final physical page allocation. The input data of the mandatory parameter interface specifies the actual physical address space mapping relationship.

[0085] The page table tree data stream clearly indicates the page table hierarchy relationship, various page table types, and quantities. The data layer will parse this data stream and traverse all branches and nodes in the page table tree using a depth-first algorithm (that is, explore a branch as deeply as possible until it can no longer continue, and then backtrack and explore other branches). Such a traversal rule is designed to ensure that the cascading relationship between page tables is not damaged and at the same time recursively traverse all nodes completely.

[0086] During the process of traversing the entire page table tree, the application interface will dynamically allocate the final page table data according to the current page table information. First, it is to determine the storage address of each page table entry. The page table allocator will apply for an available address from the address allocation space, and then write the content of the page table data at this address (that is, fill the physical page address applied for into the page table data field).

[0087] For example, when traversing to the third-level page table and the current page table entry is a PDE (page directory entry), the page table allocator will look for the reserved third-level page table storage space in the page table region specified by the address allocation space and check if there is a free area available for allocation. If a free space is found, the system will allocate the corresponding storage address for it; similarly, when traversing to a page table entry that is a PTE (page table entry), the page table allocator will allocate a physical page for it from the physical address region (pa region) specified by the address allocation space.

[0088] Typical application scenarios of the page table data allocation method specifically include:

[0089] 1) In large-scale random testing, the system needs to generate various page table types and their combinations to cover a wide range of verification scenarios. Through the application programming interface provided by the solution, the user can specify or not specify the input data of the first non-required parameter interface and the input data of the second non-required parameter interface to generate a random page table tree structure. Each node in the page table tree can randomly generate different types of page table entries (such as PDE, PTE, etc.), and the number and storage location of the page table entries are also randomly allocated. This randomness ensures the diversity of the test, can cover more page table combinations and boundary cases, thereby improving the verification coverage. The application programming interface in this solution supports the generation of fully random, randomly controllable, and fixed-shape page table trees, and the user can flexibly select the generation method according to the test requirements. The generated page table data will be recorded in JSON format for subsequent analysis and debugging.

[0090] 2) In fixed stimulus testing, the user usually needs to generate a specific page table structure to verify certain specific functions or scenarios. By specifying the input data of the first non-required parameter interface, the user can generate a fixed-shape page table tree to ensure that the same page table structure is used in each simulation. The application programming interface will generate the corresponding page table data according to the tree structure specified by the user and ensure that the type, number, and storage location of the page table entries meet the expectations. The application programming interface supports the user to customize the page table tree structure to ensure that the generated page table data is consistent with the expectations. By optimizing the multi-level page table allocation algorithm, complex page table structures can be generated quickly, significantly improving the simulation performance.

[0091] 3) In page switching testing, the system needs to handle scenarios such as page faults or context switches. When a page fault occurs, the system may need to refill the page table data at a specific level. Through the aforementioned application programming interface, the user can dynamically generate new page table data and accurately replace the page table data stored in the original page table position without destroying the original data storage structure, supporting the dynamic generation of page table data multiple times during the simulation to ensure flexibility and efficiency during page switching, that is, supporting dynamic overwriting or replacement of the original page table data to ensure quick response during page faults or context switches.

[0092] 4) In the cross-verification between the SOC Level and the IP Level, it is necessary to generate and reuse page table data to ensure the consistency of verification at different levels. Through the aforementioned application programming interface, users can conveniently describe or specify the page table structure and quickly exchange address configuration information between the SOC Level and the IP Level. The page table data generated by the aforementioned application programming interface can be recorded in a general format (such as JSON), which is convenient for reuse and verification between different levels, supports a unified system address space allocation method, and ensures the consistency of page table data between the SOC Level and the IP Level. Through the tree structure and the doubly linked list allocation algorithm, a complex page table structure can be quickly generated, significantly improving the efficiency of cross-verification.

[0093] Embodiment 4

[0094] Figure 5 It is a schematic structural diagram of a page table data allocation device provided in Embodiment 4 of the present invention. As Figure 5 shown, the device includes:

[0095] A data acquisition module 310, configured to read the input data of the non-essential parameter interface and the input data of the essential parameter interface based on the test request of the MMU circuit;

[0096] A page table tree establishment module 320, configured to create a target page table tree based on the input data of the non-essential parameter interface;

[0097] A page table data allocation module 330, configured to manage the address allocation space of the target page table tree according to the input data of the essential parameter interface and the doubly linked list structure, and allocate page table data to the address allocation space of the target page table tree while traversing the target page table tree.

[0098] The technical solution of the embodiment of the present invention reads the input data of the non-essential parameter interface and the input data of the essential parameter interface through a test request based on the MMU circuit, thereby creating a target page table tree based on the input data of the non-essential parameter interface, and then managing the address allocation space of the target page table tree according to the input data of the essential parameter interface and the double-linked list structure, and while traversing the target page table tree, allocating the address allocation space of the target page table tree and allocating page table data. This solution is applicable to the MMU circuit verification and simulation scenario, and can obtain the input data of the non-essential parameter interface and the input data of the essential parameter interface flexibly configured by the user according to the test needs, and automatically generate a target page table tree that meets the test requirements based on the input data of the non-essential parameter interface, and manage the address allocation space of the target page table tree through the double-linked list structure, optimizing the memory allocation efficiency and avoiding fragmentation problems, realizing the optimized allocation of page table data, solving the problems of strong data dependence and low generation efficiency of existing page table data allocation, and being unable to meet the large-scale random test requirements of the MMU IP level, being able to improve the generation efficiency of page table data, breaking the data dependence of page table data allocation, and meeting the large-scale random test requirements of the MMU IP level.

[0099] Optionally, the page table tree establishment module 320 is specifically configured to create a target page table tree with a fixed shape according to the first non-essential parameter interface input data when the first non-essential parameter interface input data in the non-essential parameter interface input data is not empty; generate a fully random target page table tree when both the first non-essential parameter interface input data and the second non-essential parameter interface input data in the non-essential parameter interface input data are empty; and generate a non-fully random target page table tree when the first non-essential parameter interface input data in the non-essential parameter interface input data is empty and the second non-essential parameter interface input data is not empty.

[0100] Optionally, the address allocation space of the target page table tree includes a page table data storage address space and a page table data mapped physical address space; the page table data allocation module 330 includes an address space management unit and a page table data allocation unit. The address space management unit is configured to parse the input data of the essential parameter interface to determine the page table data storage address space and the page table data mapped physical address space; manage the page table data storage address space based on the first double-linked list structure, and manage the page table data mapped physical address space based on the second double-linked list structure.

[0101] Optionally, the address space management unit is configured to determine the free space of the page table data storage address managed by the first double-linked list structure when the current page table entry in the target page table tree being traversed is a page directory entry; and allocate the page table data to the free space of the page table data storage address managed by the first double-linked list structure.

[0102] Optionally, a page table data allocation unit is configured to determine the free space of the physical address mapped by the page table data managed by the second doubly linked list structure when traversing that the current page table entry in the target page table tree is a page table entry; and allocate the page table data to the free space of the physical address mapped by the page table data managed by the second doubly linked list structure.

[0103] Optionally, the page table data allocation device further includes a data format conversion module, configured to convert the target page table tree for which the page table data allocation is completed into a data format in JSON format to obtain simulation analysis correlation data; wherein at least two child nodes branch out backward from the root node in the target page table tree, and at least two child nodes branch out backward from a non-leaf node in the target page table tree.

[0104] Optionally, the page table data allocation device further includes a page table data update module, configured to obtain a page table tree re-population instruction; wherein the page table tree re-population instruction includes at least one of a specific level re-population instruction, a specific branch re-population instruction, and a specific node re-population instruction; determine the data nodes to be updated in the target page table tree for which the page table data allocation is completed according to the page table tree re-population instruction, and re-allocate the page table data to the data nodes to be updated.

[0105] The page table data allocation device provided by the embodiments of the present invention can execute the page table data allocation method provided by any embodiment of the present invention, and has corresponding functional modules and beneficial effects for executing the method.

[0106] Embodiment 5

[0107] Figure 6 The structural schematic diagram of an electronic device that can be used to implement the embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The components shown herein, their connections and relationships, and their functions are only for illustration, and are not intended to limit the implementation of the present invention described herein and / or claimed.

[0108] As Figure 6As shown, the electronic device 10 includes at least one processor 11 and a memory communicatively connected to the at least one processor 11, such as ROM 12, RAM 13, etc. Among them, the memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the ROM 12 or the computer program loaded from the storage unit 18 into the RAM 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, ROM 12, and RAM 13 are connected to each other through a bus 14. The I / O interface 15 is also connected to the bus 14. The ROM 12 is a read-only memory, the RAM 13 is a random access memory, and the I / O interface 15 is an input / output interface.

[0109] Multiple components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disc, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0110] The processor 11 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the page table data allocation method.

[0111] In some embodiments, the page table data allocation method can be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the page table data allocation method described above can be executed. Alternatively, in other embodiments, the processor 11 can be configured to execute the page table data allocation method in any other appropriate manner (e.g., by means of firmware).

[0112] The various embodiments of the systems and techniques described above in this specification can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems-on-chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from, and transmits data and instructions to, a storage system, at least one input device, and at least one output device.

[0113] The computer programs for implementing the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The computer programs can be executed entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

[0114] In the context of the present invention, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0115] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the electronic device. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0116] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), blockchain network, and the Internet.

[0117] The computing system can include a client and a server. The client and the server are generally far from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system and solves the defects of traditional physical hosts and VPS servers, such as high management difficulty and weak business scalability.

[0118] The embodiments of the present application also disclose a computer program product, which includes a computer program that, when executed by a processor, implements the page table data allocation method provided in any embodiment of the present application. This program product and the page table data allocation methods disclosed in the embodiments of the present application belong to the same inventive concept, and thus will not be elaborated herein.

[0119] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0120] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A page table data allocation method, characterized in that, Including: Based on a test request of a memory management unit (MMU) circuit, reading input data of a non-required parameter interface and input data of a required parameter interface; Based on the input data of the non-required parameter interface, creating a target page table tree; According to the input data of the required parameter interface and a doubly linked list structure, managing the address allocation space of the target page table tree, and while traversing the target page table tree, allocating the address allocation space of the target page table tree and allocating page table data.

2. The method according to claim 1, characterized in that, Based on the input data of the non-required parameter interface, creating a target page table tree, including: When the first non-required parameter interface input data in the input data of the non-required parameter interface is not empty, creating a target page table tree with a fixed shape according to the first non-required parameter interface input data; When both the first non-required parameter interface input data and the second non-required parameter interface input data in the input data of the non-required parameter interface are empty, generating a completely random target page table tree; When the first non-required parameter interface input data in the input data of the non-required parameter interface is empty and the second non-required parameter interface input data is not empty, generating a non-completely random target page table tree.

3. The method according to claim 1, characterized in that, The address allocation space of the target page table tree includes a page table data storage address space and a page table data mapped physical address space; According to the input data of the required parameter interface and a doubly linked list structure, managing the address allocation space of the target page table tree, including: Parsing the input data of the required parameter interface to determine the page table data storage address space and the page table data mapped physical address space; Managing the page table data storage address space based on a first doubly linked list structure and managing the page table data mapped physical address space based on a second doubly linked list structure.

4. The method according to claim 3, characterized in that, Allocating page table data to the address allocation space of the target page table tree, including: When the current page table entry in the target page table tree being traversed is a page directory entry, determining the free space of the page table data storage address managed by the first doubly linked list structure; Allocating the page table data to the free space of the page table data storage address managed by the first doubly linked list structure.

5. The method according to claim 3, wherein Allocating page table data to the address allocation space of the target page table tree, including: When the current page table entry in the target page table tree being traversed is a page table entry, determining the free space of the page table data mapped physical address managed by the second doubly linked list structure; Allocating the page table data to the free space of the page table data mapped physical address managed by the second doubly linked list structure.

6. The method according to claim 1, wherein After allocating page table data to the address allocation space of the target page table tree, including: Converting the target page table tree with completed page table data allocation into a data format in JSON format to obtain simulation analysis associated data; Wherein, at least two child nodes branch out backward from the root node in the target page table tree, and at least two child nodes branch out backward from the non-leaf nodes in the target page table tree.

7. The method according to claim 1, wherein After allocating page table data to the address allocation space of the target page table tree, it further includes: Obtain a page table tree repopulation instruction; wherein, the page table tree repopulation instruction includes at least one of a specific level repopulation instruction, a specific branch repopulation instruction, and a specific node repopulation instruction; According to the page table tree repopulation instruction, determine the data to be updated nodes of the target page table tree that has completed page table data allocation, and reallocate page table data to the data to be updated nodes.

8. A page table data allocation device, characterized in that, Includes: A data acquisition module, configured to read non-required parameter interface input data and required parameter interface input data based on a test request of an MMU circuit; A page table tree establishment module, configured to create a target page table tree based on the non-required parameter interface input data; A page table data allocation module, configured to manage the address allocation space of the target page table tree according to the required parameter interface input data and a doubly linked list structure, and while traversing the target page table tree, allocate page table data to the address allocation space of the target page table tree.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the page table data allocation method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions, and the computer instructions are used to implement the page table data allocation method according to any one of claims 1-7 when executed by a processor.

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