Chip and replaceable accessory

Abstract

The invention provides a chip and a replaceable accessory, and the chip comprises a connecting part, and the connecting part comprises a first contact part which is electrically connected with a first port of host equipment and receives a first signal outputted by the first port of the host equipment; the second contact part is used for being electrically connected with a second port of the host equipment and receiving a second signal output by the second port of the host equipment; and the leading-out part is electrically connected with the first contact part and the second contact part respectively, and the leading-out part is used for outputting a superposed signal of the first signal and the second signal and controlling a function module in the chip to realize a function matched with the first signal and the second signal through the superposed signal. In the embodiment of the invention, the voltage drop on the power supply signal transmission path can be reduced by reducing the voltage division proportion of the resistor on the power supply signal transmission path, and the function module can obtain more stable power supply, so that the stability and the reliability of the chip are improved.

Description

[0001] This application claims priority to the following Chinese patent applications, the entire contents of which are incorporated herein by reference.

[0002] 1. Application date: May 7, 2024; Application number: 202410558529.9; Application title: A consumable chip and a consumable cartridge; 2. Application date: May 15, 2024; Application number: 202410607700.0; Application title: A consumable chip and a consumable cartridge; 3. Application date: June 12, 2024; Application number: 202410756520.9; Application title: A consumable chip and a consumable cartridge. Technical Field

[0003] This application relates to the field of electronic technology, and particularly to a chip and a replaceable accessory. Background Art

[0004] In order to enrich the features of a host device, the host device often uses some peripheral replaceable accessories. When a replaceable accessory is used on a host device, the host device often needs to authenticate the source of the replaceable accessory. On the replaceable accessory, there is often a chip for identity authentication, and authentication information is stored in the chip. In addition, information such as the usage history or service life of the replaceable accessory is also stored in the chip. The host device can be a device such as an image forming apparatus, a mobile terminal, a computer, etc., and correspondingly, the replaceable accessory can be a consumable cartridge, a headset, a battery, a peripheral device, etc., which are modules containing a chip.

[0005] On the host device and the chip, corresponding communication ports are respectively configured. Specifically, the communication ports may include a data port, a chip select port, a clock port, a power port, and a ground port. When the replaceable accessory is installed on the host device, the data port, chip select port, clock port, power port, and ground port on the host device are respectively electrically connected to the data port, chip select port, clock port, power port, and ground port on the chip, so as to realize the transmission of data signals, chip select signals, clock signals, power signals, and ground signals.

[0006] In some application scenarios, the current output through the power port of the host device may not be able to drive the chip, which may cause abnormalities in the host device. To address this problem, one implementation solution in related technologies is as follows: In addition to being electrically connected to the power port of the host device, the power port of the chip is also electrically connected to other ports of the host device. Specifically, a connection part is provided on the chip, and the connection part is used to connect multiple communication ports including the power port in the host device at the same time, and a certain point of the connection part (for the sake of description, referred to as the "lead-out part") is electrically connected to the power port of the chip. It can be understood that through the above connection method, multiple communication ports including the power port in the host device can supply power to the power port of the chip, and thus the current input to the power port of the chip can be increased.

[0007] However, if the position of the lead-out part in the connection part is set unreasonably, it may increase the voltage division ratio of the resistance on the power signal transmission path in the connection part, and further increase the voltage drop on the power signal transmission path, affecting the stability and reliability of the chip.

[0008] It should be noted that the information disclosed in the background art part of this application is only intended to deepen the understanding of the general background art of this application, and should not be regarded as an admission or any form of implication that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0009] This application provides a chip and a replaceable accessory to facilitate solving the problem in the prior art that if the position of the lead-out part in the connection part is set unreasonably, it may increase the voltage division ratio of the resistance on the power signal transmission path in the connection part, and further increase the voltage drop on the power signal transmission path, affecting the stability and reliability of the chip.

[0010] In a first aspect, an embodiment of this application provides a chip for communicating and connecting with a host device. The chip includes a connection part, and the connection part includes: A first contact part for electrically connecting with the first port of the host device and receiving a first signal output from the first port of the host device, where the first signal is a power signal; A second contact part for electrically connecting with the second port of the host device and receiving a second signal output from the second port of the host device, where the second signal is a non-power signal; A lead-out part electrically connected to the first contact part and the second contact part respectively. The lead-out part is used to output a superimposed signal of the first signal and the second signal, and control a functional module in the chip through the superimposed signal to implement a function matching the first signal and the second signal; Wherein, the equivalent resistance between the first contact part and the lead-out part is less than the equivalent resistance between the second contact part and the lead-out part.

[0011] In a possible implementation, the connecting portion includes: A conductive region, wherein the first contact portion, the second contact portion, and the lead-out portion are located in the conductive region, and the distance between the first contact portion and the lead-out portion is less than the distance between the second contact portion and the lead-out portion.

[0012] In a possible implementation, the conductive region includes: A first conductive sub-region, wherein the first contact portion and the second contact portion are located in the first conductive sub-region; A second conductive sub-region, wherein the lead-out portion is located in the second conductive sub-region; wherein, the resistivity of the first conductive sub-region is less than the resistivity of the second conductive sub-region.

[0013] In a possible implementation, the first conductive sub-region includes: A third conductive sub-region, wherein the first contact portion is located in the third conductive sub-region; A fourth conductive sub-region, wherein the second contact portion is located in the fourth conductive sub-region; wherein, the resistivity of the third conductive sub-region and the resistivity of the fourth conductive sub-region are the same or different.

[0014] In a possible implementation, the resistivity of the first contact portion and / or the second contact portion is less than the resistivity of the conductive region.

[0015] In a possible implementation, the connecting portion includes: A first conductive path, wherein the first contact portion is electrically connected to the lead-out portion through the first conductive path; A second conductive path, wherein the second contact portion is electrically connected to the lead-out portion through the second conductive path; wherein, the length of the first conductive path is less than the length of the second conductive path, and / or the resistivity of the first conductive path is less than the resistivity of the second conductive path.

[0016] In a possible implementation, the connecting portion further includes: An insulating region, which is disposed around the first conductive path and the second conductive path, and the color and / or texture of the insulating region match those of the first conductive path and the second conductive path.

[0017] In a possible implementation, the second signal is a chip select signal, a clock signal, or a data signal.

[0018] In a possible implementation, the connection part and the functional module are arranged on the same layer of the chip, and the connection part is electrically connected to the functional module through a wire.

[0019] In a possible implementation, the connection part and the functional module are arranged on different layers of the chip, and the connection part is electrically connected to the functional module through a via hole.

[0020] In a second aspect, an embodiment of the present application provides a chip for communicating and connecting with a host device. The chip includes: a connection part, and the connection part includes: A first contact part for electrically connecting to a first port of the host device and receiving a first signal output by the first port of the host device, where the first signal is a power signal; A second contact part for electrically connecting to a second port of the host device and receiving a second signal output by the second port of the host device, where the second signal is a non-power signal; A lead-out part electrically connected to the first contact part and the second contact part respectively. The lead-out part is used for outputting a superimposed signal of the first signal and the second signal, and controlling a functional module in the chip through the superimposed signal to implement a function matching the first signal and the second signal; Wherein, when the first signal is at a high level and the second signal is at a low level, the voltage of the superimposed signal is greater than or equal to the minimum operating voltage of the functional module.

[0021] In a possible implementation, the chip further includes: An analysis circuit, an input end of the analysis circuit is electrically connected to the lead-out part. The analysis circuit is used for analyzing the superimposed signal, and outputting a first analysis signal at a first output end of the analysis circuit and outputting a second analysis signal at a second output end of the analysis circuit; A first port of the functional module is electrically connected to the first output end of the analysis circuit. The first port of the functional module is used for receiving the first analysis signal output by the first output end of the analysis circuit, and implementing a function matching the first signal through the first analysis signal; A second port of the functional module is electrically connected to the second output end of the analysis circuit. The second port of the functional module is used for receiving the second analysis signal output by the second output end of the analysis circuit, and implementing a function matching the second signal through the second analysis signal; In a possible implementation, the input end of the analysis circuit is electrically connected to the first output end of the analysis circuit, and the first analysis signal output by the first output end of the analysis circuit is the superimposed signal; The parsing circuit includes a comparison circuit. The input end of the comparison circuit is electrically connected to the lead-out part, and the output end of the comparison circuit is electrically connected to the second port of the functional module. The input end of the comparison circuit is used to receive the superimposed signal, and the output end of the comparison circuit is used to output the second parsing signal. The input end of the comparison circuit is the input end of the parsing circuit, and the output end of the comparison circuit is the second output end of the parsing circuit; Wherein, when the first signal is at a high level and the second signal is at a low level, the second parsing signal is at a low level; when the first signal is at a high level and the second signal is at a high level, the second parsing signal is at a high level.

[0022] In a possible implementation manner, the comparison circuit includes: A voltage output unit, the output end of the voltage output unit is used to output a first target voltage; when the first signal is at a high level and the second signal is at a low level, the voltage of the superimposed signal is less than the first target voltage; when the first signal is at a high level and the second signal is at a high level, the voltage of the superimposed signal is greater than the first target voltage; A switch unit, the first end of the switch unit is electrically connected to the lead-out part, the second end of the switch unit is electrically connected to the second port of the functional module, the control end of the switch unit is electrically connected to the output end of the voltage output unit, the first end of the switch unit is the input end of the comparison circuit, and the second end of the switch unit is the output end of the comparison circuit; A resistive device, the first end of the resistive device is electrically connected to the second end of the switch unit, and the second end of the resistive device is connected to a first reference voltage; Wherein, when the voltage at the first end of the switch unit is less than or equal to the voltage at the control end of the switch unit, the switch unit is turned off, and the second end of the switch unit outputs a low level; when the voltage at the first end of the switch unit is greater than the voltage at the control end of the switch unit, the switch unit is turned on, and the second end of the switch unit outputs a high level.

[0023] In a possible implementation manner, the voltage output unit includes: A unidirectional conduction device, the first end of the unidirectional conduction device is electrically connected to the lead-out part, and the first end of the unidirectional conduction device conducts unidirectionally from the first end to the second end; A capacitive device, the first end of the capacitive device is electrically connected to the second end of the unidirectional conduction device, the second end of the capacitive device is connected to a second reference voltage. When the capacitive device is fully charged, the first end of the capacitive device outputs the first target voltage, and the first end of the capacitive device is the output end of the voltage output unit.

[0024] In a possible implementation, the switch unit includes: A first transistor, a first end of the first transistor is electrically connected to the lead-out portion, a second end of the first transistor is electrically connected to a second port of the functional module, a control end of the first transistor is electrically connected to a node between the unidirectional conduction device and the capacitive device, and the first end, the second end, and the control end of the first transistor are respectively a first end, a second end, and a control end of the switch unit; Wherein, when a voltage of the first end of the first transistor is less than a voltage of the control end of the first transistor, the first transistor is turned off; when the voltage of the first end of the first transistor is greater than the voltage of the control end of the first transistor, the first transistor is turned on.

[0025] In a possible implementation, the switch unit includes: A second transistor, a first end of the second transistor is electrically connected to the lead-out portion, a control end of the second transistor is electrically connected to the node between the unidirectional conduction device and the capacitive device, the first end of the second transistor is a first end of the switch unit, and the control end of the second transistor is a control end of the switch unit; wherein, when a voltage of the first end of the second transistor is less than a voltage of the control end of the second transistor, the second transistor is turned off; when the voltage of the first end of the second transistor is greater than the voltage of the control end of the second transistor, the second transistor is turned on; A third transistor, a first end of the third transistor is electrically connected to the lead-out portion, a second end of the third transistor is electrically connected to the second port of the functional module, a control end of the third transistor is electrically connected to a second end of the second transistor, the first end of the third transistor is a first end of the switch unit, and the second end of the third transistor is a second end of the switch unit; wherein, when a voltage of the first end of the third transistor is less than a voltage of the control end of the third transistor, the third transistor is turned off; when the voltage of the first end of the third transistor is greater than the voltage of the control end of the third transistor, the third transistor is turned on.

[0026] In a possible implementation, the comparison circuit includes: A comparator, a first input terminal of the comparator is electrically connected to the lead-out portion, a second input terminal of the comparator is configured to receive a second target voltage, an output terminal of the comparator is electrically connected to the second port of the functional module, the first input terminal of the comparator is an input terminal of the comparison circuit, and the output terminal of the comparator is an output terminal of the comparison circuit; Wherein, when the first signal is at a high level and the second signal is at a low level, the voltage at the first input terminal of the comparator is less than the second target voltage, and the output terminal of the comparator outputs a low level; when the first signal is at a high level and the second signal is at a high level, the voltage at the first input terminal of the comparator is greater than or equal to the second target voltage, and the output terminal of the comparator outputs a high level.

[0027] In a possible implementation, the parsing circuit is disposed inside or outside the functional module.

[0028] In a third aspect, an embodiment of the present application provides a replaceable accessory, including the chip according to any one of the first item and the second item.

[0029] In the embodiment of the present application, by reasonably designing the position of the lead-out portion, the equivalent resistance between the first contact portion and the lead-out portion is less than the equivalent resistance between the second contact portion and the lead-out portion, thereby reducing the voltage division ratio of the resistance on the power signal transmission path. It can be understood that by reducing the voltage division ratio of the resistance on the power signal transmission path, the voltage drop on the power signal transmission path can be reduced, ensuring that the functional module can obtain a more stable power supply, thereby improving the stability and reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0031] Figure 1 It is a structural block diagram of a communication system provided by an embodiment of the present application; Figure 2 It is a schematic diagram of the connection relationship between a host device and a chip provided by an embodiment of the present application; Figure 3 It is a schematic diagram of the structure of a probe holder of a host device provided by an embodiment of the present application; Figure 4 It is a schematic diagram of the structure of a replaceable accessory provided by an embodiment of the present application; Figure 5 It is a schematic diagram of the structure of a chip provided by an embodiment of the present application; Figure 6 It is a partial structural schematic diagram of a data probe provided by an embodiment of the present application; Figure 7A It is a schematic diagram of the structure of the first chip provided by an embodiment of the present application; Figure 7BSchematic diagram of the second chip provided by the embodiment of the present application; Figure 8 Equivalent circuit diagram of a connection part provided by the embodiment of the present application; Figure 9 Schematic diagram of the third chip provided by the embodiment of the present application; Figure 10 Schematic diagram of the fourth chip provided by the embodiment of the present application; Figure 11 Schematic diagram of the fifth chip provided by the embodiment of the present application; Figure 12 Schematic diagram of the sixth chip provided by the embodiment of the present application; Figure 13 Schematic diagram of the seventh chip provided by the embodiment of the present application; Figure 14A Schematic diagram of the eighth chip provided by the embodiment of the present application; Figure 14B Schematic diagram of the ninth chip provided by the embodiment of the present application; Figure 15 Schematic circuit diagram of the first chip provided by the embodiment of the present application; Figure 16 Schematic circuit diagram of the second chip provided by the embodiment of the present application; Figure 17 Schematic circuit diagram of the third chip provided by the embodiment of the present application; Figure 18 Schematic circuit diagram of the fourth chip provided by the embodiment of the present application; Figure 19 Schematic circuit diagram of the fifth chip provided by the embodiment of the present application; Figure 20 A signal timing diagram provided by the embodiment of the present application; Figure 21 Relationship diagram between voltage and the state of the first transistor provided by the embodiment of the present application; Figure 22 Another signal timing diagram provided by the embodiment of the present application; Figure 23 Relationship diagram between voltage and the state of the first transistor provided by the embodiment of the present application; Figure 24 Schematic circuit diagram of the sixth chip provided by the embodiment of the present application; Figure 25 Schematic circuit diagram of the seventh chip provided by the embodiment of the present application. Detailed implementation manners

[0032] For a better understanding of the technical solution of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0033] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0034] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0035] It should be understood that the term " / and" used herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A / and B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally indicates that the associated objects before and after are in an "or" relationship.

[0036] See Figure 1 , which is a structural block diagram of a communication system provided by an embodiment of the present application. As Figure 1 shown, the communication system includes a host device 10 and a replaceable accessory 20, and a chip 21 is provided on the replaceable accessory 20. Corresponding communication ports are respectively configured on the host device 10 and the chip 21. When the replaceable accessory 20 is installed on the host device 10, the communication ports of the host device 10 and the chip 21 are electrically connected, and a communication link is established between the host device 10 and the chip 21. Information can be transmitted between the host device 10 and the chip 21 through this communication link. Specifically, when the host device 10 sends a signal to the chip 21, the host device 10 is the sender and the chip 21 is the receiver; when the chip 21 sends a signal to the host device 10, the chip 21 is the sender and the host device 10 is the receiver.

[0037] In specific implementation, the host device 10 can be a device such as an image forming apparatus, a mobile terminal, a computer, etc., and correspondingly, the replaceable accessory 20 can be a module such as a consumable cartridge, an earphone, a battery, a peripheral device, etc. Identity data, encrypted data, remaining service life data, etc. can be stored in the chip 21. The host device 10 can perform identity authentication on the replaceable accessory 20 through the identity data, implement encrypted communication between the host device 10 and the chip 21 through the encrypted data, and determine the remaining service life of the replaceable accessory 20 through the remaining service life data.

[0038] Exemplarily, the host device 10 is an image forming apparatus, and correspondingly, the replaceable accessory 20 is a consumable cartridge, and the remaining service life data is the consumable remaining amount. It can be understood that the initial value of the consumable remaining amount is usually 100%. As the consumable cartridge is used, the recording material (for example, toner or ink) in the consumable cartridge gradually decreases until it reaches 0. When the consumable remaining amount in the consumable cartridge is 0, it means that the recording material in the consumable cartridge has been exhausted, and at this time, the consumable cartridge needs to be replaced so that the image forming apparatus can continue to perform the image forming operation.

[0039] See Figure 2 , which is a schematic diagram of the connection relationship between a host device and a chip provided by an embodiment of the present application. As Figure 2 shown, the communication ports on the host device 10 and the chip 21 respectively include a data port (SDA), a chip select port (RST), a clock port (SCL), a power supply port (VCC), and a ground port (GND). When the replaceable accessory 20 is installed on the host device 10, the data port, chip select port, clock port, power supply port, and ground port on the host device 10 are respectively connected to the data port, chip select port, clock port, power supply port, and ground port on the chip 21 in a one-to-one correspondence, so as to realize the transmission of data signals, chip select signals, clock signals, power supply signals, and ground signals. Among them, the chip select signal is a key signal to ensure orderly communication in a multi-chip system, and bus conflicts are avoided by selecting a specific chip; the clock signal is a periodic signal with alternating high and low levels; the power supply signal can provide a working voltage for the chip 21; the ground signal can provide a unified reference low level between the host device 10 and the chip 21 to ensure the correctness and stability of the communication process.

[0040] It should be added that the type and number of communication ports between the host device 10 and the chip 21 are related to the communication protocol adopted by the host device 10 and the chip 21. The types and numbers of communication ports corresponding to different communication protocols are usually different, and the embodiments of the present application do not make specific limitations in this regard. However, those skilled in the art should understand that in existing or possibly designed future communication protocols, there should usually be at least two communication ports, and at least one of them should include a power supply port. Further, the power supply port involved in the embodiments of the present application can be an independent power supply port (only used for transmitting power supply signals), or a multi-functional power supply port (in addition to transmitting power supply signals, it can also transmit other signals, such as clock signals, data signals, etc.), and the embodiments of the present application do not make specific limitations in this regard.

[0041] In a specific implementation, the communication ports between the host device 10 and the chip 21 are in physical contact to achieve an electrical connection between the communication ports of the host device 10 and the chip 21. For example, the communication port on the host device 10 is electrically connected to a probe pin, and the communication port on the chip 21 is electrically connected to a contact portion. When the replaceable accessory 20 is installed on the host device 10, the probe pins on the host device 10 are in physical contact with the contact portions on the chip 21, achieving an electrical connection between the communication ports of the host device 10 and the chip 21. Regarding its specific structure, it will be described in detail below.

[0042] See Figure 3 , which is a schematic structural diagram of a probe pin holder of a host device provided by an embodiment of the present application. For ease of description, the X, Y, and Z directions perpendicular to each other are defined in Figure 3 . As Figure 3 shown, the probe pin holder 11 includes a front end surface 111 of the probe pin holder in the direction of the Y-axis arrow, a front end surface 112 of the probe pin holder in the direction of the X-axis arrow, and further includes data probe pins 1101, chip select probe pins 1102, clock probe pins 1103, power supply probe pins 1104, and ground probe pins 1105 that are staggeredly distributed along the Z-axis direction. Among them, the data probe pins 1101, chip select probe pins 1102, clock probe pins 1103, power supply probe pins 1104, and ground probe pins 1105 are respectively connected in one-to-one correspondence with the data port, chip select port, clock port, power supply port, and ground port on the host device 10.

[0043] See Figure 4 , which is a schematic structural diagram of a replaceable accessory provided by an embodiment of the present application. As Figure 4 shown, the replaceable accessory 20 includes a replaceable accessory body 201, and a chip 21 is provided on the outer surface of the replaceable accessory body 201. It should be noted that in the replaceable accessory 20 shown in Figure 4 , the structure of the replaceable accessory body 201 and the setting position of the chip 21 on the replaceable accessory body 201 are only an exemplary illustration of an embodiment of the present application, and should not be regarded as a limitation of the protection scope of the present application.

[0044] See Figure 5 , which is a schematic structural diagram of a chip provided by an embodiment of the present application. As Figure 5As shown, the chip 21 includes a data contact portion 21011, a chip select contact portion 21012, a clock contact portion 21013, a power supply contact portion 21014, and a ground contact portion 21015. In addition, the chip 21 usually also has functional modules to implement related functions such as data storage and processing. Specifically, the functional modules may include a control unit, a storage unit, etc. Among them, the control unit is used to control the communication with the host device. Specifically, the control unit may be a single-chip microcomputer (MCU), a microcontroller, an FPGA, a logic circuit (ASIC), etc. The storage unit may use common non-volatile storage units (such as EPROM, EEPROM, FLASH, ferroelectric storage units, phase change storage units, etc.), or may adopt a scheme of a volatile storage unit plus a power supply (for example, SRAM plus a battery or a capacitor, DRAM plus a battery or a capacitor, etc.).

[0045] In the embodiment of the present application, the data port, chip select port, clock port, power supply port, and ground port on the chip 21 are specifically the data port, chip select port, clock port, power supply port, and ground port on the functional module of the chip 21. The data contact portion 21011, chip select contact portion 21012, clock contact portion 21013, power supply contact portion 21014, and ground contact portion 21015 are respectively connected to the data port, chip select port, clock port, power supply port, and ground port on the functional module in one-to-one correspondence.

[0046] When the replaceable accessory 20 is installed on the host device 10, the data contact pin 1101, chip select contact pin 1102, clock contact pin 1103, power supply contact pin 1104, and ground contact pin 1105 of the host device 10 respectively come into contact with the data contact portion 21011, chip select contact portion 21012, clock contact portion 21013, power supply contact portion 21014, and ground contact portion 21015 on the chip 21, thereby establishing a communication link between the host device 10 and the chip 21.

[0047] See Figure 6 , which is a partial structural schematic diagram of a data contact pin provided by the embodiment of the present application. As Figure 6As shown in the figure, the data probe 1101 includes a data probe tip 11011, a data probe front end 11012, a data probe inclined end 11013, and a data probe tip 11014. In a specific implementation, the electrical connection between the data probe 1101 and the data contact portion 21011 is usually achieved by forming a contact between the data probe tip 11014 and the data contact portion 21011 on the chip 21. Of course, those skilled in the art can also form a contact between the data probe 1101 and the data contact portion 21011 on the chip 21 through the data probe tip 11011, the data probe front end 11012, or the data probe inclined end 11013 according to actual needs. The embodiments of the present application do not make specific limitations on this.

[0048] In addition, the structures and working principles of other probes (chip select probe 1102, clock probe 1103, power supply probe 1104, and ground probe 1105) in the host device 10 are similar to those of the data probe 1101. For the sake of brevity, they will not be described in detail here.

[0049] In some application scenarios, the current output from the power supply port of the host device 10 may not be able to drive the functional modules in the chip 21, which may cause the host device 10 to malfunction. To address this problem, a solution in the related art is that in addition to being electrically connected to the power supply port of the host device 10, the power supply port of the chip 21 is also electrically connected to other ports of the host device 10.

[0050] Specifically, a connection portion is provided on the chip 21. The connection portion simultaneously connects multiple communication ports including the power supply port in the host device 10, and a certain point of the connection portion (for the sake of easy description, called the "lead-out portion") is electrically connected to the power supply port of the functional module in the chip 21. It can be understood that through the above connection method, multiple communication ports including the power supply port in the host device 10 can supply power to the power supply port of the functional module, and thus the current input to the power supply port of the functional module can be increased.

[0051] See Figure 7A , which is a schematic structural diagram of a chip provided by the embodiments of the present application. As Figure 7A shown, the chip 21 includes a substrate 210, and the substrate 210 includes a first plane 2101. A connection portion 21016 is provided on the first plane 2101. The connection portion 21016 includes a first contact portion 210161, a second contact portion 210162, and a lead-out portion 210163. The first contact portion 210161 and the second contact portion 210162 are respectively electrically connected to the lead-out portion 210163.

[0052] In the embodiment of the present application, the first contact portion 210161 is used to be electrically connected to the first port of the host device 10 to receive the first signal output by the first port of the host device 10; the second contact portion 210162 is used to be electrically connected to the second port of the host device 10 to receive the second signal output by the second port of the host device 10. The first end of the lead-out portion 210163 is electrically connected to the first contact portion 210161 and the second contact portion 210162 respectively to obtain a superimposed signal composed of the first signal and the second signal. Specifically, the first port is a power supply port, and the second port is a non-power supply port; correspondingly, the first signal is a power supply signal, and the second signal is a non-power supply signal. That is to say, the superimposed signal is a signal composed of the power supply signal and the non-power supply signal output by the host device 10.

[0053] Furthermore, the chip 21 further includes a functional module 21021 to implement related functions such as data storage and processing. Specifically, the functional module may include a control unit, a storage unit, etc. The second end of the lead-out portion 210163 is electrically connected to the first port (i.e., the power supply port) of the functional module 21021 to supply power to the power supply port of the functional module 21021 through the superimposed signal. Since the current of the superimposed signal includes both the power supply signal and the non-power supply signal, the current of the superimposed signal is larger. By supplying power to the power supply port of the functional module 21021 through the superimposed signal, the current input to the power supply port of the functional module 21021 can be increased.

[0054] In a possible implementation manner, the connection portion 21016 includes a conductive region, and the first contact portion 210161, the second contact portion 210162, and the lead-out portion 210163 are located in the conductive region. It can be understood that the first contact portion 210161 and the second contact portion 210162 can be electrically connected to the lead-out portion 210163 respectively through the conductive region.

[0055] In a specific implementation, the conductive region may be formed of a carbon material, specifically a carbon film or carbon oil. The carbon film or carbon oil is a thin-film resistance material and can be prepared by processes such as Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD). Since the resistivity of the carbon film or carbon oil (the resistance value per unit distance on the surface of the carbon film or carbon oil) is large, if the position of the lead-out portion 210163 is not selected reasonably, a large voltage drop may be generated on the power supply signal transmission path (between the first contact portion 210161 and the lead-out portion 210163), thereby affecting the stability and reliability of the functional module 21021.

[0056] It should be noted that, in addition to carbon materials, other conductive materials may also be used to prepare the conductive region, and the embodiments of the present application do not specifically limit the materials for preparing the conductive region.

[0057] See Figure 8 , which is an equivalent circuit diagram of a connection part provided by an embodiment of the present application. As Figure 8 shown, in the connection part 21016, the equivalent resistance between the first contact part 210161 and the lead-out part 210163 is the first resistance R1, and the equivalent resistance between the second contact part 210162 and the lead-out part 210163 is the second resistance R2. It can be understood that in the conductive region, the setting position of the lead-out part 210163 will affect the resistance values of the first resistance R1 and the second resistance R2. If the position of the lead-out part 210163 is set unreasonably, it may increase the resistance on the power signal transmission path (between the first contact part 210161 and the lead-out part 210163) in the connection part 21016, that is, the first resistance R1. It can be understood that when the first signal is at a high level and the second signal is at a low level, the larger the partial voltage ratio of the first resistance R1 in the total resistance of the first resistance R1 and the second resistance R2, the larger the voltage drop on the power signal transmission path. A large voltage drop on the power signal transmission path may cause the voltage of the superimposed signal output by the lead-out part 210163 to be too small. If the voltage of the superimposed signal is less than the minimum operating voltage of the functional module 21021, it may cause the functional module 21021 to fail to work properly, and further result in poor stability and reliability of the functional module 21021.

[0058] Exemplarily, when the first port of the host device 10 outputs a high level (voltage is V1) and the second port outputs a low level (voltage is a reference voltage lower than the high level, generally considered to be between 0V and 1.5V, in some embodiments, this voltage approaches 0V. For the convenience of subsequent calculation of the superimposed voltage, we take 0V when the voltage is at a low level for calculation. Those skilled in the art can understand that regarding the voltage as 0V when the voltage is at a low level in the subsequent embodiments is for the convenience of showing the embodiments and should not be regarded as a limitation of the present application), the voltage V of the superimposed signal output by the lead-out part 210163 is V = (R2 / (R1 + R2)) × V1. It can be understood that the larger the first resistance R1, the smaller the voltage V of the lead-out part 210163. If the voltage V of the lead-out part 210163 is lower than the minimum operating voltage of the functional module 21021, it may cause the functional module 21021 to fail to work properly.

[0059] To solve the above problems, in the embodiments of the present application, by reasonably designing the position of the lead-out portion 210163, the equivalent resistance (the first resistance R1) between the first contact portion 210161 and the lead-out portion 210163 is made smaller than the equivalent resistance (the second resistance R2) between the second contact portion 210162 and the lead-out portion 210163, thereby reducing the voltage division ratio of the resistance on the power signal transmission path. It can be understood that by reducing the voltage division ratio of the resistance on the power signal transmission path, the voltage drop on the power signal transmission path can be reduced, ensuring that the functional module 21021 can obtain a more stable power supply, thereby improving the stability and reliability of the functional module 21021.

[0060] Exemplarily, by reasonably designing the position of the lead-out portion 210163, the resistance values of the first resistance R1 and the second resistance R2 are 1 kΩ and 3 kΩ respectively. When the first port of the host device 10 outputs a high level (voltage is 3.3V) and the second port outputs a low level (voltage is 0V), the voltage V of the superimposed signal output by the lead-out portion 210163 is V = (3 / (1 + 3)) × 3.3 ≈ 2.5V. Assuming that the minimum operating voltage of the functional module 21021 is 2.1V, through the above resistance value distribution of the first resistance R1 and the second resistance R2, it can be ensured that the voltage of the lead-out portion 210163 is always greater than the minimum operating voltage of the functional module 21021, thereby improving the stability and reliability of the chip 21.

[0061] In the embodiments of the present application, the second port is a chip select port, and correspondingly, the second signal is a chip select signal. That is to say, the chip 21 can be connected to the power port of the host device 20 through the first contact portion 210161 of the connection portion 21016, and connected to the chip select port of the host device 20 through the second contact portion 210162 of the connection portion 21016.

[0062] As described above, in addition to the power port and the chip select port, the communication ports of the host device 20 also include a data port, a clock port, and a ground port. As Figure 7A shown, corresponding to the data port, the clock port, and the ground port of the host device, a data contact portion 21011, a clock contact portion 21013, and a ground contact portion 21015 are also provided on the first plane 2101 of the chip 21. The data contact portion 21011, the clock contact portion 21013, and the ground contact portion 21015 are respectively used for electrically connecting to the data port, the clock port, and the ground port of the host device 10.

[0063] It is understandable that if the resistivity of the conductive region is uniform, within the conductive region, the longer the distance between two points, the generally larger the equivalent resistance. Based on this principle, the distance between the first contact portion 210161 and the lead-out portion 210163 can be set to be less than the distance between the second contact portion 210162 and the lead-out portion 210163, so as to achieve that the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 is less than the equivalent resistance between the second contact portion 210162 and the lead-out portion 210163.

[0064] Exemplarily, in Figure 7A the distance between the first contact portion 210161 and the lead-out portion 210163 is D1 (for the convenience of description, referred to as "the first distance D1"), and the distance between the second contact portion 210162 and the lead-out portion 210163 is D2 (for the convenience of description, referred to as "the second distance D2"), where D1 < D2.

[0065] It should be added that when the resistivity of the conductive region is non-uniform, by setting the first distance D1 to be less than the second distance D2, it is also possible to achieve that the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 is less than the equivalent resistance between the second contact portion 210162 and the lead-out portion 210163. Therefore, the resistivity of the conductive region in the embodiments of the present application is not specifically limited.

[0066] In practical applications, the replaceable accessory 20 is usually installed or removed on the host device 10 in a sliding manner. During the sliding process, the contact pins on the host device 10 will rub against the contact portions on the chip, which may cause the positions of the first contact portion 210161 and the second contact portion 210162 to shift. It is understandable that the shift of the positions of the first contact portion 210161 and the second contact portion 210162 will cause the resistance values of the first resistor R1 and the second resistor R2 to change, and further may affect the voltage division ratio of the resistors on the power signal transmission path.

[0067] In order to reduce the influence on the voltage division ratio of the resistors on the power signal transmission path caused by the shift of the positions of the first contact portion 210161 and the second contact portion 210162, the embodiments of the present application perform differential setting on the resistivity of the first contact portion 210161 and / or the second contact portion 210162 itself, or on the resistivity of the conductive region where the first contact portion 210161 and / or the second contact portion 210162 is located. This will be described below with reference to the drawings.

[0068] See Figure 9, which is a schematic structural diagram of a chip provided by an embodiment of the present application. In the embodiment of the present application, the resistivity of the first contact portion 210161 and / or the second contact portion 210162 itself is differentially set so that the resistivity of the first contact portion 210161 and / or the second contact portion 210162 is less than the resistivity of the conductive region.

[0069] Since the smaller the resistivity, the smaller the resistance value corresponding to the unit distance, configuring the first contact portion 210161 and / or the second contact portion 210162 to have a smaller resistivity can reduce the resistance value deviation of the first resistor R1 and / or the second resistor R2 caused by the position offset of the first contact portion 210161 and / or the second contact portion 210162, and improve the stability of the voltage division ratio of the resistors on the power signal transmission path.

[0070] See Figure 10 , which is a schematic structural diagram of a chip provided by an embodiment of the present application. In the embodiment of the present application, the conductive region is divided into a first electron-conducting region 21016A and a second electron-conducting region 21016B. Among them, the first contact portion 210161 and the second contact portion 210162 are located in the first electron-conducting region 21016A, the lead-out portion 210163 is located in the second electron-conducting region 21016B, and the resistivity of the first electron-conducting region 21016A is less than the resistivity of the second electron-conducting region 21016B. That is to say, the resistivity of the conductive region where the first contact portion 210161 and the second contact portion 210162 are located is less than the resistivity of the conductive region where the lead-out portion 210163 is located.

[0071] Since the smaller the resistivity, the smaller the resistance value corresponding to the unit distance, configuring the conductive region where the first contact portion 210161 and the second contact portion 210162 are located to have a smaller resistivity can reduce the resistance value deviation of the first resistor R1 and / or the second resistor R2 caused by the position offset of the first contact portion 210161 and / or the second contact portion 210162, and improve the stability of the voltage division ratio of the resistors on the power signal transmission path.

[0072] See Figure 11 , which is a schematic structural diagram of a chip provided by an embodiment of the present application. This embodiment is the same as Figure 10The difference of the illustrated embodiment is that the first electron - conducting region 21016A is further divided into a third electron - conducting region 21016A1 and a fourth electron - conducting region 21016A2. Among them, the first contact portion 210161 is located within the third electron - conducting region 21016A1, and the second contact portion 210162 is located within the fourth electron - conducting region 21016A2. That is to say, the first contact portion 210161 and the second contact portion 210162 are respectively located in different electron - conducting regions. Therefore, the resistivity of the conductive regions where the first contact portion 210161 and the second contact portion 210162 are located can be configured more flexibly to meet the resistivity configuration requirements of different application scenarios.

[0073] Specifically, the third electron - conducting region 21016A1 and the fourth electron - conducting region 21016A2 can be configured with different resistivities. For example, the resistivity of the third electron - conducting region 21016A1 is less than the resistivity of the fourth electron - conducting region 21016A2. In the embodiment of the present application, since the first contact portion 210161 is located within the third electron - conducting region 21016A1, configuring the resistivity of the third electron - conducting region 21016A1 to be less than the resistivity of the fourth electron - conducting region 21016A2 can minimize the equivalent resistance (the first resistance R1) between the first contact portion 210161 and the lead - out portion 210163, thereby reducing the voltage - division ratio of the resistance on the power - signal transmission path.

[0074] Of course, those skilled in the art can also configure the resistivity of the third electron - conducting region 21016A1 to be greater than the resistivity of the fourth electron - conducting region 21016A2 according to actual needs, or configure the third electron - conducting region 21016A1 and the fourth electron - conducting region 21016A2 with the same resistivity. The embodiment of the present application does not make specific limitations in this regard.

[0075] It should be supplemented and explained that, for the sake of convenience of description, in Figures 7A - 11 the illustrated embodiment, taking "rectangle" as an example, the shapes of the conductive region, the first electron - conducting region 21016A, the second electron - conducting region 21016B, the third electron - conducting region 21016A1, the fourth electron - conducting region 21016A2, the first contact portion 210161 and the second contact portion 210162 are exemplarily illustrated. Those skilled in the art should understand that in addition to "rectangle", the shapes of the above - mentioned regions or contact portions can also be set to other regular shapes or irregular shapes. The embodiment of the present application does not make specific limitations in this regard.

[0076] See Figure 12 which is a schematic structural diagram of a chip provided by the embodiment of the present application. This embodiment is the same as Figures 7A - 11The difference of the illustrated embodiment is that the connecting portion 21016 includes a first conductive path and a second conductive path. The first contact portion 210161 is electrically connected to the lead-out portion 210163 through the first conductive path; the second contact portion 210162 is electrically connected to the lead-out portion 210163 through the second conductive path. That is to say, the electrical connection between the first contact portion 210161 and the second contact portion 210162 and the lead-out portion 210163 is realized through the conductive paths.

[0077] In a specific implementation, the first conductive path and the second conductive path may be formed of a carbon material, specifically, a carbon film or carbon oil. Since the resistivity of the carbon film or carbon oil (the resistance value per unit distance on the surface of the carbon film or carbon oil) is relatively large, if the position of the lead-out portion 210163 is not reasonably selected, a relatively large voltage drop may be generated on the power signal transmission path (the first conductive path), thereby affecting the stability and reliability of the functional module 21021.

[0078] It should be added that, in addition to the carbon material, the first conductive path and the second conductive path may also be prepared from other conductive materials, and the embodiments of the present application do not specifically limit the materials for preparing the first conductive path and the second conductive path.

[0079] In a possible implementation manner, the length L1 of the first conductive path is less than the length L2 of the second conductive path. It can be understood that the longer the conductive path, the generally larger the equivalent resistance of the conductive path. Therefore, by setting the length L1 of the first conductive path to be less than the length L2 of the second conductive path, the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 can be made less than the equivalent resistance between the second contact portion 210162 and the lead-out portion 210163.

[0080] In practical applications, when the length L1 of the first conductive path is less than the length L2 of the second conductive path, the distance (linear distance, that is, the first distance D1) between the first contact portion 210161 and the lead-out portion 210163 may also be greater than or equal to the distance (linear distance, that is, the second distance D2) between the second contact portion 210162 and the lead-out portion 210163.

[0081] Exemplarily, in Figure 12 , and L1 < L2, and D1 > D2. It can be understood that the resistance of the conductive path is mainly affected by the length and resistivity of the conductive path. Therefore, although the first distance D1 is greater than the second distance D2, since the length L1 of the first conductive path is less than the length L2 of the second conductive path, when the resistivity of the first conductive path and the second conductive path is the same, the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 is less than the equivalent resistance between the second contact portion 210162 and the lead-out portion 210163.

[0082] It should be noted that when the resistivity of the first conductive path and the second conductive path is different, by setting the length L1 of the first conductive path to be less than the length L2 of the second conductive path, it is still possible to achieve that the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 is less than the equivalent resistance between the second contact portion 210162 and the lead-out portion 210163. The embodiments of the present application do not make specific restrictions on this.

[0083] In a possible implementation manner, the resistivity of the first conductive path is less than the resistivity of the second conductive path. It can be understood that the greater the resistivity of the conductive path, the greater the equivalent resistance of the conductive path usually is. Therefore, by setting the resistivity of the first conductive path to be less than the resistivity of the second conductive path, it is possible to achieve that the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 is less than the equivalent resistance between the second contact portion 210162 and the lead-out portion 210163.

[0084] In a possible implementation manner, the length L1 of the first conductive path is less than the length L2 of the second conductive path, and the resistivity of the first conductive path is less than the resistivity of the second conductive path. In the embodiments of the present application, by simultaneously setting "the length L1 of the first conductive path is less than the length L2 of the second conductive path" and "the resistivity of the first conductive path is less than the resistivity of the second conductive path", it is possible to achieve that the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 is less than the equivalent resistance between the second contact portion 210162 and the lead-out portion 210163, and the voltage division ratio of the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 can be minimized.

[0085] It can be understood that in Figures 7A - 11 the shown conductive region, the conductive path between the first contact portion 210161 and the lead-out portion 210163 is equivalent to the straight-line path between the first contact portion 210161 and the lead-out portion 210163; the conductive path between the second contact portion 210162 and the lead-out portion 210163 is equivalent to the straight-line path between the second contact portion 210162 and the lead-out portion 210163. In the embodiments of the present application, since the first conductive path and the second conductive path can be bent, therefore, in a limited area, a greater difference in the lengths of the conductive paths (the difference between the length L1 of the first conductive path and the length L2 of the second conductive path) can be obtained, and further, the voltage division ratio of the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 can be minimized. Of course, those skilled in the art can also set the first conductive path and the second conductive path to be straight lines according to actual needs, and the embodiments of the present application do not make specific restrictions on this.

[0086] In addition, with respect to the conductive region, the connection between the first contact portion 210161 and the lead-out portion 210163 and the connection between the second contact portion 210162 and the lead-out portion 210163 are realized through conductive paths, which can reduce the use of conductive materials in the connection portion 21016, that is, save conductive materials. For example, reduce the use of carbon film or carbon oil.

[0087] See Figure 13 , which is a schematic structural diagram of a chip provided by an embodiment of the present application. The difference between this embodiment and Figure 12 the embodiment shown is that the connection portion 21016 further includes an insulating region 210164 disposed around the first conductive path and the second conductive path, and the insulating region 210164 can be an insulating coating. Through the insulating region 210164, the first conductive path and the second conductive path can be prevented from interfering with each other, thereby obtaining a more stable superimposed signal and improving the stability and reliability of the chip 21.

[0088] Furthermore, in order to prevent illegal elements from stealing the design parameters of the connection portion 21016, improve the security of the chip 21, and make the connection portion 21016 more beautiful, the color and / or texture of the insulating region 210164 can be set to match the color and / or texture of the first conductive path and the second conductive path.

[0089] In specific implementation, the connection region, connection sub-region, and / or conductive path in the connection portion 21016 can be directly deposited by processes such as physical vapor deposition or chemical vapor deposition. After deposition, the required connection region, connection sub-region, and / or conductive path can also be obtained through cutting or trimming. It can be understood that directly depositing and preparing the connection region, connection sub-region, and / or conductive path by the deposition process can simplify the manufacturing process of the chip 21. After deposition, by cutting or trimming to obtain the required connection region, connection sub-region, and / or conductive path, the required resistance value range can be flexibly adjusted. Those skilled in the art can select the corresponding manufacturing process according to actual needs, and the embodiments of the present application do not make specific limitations thereto.

[0090] See Figure 14A , which is a schematic structural diagram of a chip provided by an embodiment of the present application. The difference between the embodiments of the present application and Figure 7A the embodiment shown is that in the embodiments of the present application, the second port is a clock port, and correspondingly, the second signal is a clock signal. That is to say, the chip 21 can connect to the power supply port of the host device 20 through the first contact portion 210161 of the connection portion 21016, connect to the clock port of the host device 20 through the second contact portion 210162 of the connection portion 21016, and increase the current input to the power supply port of the chip 21 through the superposition of the power signal and the clock signal.

[0091] As described above, in addition to the power port and the clock port, the communication ports of the host device 20 further include a data port, a chip select port, and a ground port. As Figure 14A shown, corresponding to the data port, the chip select port, and the ground port of the host device, a data contact portion 21011, a chip select contact portion 21012, and a ground contact portion 21015 are further provided on the first plane 2101 of the chip 21. The data contact portion 21011, the chip select contact portion 21012, and the ground contact portion 21015 are respectively used for electrically connecting to the data port, the chip select port, and the ground port of the host device 10.

[0092] In some possible implementation manners, the second port may further be a data port, and correspondingly, the second signal is a data signal. That is to say, by superimposing the power signal and the data signal, the current input to the power port of the chip 21 is increased. For the specific content of the embodiments of the present application, reference may be made to the above description. For the sake of brevity, it will not be elaborated herein.

[0093] In some application scenarios, the chip select signal is active high. That is to say, when the chip 21 is operating, the chip select signal is always in a high level state, while the clock signal and the data signal are usually composed of level signals that change between high and low. Therefore, compared with the clock signal and the data signal, superimposing the chip select signal and the power signal can obtain a more stable superimposed signal when the chip 21 is operating, thereby improving the stability and reliability of the chip 21.

[0094] In practical applications, the chip 21 may have a multi-layer structure, that is, the chip 21 includes multiple layers. It can be understood that when the chip 21 includes multiple layers, the connection portion 21016 and the functional module 21021 may be provided on the same layer of the chip 21, or may be provided on different layers of the chip 21.

[0095] In a possible implementation manner, the connection portion 21016 and the functional module 21021 are provided on the same layer of the chip 21. In this case, the connection portion 21016 can be directly electrically connected to the functional module 21021 through a wire. Specifically, the lead-out portion 210163 of the connection portion 21016 is directly electrically connected to the functional module 21021 through a wire.

[0096] Exemplarily, in Figure 7A and Figure 14A the connection portion 21016 is provided on the first plane 2101 of the chip 21, and the functional module 21021 is also provided on the first plane 2101 of the chip 21, that is, the connection portion 21016 and the functional module 21021 are provided on the same layer of the chip 21. The connection portion 21016 can be directly electrically connected to the functional module 21021 through a wire (not shown in the figure).

[0097] In a possible implementation, the connection part 21016 and the functional module 21021 are arranged on different layers of the chip 21. In this case, the connection part 21016 can be electrically connected to the functional module 21021 through a via. Specifically, the lead-out part 210163 of the connection part 21016 is electrically connected to the functional module 21021 through a via. When the lead-out part 210163 is electrically connected to the functional module 21021 through a via, the lead-out part 210163 can be arranged on the back surface of the connection part 21016, that is, on the side facing the substrate 210.

[0098] Exemplarily, in Figure 7B and Figure 14B the connection part 21016 is arranged on the first plane 2101 of the chip 21, and the functional module 21021 is arranged on the second plane (not shown in the figure) of the chip 21, that is, the connection part 21016 and the functional module 21021 are arranged on different layers of the chip 21. The lead-out part 210163 of the connection part 21016 is arranged on the back surface of the connection part 21016, that is, on the side facing the substrate 210. The lead-out part 210163 of the connection part 21016 is electrically connected to the functional module 21021 through a via (not shown in the figure).

[0099] It can be understood that each signal output by the host device 10 has a specific function. After the first signal and the second signal are superimposed, the functions that the first signal and the second signal should achieve are generally not affected. That is to say, the functional module 21021 in the chip 21 can be controlled by superimposing signals to achieve functions matching the first signal and the second signal.

[0100] See Figure 15 , which is a schematic circuit structure diagram of a chip provided by an embodiment of the present application. As Figure 15 shown, the chip 21 includes a first resistor R1, a second resistor R2, an analysis circuit, and a functional module 21021. Among them, the first resistor R1 is the equivalent resistor between the first contact part 210161 and the lead-out part 210163 in the connection part 21016; the second resistor R2 is the equivalent resistor between the second contact part 210162 and the lead-out part 210163 in the connection part 21016. The first contact part 210161 is used to connect the first port (power supply port) of the host device 10 and receive the first signal (power supply signal) sent by the host device 10; the second contact part 210162 is used to connect the second port (non-power supply port) of the host device 10 and receive the second signal (non-power supply signal) sent by the host device 10; the lead-out part 210163 is used to output a superimposed signal composed of the first signal and the second signal.

[0101] The input end of the parsing circuit is electrically connected to the lead-out part 210163. The parsing circuit is used to parse the superimposed signal, and output a first parsing signal at the first output end of the parsing circuit and a second parsing signal at the second output end of the parsing circuit. It can be understood that the first parsing signal is the parsed power supply signal, and the second parsing signal is the parsed non-power supply signal. Specifically, when the second port is a chip select port, the second parsing signal is the parsed chip select signal; when the second port is a clock port, the second parsing signal is the parsed clock signal; when the second port is a data port, the second parsing signal is the parsed data signal.

[0102] The first port (power supply port) of the functional module 21021 is electrically connected to the first output end of the parsing circuit. The first port of the functional module 21021 is used to receive the first parsing signal output from the first output end of the parsing circuit, and realize the function matching the first signal through the first parsing signal. Specifically, in order to realize the function matching the first signal through the first parsing signal, it is necessary to ensure that the first parsing signal and the first signal have the same level state (that is, when the first signal is high level, the first parsing signal should also be high level; when the first signal is low level, the first parsing signal should also be low level). In addition, since the functional module 21021 usually has a minimum operating voltage, when the first signal is high level, the voltage of the first parsing signal should be greater than or equal to the minimum operating voltage of the functional module 21021.

[0103] The second port (non-power supply port) of the functional module 21021 is electrically connected to the second output end of the parsing circuit. The second port of the functional module 21021 is used to receive the second parsing signal output from the second output end of the parsing circuit, and realize the function matching the second signal through the second parsing signal. Specifically, in order to realize the function matching the second signal through the second parsing signal, it is necessary to ensure that the second parsing signal and the second signal have the same level state (that is, when the second signal is high level, the second parsing signal should also be high level; when the second signal is low level, the second parsing signal should also be low level).

[0104] See Figure 16 For a schematic circuit structure diagram of a chip provided by an embodiment of the present application. The difference between the embodiment of the present application and Figure 15 the embodiment shown is that the input end of the parsing circuit is electrically connected to the first output end of the parsing circuit. It can be understood that according to this connection relationship, the first parsing signal output from the first output end of the parsing circuit is the superimposed signal. That is to say, the function matching the first signal is realized through the superimposed signal.

[0105] It is understandable that, in order to achieve a function matching the first signal through the superimposed signal, when the functional module 21021 is in the working state, the voltage of the superimposed signal should be greater than or equal to the minimum working voltage of the functional module 21021. Additionally, since the first signal is a power supply signal, when the functional module 21021 is in the working state, the first signal is usually at a high level. However, the second signal may be at a high level or a low level. Therefore, there are two cases when the functional module 21021 is in the working state: one is that the first signal is at a high level and the second signal is at a high level; the other is that the first signal is at a high level and the second signal is at a low level.

[0106] Upon further analysis, when the first signal and the second signal are both at a high level, there is usually no voltage drop or only a small voltage drop in the power supply signal transmission path. At this time, the voltage of the superimposed signal composed of the first signal and the second signal is usually large. For example, when both the first signal and the second signal are at a high level with a voltage value of 3.3V, the voltage of the superimposed signal is usually also 3.3V. When the first signal is at a high level and the second signal is at a low level, due to the presence of the first resistor R1, there is usually a certain voltage drop in the power supply signal transmission path. At this time, the voltage of the superimposed signal composed of the first signal and the second signal is usually small. For example, when the first signal is at a high level with a voltage value of 3.3V and the second signal is at a low level with a voltage value of 0V, if a voltage drop of 0.7V occurs in the power supply signal transmission path due to the presence of the first resistor R1, then the voltage of the superimposed signal is 3.3V - 0.7V = 2.5V.

[0107] That is to say, compared with the state where "the first signal and the second signal are both at a high level", when the first signal is at a high level and the second signal is at a low level, the voltage of the superimposed signal composed of the first signal and the second signal is usually small. Therefore, in order to achieve a function matching the first signal through the superimposed signal, it is usually only necessary to ensure that "when the first signal is at a high level and the second signal is at a low level, the voltage of the superimposed signal is greater than or equal to the minimum working voltage of the functional module 21021".

[0108] Furthermore, the parsing circuit further includes a comparison circuit. The input end of the comparison circuit (i.e., the input end of the parsing circuit) is electrically connected to the lead-out portion 210163 for receiving the superimposed signal; the output end of the comparison circuit (i.e., the second output end of the parsing circuit) is electrically connected to the second port of the functional module 21021 for outputting the second parsing signal.

[0109] In the embodiment of the present application, the comparison circuit is configured such that when the first signal is at a high level and the second signal is at a low level, the second parsing signal is at a low level; when the first signal is at a high level and the second signal is at a high level, the second parsing signal is at a high level. That is to say, when the first signal is at a high level (at this time, the functional module 21021 can operate normally), the second parsing signal and the second signal have the same level state, and thus a function matching the second signal can be implemented through the second parsing signal.

[0110] It should be added that Figure 16 This is only a possible implementation manner provided by the embodiment of the present application, and it should not be regarded as a limitation on the protection scope of the present application. Exemplarily, those skilled in the art can also perform corresponding processing on the superimposed signal according to actual needs (such as amplification processing, filtering processing, etc.), and then obtain the first parsing signal and the second parsing signal that can meet the above requirements through the processed superimposed signal.

[0111] For the specific content of the embodiment of the present application, reference can be made to the descriptions of other embodiments in the foregoing text. For the sake of brevity, it will not be elaborated here.

[0112] See Figure 17 , which is a schematic circuit diagram of a chip provided by the embodiment of the present application. The difference between the embodiment of the present application and Figure 16 the embodiment shown is that the comparison circuit includes a voltage output unit, a switch unit, and a resistive device.

[0113] Specifically, the output terminal of the voltage output unit is used to output a first target voltage. The first end of the switch unit (i.e., the input terminal of the comparison circuit) is electrically connected to the lead-out portion 210163, the second end of the switch unit (i.e., the output terminal of the comparison circuit) is electrically connected to the second port of the functional module 21021, and the control terminal of the switch unit is electrically connected to the output terminal of the voltage output unit. The first end of the resistive device is electrically connected to the second end of the switch unit, and the second end of the resistive device is connected to the first reference voltage GND1.

[0114] In the embodiment of the present application, the voltage output unit is configured such that when the first signal is at a high level and the second signal is at a low level, the voltage of the superimposed signal is less than the first target voltage; when the first signal is at a high level and the second signal is at a high level, the voltage of the superimposed signal is greater than the first target voltage. The switch unit is configured such that when the voltage at the first end of the switch unit is less than or equal to the voltage at the control terminal of the switch unit, the switch unit is turned off, and the second end of the switch unit outputs a low level; when the voltage at the first end of the switch unit is greater than the voltage at the control terminal of the switch unit, the switch unit is turned on, and the second end of the switch unit outputs a high level.

[0115] According to the above configurations of the voltage output unit and the switch unit, when the first signal is at a high level and the second signal is at a low level, the voltage of the superimposed signal is less than the first target voltage, that is, the voltage at the first end of the switch unit is less than or equal to the voltage at the control end of the switch unit. At this time, the switch unit is turned off, and the second end of the switch unit outputs a low level. That is to say, when the first signal is at a high level and the second signal is at a low level, the second end of the switch unit outputs a low level, that is, the second parsing signal is at a low level. When the first signal is at a high level and the second signal is at a high level, the voltage of the superimposed signal is greater than the first target voltage, that is, the voltage at the first end of the switch unit is greater than the voltage at the control end of the switch unit. At this time, the switch unit is turned on, and the second end of the switch unit outputs a high level. That is to say, when the first signal is at a high level and the second signal is at a high level, the second end of the switch unit outputs a high level, that is, the second parsing signal is at a high level.

[0116] In summary, in the embodiment of the present application, the second parsing signal and the second signal have the same level state, and thus the function matching the second signal can be realized through the second parsing signal.

[0117] For the specific content of the embodiment of the present application, reference can be made to the descriptions of other embodiments in the foregoing. For the sake of brevity, it will not be elaborated herein.

[0118] See Figure 18 , which is a schematic circuit structure diagram of a chip provided by an embodiment of the present application. The difference between the embodiment of the present application and Figure 17 The embodiment shown is that the voltage output unit includes a unidirectional conduction device and a capacitive device. Among them, the first end of the unidirectional conduction device is electrically connected to the lead-out portion 210163, and the first end of the unidirectional conduction device conducts unidirectionally from the first end to the second end; the first end of the capacitive device (i.e., the output end of the voltage output unit) is electrically connected to the second end of the unidirectional conduction device, and the second end of the capacitive device is connected to the second reference voltage GND2. When the capacitive device is fully charged, the first end of the capacitive device outputs the first target voltage.

[0119] In the embodiment of the present application, the output of the first target voltage is realized by using the unidirectional conduction of the unidirectional conduction device and the charge and discharge characteristics of the capacitive device. Of course, those skilled in the art can also adopt other circuit structures to output the first target voltage according to actual needs. For example, the first target voltage is output through an independent voltage module, and the embodiment of the present application does not make specific limitations on this.

[0120] For the convenience of understanding, the technical solution provided by the embodiment of the present application will be described in detail below in conjunction with a specific circuit structure.

[0121] See Figure 19 , which is a schematic circuit structure diagram of a chip provided by an embodiment of the present application. As Figure 19As shown, in the embodiment of the present application, the unidirectional conduction device is diode D, and the capacitive device is capacitor C. The positive electrode of diode D is electrically connected to lead-out portion 210163; the first end of capacitor C (i.e., the output end of the voltage output unit) is electrically connected to the negative electrode of diode D, and the second end of capacitor C is connected to second reference voltage GND2. When capacitor C is fully charged, the first end of capacitor C outputs the first target voltage.

[0122] In addition, the switching unit includes first transistor Q1 (for example, it can be a PMOS transistor); the resistive device includes third resistor R3. The first end of first transistor Q1 (i.e., the first end of the switching unit) is electrically connected to lead-out portion 210163, the second end of first transistor Q1 (i.e., the first end of the switching unit) is electrically connected to the second port of functional module 21021, and the control end of first transistor Q1 (i.e., the control end of the switching unit) is electrically connected to the node between the unidirectional conduction device and the capacitive device. In the embodiment of the present application, first transistor Q1 is configured such that: when the voltage at the first end of first transistor Q1 is less than the voltage at the control end of first transistor Q1, first transistor Q1 is cut off; when the voltage at the first end of first transistor Q1 is greater than the voltage at the control end of first transistor Q1, first transistor Q1 is turned on.

[0123] For ease of understanding, taking the second port as the chip select port as an example, the Figure 19 working principle of the shown circuit is described by way of example. It can be understood that when the second port is the chip select port, the second signal is the chip select signal.

[0124] Specifically, when the received chip select signal is 0V, the voltages at node A and node B are affected by the voltage division ratio, and the voltage division ratio is determined by the position of lead-out portion 210163. Different positions of lead-out portion 210163 result in different equivalent resistances between lead-out portion 210163 and first contact portion 210161 and second contact portion 210162.

[0125] Suppose the structure of connection portion 21016 is as Figure 7A shown. The first distance D1 between lead-out portion 210163 and first contact portion 210161 is 1 mm, the second distance D2 between lead-out portion 210163 and second contact portion 210162 is 3 mm, and the resistivity α is 1 kΩ / mm. Therefore, the resistance values of first resistor R1 and second resistor R2 are 1 kΩ and 3 kΩ respectively, and the total resistance R' is 1 kΩ + 3 kΩ = 4 kΩ.

[0126] See Figure 20 and Figure 21, at time T1, the voltage of the power signal received by the first contact portion 210161 is 3.3V, and the voltage of the chip select signal received by the second contact portion 210162 is 0V. At this time, since the power supply has just started and the capacitor C has not been charged, the voltage of node A is 0V. Since the proportion of the second resistor R2 in the total resistance is 3kΩ / 4kΩ = 0.75, the voltage of node B is 3.3V 0.75, that is, about 2.5V. At this time, the voltage of node B is greater than the voltage of node A, and the first transistor Q1 is turned on. The voltage of node E is the voltage of node B, that is, the chip select port of the function module 21021 receives a voltage of 2.5V.

[0127] At the time of T1 - T2, after the power supply voltage stabilizes, the voltage of node B is 3.3V 0.75, that is, about 2.5V. Since the diode D will generate a voltage drop of 0.7V, the voltage of node A is obtained as (3.3V 0.75 - 0.7V), that is, about 1.8V. At this time, the voltage of node B is greater than the voltage of node A, and the first transistor Q1 is turned on. The voltage of node E is the voltage of node B, that is, the chip select port of the function module 21021 receives a voltage of 2.5V.

[0128] At time T2, the voltages of the power signal and the chip select signal received by the first contact portion 210161 and the second contact portion 210162 are both 3.3V. Therefore, the voltage of node B is 3.3V. Since the diode D will generate a voltage drop of 0.7V, the voltage of node A is (3.3V - 0.7V), that is, about 2.6V. The voltage of node B is greater than the voltage of node A, and the first transistor Q1 is turned on. The voltage of node E is the voltage of node B, that is, the chip select port of the function module 21021 receives a voltage of 3.3V.

[0129] At time T3, the voltage of the power signal received by the first contact portion 210161 is 3.3V, and the voltage of the chip select signal received by the second contact portion 210162 is 0V. Due to the charging effect of the capacitor C and the fact that the capacitor C cannot discharge (the floating gate is insulated and the diode D conducts unidirectionally), the charge of the capacitor C remains basically unchanged. Therefore, node A maintains 2.6V, while the voltage of node B is 3.3V 0.75, that is, about 2.5V. The voltage of node B is less than the voltage of node A, and the first transistor Q1 is turned off. The voltage of node E is the first reference voltage GND1.

[0130] At time T4, the voltages of the power signal and the chip select signal received by the first contact portion 210161 and the second contact portion 210162 are both 3.3V. Therefore, the voltage of node A is (3.3V - 0.7V), that is, approximately 2.6V, the voltage of node B is 3.3V, the voltage of node B is greater than the voltage of node A, the first transistor Q1 is turned on, and the voltage of node E is the voltage of node B, that is, the chip select port of the functional module 21021 receives a voltage of 3.3V.

[0131] At time T5, the voltage of the power signal received by the first contact portion 210161 is 3.3V, and the voltage of the chip select signal received by the second contact portion 210162 is 0V. The voltage of node A remains 2.6V, while the voltage of node B is 3.3V 0.75, that is, approximately 2.5V. The voltage of node B is less than the voltage of node A, the first transistor Q1 is turned off, and the voltage of node E is the first reference voltage GND1.

[0132] At time T6, the voltages of the power signal and the chip select signal are both 0V, node A remains 2.6V, the voltage of node B is 0V, the voltage of node B is less than the voltage of node A, the first transistor Q1 is turned off, and the voltage of node E is the first reference voltage GND1.

[0133] At time T7, the voltage of the power signal received by the first contact portion 210161 is 3.3V, and the voltage of the chip select signal received by the second contact portion 210162 is 0V. The voltage of node A remains 2.6V, the voltage of node B is 3.3V 0.75, that is, approximately 2.5V, the voltage of node B is less than the voltage of node A, the first transistor Q1 is turned off, and the voltage of node E is the first reference voltage GND1.

[0134] At time T8, the voltages of the power signal and the chip select signal received by the first contact portion 210161 and the second contact portion 210162 are both 3.3V. Therefore, the voltage of node A is (3.3V - 0.7V), that is, approximately 2.6V, the voltage of node B is 3.3V, the voltage of node B is greater than the voltage of node A, the first transistor Q1 is turned on, and the voltage of node E is the voltage of node B, that is, the chip select port of the functional module 21021 receives a voltage of 3.3V.

[0135] To ensure that the functional module 21021 can obtain the minimum operating voltage normally when the chip select signal is at a low level and the equivalent resistance divides the voltage. The condition should be satisfied: the maximum power supply voltage Voltage division ratio >= the minimum operating voltage of the functional module 21021. For example, if the minimum operating voltage of the functional module 21021 is 2.1V, then the voltage of node B should be greater than or equal to 2.1V.

[0136] In addition, the first transistor Q1 needs to be able to control the conduction and cut-off of the signal according to the high-level effective characteristic of the chip select signal. Then, the voltage of node B needs to be <= the voltage when the capacitor C is fully charged, that is, 3.3V - 0.7V (using the diode D to step down the voltage). Therefore, the voltage of node B should be between 2.1V and 2.6V. From this, the resistance ratio of the first resistor R1 and the second resistor R2 is determined. For example, if the voltage of node B selected above is 2.5V, the voltage division ratio can be obtained: 3.3V / 2.5V is approximately 0.75, and from this, the resistance values of the first resistor R1 and the second resistor R2 are determined.

[0137] It can be understood that in the above embodiment, the second port is the chip select port. For the sake of easy understanding, below, taking the clock port (the second port is the clock port) as an example, Figure 19 the working principle of the shown circuit is exemplarily described again. It can be understood that when the second port is the clock port, the second signal is the clock signal.

[0138] Specifically, when the received clock signal is 0V, the voltages of node A and node B are affected by the voltage division ratio, and the voltage division ratio is determined by the position of the lead-out part 210163. The position of the lead-out part 210163 is different, and the equivalent resistances of the lead-out part 210163 and the first contact part 210161, the second contact part 210162 are also different.

[0139] Suppose the structure of the connecting part 21016 is as Figure 7A shown. The first distance D1 between the lead-out part 210163 and the first contact part 210161 is 1mm, the second distance D2 between the lead-out part 210163 and the second contact part 210162 is 3mm, and the resistivity α is 1kΩ / mm. Therefore, the resistance values of the first resistor R1 and the second resistor R2 are 1 kΩ and 3 kΩ respectively, and the total resistance R' is 1kΩ + 3kΩ = 4kΩ.

[0140] Refer to Figure 22 and Figure 23 , when the power supply is just started, the voltage of the power supply signal received by the first contact part 210161 is 3.3V, and the voltage of the clock signal received by the second contact part 210162 is 0V. At this time, since the power supply is just started and the capacitor C has not been charged yet, the voltage of node A is 0V. Since the proportion of the second resistor R2 in the total resistance is 3kΩ / 4kΩ = 0.75, the voltage of node B is 3.3V × 0.75, that is, approximately 2.5V. At this time, the voltage of node B is greater than the voltage of node A, the first transistor Q1 is turned on, and the voltage of node E is the voltage of node B, that is, the clock port of the functional module 21021 receives a voltage of 2.5V.

[0141] When the power supply voltage is stable and the clock signal is at a low level, the voltage of the power supply signal received by the first contact portion 210161 is 3.3V, and the voltage of the clock signal received by the second contact portion 210162 is 0V. The voltage of node B is 3.3V 0.75, that is, approximately 2.5V. Since the diode D generates a voltage drop of 0.7V, the voltage of node A is obtained as (3.3V 0.75 - 0.7V), that is, approximately 1.8V. At this time, the voltage of node B is greater than the voltage of node A, and the first transistor Q1 is turned on. The voltage of node E is the voltage of node B, that is, the clock port of the functional module 21021 receives a voltage of 2.5V. During this process, the capacitor C is charged.

[0142] When the capacitor C is fully charged and the clock signal is at a high level, the voltages of the power supply signal and the clock signal received by the first contact portion 210161 and the second contact portion 210162 are both 3.3V. Therefore, the voltage of node A is (3.3V - 0.7V), that is, approximately 2.6V, the voltage of node B is 3.3V, the voltage of node B is greater than the voltage of node A, the first transistor Q1 is turned on, and the voltage of node E is the voltage of node B, that is, the clock port of the functional module 21021 receives a voltage of 3.3V.

[0143] When the capacitor C is fully charged and the clock signal is at a low level, the voltage of the power supply signal received by the first contact portion 210161 is 3.3V, and the voltage of the clock signal received by the second contact portion 210162 is 0V. Due to the charging effect of the capacitor C and the fact that the capacitor C cannot discharge (the floating gate is insulated and the diode D conducts unidirectionally), the charge of the capacitor C remains basically unchanged. Therefore, node A maintains 2.6V, while the voltage of node B is 3.3V 0.75, that is, approximately 2.5V. The voltage of node B is less than the voltage of node A, the first transistor Q1 is turned off, and the voltage of node E is the first reference voltage GND1.

[0144] When the voltages of the power supply signal and the clock signal are both 0V, node A maintains 2.6V, the voltage of node B is 0V, the voltage of node B is less than the voltage of node A, the first transistor Q1 is turned off, and the voltage of node E is the first reference voltage GND1.

[0145] When the power supply starts again next time and the clock signal is at a low level, node A maintains 2.6V, and the voltage of node B is 3.3V 0.75, that is, approximately 2.5V. The voltage of node B is less than the voltage of node A, the first transistor Q1 is turned off, and the voltage of node E is the first reference voltage GND1.

[0146] When the power supply is restarted next time and the clock signal is at a high level, the voltages of the power supply signal received by the first contact portion 210161 and the second contact portion 210162 and the voltage of the clock signal are both 3.3V. Therefore, the voltage of node A is (3.3V - 0.7V), that is, approximately 2.6V, the voltage of node B is 3.3V, the voltage of node B is greater than the voltage of node A, the first transistor Q1 is turned on, and the voltage of node E is the voltage of node B, that is, the clock port of the function module 21021 receives a voltage of 3.3V.

[0147] That is to say, when the power supply is just started, since the capacitor C has not been charged and the received clock signal is at a low level, the first transistor Q1 is turned on; when the capacitor C is fully charged and the received clock signal is at a high level, the first transistor Q1 is turned on; when the received clock signal is at a low level, the first transistor Q1 is turned off.

[0148] See Figure 24 , which is a schematic circuit structure diagram of a chip provided by an embodiment of the present application. The difference between the embodiment of the present application and the Figure 19 shown embodiment is that the switching unit includes two transistors, namely the second transistor Q2 (for example, it can be a PMOS transistor) and the third transistor Q3 (for example, it can be a PMOS transistor).

[0149] Specifically, the first end of the second transistor Q2 (i.e., the first end of the switching unit) is electrically connected to the lead-out portion 210163, and the control end of the second transistor Q2 (i.e., the control end of the switching unit) is electrically connected to the node between the unidirectional conduction device and the capacitor C. For the third transistor Q3, the first end of the third transistor Q3 (i.e., the first end of the switching unit) is electrically connected to the lead-out portion 210163, the second end of the third transistor Q3 (i.e., the second end of the switching unit) is electrically connected to the second port of the function module 21021, and the control end of the third transistor Q3 is electrically connected to the second end of the second transistor Q2.

[0150] In the embodiment of the present application, the second transistor Q2 is configured to: when the voltage at the first end of the second transistor Q2 is less than the voltage at the control end of the second transistor Q2, the second transistor Q2 is turned off; when the voltage at the first end of the second transistor Q2 is greater than the voltage at the control end of the second transistor Q2, the second transistor Q2 is turned on. The third transistor Q3 is configured to: when the voltage at the first end of the third transistor Q3 is less than the voltage at the control end of the third transistor Q3, the third transistor Q3 is turned off; when the voltage at the first end of the third transistor Q3 is greater than the voltage at the control end of the third transistor Q3, the third transistor Q3 is turned on.

[0151] In the normal working state, the conduction of the second transistor Q2 can ensure that electric energy flows from the capacitor C to the load. Once the current flows in the reverse direction, the second transistor Q2 will turn off, preventing the energy in the capacitor C from flowing back to the power supply or other circuit parts, thereby maintaining the electric energy in the capacitor. Additionally, when the second signal is at a high level, the third transistor Q3 needs to output a relatively large amount of electric energy to the second port of the functional module 21021. Suppose a unit of electric energy is released at node A. After passing through the second transistor Q2, it becomes 5a units of electric energy, and then after passing through Q2 again, it becomes 10a units of electric energy. Therefore, the two transistors can further prevent the loss of electric energy in the capacitor C.

[0152] Regarding the specific content of the embodiments of the present application, reference can be made to the descriptions of other embodiments in the foregoing. For the sake of brevity of expression, it will not be elaborated herein.

[0153] See Figure 25 , which is a schematic diagram of the circuit structure of a chip provided by the embodiments of the present application. The difference between the embodiments of the present application and Figure 16 the embodiment shown is that the comparison circuit includes a comparator B1. Specifically, the first input terminal of the comparator B1 (i.e., the input terminal of the comparison circuit) is electrically connected to the lead-out portion 210163, the second input terminal of the comparator B1 is used to receive the second target voltage RE, and the output terminal of the comparator B1 (i.e., the output terminal of the comparison circuit) is electrically connected to the second port of the functional module 21021.

[0154] In the embodiments of the present application, the first contact portion 210161 and the second contact portion 210162 respectively receive the first signal and the second signal, and the lead-out portion 210163 transmits the superimposed signal composed of the first signal and the second signal to the first input terminal of the comparator B1. The comparator B1 compares the voltage of the superimposed signal with the set second target voltage RE. The magnitude of the second target voltage RE satisfies the condition: "When the first signal is at a high level and the second signal is at a low level, the voltage of the superimposed signal" < the second target voltage RE < "When the first signal is at a high level and the second signal is at a high level, the voltage of the superimposed signal".

[0155] Further, when the voltage of the superimposed signal is less than the second target voltage RE, the output terminal of comparator B1 outputs a low level. That is, when the first signal is at a high level and the second signal is at a low level, the second parsing signal is at a low level. When the voltage of the superimposed signal is greater than the second target voltage RE, the output terminal of comparator B1 outputs a high level. That is, when the first signal is at a high level and the second signal is at a high level, the second parsing signal is at a high level. That is to say, through the above setting of the second target voltage RE, it can be ensured that the second parsing signal and the second signal have the same level state, and thus the function matching the second signal can be realized through the second parsing signal. In addition, when the first signal is at a low level, the functional module 21021 usually does not work, so there is no need to make a judgment.

[0156] For the sake of easy understanding, taking the second port as the chip select port as an example, the Figure 25 working principle of the shown circuit will be exemplarily described. It can be understood that when the second port is the chip select port, the second signal is the chip select signal.

[0157] Suppose the structure of the connecting part 21016 is as Figure 7A shown. The first distance D1 between the leading-out part 210163 and the first contact part 210161 is 1 mm, the second distance D2 between the leading-out part 210163 and the second contact part 210162 is 3 mm, and the resistivity α is 1 kΩ / mm. Therefore, the resistance values of the first resistor R1 and the second resistor R2 are 1 kΩ and 3 kΩ respectively, and the total resistance R’ is 1 kΩ + 3 kΩ = 4 kΩ.

[0158] The first contact part 210161 and the second contact part 210162 respectively receive the power supply signal and the chip select signal, and the leading-out part 210163 transmits the superimposed signal composed of the power supply signal and the chip select signal to the first input terminal of comparator B1. When the voltage of the power supply signal is 3.3 V and the voltage of the chip select signal is 0 V, since the proportion of the second resistor R2 in the total resistance is 3 kΩ / 4 kΩ = 0.75, the voltage of the superimposed signal is 3.3 V × 0.75, that is, about 2.5 V; when the voltage of the power supply signal is 3.3 V and the voltage of the chip select signal is 3.3 V, the voltage of the superimposed signal is 3.3 V. Therefore, a certain value between 2.5 V and 3.3 V can be selected for the second target voltage RE.

[0159] For example, the second target voltage RE is 2.6 V. When the voltage of the power supply signal is 3.3 V and the voltage of the chip select signal is 0 V, the voltage of the superimposed signal is 3.3 V 0.75, which is approximately 2.5V. Therefore, the voltage of the superimposed signal is less than the second target voltage RE, and the output terminal of comparator B1 outputs a low level, that is, the second parsing signal is at a low level. When the voltage of the power supply signal is 3.3V and the voltage of the chip select signal is 3.3V, the voltage of the superimposed signal is 3.3V. Therefore, the voltage of the superimposed signal is greater than the second target voltage RE, and the output terminal of comparator B1 outputs a high level, that is, the second parsing signal is at a high level.

[0160] For the specific content of the embodiments of the present application, reference may be made to the descriptions of other embodiments above. For the sake of brevity, it will not be repeated here.

[0161] In some possible implementation manners, the parsing circuit setting may be integrated inside the functional module 21021 or may be arranged outside the functional module 21021 in the form of a peripheral circuit. The embodiments of the present application do not make specific limitations thereto.

[0162] Corresponding to the above embodiments, the embodiments of the present application further provide a replaceable accessory, which includes the chip 21 described in any one of the above embodiments.

[0163] For the specific content of the embodiments of the present application, reference may be made to the descriptions of the above embodiments. For the sake of brevity, it will not be repeated here.

[0164] In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent the situation where A exists alone, A and B exist simultaneously, or B exists alone. Where A and B may be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one of the following" and its similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, and c may represent: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, and c may be single or multiple.

[0165] Those of ordinary skill in the art can realize that the units and algorithm steps described in the embodiments disclosed herein can be implemented by a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present application.

[0166] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0167] In several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the essence of the technical solution of the present application, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0168] The above is only the specific implementation manner of the present application. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application and should be covered by the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A chip for communicating with a host device, characterized in that: The chip includes a connecting portion, and the connecting portion includes: A first contact portion, used to be electrically connected to a first port of the host device and receive a first signal output by the first port of the host device, wherein the first signal is a power signal; A second contact portion, used to be electrically connected to a second port of the host device and receive a second signal output by the second port of the host device, wherein the second signal is a non-power signal; A lead-out portion, electrically connected to the first contact portion and the second contact portion respectively, the lead-out portion is used to output a superposition signal of the first signal and the second signal, and control a functional module in the chip through the superposition signal to implement a function matching the first signal and the second signal; The equivalent resistance between the first contact portion and the lead-out portion is smaller than the equivalent resistance between the second contact portion and the lead-out portion.

2. The chip according to claim 1, characterized in that: The connecting portion comprises: A conductive region, wherein the first contact portion, the second contact portion and the lead-out portion are located in the conductive region, and a distance between the first contact portion and the lead-out portion is smaller than a distance between the second contact portion and the lead-out portion.

3. The chip according to claim 2, characterized in that: The conductive area comprises: a first conductive sub-region, wherein the first contact portion and the second contact portion are located in the first conductive sub-region; a second conductive electron region, wherein the lead-out portion is located in the second conductive electron region; The resistivity of the first conductive sub-region is smaller than the resistivity of the second conductive sub-region.

4. The chip according to claim 3, characterized in that: The first conductive sub-region comprises: a third conductive electron region, wherein the first contact portion is located in the third conductive electron region; a fourth conductive electron region, wherein the second contact portion is located in the fourth conductive electron region; The resistivity of the third conductive sub-region and the resistivity of the fourth conductive sub-region are the same or different.

5. The chip according to claim 2, characterized in that: The resistivity of the first contact portion and / or the second contact portion is smaller than the resistivity of the conductive region.

6. The chip according to claim 1, characterized in that: The connecting portion comprises: a first conductive path, the first contact portion being electrically connected to the lead-out portion through the first conductive path; a second conductive path, the second contact portion being electrically connected to the lead-out portion through the second conductive path; The length of the first conductive path is smaller than the length of the second conductive path, and / or the resistivity of the first conductive path is smaller than the resistivity of the second conductive path.

7. The chip according to claim 6, characterized in that: The connecting portion further comprises: An insulating region is disposed around the first conductive path and the second conductive path, wherein a color and / or a texture of the insulating region matches the first conductive path and the second conductive path.

8. The chip according to claim 1, characterized in that: The second signal is a chip selection signal, a clock signal or a data signal.

9. The chip according to claim 1, characterized in that: The connection part and the functional module are arranged on the same layer of the chip, and the connection part is electrically connected to the functional module through a wire.

10. The chip according to claim 1, characterized in that: The connection part and the functional module are arranged on different layers of the chip, and the connection part is electrically connected to the functional module through a via.

11. A chip for communicating with a host device, characterized in that: The chip comprises: a connecting portion, wherein the connecting portion comprises: A first contact portion, used to be electrically connected to a first port of the host device and receive a first signal output by the first port of the host device, wherein the first signal is a power signal; A second contact portion, used to be electrically connected to a second port of the host device and receive a second signal output by the second port of the host device, wherein the second signal is a non-power signal; A lead-out portion, electrically connected to the first contact portion and the second contact portion respectively, the lead-out portion is used to output a superposition signal of the first signal and the second signal, and control a functional module in the chip through the superposition signal to implement a function matching the first signal and the second signal; When the first signal is at a high level and the second signal is at a low level, the voltage of the superimposed signal is greater than or equal to the minimum operating voltage of the functional module.

12. The chip according to claim 11, characterized in that: The chip further comprises: an analysis circuit, wherein an input end of the analysis circuit is electrically connected to the lead-out portion, and the analysis circuit is used to analyze the superimposed signal and output a first analysis signal at a first output end of the analysis circuit and output a second analysis signal at a second output end of the analysis circuit; The first port of the functional module is electrically connected to the first output terminal of the analytical circuit, and the first port of the functional module is used to receive the first analytical signal output by the first output terminal of the analytical circuit, and implement a function matching the first signal through the first analytical signal; The second port of the functional module is electrically connected to the second output end of the analysis circuit, and the second port of the functional module is used to receive the second analysis signal output by the second output end of the analysis circuit, and realize the function matching the second signal through the second analysis signal.

13. The chip according to claim 12, characterized in that: The input end of the analysis circuit is electrically connected to the first output end of the analysis circuit, and the first analysis signal outputted by the first output end of the analysis circuit is the superposition signal; The analysis circuit comprises a comparison circuit, the input end of the comparison circuit is electrically connected to the lead-out portion, the output end of the comparison circuit is electrically connected to the second port of the functional module, the input end of the comparison circuit is used to receive the superimposed signal, the output end of the comparison circuit is used to output the second analysis signal, the input end of the comparison circuit is the input end of the analysis circuit, and the output end of the comparison circuit is the second output end of the analysis circuit; When the first signal is at a high level and the second signal is at a low level, the second analysis signal is at a low level; when the first signal is at a high level and the second signal is at a high level, the second analysis signal is at a high level.

14. The chip according to claim 13, characterized in that: The comparison circuit comprises: a voltage output unit, wherein the output end of the voltage output unit is used to output a first target voltage; when the first signal is at a high level and the second signal is at a low level, the voltage of the superimposed signal is less than the first target voltage; when the first signal is at a high level and the second signal is at a high level, the voltage of the superimposed signal is greater than the first target voltage; a switch unit, wherein a first end of the switch unit is electrically connected to the lead-out portion, a second end of the switch unit is electrically connected to the second port of the functional module, a control end of the switch unit is electrically connected to the output end of the voltage output unit, a first end of the switch unit is an input end of the comparison circuit, and a second end of the switch unit is an output end of the comparison circuit; a resistive device, wherein a first end of the resistive device is electrically connected to a second end of the switch unit, and a second end of the resistive device is connected to a first reference voltage; Among them, when the voltage of the first end of the switch unit is less than or equal to the voltage of the control end of the switch unit, the switch unit is disconnected, and the second end of the switch unit outputs a low level; when the voltage of the first end of the switch unit is greater than the voltage of the control end of the switch unit, the switch unit is turned on, and the second end of the switch unit outputs a high level.

15. The chip according to claim 14, characterized in that: The voltage output unit comprises: A unidirectional conductive device, wherein a first end of the unidirectional conductive device is electrically connected to the lead-out portion, and the first end of the unidirectional conductive device is unidirectionally conductive to the second end; A capacitive device, wherein the first end of the capacitive device is electrically connected to the second end of the unidirectional conductive device, the second end of the capacitive device is connected to a second reference voltage, and when the capacitive device is fully charged, the first end of the capacitive device outputs the first target voltage, and the first end of the capacitive device is the output end of the voltage output unit.

16. The chip according to claim 14, characterized in that: The switch unit comprises: a first transistor, wherein a first end of the first transistor is electrically connected to the lead-out portion, a second end of the first transistor is electrically connected to a second port of the functional module, a control end of the first transistor is electrically connected to a node between the unidirectional conductive device and the capacitive device, and a first end, a second end and a control end of the first transistor are respectively a first end, a second end and a control end of the switch unit; When the voltage at the first end of the first transistor is less than the voltage at the control end of the first transistor, the first transistor is turned off; when the voltage at the first end of the first transistor is greater than the voltage at the control end of the first transistor, the first transistor is turned on.

17. The chip according to claim 14, characterized in that: The switch unit comprises: a second transistor, wherein the first end of the second transistor is electrically connected to the lead-out portion, the control end of the second transistor is electrically connected to a node between the unidirectional conductive device and the capacitive device, the first end of the second transistor is the first end of the switch unit, and the control end of the second transistor is the control end of the switch unit; wherein when the voltage of the first end of the second transistor is less than the voltage of the control end of the second transistor, the second transistor is turned off; and when the voltage of the first end of the second transistor is greater than the voltage of the control end of the second transistor, the second transistor is turned on; A third transistor, wherein the first end of the third transistor is electrically connected to the lead-out portion, the second end of the third transistor is electrically connected to the second port of the functional module, the control end of the third transistor is electrically connected to the second end of the second transistor, the first end of the third transistor is the first end of the switch unit, and the second end of the third transistor is the second end of the switch unit; wherein when the voltage of the first end of the third transistor is less than the voltage of the control end of the third transistor, the third transistor is turned off; and when the voltage of the first end of the third transistor is greater than the voltage of the control end of the third transistor, the third transistor is turned on.

18. The chip according to claim 13, characterized in that: The comparison circuit comprises: A comparator, wherein a first input terminal of the comparator is electrically connected to the lead-out portion, a second input terminal of the comparator is used to receive a second target voltage, an output terminal of the comparator is electrically connected to a second port of the functional module, the first input terminal of the comparator is an input terminal of the comparison circuit, and the output terminal of the comparator is an output terminal of the comparison circuit; Among them, when the first signal is a high level and the second signal is a low level, the voltage at the first input terminal of the comparator is less than the second target voltage, and the output terminal of the comparator outputs a low level; when the first signal is a high level and the second signal is a high level, the voltage at the first input terminal of the comparator is greater than or equal to the second target voltage, and the output terminal of the comparator outputs a high level.

19. The chip according to claim 12, characterized in that: The analysis circuit is arranged inside or outside the functional module.

20. A replaceable accessory, characterized in that: A chip comprising any one of claims 1 to 19.

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