Semiconductor device thermal annealing process optimization method, resistance prediction method and system

Abstract

The present invention discloses a method for optimizing the thermal annealing process of semiconductor devices, a resistance prediction method, and a system thereof. The present invention dynamically corrects the correction exponent in the thermal budget model and the baseline thermal budget parameter in the activation rate model by minimizing matching deviations, enabling the model to adapt to different thermal annealing conditions. By comparing the corrected activation rate with the target value in real time, the thermal annealing process parameters can be directly adjusted. Finally, by integrating physical models (the corrected thermal budget model and the corrected activation rate model) with a data-driven approach to achieve resistance prediction, the computational complexity and time cost of traditional pure physical simulations are significantly reduced, overcoming the reliance of traditional machine learning models on large-scale datasets and addressing the bottlenecks of traditional methods in terms of efficiency, cost, accuracy, and generalization. This provides an efficient, low-cost, and highly reliable process optimization and performance prediction solution for advanced semiconductor manufacturing.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor device preparation, and in particular relates to a semiconductor device thermal annealing process optimization method, a resistance prediction method and a system thereof. Background Art

[0002] In the field of semiconductor device manufacturing, the performance and reliability of silicon-based semiconductor devices depend to a large extent on the activation degree and distribution of dopant impurities. Among them, the thermal annealing process, as an important process step for activating dopant impurities and repairing lattice damage, plays a decisive role in the final performance of the device. Traditional thermal annealing process parameters (such as annealing temperature, time, heating and cooling rates, etc.) are usually determined based on experience or single variable control methods, resulting in problems such as insufficient impurity activation, residual lattice damage, and unstable device electrical performance in the actual production process. In addition, due to the nonlinear and multivariable coupling characteristics of the relationship between process parameters and device electrical performance, traditional prediction methods based on empirical formulas or single physical models cannot accurately predict the resistance characteristics of the doped region, limiting the accuracy and efficiency of semiconductor device manufacturing.

[0003] Traditionally, optimization of doped semiconductor thermal annealing processes and determination of resistance have relied on classical semiconductor process simulations (such as TCAD simulations) or extensive experimental testing. While these methods can provide results with a certain degree of accuracy, they also suffer from significant shortcomings: physical simulations are computationally complex and time-consuming, and struggle to replicate realistic process conditions, resulting in low simulation accuracy. While experimental measurement methods offer high reliability, they are costly and time-consuming, severely limiting the efficiency and cost-effectiveness of device process optimization.

[0004] In recent years, with the widespread application of machine learning and data-driven methods in semiconductor process and device modeling, researchers have begun to use data-driven methods to predict the relationship between process parameters and device performance. However, while purely data-driven methods can quickly generate predictions, they require a large amount of high-quality experimental data to train the model, resulting in high costs and a long modeling cycle. Furthermore, due to the lack of support from physical models, the predictions have poor generalization capabilities and are unable to cover process ranges not covered by experimental data. This is especially true as device sizes continue to shrink and their physical properties become more complex, placing higher demands on the robustness and generalization capabilities of the prediction models.

[0005] Therefore, there is an urgent need to establish a thermal annealing process parameter optimization method that is efficient, accurate, and has good generalization capabilities and can be implemented with only a small amount of experimental data to meet the needs of rapid development of advanced semiconductor manufacturing processes and agile optimization of process parameters. Summary of the Invention

[0006] The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art and to provide a method for optimizing the thermal annealing process of a semiconductor device, a resistance prediction method and a system thereof.

[0007] The present invention is implemented as follows. In a first aspect, the present invention provides a method for optimizing a thermal annealing process of a semiconductor device, wherein the semiconductor device is based on a silicon-doped semiconductor. The method comprises:

[0008] Acquire multiple pairs of data, each pair of data coming from two semiconductor devices under the same doping conditions but different thermal annealing conditions, including two sets of labeled thermal annealing process data, each set of thermal annealing process data including doping conditions and thermal annealing conditions, and the labels being the resistance values ​​of the semiconductor devices under the current thermal annealing process;

[0009] For each pair of data, two sets of thermal annealing process data are input into a thermal budget model to obtain two thermal annealing thermal budget values; the two thermal annealing thermal budget values ​​are input into an activation rate model to obtain two dopant impurity activation rates; based on the two dopant impurity activation rates and their corresponding semiconductor device resistance values, a matching deviation between the dopant impurity activation rate and the semiconductor device resistance value is calculated; the matching deviations of each pair of data are accumulated to obtain a total matching deviation;

[0010] Find a set of correction exponents of the thermal budget model and baseline thermal budget parameters of the activation rate model to minimize the total matching deviation;

[0011] The correction index and characteristic thermal budget parameters found are respectively introduced into the thermal budget model and the activation rate model to obtain the corrected thermal budget model and the corrected activation rate model;

[0012] The real-time acquired thermal annealing process data is input into a modified thermal budget model to obtain a thermal annealing modified thermal budget value; the thermal annealing modified thermal budget value is input into a modified activation rate model to obtain a doping impurity modified activation rate; and the thermal annealing process of the semiconductor device is optimized based on the comparison result of the doping impurity modified activation rate and the target value.

[0013] Preferably, the doping condition is the activation energy of the doping element; the thermal annealing condition is the thermal annealing temperature curve;

[0014] Preferably, the calculation function of the thermal budget model is as follows:

[0015] (Formula 1)

[0016] in, At the reference temperature The equivalent annealing time under , i.e. the thermal budget; is the activation energy of the doping element, m is the correction index, k is the Boltzmann constant, Over time Varying thermal annealing temperature.

[0017] Preferably, the calculation function of the activation rate model is as follows:

[0018] (Equation 2)

[0019] in is the activation rate of doping impurities, Thermal budget for thermal annealing, is the benchmark thermal budget, which is the thermal annealing thermal budget value when the activation rate of dopant impurities in silicon-based doped semiconductor is 63.2%.

[0020] Preferably, the matching deviation between the activation rate of the doping impurities and the resistance value of the semiconductor device is calculated as follows:

[0021] (Equation 3)

[0022] in represents the matching deviation between the activation rate of the doping impurities and the resistance value of the semiconductor device for the i-th pair of data; 、 They represent the two doping impurity activation rates obtained after the two sets of thermal annealing process data of the i-th pair are processed by the thermal budget model and the activation rate model; 、 They respectively represent the resistance values ​​of the semiconductor device corresponding to the two sets of thermal annealing process data of the i-th pair of data.

[0023] In a second aspect, the present invention provides a semiconductor device thermal annealing process optimization system, comprising:

[0024] Data acquisition module, responsible for acquiring thermal annealing process data of semiconductor devices in real time;

[0025] The first calculation module is responsible for inputting the real-time acquired thermal annealing process data into the modified thermal budget model to obtain the thermal annealing modified thermal budget value;

[0026] The second calculation module is responsible for inputting the thermal annealing correction thermal budget value into the correction activation rate model to obtain the doping impurity correction activation rate;

[0027] The optimization module is responsible for optimizing the thermal annealing process of semiconductor devices based on the comparison results of the activation rate corrected by the doping impurities and the target value.

[0028] In a third aspect, the present invention provides a method for predicting the resistance of a semiconductor device, wherein the semiconductor device is based on a silicon-doped semiconductor, the method comprising:

[0029] Obtaining thermal annealing process data of a semiconductor device and corresponding semiconductor device resistance;

[0030] The modified thermal budget model and the modified activation rate model are used to obtain the modified activation rate of doping impurities for the thermal annealing process data;

[0031] The training data set is constructed by using the activation rate of the doping impurity correction and the doping dose of the doping impurity, and the corresponding semiconductor device resistance value is used as a label;

[0032] Building a machine learning model and training it using training data; the input of the machine learning model is the corrected activation rate of the doping impurity and the doping dose of the doping impurity, and the output is the resistance value of the semiconductor device;

[0033] Use the trained machine learning model to predict the resistance of semiconductor devices.

[0034] Preferably, the method further includes performing standardized data preprocessing on the corrected activation rate of the doping impurities and the doping dose of the doping impurities.

[0035] Preferably, the machine learning model adopts an AdaBoost model with SVM as the base classifier.

[0036] In a fourth aspect, the present invention provides a semiconductor device resistance prediction system, comprising:

[0037] A data acquisition module is responsible for acquiring thermal annealing process data of semiconductor devices and doping dosage of doping impurities;

[0038] The resistance prediction module is responsible for inputting the thermal annealing process data of the semiconductor device and the doping dosage of the doped impurities into the trained machine learning model and outputting the predicted resistance value of the semiconductor device.

[0039] The present invention constructs a modified thermal budget model and a modified activation rate model, and realizes resistance prediction by fusing physical models with data-driven methods, significantly reducing the computational complexity and time cost of traditional pure physical simulation, and overcoming the traditional machine learning model's dependence on large-scale data sets. The combination of the two achieves the synergistic advantages of high precision, low data requirements, and strong generalization capabilities.

[0040] This invention dynamically modifies the correction exponent m in the thermal budget model and the baseline thermal budget parameter τ in the activation rate model by minimizing matching deviations, enabling the model to adapt to different thermal annealing conditions. When the actual thermal annealing process deviates from the initial model, the system automatically adjusts the parameters to minimize the deviation by calculating the total matching deviation in real time, thereby optimizing the correspondence between the dopant activation rate and the resistance value of the semiconductor device. This process significantly improves the dynamic responsiveness and process stability of process parameter optimization.

[0041] The present invention can directly adjust the thermal annealing process parameters and achieve closed-loop optimization by comparing the activation rate corrected by doping impurities with the target value in real time.

[0042] In summary, the present invention solves the bottlenecks of traditional methods in efficiency, cost, accuracy and generalization through the deep integration of physical model correction and data-driven, and provides an efficient, low-cost and highly reliable process optimization and performance prediction solution for advanced semiconductor manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 This is a flow chart of a method for optimizing a thermal annealing process for a semiconductor device provided by an embodiment of the present invention.

[0045] Figure 2 This is a flow chart of a resistance prediction method for a semiconductor device provided by an embodiment of the present invention.

[0046] Figure 3 This is a flow chart of a semiconductor device thermal annealing process optimization system provided by an embodiment of the present invention.

[0047] Figure 4 This is a flow chart of a resistance prediction system for a semiconductor device provided by an embodiment of the present invention.

[0048] Figure 5 This is a comparison result between the resistance prediction value provided by the embodiment of the present invention and the experimental value. DETAILED DESCRIPTION

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0050] The terms "including," "having," and any variations thereof, as used in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to the process, method, product, or apparatus.

[0051] Optimizing the thermal annealing process for doped semiconductors and determining resistance typically relies on classic semiconductor process simulation (such as TCAD simulation) or direct extensive experimental testing. For example, existing physical simulation prediction methods (such as TCAD simulation) are complex and computationally intensive, resulting in long prediction times, hindering rapid process optimization, and exhibiting low accuracy. Traditional purely data-driven methods (such as pure machine learning models) rely heavily on the quality and scale of datasets. However, for real-world experimental data, the complex processes, high costs, and long cycles mean that experimental data cannot meet the data scale required for data-driven modeling. Furthermore, when process parameter variations exceed the range covered by the training data, the model often struggles to provide accurate predictions and lacks the ability to generalize to unseen scenarios.

[0052] As can be seen from the above defects, the prior art has technical problems such as difficulty in optimizing the thermal annealing process of doped semiconductors and difficulty in predicting resistance.

[0053] Based on this, see Appendix Figure 1 An embodiment of the present invention provides a method for optimizing the thermal annealing process of a semiconductor device. The semiconductor device is based on a silicon-doped semiconductor. A silicon-doped semiconductor is a type of semiconductor whose electrical properties are altered by artificially introducing doping impurities into the silicon (Si) substrate. These doping impurities can include Group V elements (such as phosphorus (P) and arsenic (As)), Group III elements (such as boron (B) and aluminum (Al), and so on. For example, the metal-oxide-semiconductor field-effect transistor (MOSFET). The preparation of MOSFET usually starts with RCA chemical cleaning of the silicon wafer to remove organic and metal contamination and expose the atomically flat silicon surface; then, a field oxide layer several hundred nanometers thick is grown in the inactive area by wet or dry oxidation for electrical isolation; then, well regions and shallow source / drain regions (LDD) are formed by photolithography and ion implantation, and a 5-20 nm gate oxide layer is generated by dry oxidation at 800-1000°C; then, polysilicon or metal gate material is deposited, etched into the gate by photolithography, and sidewall spacers are formed on the gate side to control the subsequent deep implantation region; after the deep source / drain region is implanted or diffused by high-energy ion, thermal annealing must be performed to activate the doped impurities, repair the implantation damage and release the stress. Rapid thermal annealing (RTA, 900-1100°C, more than ten seconds) or furnace annealing (850-1100°C, several minutes to several hours) can be used, and the atmosphere is usually N2 or Ar; after annealing, the interconnect dielectric is deposited in sequence and CMP is performed. The wafer is then flattened, and vias and metallization layers, such as tungsten or copper, are formed. Finally, multiple layers of metal interconnects (aluminum or copper) are deposited, followed by photolithography and etching to create interconnect lines. A passivation layer is added, and wafer testing, dicing, and packaging are performed. Thermal annealing is a critical step in the MOSFET manufacturing process, as its activation efficiency directly affects threshold voltage, leakage current, carrier mobility, and device reliability.

[0054] Other silicon-doped semiconductor-based devices similar to MOSFET include: bipolar junction transistor (BJT), insulated gate bipolar transistor (IGBT), junction field effect transistor (JFET), Schottky diode (Schottky diode), thin-film transistor (TFT), silicon solar cell (Si Solar Cell), power LDMOS (Laterally Diffused MOS), and silicon-based photodiode / photodetector.

[0055] Specifically, the method comprises the following steps:

[0056] Step S1: Acquire multiple pairs of data; each pair of data is from two semiconductor devices with the same doping conditions but different thermal annealing conditions. The data includes two sets of labeled thermal annealing process data, each set of which includes the doping conditions and the thermal annealing conditions. The labels represent the resistance values ​​of the semiconductor device under the current thermal annealing process. Taking MOSFETs as an example, the resistance values ​​of various key regions of the MOSFET, such as the lightly doped drain (LDD), heavily doped source / drain regions, and polysilicon gate, significantly impact device electrical properties such as threshold voltage, off-state current, and saturation current. The resistance values ​​of these key regions are typically acquired through wafer acceptance testing (WAT). This process utilizes an integrated TLM structure: a series of metal electrodes with fixed widths and varying spacings are photolithographically formed in the test area. The resistance values ​​at each spacing are measured and a linear fit is performed on the resistance-spacing data. The slope of the fit is the sheet resistance (Ω / □), and the intercept reflects the contact resistance. Alternatively, a four-probe method can be used in the same WAT test to convert the measured resistance, probe spacing, and geometric parameters into sheet resistance. The thermal annealing process directly affects the activation rate of doped impurities, which in turn affects the resistance value. Within a certain thermal budget range, the resistance value decreases as the thermal annealing budget increases.

[0057] As an example, the doping condition is the activation energy of the doping element; and the thermal annealing condition is the thermal annealing temperature curve.

[0058] Step S2: For each pair of data, input two sets of thermal annealing process data into the thermal budget model to obtain two thermal annealing thermal budget values; input the two thermal annealing thermal budget values ​​into the activation rate model to obtain two doping impurity activation rates. 、 , i represents the i-th pair of data; according to the activation rates of the two doping impurities and their corresponding semiconductor device resistance values 、 Calculate the matching deviation between the activation rate of doping impurities and the resistance value of semiconductor devices ; Match the deviation of each pair of data Accumulate and get the total matching deviation .

[0059] In one embodiment, the calculation function of the thermal budget model is as follows:

[0060] (Formula 1)

[0061] in, At the reference temperature The equivalent annealing time under , i.e. the thermal budget; is the activation energy of the doping element, m is the correction index, k is the Boltzmann constant, Over time Varying thermal annealing temperature.

[0062] In one embodiment, the calculation function of the activation rate model is as follows:

[0063] (Equation 2)

[0064] in is the activation rate of doping impurities, t eq is the thermal annealing thermal budget, and τ is the benchmark thermal budget, for example, the thermal annealing thermal budget value when the doping impurity activation rate of the silicon-based doped semiconductor is 63.2%.

[0065] In one embodiment, the matching deviation between the activation rate of the doping impurities and the resistance value of the semiconductor device is The calculation of is as follows:

[0066] (Equation 3)

[0067] Specifically, the total matching deviation The calculation is as follows:

[0068] (Formula 4)

[0069] Where n is the total number of pairs of sample data collected.

[0070] Step S3, find a pair of thermal budget model correction index m and activation rate model reference thermal budget parameter τ, so that The value is the smallest.

[0071] Step S4: Substitute the found correction index m and characteristic thermal budget parameter τ into the thermal budget model and activation rate model respectively to obtain a corrected thermal budget model and a corrected activation rate model.

[0072] Step S5: inputting the real-time acquired thermal annealing process data into a modified thermal budget model to obtain a modified thermal budget for thermal annealing; inputting the modified thermal budget for thermal annealing into a modified activation rate model to obtain a modified activation rate for doping impurities.

[0073] Step S6: Optimize the thermal annealing process for the semiconductor device based on the comparison of the corrected activation rate of the impurity dopant with the target value. For example, during the preparation of ultra-shallow junctions, the thermal annealing thermal budget must be strictly controlled to control the diffusion of impurities. Increasing the peak temperature of the rapid thermal annealing process and increasing the heating rate can suppress the diffusion of impurities. Therefore, while ensuring that the activation rate meets the target, the thermal annealing process is optimized to suppress the diffusion of impurities and achieve the preparation of ultra-shallow junctions.

[0074] See attached Figure 2 This embodiment further provides a method for predicting the resistance of a semiconductor device, comprising:

[0075] Step S1: Build a training dataset

[0076] Obtaining thermal annealing process data of a semiconductor device and corresponding semiconductor device resistance;

[0077] The thermal annealing process data is subjected to a modified thermal budget model and a modified activation rate model to obtain a modified activation rate of doping impurities;

[0078] A training data set is constructed by using the activation rate of the doping impurities correction and the doping dose of the doping impurities, and the corresponding semiconductor device resistance value is used as a label.

[0079] Step S2: Build a machine learning model and train it using training data; the input of the machine learning model is the corrected activation rate of the doping impurities and the doping dose of the doping impurities, and the output is the resistance value of the semiconductor device.

[0080] Step S3: Use the trained machine learning model to predict the resistance of the semiconductor device.

[0081] One embodiment further includes performing standardized data preprocessing on the activation rate of the doping impurity correction and the doping dose of the doping impurity. As an example, the data preprocessing process may be as follows: the original data x is converted into a new value by subtracting its sample mean μ and dividing it by the standard deviation σ. The processed data distribution is centered at 0 and has a standard deviation of 1. Data preprocessing can eliminate the differences in the magnitude of different features and help the model converge faster.

[0082] The present invention experiments and debugs a variety of machine learning models, such as random forest model, support vector machine model, linear model, multi-layer perceptron model and other machine learning models. The final results show that the AdaBoost model with SVM as the base classifier has the fastest convergence speed and the highest prediction accuracy, so this model is adopted.

[0083] Figure 5 31 sets of test data are shown in the figure. The resistance prediction value predicted by this embodiment has an average prediction time of 0.1017s, and the error between the resistance prediction value and the experimental value is less than 1%.

[0084] The present invention only requires a small amount of experimental data (about 10 groups) to correct the thermal budget model and activation rate model. At the same time, the corrected activation rate can be combined with the doping dose of doped impurities to train the machine learning model, achieving low-cost, high-speed, and high-accuracy optimization of the thermal annealing process and resistance prediction of doped semiconductor devices.

[0085] Therefore, the present invention constructs a hybrid physical data-driven model consisting of a corrected thermal budget model, a corrected activation rate model, and a machine learning model, which is used to realize resistance prediction, significantly reducing the computational complexity and time cost of traditional pure physical simulation, and overcoming the traditional machine learning model's dependence on large-scale data sets. The combination of the two achieves the synergistic advantages of high precision, low data requirements, and strong generalization capabilities.

[0086] Finally, this embodiment also provides a semiconductor device thermal annealing process optimization system and a resistance prediction system.

[0087] See attached Figure 3 , semiconductor device thermal annealing process optimization system, including:

[0088] Data acquisition module, responsible for acquiring thermal annealing process data of semiconductor devices in real time;

[0089] The first calculation module is responsible for inputting the real-time acquired thermal annealing process data into the modified thermal budget model to obtain the thermal annealing modified thermal budget value;

[0090] The second calculation module is responsible for inputting the thermal annealing correction thermal budget value into the correction activation rate model to obtain the doping impurity correction activation rate;

[0091] The optimization module is responsible for optimizing the thermal annealing process of semiconductor devices based on the comparison results of the activation rate corrected by the doping impurities and the target value.

[0092] See attached Figure 4 , semiconductor device resistance prediction system, including:

[0093] A data acquisition module is responsible for acquiring thermal annealing process data of semiconductor devices and doping dosage of doping impurities;

[0094] The resistance prediction module is responsible for inputting the thermal annealing process data of the semiconductor device and the doping dosage of the doped impurities into the trained machine learning model and outputting the predicted resistance value of the semiconductor device.

[0095] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for optimizing a thermal annealing process of a semiconductor device, wherein the semiconductor device is based on a silicon-doped semiconductor, characterized in that: The method comprises: Acquire multiple pairs of data, each pair of data coming from two semiconductor devices under the same doping conditions but different thermal annealing conditions, including two sets of labeled thermal annealing process data, each set of thermal annealing process data including doping conditions and thermal annealing conditions, and the labels being the resistance values ​​of the semiconductor devices under the current thermal annealing process; For each pair of data, two sets of thermal annealing process data are input into a thermal budget model to obtain two thermal annealing thermal budget values; the two thermal annealing thermal budget values ​​are input into an activation rate model to obtain two dopant impurity activation rates; based on the two dopant impurity activation rates and their corresponding semiconductor device resistance values, a matching deviation between the dopant impurity activation rate and the semiconductor device resistance value is calculated; the matching deviations of each pair of data are accumulated to obtain a total matching deviation; Find a set of correction exponents of the thermal budget model and baseline thermal budget parameters of the activation rate model to minimize the total matching deviation; The correction index and characteristic thermal budget parameters found are respectively introduced into the thermal budget model and the activation rate model to obtain the corrected thermal budget model and the corrected activation rate model; The real-time acquired thermal annealing process data is input into a modified thermal budget model to obtain a thermal annealing modified thermal budget value; the thermal annealing modified thermal budget value is input into a modified activation rate model to obtain a doping impurity modified activation rate; and the thermal annealing process of the semiconductor device is optimized based on the comparison result of the doping impurity modified activation rate and the target value.

2. The method according to claim 1, characterized in that The doping condition is the activation energy of the doping element; and the thermal annealing condition is the thermal annealing temperature curve.

3. The method according to claim 2, characterized in that The calculation function of the thermal budget model is as follows: (Formula 1) in, At the reference temperature The equivalent annealing time under , i.e., the thermal budget; is the activation energy of the doping element, m is the correction index, k is the Boltzmann constant, Over time Varying thermal annealing temperature.

4. The method according to claim 3, characterized in that The calculation function of the activation rate model is as follows: (Equation 2) in is the activation rate of doping impurities, t eq is the thermal annealing thermal budget, and τ is the baseline thermal budget.

5. The method according to claim 1, characterized in that: The matching deviation between the activation rate of the doping impurities and the resistance value of the semiconductor device is calculated as follows: (Formula 3) in represents the matching deviation between the activation rate of the doping impurities and the resistance value of the semiconductor device for the i-th pair of data; 、 They represent the two doping impurity activation rates obtained after the two sets of thermal annealing process data of the i-th pair are processed by the thermal budget model and the activation rate model; 、 They respectively represent the resistance values ​​of the semiconductor device corresponding to the two sets of thermal annealing process data of the i-th pair of data.

6. A semiconductor device thermal annealing process optimization system implementing the method according to any one of claims 1 to 5, characterized in that: include: Data acquisition module, responsible for acquiring thermal annealing process data of semiconductor devices in real time; The first calculation module is responsible for inputting the real-time acquired thermal annealing process data into the modified thermal budget model to obtain the thermal annealing modified thermal budget value; The second calculation module is responsible for inputting the thermal annealing correction thermal budget value into the correction activation rate model to obtain the doping impurity correction activation rate; The optimization module is responsible for optimizing the thermal annealing process of semiconductor devices based on the comparison results of the activation rate corrected by the doping impurities and the target value.

7. A method for predicting the resistance of a semiconductor device, wherein the semiconductor device is based on a silicon-doped semiconductor, characterized in that: The method comprises: Obtaining thermal annealing process data of a semiconductor device and corresponding semiconductor device resistance; Obtaining a corrected activation rate of doping impurities using the method according to any one of claims 1 to 5 on the thermal annealing process data; The training data set is constructed by using the activation rate of the doping impurity correction and the doping dose of the doping impurity, and the corresponding semiconductor device resistance value is used as a label; Building a machine learning model and training it using training data; the input of the machine learning model is the corrected activation rate of the doping impurity and the doping dose of the doping impurity, and the output is the resistance value of the semiconductor device; Use the trained machine learning model to predict the resistance of semiconductor devices.

8. The method according to claim 7, characterized in that: The method also includes performing standardized data preprocessing on the activation rate correction of the doping impurities and the doping dose of the doping impurities.

9. The method according to claim 7, characterized in that: The machine learning model adopts the AdaBoost model with SVM as the base classifier.

10. A semiconductor device resistance prediction system implementing the method according to any one of claims 7 to 9, characterized in that: include: A data acquisition module is responsible for acquiring thermal annealing process data of semiconductor devices and doping dosage of doping impurities; The resistance prediction module is responsible for inputting the thermal annealing process data of the semiconductor device and the doping dosage of the doped impurities into the trained machine learning model and outputting the predicted resistance value of the semiconductor device.

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