Clock grid simulation time sequence labeling method and device applied to POCV analysis mode

Abstract

The invention discloses a clock grid simulation time sequence labeling method and device applied to a POCV analysis mode. The method comprises the steps that driving devices in a clock grid and root nodes of a multi-source clock tree subtree are packaged into independent logic layers through auxiliary files; the clock grid is provided with a plurality of clock paths for driving grid lines in parallel, selecting one of the paths as a reserved path, and shielding time sequence arcs of devices and wire nets outside the reserved path; performing Monte Carlo simulation to obtain mean values and standard deviations of devices and network delays in the reserved path and mean values and standard deviations of network delays of root nodes of a multi-source clock tree and input ends of the root nodes of the multi-source clock tree; equivalence is carried out on devices and nets in the reserved paths, and meanwhile, the root node of each sub-tree of the multi-source clock tree and the net delay of the input end of the multi-source clock tree are corrected. Therefore, a clock grid short circuit structure is converted into a'pseudo clock tree 'structure containing complete process fluctuation information, and accurate static time sequence analysis can be realized in a POCV mode.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation, and particularly to a clock grid simulation timing annotation method and device applied to the POCV analysis mode. Background Art

[0002] In advanced semiconductor processes represented by FinFET / GAA, process variations have a significant impact on the performance and yield of integrated circuits. The parametric on-chip variation (POCV) analysis technology can accurately characterize process variations, improve the accuracy of static timing analysis (STA), reduce pessimism in the process of timing / power analysis and optimization, and is widely used in advanced process designs.

[0003] The clock grid technology can effectively reduce the impact of process variations on the design. However, the gate-level STA algorithm of existing electronic design automation (EDA) tools is only applicable to tree-shaped clock structures and cannot handle non-tree-shaped short-circuit structures on the clock grid. This makes it impossible for EDA tools to directly obtain accurate variation information from the LVFLiberty library in the POCV analysis mode, affecting the accuracy of POCV STA.

[0004] Using EDA tools such as Spectre / FineSim, transistor-level Monte Carlo simulation can obtain variation information related to the clock grid short-circuit structure. How to completely back-annotate these fluctuation statistics into the STA architecture of the POCV analysis mode, and then accurately obtain the fluctuation description of the timing path related to the clock grid in the STA analysis stage is the main problem to be solved by the present invention. Summary of the Invention

[0005] The purpose of the present invention is to provide a clock grid simulation timing annotation method and device applied to the POCV analysis mode, aiming to solve the problem of the fluctuation description of the clock grid timing path.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions: A clock grid simulation timing annotation method applied to the POCV analysis mode, where the clock grid includes driving devices and nets; the clock grid is loaded with multiple root nodes of multi-source clock tree subtrees; the method includes: Using an auxiliary file to package the driving devices and multiple root nodes of the multi-source clock tree subtrees in the clock grid into independent logical levels respectively; The clock grid has multiple clock paths that drive grid lines in parallel. Select one of the clock paths as the reserved path, and mask the timing arcs of the driving devices and nets other than the reserved path. Use Monte Carlo simulation to obtain the mean and standard deviation of the delays of the driving devices and nets in the reserved path, as well as the mean and standard deviation of the delays of the root nodes of the multi-source clock tree and their input nets. Equivalent the mean and standard deviation of the delays of each driving device in the reserved path to an equivalent device in the reserved path. Equivalent the mean and standard deviation of the delays of each net in the reserved path to an equivalent net in the reserved path. Set the mean and standard deviation of the delays of the non-equivalent devices and non-equivalent nets in the reserved path to 0. Equivalent the mean and standard deviation of the delay of the input net of the root node of the multi-source clock tree closest to the equivalent device to the equivalent net. Equivalent the mean and standard deviation of the difference in the delays of the input nets of the remaining root nodes of the multi-source clock tree and the root node of the closest multi-source clock tree to the mean and standard deviation of the delays of the corresponding devices of the root nodes of the multi-source clock tree respectively. Perform static timing analysis on the timing paths including the clock grid and multiple sub-trees of the multi-source clock tree in the POCV analysis mode.

[0007] Preferably, the reserved path is the path with the shortest delay.

[0008] Preferably, the step of "equivalent the mean and standard deviation of the delays of each driving device in the reserved path to an equivalent device" includes: Equivalent the mean of the delays of each driving device in the reserved path to the equivalent device in the form of an accumulated sum. Equivalent the standard deviation of the delays of each driving device in the reserved path to the equivalent device in the form of the root mean square of the standard deviations.

[0009] Preferably, the step of "equivalent the mean and standard deviation of the delays of each net in the reserved path to an equivalent net" includes: Equivalent the mean of the delays of each net in the reserved path to the equivalent net in the form of an accumulated sum. Equivalent the standard deviation of the delays of each net in the reserved path to the equivalent net in the form of the root mean square of the standard deviations.

[0010] Preferably, the equivalent device is the driving device of the last-stage short-circuit line in the reserved path of the clock grid.

[0011] Preferably, the step of "equivalent the mean and standard deviation of the input net delay of the root node of the multi-source clock tree closest to the equivalent device to the equivalent net" includes: Equivalent the mean of the input net delay of the root node of the multi-source clock tree closest to the equivalent device to the equivalent net in the form of a cumulative sum; Equivalent the standard deviation of the input net delay of the root node of the multi-source clock tree closest to the equivalent device to the equivalent net in the form of the root mean square of the standard deviation.

[0012] A clock grid simulation timing annotation method applied to the POCV analysis mode, the clock grid includes devices and nets; the method includes: A computing device, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions, and when the computer-executable instructions are executed by the processor, the above-mentioned clock grid simulation timing annotation method applied to the POCV analysis mode is realized.

[0013] A computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the above-mentioned clock grid simulation timing annotation method applied to the POCV analysis mode is realized.

[0014] The advantages of the present invention are: The clock grid simulation timing annotation method and device applied to the POCV analysis mode provided by the present invention can accurately back-annotate the process fluctuation statistical data obtained by transistor-level Monte Carlo simulation to the clock grid timing path, improving the accuracy of STA analysis in the POCV mode, and is especially suitable for timing sign-off of high-performance chips in advanced processes. Description of the Drawings

[0015] Figure 1 It is a schematic diagram of the main process of a clock grid simulation timing annotation method applied to the POCV analysis mode in an embodiment of the present invention; Figure 2 It is a schematic diagram of the principle of a driving device and multiple root nodes of a multi-source clock tree in a clock grid in an embodiment of the present invention; Figure 3 It is a schematic diagram of the principle after packing a driving device and multiple root nodes of a multi-source clock tree in a clock grid into an independent logic level in an embodiment of the present invention; Figure 4 It is a schematic diagram of the principle of a reserved path in an embodiment of the present invention; Figure 5 It is a schematic diagram of the effect after timing equivalence of a driving device and a net in a clock grid reserved path in an embodiment of the present invention. Detailed implementation manners

[0016] First, in the way of transistor-level simulation, the present invention uses EDA simulation tools such as Spectre / FineSim to obtain the fluctuation statistical data of the circuits related to the short-circuit part of the clock grid, and then back-annotates by using the method proposed by the present invention, so that the timing sign-off tool (such as Synopsys PrimeTime) can convert the clock grid short-circuit structure into a timing-equivalent "pseudo-tree" structure, thereby enabling the use of the traditional STA process for analysis. The following further describes the present invention in detail with reference to the drawings and embodiments.

[0017] Refer to Figure 1 , which is the main process of a clock grid simulation timing annotation method applied to the POCV analysis mode. As Figure 1 shown, the clock grid simulation timing annotation method applied to the POCV analysis mode provided in this embodiment includes: Step S1: Use an auxiliary file to pack the driving devices and the root nodes of multiple multi-source clock tree sub-trees in the clock grid into independent logical levels respectively.

[0018] Specifically, the clock grid includes driving devices and nets; the clock grid is loaded with the root nodes of multiple multi-source clock tree sub-trees. For the STA analysis of the clock grid timing path, the auxiliary file (Side File) format supported by commercial EDA tools is used to implement the fluctuation modeling of the transistor-level Monte Carlo simulation statistical data. In order to use the auxiliary file, it is necessary to preprocess the logical levels of the devices related to the clock grid, and pack the devices that use the auxiliary file to describe the fluctuations into independent logical levels. That is, all the driving devices (Pre-Mesh Driver) in the clock grid are packed into an independent logical module; the root nodes of multiple multi-source clock trees (Post-MeshSub-Tree) sub-trees directly loaded by the clock grid are respectively packed into separate logical modules.

[0019] Refer to Figure 2 , which is the schematic diagram of a clock grid in an embodiment. This embodiment is a two-level clock grid structure with universality, including corresponding driving devices and nets. The last-level clock grid drives the root nodes of two multi-source clock tree sub-trees. Use the auxiliary file (Side File) to record the fluctuation information of the devices in the packed hierarchical module. Refer to Figure 3 , which is the schematic diagram after being packed into independent logical levels. Among them, all the clock grid driving devices have an independent logical level, and each root node of the multi-source clock tree sub-tree has an independent logical level.

[0020] Step S2: The clock grid has multiple clock paths that drive the grid lines in parallel. Select one of the clock paths as the retained path, and mask the timing arcs of the driving devices and nets other than the retained path.

[0021] Specifically, there are multiple clock paths from the root node of the clock grid to the last-level clock grid lines. Select one of the clock paths as the retained path, and mask the timing arcs of the devices and nets other than the retained path. This retained path is preferably the shortest path from the root node to the driving device of the last-level clock grid lines for ease of calculation in subsequent processing. Refer to Figure 4 , the part marked by the dashed rectangular box is the clock path that needs to be masked, and the remaining part is the selected retained path.

[0022] Step S3: Use Monte Carlo simulation to obtain the mean and standard deviation of the delays of the driving devices and nets in the retained path, as well as the mean and standard deviation of the delays of the root node of the multi-source clock tree and its input net.

[0023] Step S4: Equivalent the mean and standard deviation of the delays of each driving device in the retained path to an equivalent device in the retained path.

[0024] Specifically, the equivalent device is preferably the driving device of the short-circuit line of the last-level clock grid in the retained path. Equivalent the mean of the delays of each driving device in the retained path to the equivalent device in the form of a cumulative sum, expressed as , where is the mean of the th driving device, is the mean of the equivalent device. Equivalent the standard deviation of the delays of each driving device in the retained path to the equivalent device in the form of a root mean square, expressed as , where is the standard deviation of the th driving device, is the standard deviation of the equivalent device.

[0025] Step S5: Equivalent the mean and standard deviation of the delays of each net in the retained path to an equivalent net in the retained path.

[0026] Specifically, equivalent the mean of the delays of each net in the retained path to the equivalent net in the form of a cumulative sum, expressed as , where is the mean of the th net, is the mean of the equivalent net; equivalent the standard deviation of the delays of each net in the retained path to the equivalent net in the form of a root mean square, expressed as , where is the standard deviation of the th net, is the standard deviation of the equivalent net.

[0027] In the auxiliary file, all devices in the hierarchical module can only adopt the same device coefficient, and the nets can only adopt the same net coefficient. Through the above equivalence, there is only one effective leaf-level device and net in the clock grid retention path, enabling the auxiliary file to model the complete fluctuation information of the grid line driving circuit. Refer to Figure 5 , which is a schematic diagram of the effect after the timing equivalence of the devices and nets in a clock grid.

[0028] Step S6: Set the mean and standard deviation of the delays of non-equivalent devices and non-equivalent nets in the retention path to 0.

[0029] Specifically, set the mean and standard deviation of the delays of the driving devices and nets other than the equivalent devices and equivalent nets in the retention path to 0.

[0030] Step S7: Equivalent the mean and standard deviation of the input net delay of the root node of the multi-source clock tree closest to the equivalent device to the equivalent net.

[0031] Specifically, equivalent the mean of the input net delay of the root node of the multi-source clock tree closest to the equivalent device to the equivalent net in the form of an accumulated sum; equivalent the standard deviation of the input net delay of the root node of the multi-source clock tree closest to the equivalent device to the equivalent net in the form of the root mean square of the standard deviation. The equivalent method refers to Steps S4~S5 and will not be elaborated here.

[0032] By incorporating the mean and standard deviation of the input net delay of the root node of the multi-source clock tree closest to the equivalent device into the equivalent net in the grid driving device logic module, the timing pessimism (CRPR, Clock Reconvergence Pessimism Removal) of the clock re-convergence path is further reduced.

[0033] Step S8: Equivalent the mean and standard deviation of the difference between the input net delays of the root nodes of the remaining multi-source clock trees and the root node of the multi-source clock tree closest to the equivalent device to the mean and standard deviation of the device delays of their respective corresponding multi-source clock tree root nodes.

[0034] Specifically, for the root nodes of the remaining multi-source clock trees and the root node of the multi-source clock tree closest to the equivalent device, the mean and standard deviation of the difference in their input delays are respectively equivalent to the mean and standard deviation of the device delays of their respective corresponding multi-source clock tree root nodes. The mean is equivalent in the form of an accumulated sum, and the standard deviation is equivalent in the form of the root mean square.

[0035] The mean of the difference in the input net delays between the root nodes of the remaining multi-source clock trees and the root node of the multi-source clock tree closest to the equivalent device is denoted as , where, is the average value of the wire delay at the input terminal of the root node of the th multi-source clock tree subtree, is the average value of the wire delay at the input terminal of the root node of the multi-source clock tree subtree closest to the equivalent device; the standard deviation of the delay difference is expressed as , where is the standard deviation of the wire delay at the input terminal of the root node of the th multi-source clock tree subtree, is the standard deviation of the wire delay at the input terminal of the root node of the multi-source clock tree subtree closest to the equivalent device.

[0036] Step S9: Perform static timing analysis on the timing path including the clock grid and multiple multi-source clock tree subtrees in the POCV analysis mode.

[0037] Specifically, through the operations of the foregoing steps, the clock grid and multiple multi-source clock tree subtrees are transformed into a "pseudo clock tree" containing complete process variation information, and accurate static timing analysis can be performed in the POCV analysis mode.

[0038] This embodiment provides a computing device, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions, and when the computer-executable instructions are executed by the processor, the clock grid simulation timing annotation method applied to the POCV analysis mode is implemented.

[0039] This embodiment also provides a computer-readable storage medium, which stores computer-executable instructions, and when the computer-executable instructions are executed by the processor, the clock grid simulation timing annotation method applied to the POCV analysis mode is implemented.

[0040] Those skilled in the art should be able to realize that the method steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of electronic hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in the form of electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0041] The term "including" or any other similar term is intended to cover non-exclusive inclusion, so that a parameter, method, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to these parameters, methods, or devices.

[0042] The above are the preferred embodiments of the present invention and the technical principles applied therein. For those skilled in the art, any obvious changes such as equivalent transformations and simple substitutions based on the technical solution of the present invention without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention.

Claims

1. A clock grid simulation timing annotation method applied to the POCV analysis mode, the clock grid including a driving device and a net; the clock grid being loaded with a plurality of multi-source clock tree sub-root nodes; characterized in that, The method includes: Using an auxiliary file to package the driving devices in the clock grid and the root nodes of multiple multi-source clock tree sub-trees into independent logical levels respectively; The clock grid has multiple clock paths with parallel driving grid lines. Select one of the clock paths as the reserved path, and mask the timing arcs of the driving devices and nets other than the reserved path; Adopting Monte Carlo simulation to obtain the mean and standard deviation of the delays of the driving devices and nets in the reserved path, as well as the mean and standard deviation of the delays of the root nodes of the multi-source clock tree sub-trees and their input-terminal nets; Equivalent the mean and standard deviation of the delays of each driving device in the reserved path to an equivalent device in the reserved path; Equivalent the mean and standard deviation of the delays of each net in the reserved path to an equivalent net in the reserved path; Set the mean and standard deviation of the delays of the non-equivalent devices and non-equivalent nets in the reserved path to 0; Equivalent the mean and standard deviation of the delay of the input-terminal net of the root node of the multi-source clock tree sub-tree closest to the equivalent device to the equivalent net; Equivalent the mean and standard deviation of the difference between the delays of the input-terminal nets of the remaining root nodes of the multi-source clock tree sub-trees and the root node of the closest multi-source clock tree sub-tree to the mean and standard deviation of the delays of the devices corresponding to their respective multi-source clock tree sub-tree root nodes; Perform static timing analysis on the timing paths including the clock grid and multiple multi-source clock tree sub-trees in the POCV analysis mode.

2. The clock grid simulation timing annotation method applied to the POCV analysis mode according to claim 1, wherein, The reserved path is the path with the shortest delay.

3. The clock grid simulation timing annotation method applied to the POCV analysis mode as described in claim 1, wherein The step of "equivalent the mean and standard deviation of the delays of each driving device in the reserved path to an equivalent device in the reserved path" includes: Equivalent the mean of the delays of each driving device in the reserved path to the equivalent device in the form of a cumulative sum; Equivalent the standard deviation of the delays of each driving device in the reserved path to the equivalent device in the form of the root mean square of the standard deviations.

4. The clock grid simulation timing annotation method applied to the POCV analysis mode according to claim 1, wherein The step of "equivalent the mean and standard deviation of the delays of each net in the reserved path to an equivalent net in the reserved path" includes: Equivalent the mean of the delays of each net in the reserved path to the equivalent net in the form of a cumulative sum; Equivalent the standard deviation of the delays of each net in the reserved path to the equivalent net in the form of the root mean square of the standard deviations.

5. The clock grid simulation timing annotation method applied to the POCV analysis mode according to claim 1, characterized in that The equivalent device is the driving device of the last-stage short-circuit line in the reserved path of the clock grid.

6. The clock grid simulation timing annotation method applied to the POCV analysis mode according to claim 1, wherein The step of "equivalent the mean and standard deviation of the delay of the input-terminal net of the root node of the multi-source clock tree sub-tree closest to the equivalent device to the equivalent net" includes: Equivalent the mean of the delay of the input-terminal net of the root node of the multi-source clock tree sub-tree closest to the equivalent device to the equivalent net in the form of a cumulative sum; Equivalent the standard deviation of the delay of the input-terminal net of the root node of the multi-source clock tree sub-tree closest to the equivalent device to the equivalent net in the form of the root mean square of the standard deviations.

7. A computing device, including: A memory and a processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the clock grid simulation timing annotation method applied to the POCV analysis mode described in any one of claims 1 to 6 is implemented.

8. A computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by a processor, the clock grid simulation timing annotation method applied to the POCV analysis mode described in any one of claims 1 to 6 is implemented.

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