A power supply circuit for non-volatile memory on an FPGA chip

Abstract

The present invention discloses a power supply circuit for a non-volatile memory on an FPGA, belonging to the technical field of power management. In the power supply circuit, a low-dropout linear regulator is used to output a first power supply voltage according to a reference voltage and a feedback voltage; the reference voltage is obtained by adding a first voltage proportional to the absolute temperature and a second voltage inversely proportional to the absolute temperature; both the first voltage and the second voltage are generated based on the current Iptat generated by a bandgap reference circuit; a level conversion circuit is used to receive an external signal and convert its voltage domain, and output an enable signal; an inverter group is used to shape the enable signal and perform an inversion operation on it to obtain an inverted enable signal; a power switch is used to output or not output a second power supply voltage under the control of the inverted enable signal, and the second power supply voltage is generated based on the first power supply voltage, thereby providing a power supply circuit with a simple structure and low power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of power management, and particularly relates to a power supply circuit for a non-volatile memory on an FPGA (Field Programmable Gate Array). Background Art

[0002] Many IP cores (Intellectual Property cores), including Hard IP and Soft IP, are usually integrated in an FPGA chip. The OTP (One Time Programmable) Memory circuit, as a small-capacity Hard IP, is integrated into the FPGA chip and finally integrated into the layout of the FPGA by the foundry through IP merge.

[0003] OTP is a typical non-volatile memory (NVM), and the data is not lost when the power is off. It is often used to store the trimming bits of analog quantities in the FPGA chip, such as the trimming bits of analog circuits such as oscillators, bandgap references, and data converter reference voltages. And the data is written fixedly during CP (chip probing) testing and is not lost when the power is off. The power supply required by this Hard IP includes three power supply voltages: VDD, VDDQ, and Vfsource. The FPGA power supply has three power supply voltages: VCC, VCCEXT, and VCCIO. The VDD power supply voltage of OTP is the same as the VCC power supply voltage of the FPGA, while VDDQ and Vfsource are inconsistent with VCCEXT and VCCIO of the FPGA chip. Therefore, an on-chip circuit needs to be designed to generate VDDQ and Vfsource.

[0004] In the existing power supply circuit, the method for generating VDDQ is to use the reference voltage generated by the bandgap reference, generate a reference voltage through a buffer circuit, and then generate VDDQ through a low-dropout linear regulator; the existing method for generating Vfsource is to provide the Vfsource voltage by designing a sub-regulator, and meet the requirements of Vfsource by turning on or off the sub-regulator.

[0005] However, the introduction of the buffer circuit and the sub-regulator will increase the cost, area, and power consumption of the chip. Therefore, how to provide a power supply circuit with a simple structure and low power consumption has become an important issue. Summary of the Invention

[0006] To solve the above problems existing in the prior art, the present invention provides a power supply circuit for a non-volatile memory on an FPGA chip.

[0007] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0008] The present invention provides a power supply circuit for a non-volatile memory on an FPGA chip, and the power supply circuit includes a low-dropout linear regulator, a level conversion circuit, an inverter group, and a power switch;

[0009] The low-dropout linear regulator is configured to output a first supply voltage according to a reference voltage and a feedback voltage; the reference voltage is obtained by adding a first voltage proportional to the absolute temperature and a second voltage inversely proportional to the absolute temperature; both the first voltage and the second voltage are generated based on the current Iptat; the current Iptat is generated by a bandgap reference circuit;

[0010] The level conversion circuit is configured to receive an external signal, convert the voltage domain of the external signal, and output an enable signal;

[0011] The inverter group is configured to shape the enable signal and perform an inversion operation on the shaped enable signal to obtain an inverted enable signal;

[0012] The power switch is configured to output or not output a second supply voltage under the control of the inverted enable signal, and the second supply voltage is generated based on the first supply voltage.

[0013] Optionally, the low-dropout linear regulator includes a current mirror, a first resistor, a PNP, a single-stage amplifier, a trench PMOS, a first feedback resistor, and a second feedback resistor;

[0014] The first end of the current mirror inputs the current Iptat. The second end of the current mirror is connected to the third end of the current mirror and inputs VCCEXT of the FPGA. The fourth end of the current mirror is connected to the first end of the first resistor. The base of the PNP is connected to the collector of the PNP and grounded. The emitter of the PNP is connected to the second end of the first resistor. The first end of the first resistor is connected to the negative input terminal of the single-stage amplifier. The positive input terminal of the single-stage amplifier is connected to the first end of the second feedback resistor. The second end of the second feedback resistor is connected to the collector of the PNP. The second end of the first feedback resistor is connected to the positive input terminal of the single-stage amplifier. The first end of the first feedback resistor is connected to the drain of the trench PMOS. The source of the trench PMOS is connected to the third end of the current mirror. The gate of the trench PMOS is connected to the output terminal of the single-stage amplifier. The drain of the trench PMOS outputs the first supply voltage.

[0015] Optionally, the single-stage amplifier includes a folded cascode amplifier.

[0016] Optionally, the current mirror includes PMOS1 and PMOS2;

[0017] The source of PMOS1 is connected to the source of PMOS2 and inputs the VCCEXT. The drain of PMOS1 is connected to the gate of PMOS1 and inputs the current Iptat. The gate of PMOS1 is connected to the gate of PMOS2. The drain of PMOS2 is connected to the first end of the first resistor. The source of PMOS2 is connected to the source of the trench PMOS.

[0018] Optionally, the inverter group includes three cascaded inverters.

[0019] Optionally, the power switch includes PMOS11 and NMOS5;

[0020] Wherein, the source of PMOS11 inputs the first supply voltage. The gate of PMOS11 and the gate of NMOS5 are commonly connected to the output terminal of the inverter group. The drain of PMOS11 and the drain of NMOS5 are connected and output the second supply voltage. The source of NMOS5 is connected to the fourth end of the level conversion circuit and grounded.

[0021] Optionally, the level conversion circuit includes PMOS12, PMOS13, NMOS6, NMOS7 and a fifth inverter;

[0022] The source of the PMOS12 is connected to the source of the PMOS13 and inputs the VCCEXT of the FPGA. The gate of the PMOS12 is connected to the drain of the PMOS13. The gate of the PMOS13 is connected to the drain of the PMOS12. The drain of the NMOS6 is connected to the drain of the PMOS12. The gate of the NMOS6 is connected to the input terminal of the fifth inverter and inputs the external signal. The sources of the NMOS6 and the NMOS7 are connected together and grounded. The gate of the NMOS7 is connected to the output terminal of the fifth inverter. The drain of the NMOS7 is connected to the drain of the PMOS13 and outputs the enable signal.

[0023] In the power supply circuit of the on-chip non-volatile memory of the FPGA provided by the present invention, the low-dropout linear regulator is used to output the first power supply voltage according to the reference voltage and the feedback voltage. Among them, the temperature-independent reference voltage is obtained by adding a first voltage proportional to the absolute temperature and a second voltage inversely proportional to the absolute temperature. Both the first voltage and the second voltage are generated based on the current Iptat, and the current Iptat is generated by the bandgap reference circuit. Compared with the existing power supply circuit, such a design reduces the buffer circuit between the bandgap reference circuit and the low-dropout linear regulator, thereby reducing the chip area, saving power consumption, and reducing the introduction of additional noise. The second power supply voltage can be output or not output under the control of the reverse conversion enable signal through the power switch. The second power supply voltage is generated based on the first power supply voltage, and there is no need to design a sub-regulator to provide the second power supply voltage as in the existing power supply circuit, which reduces the circuit complexity and area and saves power consumption.

[0024] The following will further describe the present invention in detail with reference to the drawings. Description of the Drawings

[0025] Figure 1 is a schematic structural diagram of a power supply circuit of an on-chip non-volatile memory of the FPGA provided by an embodiment of the present invention;

[0026] Figure 2 is a schematic structural diagram of the low-dropout linear regulator provided by an embodiment of the present invention;

[0027] Figure 3 is a schematic structural diagram of the miller compensation low-dropout linear regulator provided by an embodiment of the present invention;

[0028] Figure 4 is a schematic diagram of the miller compensation capacitor feedback effect;

[0029] Figure 5 is a schematic diagram of the miller compensation capacitor feedforward effect;

[0030] Figure 6It is a schematic structural diagram of the level conversion circuit provided by an embodiment of the present invention. Detailed implementation manners

[0031] The present invention will be further described in detail below in conjunction with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0032] In order to solve the problem that the buffer circuit and the sub-regulator introduced in the existing power supply circuit will increase the cost, area and power consumption of the chip, an embodiment of the present invention provides a power supply circuit for the on-chip non-volatile memory of an FPGA. Refer to Figure 1 , Figure 1 It is a schematic structural diagram of a power supply circuit for the on-chip non-volatile memory of an FPGA provided by an embodiment of the present invention. The power supply circuit includes: a low-dropout linear regulator (LDO regulator), a level shifter, an inverter group, and a power switch.

[0033] Among them, the input end of the low-dropout linear regulator and the second end of the level shifter both input the VCCEXT power supply voltage of the FPGA. The output end of the low-dropout linear regulator is connected to the first end of the power switch. The second end of the power switch is grounded. The third end of the power switch is connected to Vfsource. The fourth end of the power switch is connected to the output end of the inverter group. The first end of the level shifter inputs an external signal. The fourth end of the level shifter is grounded. The third end of the level shifter is connected to the input end of the inverter group.

[0034] In the embodiment of the present invention, the low-dropout linear regulator is used to output a first power supply voltage according to a reference voltage and a feedback voltage; the reference voltage is obtained by adding a first voltage proportional to the absolute temperature and a second voltage inversely proportional to the absolute temperature; both the first voltage and the second voltage are generated based on the current Iptat; the current Iptat is generated by a bandgap reference circuit;

[0035] The level shifter is used to receive an external signal, convert the voltage domain of the external signal, and output an enable signal;

[0036] The inverter group is used to shape the enable signal and perform an inversion operation on the shaped enable signal to obtain an inverted enable signal;

[0037] The power switch is used to output or not output a second power supply voltage under the control of the inverted enable signal. The second power supply voltage is generated based on the first power supply voltage.

[0038] In the embodiment of the present invention, the first power supply voltage serves as the VDDQ of the OTP, and the second power supply voltage serves as the Vfsource of the OTP.

[0039] Refer to Figure 2, Figure 2 FIG. 92 is a schematic structural diagram of a low dropout linear regulator provided by an embodiment of the present invention. The low dropout linear regulator includes a current mirror, a first resistor R1, a PNP, a single-stage amplifier, a trench PMOS, a first feedback resistor Rfb1, and a second feedback resistor Rfb2;

[0040] A current Iptat is input to a first end of the current mirror. A second end of the current mirror is connected to a third end of the current mirror and inputs VCCEXT of an FPGA. A fourth end of the current mirror is connected to a first end of the first resistor. A base of the PNP is connected to a collector of the PNP and grounded. An emitter of the PNP is connected to a second end of the first resistor. The first end of the first resistor is connected to a negative input end of the single-stage amplifier. A positive input end of the single-stage amplifier is connected to a first end of the second feedback resistor. A second end of the second feedback resistor is connected to the collector of the PNP. A second end of the first feedback resistor is connected to the positive input end of the single-stage amplifier. A first end of the first feedback resistor is connected to a drain of the trench PMOS. A source of the trench PMOS is connected to the third end of the current mirror. A gate of the trench PMOS is connected to an output end of the single-stage amplifier. A first supply voltage VDDQ is output from the drain of the trench PMOS.

[0041] Generally, a bandgap reference circuit cannot directly provide a reference for a low dropout linear regulator. A buffer needs to be added between the bandgap reference circuit and the low dropout linear regulator, and the buffer provides a reference voltage for the low dropout linear regulator circuit. However, this will increase the chip area and power consumption, and will also introduce additional noise and interference.

[0042] In the embodiment of the present invention, a current mirror is used to copy a current Iptat (proportional to absolute temperature) generated by a bandgap reference circuit to generate a Vref (voltage reference) independent of temperature.

[0043] In the embodiment of the present invention, the reference voltage is obtained by adding a first voltage proportional to absolute temperature and a second voltage inversely proportional to absolute temperature. Among them, both the first voltage and the second voltage are generated by using the current Iptat copied by the current mirror; the current Iptat is generated by the bandgap reference circuit. The feedback voltage is generated through the first feedback resistor and the second feedback resistor.

[0044] Specifically, the current Iptat passes through the first resistor and the PNP, that is, a PNP-type BJT (bipolar junction transistor), to generate a temperature-independent Vref (voltage reference). The principle is as follows: After the current Iptat is replicated by a current mirror, it flows through the first resistor and the PNP. The voltage generated across the first resistor is proportional to the absolute temperature and is called the first voltage ΔVbe. The current flows through the diode-connected PNP, and the second voltage Vce between the collector and emitter of the PNP is equal to the voltage Vbe between the base and emitter, that is ; Vbe is inversely proportional to the absolute temperature, and the sum of ΔVbe and Vbe is the temperature-independent reference voltage Vref.

[0045] For example, , , then the reference voltage .

[0046] The low-dropout linear regulator uses the first feedback resistor, the second feedback resistor, and the trench-type PMOS, that is, a PMOSFET (Positive channel-Metal-Oxide-Semiconductor Feild Effect Transistor) type power transistor to generate the required output voltage.

[0047] For example, the input voltage (Vin) is the VCCEXT power supply voltage of the FPGA, and this voltage is 3.3V. Then the output voltage (Vout) is the VDDQ required for OTP, and its magnitude is 2.5V.

[0048] In one implementation, the current mirror includes PMOS1 and PMOS2. Among them, the source of PMOS1 is connected to the source of PMOS2 and inputs the VCCEXT power supply voltage of the FPGA. The drain of PMOS1 is connected to the gate of PMOS1 and inputs the current Iptat. The gate of PMOS1 is connected to the gate of PMOS2. The drain of PMOS2 is connected to the negative input terminal of the single-stage amplifier, and the source of PMOS2 is connected to the source of the trench-type PMOS.

[0049] In one implementation, the inverter group includes three cascaded inverters. That is, it includes the cascaded first inverter, second inverter, and third inverter.

[0050] Specifically, the input terminal of the first inverter is connected to the third terminal of the level conversion circuit. The output terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the fourth terminal of the power switch.

[0051] In an embodiment of the present invention, the first inverter is used to shape and invert the enable signal, the second inverter is used to shape and invert the signal output by the first inverter, and the third inverter is used to shape and invert the signal output by the second inverter, and finally output the inverted enable signal. The three cascaded inverters are mainly used to improve its driving ability, so that the enable signal has a stronger driving ability and a steeper edge.

[0052] Vout generated by the low-dropout linear regulator is used as the power supply VDDQ for the OTP circuit. When performing a programming operation, the OTP circuit also requires a power supply Vfsource. The OTP circuit is turned on when running the write function and turned off when running the read function, and this programming operation occurs only once.

[0053] Specifically, the external signal, that is, the wr_en signal, is sent by the EFB (Embedded Function Blocks) circuit in the FPGA. The high level of the wr_en signal is 1.2 and the low level is 0. The high level of the power switch is 3.3 and the low level is 0.

[0054] In an embodiment of the present invention, the voltage domain of the wr_en signal sent by the EFB is VCC, while the voltage domain of the inverter group and the powerswich is VCCEXT. Therefore, in an embodiment of the present invention, a level conversion circuit is used to convert the voltage domain of the wr_en signal to ensure the correct inversion of the wr_en signal.

[0055] When the OTP circuit is running the write function, the level conversion circuit converts the level amplitude of the wr_en signal from 1.2 to 3.3, and turns on the power switch to perform an operation of generating and outputting a second power supply voltage based on the first power supply voltage.

[0056] When the OTP circuit is running the read function, the level amplitude of the wr_en signal is 0, and the power switch is turned off without performing an operation of generating a second power supply voltage based on the first power supply voltage.

[0057] In an embodiment of the present invention, a low dropout linear regulator is configured to output a first supply voltage based on a reference voltage and a feedback voltage; wherein, the temperature-independent reference voltage is obtained by adding a first voltage proportional to the absolute temperature and a second voltage inversely proportional to the absolute temperature; both the first voltage and the second voltage are generated based on the current Iptat; the current Iptat is generated by a bandgap reference circuit. Compared with the existing power supply circuit, the buffer circuit between the bandgap reference circuit and the low dropout linear regulator is reduced, thereby reducing the chip area, saving power consumption, and reducing the introduction of additional noise. The second supply voltage can be output or not output under the control of a reverse enable signal through a power switch. The second supply voltage is generated based on the first supply voltage, and there is no need to design a sub-regulator to provide the second supply voltage as in the existing power supply circuit, reducing the circuit complexity and area and saving power consumption.

[0058] The power supply circuit for the on-chip non-volatile memory of an FPGA provided by the embodiment of the present invention provides a low dropout linear regulator with a simple structure, high certainty, and stability for the OTP circuit, and provides a one-time power supply during programming through a power switch.

[0059] The voltage drop (Vdropout) generated by the low dropout linear regulator provided by the embodiment of the present invention is small. , so a trench PMOS is used as the power transistor. When the trench PMOS is used as the power transistor, the power transistor, the first feedback resistor, and the second feedback resistor together form a common-source amplifier stage. The power transistor, the first feedback resistor, and the second feedback resistor are referred to as the power stage. The single amplifier and the power stage form a two-stage amplifier. Also, because this low dropout linear regulator has negative feedback and operates in a closed-loop state, frequency compensation is required.

[0060] In an embodiment of the present invention, in order to reduce the impact of offset on the system, the gain of the single amplifier needs to be made very large. The single amplifier used in the embodiment of the present invention is a folded cascode amplifier, and cascode Miller compensation is used during frequency compensation. Refer to Figure 3 , Figure 3 is a schematic structural diagram of the Miller compensation low dropout linear regulator provided by the embodiment of the present invention. The compensation capacitor Cc is no longer connected between the output terminal of the single amplifier and the output terminal of the power stage, but is connected between the cascode stage of the folded cascode amplifier and the output terminal of the power stage. Refer to Figure 4 and Figure 5 , Figure 4 is a schematic diagram of the Miller compensation capacitor feedback effect. Figure 5It is a schematic diagram of the feedforward effect of the Miller compensation capacitor. Like most capacitors, the compensation capacitor is bidirectional, which means that the compensation capacitor can conduct both feedback current and feedforward current simultaneously. The feedforward current flows through the compensation capacitor Cc and generates a small output signal at the output node. This is the current that generates the zero point, and it is a positive zero point. To eliminate this positive zero point, the compensation capacitor must be made directional. In other words, a transistor must be connected in series to cut off the feedforward path or a small resistor must be connected in series to cancel the feedforward effect caused by the feedback. The single-stage amplifier used in the low dropout linear regulator provided by the embodiment of the present invention is a folded cascode amplifier, which has a cascode stage by itself. The compensation capacitor Cc is connected between the output terminal and the cascode stage, rather than directly between the power stage output terminal and the output terminal of the single-stage amplifier. This breaks the feedforward path of the compensation capacitor, avoids the positive zero point, and therefore no additional zero-adjusting resistor or transistor is required to eliminate this positive zero point. Moreover, it has a higher compensation efficiency, reduces the chip area, and saves power consumption.

[0061] In the embodiment of the present invention, referring to Figure 3 , the folded cascode amplifier includes PMOS3, PMOS4, PMOS5, PMOS6, PMOS7, PMOS8, PMOS9, PMOS10, NMOS1, NMOS2, NMOS3, and NMOS4;

[0062] The source of PMOS3 is connected to VCCEXT. The source of PMOS3 is connected to the source of PMOS9. The gate of PMOS3 is connected to the first bias voltage pb1. The drain of PMOS3 is connected to the source of PMOS4. The gate of PMOS4 is connected to the second bias voltage pb2. The drain of PMOS4 is connected to the sources of PMOS5 and PMOS6. The gate of PMOS5 is connected to Vfb. The gate of PMOS6 is connected to Vref. The drain of PMOS5 is connected to the drain of NMOS3. The drain of PMOS6 is connected to the drain of NMOS4. The gates of NMOS3 and NMOS4 are connected to each other and are both connected to the third bias voltage nb1. The sources of NMOS3 and NMOS4 are connected to each other and grounded. The source of NMOS1 is connected to the drain of NMOS3. The gates of NMOS1 and NMOS2 are connected to each other and are both connected to the fourth bias voltage nb2. The source of NMOS2 is connected to the drain of NMOS4. The drain of NMOS2 is connected to the drain of PMOS8. The drain of PMOS7 is connected to the drain of NMOS1. The gate of PMOS7 is connected to the gate of PMOS8. The gate of PMOS9 is connected to the gate of PMOS10. The drain of PMOS9 is connected to the source of PMOS7. The gate of PMOS9 is connected to the drain of PMOS7. The drain of PMOS10 is connected to the source of PMOS8. The sources of PMOS9 and PMOS10 are connected to each other and connected to VCCEXT. The source of the trench PMOS is connected to VCCEXT. The gate of the trench PMOS is connected to the drains of PMOS8 and NMOS2. The drain of the trench PMOS outputs VDDQ. The first end of the compensation capacitor Cc is connected to the drain of PMOS10 and the source of PMOS8. The second end of the compensation capacitor Cc is connected to the drain of the trench PMOS. The first end of the first feedback resistor is connected to the drain of the trench PMOS. The second end of the first feedback resistor is connected to the first end of the second feedback resistor. The second end of the second feedback resistor is connected to the source of NMOS4.

[0063] In one implementation, referring to Figure 1 , the power switch includes PMOS11 and NMOS5;

[0064] Wherein, the source of PMOS11 inputs the first power supply voltage VDDQ. The gates of PMOS11 and NMOS5 are commonly connected to the output end of the third inverter. The drains of PMOS11 and NMOS5 are connected to each other and output Vfsource. The source of NMOS5 is connected to the fourth end of the level conversion circuit and grounded.

[0065] It should be noted that since the power switch requires a large current, the sizes of PMOS11 and NMOS5 provided in the embodiments of the present invention are relatively large.

[0066] In one implementation, referring to Figure 6 ,Figure 6 FIG. Figure 6 is a schematic structural diagram of a level conversion circuit provided by an embodiment of the present invention. The level conversion circuit includes PMOS12, PMOS13, NMOS6, NMOS7, and a fifth inverter.

[0067] Wherein, the source of PMOS12 is connected to the source of PMOS13 and inputs VCCEXT of the FPGA. The gate of PMOS12 is connected to the drain of PMOS13, the gate of PMOS13 is connected to the drain of PMOS12, the drain of NMOS6 is connected to the drain of PMOS12, the gate of NMOS6 is connected to the input end of the fifth inverter and inputs an external signal. The sources of NMOS6 and NMOS7 are connected together and grounded. The gate of NMOS7 is connected to the output end of the fifth inverter, and the drain of NMOS7 is connected to the drain of PMOS13 and outputs an enable signal.

[0068] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present invention.

[0069] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0070] Although the present invention has been described in connection with various embodiments herein, however, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by viewing the accompanying drawings and the disclosure. In the description of the present invention, the term "including" does not exclude other components or steps, the term "one" or "a" does not exclude a plurality of cases, and the meaning of "a plurality" is two or more unless otherwise specifically defined. In addition, certain measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0071] In the present invention, unless otherwise clearly specified or limited, terms such as "installed", "connected", "coupled", "fixed", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0072] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A power supply circuit for a non-volatile memory on an FPGA chip, characterized in that, The power supply circuit includes a low dropout linear regulator, a level conversion circuit, an inverter group, and a power switch; The low dropout linear regulator is configured to output a first supply voltage according to a reference voltage and a feedback voltage; the reference voltage is obtained by adding a first voltage proportional to the absolute temperature and a second voltage inversely proportional to the absolute temperature; both the first voltage and the second voltage are generated based on the current Iptat; the current Iptat is generated by a bandgap reference circuit; The level conversion circuit is configured to receive an external signal and convert the voltage domain of the external signal to output an enable signal; The inverter group is configured to shape the enable signal and perform an inversion operation on the shaped enable signal to obtain an inverted enable signal; The power switch is configured to output or not output a second supply voltage under the control of the inverted enable signal, and the second supply voltage is generated based on the first supply voltage; The low dropout linear regulator includes a current mirror, a first resistor, a PNP, a single-stage amplifier, a trench PMOS, a first feedback resistor, and a second feedback resistor; The first end of the current mirror inputs the current Iptat, the second end of the current mirror is connected to the third end of the current mirror and inputs VCCEXT of the FPGA, the fourth end of the current mirror is connected to the first end of the first resistor, the base of the PNP is connected to the collector of the PNP and grounded, the emitter of the PNP is connected to the second end of the first resistor, the first end of the first resistor is connected to the negative input terminal of the single-stage amplifier, the positive input terminal of the single-stage amplifier is connected to the first end of the second feedback resistor, the second end of the second feedback resistor is connected to the collector of the PNP, the first end of the first feedback resistor is connected to the positive input terminal of the single-stage amplifier, the second end of the first feedback resistor is connected to the drain of the trench PMOS, the source of the trench PMOS is connected to the third end of the current mirror, the gate of the trench PMOS is connected to the output terminal of the single-stage amplifier, and the drain of the trench PMOS outputs the first supply voltage.

2. The power supply circuit according to claim 1, wherein The single-stage amplifier includes a folded cascode amplifier.

3. The power supply circuit according to claim 1, characterized in that The current mirror includes PMOS1 and PMOS2; The source of PMOS1 is connected to the source of PMOS2 and inputs the VCCEXT, the drain of PMOS1 is connected to the gate of PMOS1 and inputs the current Iptat, the gate of PMOS1 is connected to the gate of PMOS2, the drain of PMOS2 is connected to the first end of the first resistor, and the source of PMOS2 is connected to the source of the trench PMOS.

4. The power supply circuit according to claim 1, wherein, The inverter group includes three cascaded inverters.

5. The power supply circuit according to claim 1, wherein The power switch includes PMOS11 and NMOS5; Among them, the source of the PMOS11 inputs the first supply voltage, the gates of the PMOS11 and the NMOS5 are commonly connected to the output terminal of the inverter group, the drains of the PMOS11 and the NMOS5 are connected and output the second supply voltage, and the source of the NMOS5 is connected to the fourth terminal of the level conversion circuit and grounded.

6. The power supply circuit according to claim 1, characterized in that, The level conversion circuit includes a PMOS12, a PMOS13, an NMOS6, an NMOS7, and a fifth inverter; The source of the PMOS12 is connected to the source of the PMOS13 and inputs the VCCEXT of the FPGA. The gate of the PMOS12 is connected to the drain of the PMOS13, the gate of the PMOS13 is connected to the drain of the PMOS12, the drain of the NMOS6 is connected to the drain of the PMOS12, the gate of the NMOS6 is connected to the input terminal of the fifth inverter and inputs the external signal. The sources of the NMOS6 and the NMOS7 are connected and grounded. The gate of the NMOS7 is connected to the output terminal of the fifth inverter, and the drain of the NMOS7 is connected to the drain of the PMOS13 and outputs the enable signal.

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