Semiconductor chip packaging defect-free pit technology and device

Abstract

Embodiments of the subject matter described herein relate to semiconductor chip packages, and more particularly, to quad flat no-lead (QFN) burr-free pit packages, small no-lead (SON) burr-free and defect-free pit packages, and process schemes for creating burr-free pits after singulation without the need for additional deburring processes.

Description

Technical Field

[0001] Embodiments of the subject matter described herein relate to semiconductor chip packages, and more particularly, to quad flat no-lead (QFN) deburr-free dimple packages, small outline no-lead (SON) deburr-free and defect-free dimple packages, and process schemes for creating deburr-free dimples without additional deburring processes after singulation. Background Art

[0002] Quad flat no-lead (QFN) and small outline no-lead (SON) packages are used to encapsulate one or more integrated circuit dies while retaining exposed pads that physically and electrically connect the integrated circuit die to a printed circuit board (PCB). These QFN and SON packages are surface mount technologies that use peripheral lead pads on the bottom of the package to connect the integrated circuit die to the surface of the PCB without vias to provide electrical contact with the PCB. Conventional QFN and SON packaging methods have been implemented and result in dimple burrs after singulation. Dimple burrs are typically caused after cutting.

[0003] In the related art, during the singulation or sawing process, burrs tend to accumulate in the dimples. If the accumulation is sufficient and the burrs are not removed, the burrs may affect the solder joint reliability of the device. Removing these burrs requires additional process steps and is difficult, time-consuming, and costly. Additionally, fine-pitch QFN and SON packages (e.g., less than 1.0 mm) are more prone to burr accumulation, and given the geometric complexity of these two packages, the deburring process may not be achievable, which may result in semiconductor packages not using dimples.

[0004] Accordingly, there is a need for an improved integrated circuit chip package and manufacturing method to address the various problems in the art that the inventors have discovered, where after reading the remainder of the present application with reference to the drawings and the following detailed description, the various limitations and disadvantages of conventional solutions and techniques will become apparent to those skilled in the art, but it should be understood that this description of the related art is not intended as an admission that the described subject matter is prior art. Summary of the Invention

[0005] One aspect of the present invention relates to semiconductor chip packages, and more particularly, to quad flat no-lead (QFN) deburr-free dimple packages and small outline no-lead (SON) defect-free packages having dimples after a singulation process or other separation process. In one process scheme, the semiconductor package includes deburr-free dimples after singulation without the need for additional deburring processes.

[0006] The following description will set forth additional features and advantages of the invention, and some of these features and advantages will be apparent in the description or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0007] In some aspects, the techniques described herein relate to a semiconductor package that includes a lead frame having a plurality of leads. The package also includes a semiconductor die mounted on the lead frame. Bonding pads on the die are electrically connected to some of the leads, and a molding compound encapsulates the die. The leads and the electrical connections are exposed at a corner sidewall of the semiconductor package, and an exposed portion of each of the leads is flush with two adjacent sides of the device. A portion of the lead, a pit, is partially recessed or includes a polymeric material disposed in a portion of the pit. The polymeric material is configured to prevent defects such as burrs, smears, and other defects during a singulation process.

[0008] In some aspects, in the techniques described herein, the polymeric material includes a material having a thickness formed to be about 20 microns or greater.

[0009] In some aspects, in the techniques described herein, the polymeric material includes a material selected from the group consisting of polyimide, polyacrylate, and silicone. The polymeric material can also be a thermoplastic polymer and a thermosetting polymer.

[0010] The Summary of the Invention section is neither intended nor should it be construed to represent the entire scope and extent of the disclosure. Additional benefits, features, and embodiments of the disclosure are set forth in the drawings and the description below, and as described in the claims. Accordingly, it should be understood that the Summary of the Invention section may not contain all aspects and embodiments claimed herein.

[0011] Furthermore, the disclosure herein is not intended to be in any way limiting or restrictive. Additionally, the disclosure is intended to provide to a person of ordinary skill in the art an understanding of one or more representative embodiments that support the claims. Thus, it is important that the claims be regarded as having a scope that includes the various features of the disclosure, so long as such constructs do not depart from the scope of the methods and devices consistent with the disclosure (including the originally filed claims). Additionally, the disclosure is intended to cover and include obvious improvements and modifications of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A more complete understanding of the subject matter may be obtained by reference to the Detailed Description and claims when considered in conjunction with the following drawings, in which like reference numerals refer to like elements throughout.

[0013] Figure 1is a perspective view of a semiconductor package device having a burr-free pit according to an embodiment.

[0014] Figure 2 According to the embodiment Figure 1 A cross-sectional view of a semiconductor package device taken along line 1-1 before singulation.

[0015] Figure 3 According to the embodiment Figure 1 A cross-sectional view of the device along line 1-1 after singulation.

[0016] Figure 4 According to the manufacturing method of the embodiment Figure 1 A flow chart of a method for an apparatus.

[0017] Figures 5 to 9 A method for forming a Figure 1 Simplified cross-sectional view of a series of fabrication steps for a device.

[0018] Figure 10 is a perspective view of a semiconductor package device having a burr-free pit according to another embodiment. DETAILED DESCRIPTION

[0019] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the words "exemplary" and "example" mean "serving as an example, instance, or illustration". Any embodiment described herein as exemplary or example is not necessarily to be construed as being preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any explicit or implicit theory presented in the foregoing technical field, background technology, or the following detailed description.

[0020] Figure 1 is a perspective view of a semiconductor package device having a burr-free pit according to an embodiment.

[0021] refer to Figure 1 , the semiconductor package 100 is a QFN package having a generally square or rectangular shape and is relatively small. For example, in one embodiment, the semiconductor package 100 is approximately 0.6 mm×0.6 mm (L×W) or less. The package includes a body 102, leads 104, and a thermal pad 106. The leads 104 are flush with the bottom surface and side surfaces of the package 100. The leads 104 include burr-free pits 108. The burr-free pits 108 can be used as an enhanced feature for forming a wettable side, for example, an enhanced feature configured to meet predetermined lead spacing criteria, closer geometries, etc. Unlike the related art, the pits 108 are burr-free without the need for an additional deburring process step for removing burrs or other defects formed during the singulation process.

[0022] Figure 2 Cross-sectional view of a semiconductor package device according to an embodiment of the figures before singulation.

[0023] Reference Figure 2 , the QFN semiconductor package 100 includes a semiconductor die 202 electrically connected to leads 204 by bonding wires 206. The semiconductor die 202 is attached to a body 212 by a die attach material 214. Before the singulation process, the leads include pits 208. The die 202, portions of the leads 204, the bonding wires 206, and the plating 207 are encapsulated by a molding compound 208. The plating 207 can be a metallic material or an alloy material, such as Ni, Pd, AuAg / Au material, combinations thereof, etc. Before the singulation or dicing process, a polymeric material 210 is formed in portions of the pits 208. The polymeric material 210 can include a thermoplastic material, a thermosetting material, such as a polyimide material, a polyacrylate material, a silicone material, combinations thereof, etc. The polymeric material can have a thickness of 20 microns or greater.

[0024] Figure 3 is according to an embodiment of Figure 1 Cross-sectional view of the device along line 1-1 after singulation.

[0025] Reference Figure 3 , after a singulation process such as a sawing or dicing process, the semiconductor package 100 includes deburr-free pits 108. That is, the pits formed after the singulation process do not have any burr accumulation and are deburr-free, and the singulation process does not include a deburring process, such as etching or other chemical deburring processes. The pits 108 do not have burrs or metal stain accumulation defects or other defects, e.g., no defects including burrs, metal stains, or other defects are generated during the singulation process.

[0026] Figure 4 is a flowchart of a method for manufacturing a Figure 1 device according to an embodiment. By viewing Figures 5 to 9 while viewing Figure 4 the steps, Figure 4 can be best understood.

[0027] Reference Figure 4 , Figure 4A semiconductor packaging process flow 400 for forming semiconductor packages such as QFN burr-free packages, SON packages, etc. is shown. The process flow 400 does not include additional deburring process steps, such as chemical deburring processes. In step 410, a conductive metal sheet, such as copper or other conductive metal, is provided. The lead frame may include a lead frame array. In step 420, a resist is applied to the metal sheet. In step 430, the metal sheet is etched by etching or other processes to form one or more lead frames 502, such as a lead frame array, and also form pits 504.

[0028] In step 440, after the pits are formed, a plating layer 506 is formed on the lead frame 502 and the pits 504 or only on selected portions thereof as needed. The plating step 440 is preferably performed using an electroplating or electrodeposition process, during which the lead frame including the lead ends or edges is coated with a solderable layer of a plating material described herein, such as Ni / Pd / Au Ag / Au materials. During the electroplating process, the leads can be connected to a potential source such that these leads form cathodes during the electroplating or electrodeposition process. The electroplating or electrodeposition process causes a conductive wettable metal layer to be deposited on the exposed surfaces of the lead frame. It should be noted that the lead frame may include bare copper, or the lead frame may be pre-plated with silver, for example, at the bonding surface (the back side is usually kept as bare copper), and a tin or tin alloy coating can be applied to the exposed lead ends before or after the lead frame is cut into individual semiconductor devices.

[0029] In step 450, a polymer material 508 is formed in at least a portion of the pits 504. The polymer material 508 may include thermoplastic materials, thermosetting materials, such as polyimide materials, polyacrylate materials, silicone materials, combinations thereof, etc. In a preferred embodiment, the polymer material 508 may have a thickness of 20 microns or greater. The polymer material 508 can be formed by dispensing, screen printing, gluing, combinations thereof, etc.

[0030] Step 460 is an optional pasting step of pasting the lead frame or the lead frame array 502 with a tape layer 510 applied to the back side of the lead frame. The tape 510 is configured to prevent the lead frame 502 from deforming before use.

[0031] In step 470, the die 520 is mounted on the leads of the lead frame (such as each lead frame) and attached to the leads of the lead frame. In the current preferred embodiment, the corners of the non-active side of the die rest on the inner portions of the leads and are attached to the inner portions of the leads. The die 522 can be attached to the leads using die attach adhesive or double-sided tape 522.

[0032] Step 480 is a wire bonding step, where the die bond pads are electrically connected to the corresponding leads in the leadframe by bonding wires. In an alternative embodiment, the die can be a flip chip die and have solder bumps on the die bond pads, and then the die is mounted on the leadframe with the active side of the die facing the leadframe such that the die bond pads are in direct contact with the leads.

[0033] In step 490, the wire bonding step is followed by an encapsulation or molding step, where the leadframe, die, and bonding wires are covered with a molding compound 522, as is known in the art. The molding step preferably includes a molded array process (MAP), where several components formed on an array of leadframes are all molded simultaneously. After the molding step, laser marking is performed, and if there is a tape on the bottom surface of the leadframe array, the tape is removed in a de-taping step.

[0034] In step 495, the components are separated from each other in a singulation step, where a saw blade cuts the assembled device and separates the assembled devices from each other. The polymeric material 508 prevents any accumulation of burrs or other defects in the plating 506. Thus, no further deburring or processing is required.

[0035] Figures 5 to 9 Shows a simplified cross-sectional view of a series of manufacturing steps for forming Figure 1 a device according to an embodiment.

[0036] Reference Figures 5 to 9 , Figures 5 to 9 shows a simplified cross-sectional view of a series of manufacturing steps 410 - 495 for a semiconductor package 100 according to an embodiment for Figure 1 forming the same.

[0037] Reference Figure 5 , the leadframe 502 includes an array of leadframes having pits 504. In Figure 6 , after the plating 506 has been formed as described herein with respect to Figure 4 , the polymeric material 508 is disposed in the pits 508. The polymeric material 508 is used to prevent the formation of burrs, smears, and other defects on the plating 506 during the singulation process. In a preferred embodiment, the polymeric material 508 forms to a thickness of 20 microns or greater in at least a portion of the pits 504. The polymeric material 508 can include thermoplastic materials, thermosetting materials, such as polyimide materials, polyacrylate materials, silicone materials, combinations thereof, etc. Figure 7 Shows an optional step 460, where a tape 510 is provided on the leadframe or an array of leadframes.

[0038] Reference Figure 8, the die 520 is attached, mounted, and affixed to the leads of a lead frame (such as each lead frame) by wire bonding with a bonding material 522, wherein the die bonding pads are electrically connected to corresponding leads among the leads by bonding wires 524. In Figure 9 , the components have been separated from each other in a single parting step 495. The polymeric material 508 prevents any accumulation of burrs, smudges, or other defects of the plating 506, thereby showing a burr-free or defect-free pit 524( Figure 1 ).

[0039] Figure 10 is a perspective view of a semiconductor package device having burr-free pits according to another embodiment. Referring to Figure 10 , referring to Figure 4 The process described can also be used to form burr-free or defect-free pits without an additional deburring process step. Figure 10 includes a SON semiconductor having a generally square or rectangular shape and being smaller. For example, in one embodiment, the semiconductor package 100 is about 0.6 mm × 0.6 mm (L × W) or smaller. The package includes a body 1002, leads 1004, and a thermal pad 1006. The leads 1004 include burr-free pits 1008. The burr-free pits 1008 can be used as enhancing features for forming wettable sides, for example, enhancing features configured to meet a predetermined lead pitch standard, a closer geometry, etc. Different from the related art, the pits 1008 are burr-free, stain-free, or free of other defects without an additional deburring process step for removing burrs or other defects formed during the single parting process.

[0040] In some aspects, the techniques described herein relate to a method of forming a lead frame for a semiconductor package, including: providing a sheet of conductive material; applying a resist material on the sheet of conductive material in a predetermined pattern; etching the conductive material to form a lead frame having leads extending to the corners of the lead frame such that each corner lead has a pit formed at its outer surface; applying a metal or metal alloy to the exposed lead ends of the leads; and applying a polymeric material to a portion of the pits to a predetermined thickness.

[0041] In some aspects, the techniques described herein relate to a method in which the metal or metal alloy is applied by electroplating or electrodeposition.

[0042] In some aspects, the techniques described herein relate to a method in which the predetermined thickness is 20 microns or greater.

[0043] In some aspects, the techniques described herein relate to a method in which the metal or metal alloy includes one or more of NiPdAu, NiPdAuAg, and NiPd.

[0044] In some aspects, the techniques described herein relate to a method that additionally includes applying a tape to a portion of a lead frame.

[0045] In some aspects, the techniques described herein relate to a method in which the polymeric material includes a thermoplastic material.

[0046] In some aspects, the techniques described herein relate to a method in which the polymeric material includes a material selected from the group consisting of a thermoplastic polymer and a thermosetting polymer.

[0047] In some aspects, the techniques described herein relate to a method in which the polymeric material includes a material selected from the group consisting of polyimide, polyacrylate, and silicone.

[0048] In some aspects, the techniques described herein relate to a method that additionally includes cutting the lead frame through a pit and a portion of the polymeric material, wherein the pit of each corner lead has no burrs or defects after cutting.

[0049] In some aspects, the techniques described herein relate to a method of forming a semiconductor package having burr-free pits, including: providing an array of rectangular lead frames, wherein each lead frame in the array of rectangular lead frames has leads extending to the corners of each lead frame and pits at the outer surfaces of the leads; applying a metal or metal alloy to the exposed lead ends of the leads; applying a polymeric material in a portion of the pits, wherein the polymeric material is configured to prevent the accumulation of defects including one or more burrs; mounting and attaching a semiconductor die to the lead frame; electrically connecting bond pads on the semiconductor die to each semiconductor die on a different lead among the leads of the lead frame on which the semiconductor die is mounted; and encapsulating the semiconductor die and the electrical connections with a molding compound; and cutting the array of lead frames through the pits and a portion of the polymeric material to separate individual devices from adjacent devices, whereby each device has corner bond pads configured to be substantially flush with its molding compound, and wherein the pits of each corner lead have no burrs or defects after cutting.

[0050] In some aspects, the techniques described herein relate to a method in which the metal or alloy is applied by electroplating or electrodeposition.

[0051] In some aspects, the techniques described herein relate to a method in which the metal or metal alloy includes one or more of NiPdAu, NiPdAuAg, and NiPd.

[0052] In some aspects, the techniques described herein relate to a method in which the step of electrically connecting includes attaching bonding wires to the die bond pads and the corresponding leads in the leads.

[0053] In some aspects, the techniques described herein relate to a method in which a non-active side of a semiconductor die is attached to leads of each lead frame in a corresponding lead frame.

[0054] In some aspects, the techniques described herein relate to a method in which a polymeric material comprises a thermoplastic material.

[0055] In some aspects, the techniques described herein relate to a method in which a polymeric material comprises a material selected from the group consisting of a thermoplastic polymer and a thermosetting polymer.

[0056] In some aspects, the techniques described herein relate to a method in which a polymeric material comprises a material selected from the group consisting of polyimide, polyacrylate, and silicone.

[0057] In some aspects, the techniques described herein relate to a method in which a polymeric material comprises a material having a thickness formed to be about 20 micrometers or greater.

[0058] In some aspects, the techniques described herein relate to a semiconductor package comprising: a lead frame including a plurality of leads; a semiconductor die mounted on the lead frame, wherein bonding pads on the semiconductor die are electrically connected to corresponding ones of the leads; and a molding compound encapsulating the semiconductor die, the leads, and the electrical connections, wherein ends of the leads are exposed at corner sidewalls of the semiconductor package, and wherein an exposed portion of each of the leads is flush with two adjacent sides of the device and includes a pit, and the pit includes a polymeric material disposed in a portion of the pit.

[0059] In some aspects, the techniques described herein relate to a semiconductor package in which a polymeric material comprises a material selected from the group consisting of a thermoplastic polymer and a thermosetting polymer.

[0060] For simplicity, conventional semiconductor manufacturing techniques may not be described in detail herein. Additionally, certain terms may be used herein only for reference purposes, and thus such terms are not intended to be limiting, and unless the context clearly indicates otherwise, the terms “first,” “second,” and other such numerical terms referring to structures do not imply an order or sequence.

[0061] The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that an element is directly joined to another element (or directly communicates with another element), and not necessarily joined mechanically. Similarly, unless otherwise expressly stated, "coupled" means that an element is directly or indirectly joined to another element (or directly or indirectly communicates with another element), and not necessarily joined mechanically. Thus, although the schematic illustrations shown in the figures depict an exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in embodiments of the subject matter depicted.

[0062] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that a vast number of variations exist. It should also be understood that one or more of the exemplary embodiments described herein are not intended to limit in any way the scope, applicability, or configuration of the claimed subject matter. Indeed, the foregoing detailed description will provide those skilled in the art with a convenient guide for implementing one or more of the described embodiments. It should be understood that various changes may be made in the function and arrangement of elements without departing from the scope defined by the claims, which scope includes known equivalents and foreseeable equivalents at the time of filing this patent application.

Claims

1. A method for forming a lead frame for a semiconductor package, characterized in that: include: providing a sheet of conductive material; applying a resist material in a predetermined pattern on the sheet of conductive material; etching the conductive material to form a lead frame having leads extending to corners of the lead frame such that each corner lead has a dimple formed at an outer surface thereof; applying a metal or metal alloy to the exposed lead ends of the leads; as well as A polymer material is applied to a portion of the recess to a predetermined thickness.

2. The method according to claim 1, characterized in that The metal or metal alloy is applied by electroplating or electrodeposition.

3. The method according to claim 1, characterized in that The predetermined thickness is 20 micrometers or greater.

4. The method according to claim 1, characterized in that The metal or metal alloy includes one or more of NiPdAu, NiPdAuAg and NiPd.

5. The method according to claim 1, characterized in that Also included is applying tape to portions of the lead frame.

6. The method according to claim 1, characterized in that The polymer material includes a thermoplastic material.

7. The method according to claim 1, characterized in that The polymer material includes a material selected from the group consisting of thermoplastic polymers and thermosetting polymers, or the polymer material includes a material selected from the group consisting of polyimide, polyacrylate, and silicone.

8. The method according to claim 1, characterized in that Also included is cutting the lead frame through the dimple and a portion of the polymer material, wherein the dimple of each corner lead is free of burrs or defects after cutting.

9. A method for forming a semiconductor package having a burr-free pit, characterized in that: include: providing a rectangular lead frame array, wherein each lead frame in the rectangular lead frame array has leads extending to corners of each lead frame and dimples at outer surfaces of the leads; applying a metal or metal alloy to the exposed lead ends of the leads; applying a polymer material in a portion of the dimple, wherein the polymer material is configured to prevent accumulation of defects including one or more burrs; mounting and attaching a semiconductor die to the lead frame; electrically connecting a bonding pad on the semiconductor die to each semiconductor die on a different one of the leads of the lead frame on which the semiconductor die is mounted; as well as encapsulating the semiconductor die and electrical connections with a molding compound; as well as The lead frame array is cut through the dimples and a portion of the polymer material to separate individual devices from adjacent devices, whereby each device has a corner bond pad configured to be substantially flush with its molding compound, and wherein the dimples of each corner lead are free of burrs or defects after cutting.

10. A semiconductor package, characterized in that: include: A lead frame, the lead frame comprising a plurality of leads; a semiconductor die mounted on the lead frame, wherein bonding pads on the semiconductor die are electrically connected to corresponding ones of the leads; as well as a molding compound encapsulating the semiconductor die, the leads, and the electrical connections, wherein ends of the leads are exposed at corner sidewalls of the semiconductor package, and Wherein an exposed portion of each of the leads is flush with two adjacent sides of the device and comprises a recess comprising a polymer material disposed in a portion of the recess.

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