Manufacturing method of semiconductor device
By forming a double-step trench structure during the manufacturing process of semiconductor devices, the problem that single step is not conducive to metal layer filling is solved, and the effect of reducing the metal layer volume and process cost is achieved.
Patent Information
- Application Number
- CN202311785543.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-22
- Publication Date
- 2025-06-24
AI Technical Summary
In the rear-stage process of semiconductor devices, when forming an interconnect structure, the single step trench is not conducive to the filling of the metal layer, resulting in the excessive volume of the metal layer and increasing the process cost.
By forming a first dielectric layer, a second dielectric layer and a third dielectric layer in sequence on the substrate, and forming a patterned photoresist layer on the third dielectric layer, the first trench and the second trench are etched to form a step-shaped at the junction of the lower part of the trench and the upper part, forming a double step structure for subsequent metal layer filling.
It realizes the reduction of the volume of the metal layer filled in the trench, saves masks, reduces process costs, and improves the reliability of semiconductor devices.
Smart Images
Figure CN120199727A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly relates to a manufacturing method of a semiconductor device. Background Art
[0002] With the continuous development of integrated circuit manufacturing technology, the integration degree of integrated circuits is getting higher and higher. In the back-end process of semiconductor devices, an interconnect structure needs to be formed. When forming the interconnect structure, trenches need to be formed in the dielectric layer first, and then a metal layer is filled in the trenches to form the interconnect structure. In order to improve the reliability of semiconductor devices with large-sized scribe lines (Seal ring) and reduce the delay of RC (resistance-capacitance) signals, the damascene process is usually adopted. The process methods of damascene include two types: via first and trench first or trench first and via first in the dielectric layer. Specifically, as Figure 1 shown, a dielectric layer 11 is formed on a substrate 10. Trenches 11a are formed by etching the dielectric layer 11. The junction between the trenches 11a and the dielectric layer 11 has a single step, but the single step is not conducive to the subsequent filling of the metal layer. Summary of the Invention
[0003] The purpose of the present invention is to provide a manufacturing method of a semiconductor device to reduce the volume of the metal layer filled in the trench, save masks, and reduce the process cost.
[0004] To achieve the above purpose, the present invention provides a manufacturing method of a semiconductor device, including:
[0005] Providing a substrate, on which a first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially stacked. Through holes are formed in the third dielectric layer, the second dielectric layer, and the first dielectric layer, and the material of the second dielectric layer is different from the materials of the first dielectric layer and the third dielectric layer;
[0006] Forming a patterned photoresist layer on the third dielectric layer, and the patterned photoresist layer exposes the through holes and part of the third dielectric layer;
[0007] Using the patterned photoresist layer as a mask to etch the exposed third dielectric layer to form a first trench, the first trench exposes part of the second dielectric layer. The junction between the lower part and the upper part of the first trench is stepped, and the width of the lower part of the first trench is smaller than the width of the upper part of the first trench;
[0008] Using the patterned photoresist layer as a mask, sequentially etch the third dielectric layer and the second dielectric layer below the first trench to form a second trench, where the second trench communicates with the through hole. Among them, the top surface and the side wall of the second dielectric layer in the second trench form a first step, and the top surface and the side wall of the first dielectric layer at the bottom of the second trench form a second step; and,
[0009] Fill the metal layer in the second trench and the through hole.
[0010] Optionally, in the manufacturing method of the semiconductor device, before forming the patterned photoresist layer on the third dielectric layer, the manufacturing method of the semiconductor device further includes:
[0011] Fill a bottom anti-reflection layer in the through hole, and the top surface of the bottom anti-reflection layer is lower than the top surface of the third dielectric layer.
[0012] Optionally, in the manufacturing method of the semiconductor device, the patterned photoresist layer has an opening, the opening is aligned with the bottom anti-reflection layer, and the width of the opening is greater than the width of the bottom anti-reflection layer and exposes a part of the third dielectric layer.
[0013] Optionally, in the manufacturing method of the semiconductor device, the method of etching the exposed third dielectric layer to form the first trench using the patterned photoresist layer as a mask includes:
[0014] Using the patterned photoresist layer as a mask, perform a main etch on a partial thickness of the third dielectric layer and a partial thickness of the bottom anti-reflection layer in the third dielectric layer to form the upper part of the first trench; and,
[0015] Perform an over-etch on the remaining third dielectric layer and the bottom anti-reflection layer in the third dielectric layer below the upper part of the first trench to form the lower part of the first trench.
[0016] Optionally, in the manufacturing method of the semiconductor device, during the main etch process, the etching gas used includes carbon tetrafluoride and oxygen.
[0017] Optionally, in the manufacturing method of the semiconductor device, during the over-etch process, the etching selectivity of the third dielectric layer is greater than the etching selectivity of the second dielectric layer. Among them, the etching gas used during the over-etch process includes octafluorocyclobutane and oxygen, and the flow rate of the oxygen gas during the over-etch process is less than the flow rate of the oxygen gas during the main etch process.
[0018] Optionally, in the method for manufacturing the semiconductor device, during the main etching and over-etching processes, polymers are formed on the sidewalls and bottom of the first trench, and the thickness of the polymers formed during the over-etching process is greater than that of the polymers formed during the main etching process.
[0019] Optionally, in the method for manufacturing the semiconductor device, during the process of etching the second dielectric layer below the first trench, the bottom anti-reflection layer is also etched to remove the bottom anti-reflection layer in the second dielectric layer;
[0020] After forming the second trench and before filling the metal layer, the patterned photoresist layer and the remaining bottom anti-reflection layer are removed.
[0021] Optionally, in the method for manufacturing the semiconductor device, a conductive layer and an etch stop layer covering the conductive layer are further formed between the substrate and the first dielectric layer, and the via also penetrates through the etch stop layer.
[0022] Optionally, in the method for manufacturing the semiconductor device, the materials of the first dielectric layer and the third dielectric layer are both silicon oxide, and the material of the second dielectric layer is silicon nitride.
[0023] In the method for manufacturing the semiconductor device provided by the present invention, there are vias in the third dielectric layer, the second dielectric layer, and the first dielectric layer. By using the patterned photoresist layer as a mask, the exposed third dielectric layer in the patterned photoresist layer is etched to form a first trench. The first trench exposes part of the second dielectric layer. The junction between the lower part and the upper part of the first trench is stepped and the width of the lower part of the first trench is smaller than that of the upper part of the first trench. Then, using the patterned photoresist layer as a mask, the third dielectric layer and the second dielectric layer below the first trench are etched in sequence to form a second trench. Among them, the second trench communicates with the via. The top surface and the sidewall of the second dielectric layer in the second trench form a first step, and the top surface and the sidewall of the first dielectric layer at the bottom of the second trench form a second step, that is, a double step is formed. In this way, it is beneficial to the subsequent filling of the metal layer and can reduce the volume of the metal layer filled in the second trench and the via subsequently. In addition, the double step is formed by one patterned photoresist layer (or one mask), which can save one mask and reduce the process cost. Description of the Drawings
[0024] Figure 1 is a schematic cross-sectional view of the structure of a semiconductor device in the prior art;
[0025] Figure 2 is a schematic flow chart of the method for manufacturing the semiconductor device provided by the embodiment of the present invention;
[0026] Figures 3 to 10 It is a schematic cross-sectional view of a structure formed in the manufacturing method of a semiconductor device provided by an embodiment of the present invention;
[0027] Figure 11 It is a SEM schematic diagram when forming a metal layer in the manufacturing method of a semiconductor device provided by an embodiment of the present invention;
[0028] The description of the reference numerals in the drawings is as follows:
[0029] 10 - Substrate; 11 - Dielectric layer; 11a - Trench;
[0030] 100 - Substrate; 101 - First dielectric layer; 102 - Second dielectric layer; 103 - Third dielectric layer; 104 - Conductive layer; 105 - Etch stop layer; 106 - Through hole; 110 - Bottom anti - reflection layer; 120 - Patterned dielectric anti - reflection layer; 130 - Patterned photoresist layer; 130a - Opening; 140 - First trench; 140a - Upper part; 140b - Lower part; 141 - Polymer; 150 - Second trench; 150a - First step; 150b - Second step; 160 - Metal layer. Detailed implementation manners
[0031] The following further describes in detail the manufacturing method of the semiconductor device proposed by the present invention in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non - precise scales, only for facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.
[0032] Figure 1 It is the manufacturing method of a semiconductor device provided by an embodiment of the present invention. As Figure 1 shown, an embodiment of the present invention provides a manufacturing method of a semiconductor device, including:
[0033] Step S1: Provide a substrate, on which a first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially stacked. There are through holes in the third dielectric layer, the second dielectric layer, and the first dielectric layer, and the material of the second dielectric layer is different from the materials of the first dielectric layer and the third dielectric layer;
[0034] Step S2: Form a patterned photoresist layer on the third dielectric layer, and the patterned photoresist layer exposes the through holes and part of the third dielectric layer;
[0035] Step S3: Using the patterned photoresist layer as a mask, etching the exposed third dielectric layer to form a first trench, the first trench exposing a part of the second dielectric layer, the junction between the lower part and the upper part of the first trench being stepped, and the width of the lower part of the first trench being smaller than the width of the upper part of the first trench;
[0036] Step S4: Using the patterned photoresist layer as a mask, etching the third dielectric layer and the second dielectric layer below the first trench in sequence to form a second trench, the second trench communicating with the through hole, wherein the top surface and the side wall of the second dielectric layer in the second trench form a first step, and the top surface and the side wall of the first dielectric layer at the bottom of the second trench form a second step; and,
[0037] Step S5: Filling a metal layer in the second trench and the through hole.
[0038] Figures 3 to 10 is a schematic cross-sectional view of a structure formed in the manufacturing method of a semiconductor device provided by an embodiment of the present invention. The following will be combined with the attached Figures 3 to 10 to describe in more detail the manufacturing method of the semiconductor device provided by this embodiment.
[0039] Refer to Figure 3 , perform step S1 to provide a substrate 100, on which a first dielectric layer 101, a second dielectric layer 102, and a third dielectric layer 103 are sequentially stacked. A through hole 106 is formed in the third dielectric layer 103, the second dielectric layer 102, and the first dielectric layer 101, and the material of the second dielectric layer 102 is different from the materials of the first dielectric layer 101 and the third dielectric layer 103. In this embodiment, the substrate 100 may be a silicon substrate 100, and required electronic components, such as transistors, may be prefabricated in the substrate 100.
[0040] As an example, the materials of the first dielectric layer 101 and the third dielectric layer 103 may be silicon oxide, and the material of the second dielectric layer 102 may be silicon nitride.
[0041] As Figure 3 shown, a conductive layer 104 and an etch stop layer 105 covering the conductive layer 104 are further formed between the substrate 100 and the first dielectric layer 101. Among them, the conductive layer 104 may be used to form an interconnect structure, and the material of the conductive layer 104 may be a metal, such as copper or aluminum, etc. The material of the etch stop layer 105 may be nitrogen-doped silicon carbide (NDC, Nitrogen doped Silicon Carbide)
[0042] Next, asFigure 4 As shown, a dry etching process can be adopted to etch the third dielectric layer 103, the second dielectric layer 102, and the first dielectric layer 101 in sequence to form a through hole 106, that is, the through hole 106 penetrates the third dielectric layer 103, the second dielectric layer 102, and the first dielectric layer 101, and the through hole 106 can also extend into the etch stop layer 105; and, as Figure 5 shown, a bottom anti-reflection coating (BARC) 110 is filled in the through hole 106, and the top surface of the bottom anti-reflection coating 110 is lower than the top surface of the third dielectric layer 103. The material of the bottom anti-reflection coating 110 can be an organic material, so that the bottom anti-reflection coating 110 has a certain fluidity and can fill the entire through hole 106. Among them, the bottom anti-reflection coating 110 can also extend into the etch stop layer 105.
[0043] As Figure 6 shown, step S2 is performed to form a patterned photoresist layer 130 on the third dielectric layer 103, and the patterned photoresist layer 130 exposes a part of the third dielectric layer 103. Specifically, a photoresist layer can be formed on the third dielectric layer 103 by spin coating, and the photoresist layer is patterned by exposure and development processes to form the patterned photoresist layer 130. The patterned photoresist layer 130 has an opening 130a, the opening 130a is aligned with the bottom anti-reflection coating 110, and the width of the opening 130a is greater than the width of the bottom anti-reflection coating 110 and exposes a part of the third dielectric layer 103.
[0044] In this embodiment, as Figure 6 shown, before forming the patterned photoresist layer 130, a dielectric anti-reflection coating (DARC) can be first formed on the third dielectric layer 103, and then, a patterned photoresist layer 130 is formed on the dielectric anti-reflection coating, and the dielectric anti-reflection coating is etched using the patterned photoresist layer 130 as a mask to form a patterned dielectric anti-reflection layer 120. Among them, the material of the dielectric anti-reflection coating can be silicon oxynitride.
[0045] As Figure 8 shown, step S3 is performed to etch the exposed third dielectric layer 103 using the patterned photoresist layer 130 as a mask to form a first trench 140, the first trench 140 exposes a part of the second dielectric layer 102, the junction of the lower part 140b and the upper part 140a of the first trench 140 is stepped, and the width of the lower part 140b of the first trench 140 is smaller than the width of the upper part 140a of the first trench 140.
[0046] Specifically, the method for forming the first trench 140 includes: First, as Figure 6 shown, using the patterned photoresist layer 130 as a mask, a main etching is performed on a partial thickness of the third dielectric layer 103 and a partial thickness of the bottom anti-reflection layer 110 in the third dielectric layer 103 to form the upper portion 140a of the first trench 140. That is, after the main etching, a partial thickness of the third dielectric layer 103 remains below the upper portion 140a of the first trench 140.
[0047] In this embodiment, the etching process used for the main etching is a plasma etching process, and the etching gas used in the main etching process includes carbon tetrafluoride and oxygen. Since the etching gas in the main etching process includes oxygen, during the main etching process, a polymer will be formed on the top surface of the etched third dielectric layer 103 and the sidewalls and bottom of the upper portion 140a of the first trench 140. The polymer can block etching during the main etching process, which is beneficial to stopping the etching at the top surface of the partial thickness of the third dielectric layer 103.
[0048] Then, as Figure 8 shown, an over-etching is performed on the remaining third dielectric layer 103 below the upper portion 140a of the first trench 140 and the bottom anti-reflection layer 110 in the third dielectric layer 103 to form the lower portion 140b of the first trench 140. Further, since there is a vertex angle at the junction of the third dielectric layer 103 and the bottom anti-reflection layer 110 (as shown in the Figure 6 dashed box), during the over-etching process, charges are likely to accumulate at the vertex angle. Therefore, the etching rate of the third dielectric layer 103 at the junction with the bottom anti-reflection layer 110 is faster than that of the third dielectric layer 103 in other regions. Thus, after the third dielectric layer 103 near the junction with the bottom anti-reflection layer is removed, a part of the third dielectric layer 103 far from the bottom anti-reflection layer 110 remains, so that the junction of the lower portion 140b and the upper portion 140a of the formed first trench 140 is stepped (as shown in the Figure 7 figure).
[0049] Further, the etching selectivity of the third dielectric layer 103 during the over-etching process is greater than that of the second dielectric layer 102. In this way, a higher etching selectivity ratio can be achieved between the third dielectric layer 103 and the second dielectric layer 102. During the over-etching process, a polymer 141 is formed on the sidewalls and bottom of the first trench 140. The thickness of the polymer 141 at the bottom of the first trench 140 is greater than that of the polymer 141 on the sidewalls of the first trench 140. The polymer 141 at the bottom of the first trench 140 can block the vertical etching during the etching process, thereby reducing the vertical etching rate of the third dielectric layer 103 and increasing the lateral etching rate of the third dielectric layer 103, so that the etching stops on the surface of the second dielectric layer 102.
[0050] In this embodiment, the etching gas used during the over-etching process includes perfluorocyclobutane, so that a higher etching selectivity ratio can be achieved between the third dielectric layer 103 and the second dielectric layer 102 during the etching process. The etching selectivity ratio can be greater than 20:1, for example. Further, the etching gas used during the over-etching process also includes oxygen, and the flow rate of the oxygen gas during the over-etching process is lower than that of the oxygen gas during the main etching process. In this way, the thickness of the polymer 141 generated during the over-etching process can be adjusted. The flow rate of the oxygen gas during the over-etching process can be 30% - 50% lower than that of the oxygen gas during the main etching process to increase the thickness of the polymer 141 formed during the over-etching process, thereby blocking the vertical etching. During the over-etching process, the polymer 141 will adhere to the etching surface, that is, a polymer 141 can be formed on the exposed surface of the second dielectric layer 102 (i.e., the bottom of the first trench 140), which is beneficial to blocking the etching and making the over-etching stop on the surface of the second dielectric layer 102. Among them, the polymer 141 is formed by the combination of the patterned photoresist layer 130 during the over-etching process, the oxygen in the etching gas, and the etching products.
[0051] Next, step S4 is executed. Using the patterned photoresist layer 130 as a mask, the third dielectric layer 103 and the second dielectric layer 102 below the first trench 140 are etched in sequence to form a second trench 150, and the second trench 150 communicates with the through hole 106. Specifically, the method for forming the second trench 150 includes: using the patterned photoresist layer 130 as a mask, etching the third dielectric layer 103 at the junction of the upper part 140a and the lower part 140b of the first trench 140 and a part of the thickness of the second dielectric layer 102 below it, and etching the second dielectric layer 102 exposed at the bottom of the first trench 140 to form the second trench 150.
[0052] Specifically, a dry etching process, such as a plasma etching process, may be employed to sequentially etch the third dielectric layer 103 at the junction of the upper portion 140a and the lower portion 140b of the first trench 140 and a partial thickness of the second dielectric layer 102 therebelow, and etch the second dielectric layer 102 exposed at the bottom of the first trench 140 to form a second trench 150. Herein, the etching rate of the second dielectric layer 102 may be the same as or close to the etching rate of the first dielectric layer 101. Since the junction of the upper portion 140a and the lower portion 140b of the first trench 140 is stepped, after etching the third dielectric layer 103 at the junction of the upper portion 140a and the lower portion 140b of the first trench 140 and a partial thickness of the second dielectric layer 102 therebelow, the etched second dielectric layer 102 below the junction of the upper portion 140a and the lower portion 140b of the first trench 140 is also stepped, that is, the top surface and the sidewall of the second dielectric layer 102 in the second trench 150 form a first step 150a.
[0053] As Figure 9 shown, in step S4, when etching the third dielectric layer 103 and the second dielectric layer 102, the portion of the bottom anti-reflection layer 110 located in the second dielectric layer 102 is also etched synchronously to remove the bottom anti-reflection layer 110 in the second dielectric layer 102, so that the formed second trench 150 penetrates through the second dielectric layer 102.
[0054] As Figure 9 shown, after forming the second trench 150, the patterned photoresist layer and the remaining bottom anti-reflection layer 110 are removed. Among them, an oxygen plasma may be used to remove the patterned photoresist layer 130 and the remaining bottom anti-reflection layer 110.
[0055] As Figure 9 shown, a part of the first dielectric layer 101 is exposed at the bottom of the second trench 150. The top surface and the sidewall (i.e., the sidewall of the through hole 106) of the first dielectric layer 101 at the bottom of the second trench 150 form a second step 150b, and the combination of the second step 150b and the first step 150a is beneficial to subsequent metal layer filling.
[0056] Next, step S5 is performed. As Figure 10 shown, a metal layer 160 is filled in the second trench 150 and the through hole 106. The metal layer 160 may be filled by an electroplating process (ECP). Using the metal layer 160, the second trench 150, and the through hole 106, a damascene structure can be formed, which can reduce the RC (resistance-capacitance) delay of the transmitted signal. Among them, the material of the metal layer 160 may be aluminum or copper.
[0057] Figure 11 It is a SEM schematic diagram when forming a metal layer in the manufacturing method of the semiconductor device provided by the embodiment of the present invention. As Figure 11 shown, due to the existence of the first step 150a and the second step 150b, the metal layer 160 can be fully filled in the second trench 150 and the through hole 106, improving the filling effect and the reliability of the semiconductor device.
[0058] In this embodiment, the metal layer 160, the second trench 150 and the through hole 106 can be used to form an interconnect structure. The interconnect structure can be located in the scribe line area of the substrate 100. Due to the existence of the first step 150a and the second step 150b, the volume of the metal layer 160 filled in the second trench 150 and the through hole 106 can be reduced, the area of the scribe line area occupied by the metal layer 160 can be reduced, and the wiring space in the scribe line area can be increased. In another embodiment, the second trench 150, the through hole 106 and the metal layer 160 can be located in the device area of the substrate 100.
[0059] In summary, in the manufacturing method of the semiconductor device provided by the present invention, there are through holes in the third dielectric layer, the second dielectric layer and the first dielectric layer. First, using the patterned photoresist layer as a mask, the exposed third dielectric layer in the patterned photoresist layer is etched to form a first trench. The first trench exposes part of the second dielectric layer. The junction between the lower part and the upper part of the first trench is stepped and the width of the lower part of the first trench is smaller than the width of the upper part of the first trench. Then, using the patterned photoresist layer as a mask, the third dielectric layer and the second dielectric layer below the first trench are etched in sequence to form a second trench. The second trench communicates with the through hole. Among them, the top surface and the side wall of the second dielectric layer in the second trench form a first step, and the top surface and the side wall of the first dielectric layer at the bottom of the second trench form a second step, that is, a double step is formed. In this way, it is beneficial to the subsequent filling of the metal layer and the volume of the metal layer filled in the second trench and the through hole can be reduced. In addition, the double step is formed by one layer of patterned photoresist layer (or one mask), which can save one mask and reduce the process cost.
[0060] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, Including: Providing a substrate on which a first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially stacked. Through holes are formed in the third dielectric layer, the second dielectric layer, and the first dielectric layer, and the material of the second dielectric layer is different from the materials of the first dielectric layer and the third dielectric layer; Forming a patterned photoresist layer on the third dielectric layer, the patterned photoresist layer exposing the through holes and part of the third dielectric layer; Using the patterned photoresist layer as a mask to etch the exposed third dielectric layer to form a first trench, the first trench exposing part of the second dielectric layer. The junction between the lower part and the upper part of the first trench is stepped, and the width of the lower part of the first trench is smaller than the width of the upper part of the first trench; Using the patterned photoresist layer as a mask to sequentially etch the third dielectric layer and the second dielectric layer below the first trench to form a second trench, the second trench communicating with the through hole. Wherein, the top surface and the side wall of the second dielectric layer in the second trench form a first step, and the top surface and the side wall of the first dielectric layer at the bottom of the second trench form a second step; And, Filling a metal layer in the second trench and the through hole.
2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Before forming the patterned photoresist layer on the third dielectric layer, the manufacturing method of the semiconductor device further includes: Filling a bottom anti-reflection layer in the through hole, the top surface of the bottom anti-reflection layer being lower than the top surface of the third dielectric layer.
3. The manufacturing method of the semiconductor device according to claim 2, wherein, The patterned photoresist layer has an opening, the opening being aligned with the bottom anti-reflection layer, and the width of the opening being greater than the width of the bottom anti-reflection layer and exposing part of the third dielectric layer.
4. The manufacturing method of the semiconductor device according to claim 3, characterized in that, The method of etching the exposed third dielectric layer to form the first trench using the patterned photoresist layer as a mask includes: Using the patterned photoresist layer as a mask to perform a main etch on a partial thickness of the third dielectric layer and a partial thickness of the bottom anti-reflection layer in the third dielectric layer to form the upper part of the first trench; and, Performing an over-etch on the remaining third dielectric layer and the bottom anti-reflection layer in the third dielectric layer below the upper part of the first trench to form the lower part of the first trench.
5. The manufacturing method of the semiconductor device according to claim 4, characterized in that, During the main etch process, the etching gas used includes carbon tetrafluoride and oxygen.
6. The manufacturing method of the semiconductor device according to claim 5, characterized in that, During the over-etch process, the etching selectivity of the third dielectric layer is greater than the etching selectivity of the second dielectric layer. Wherein, the etching gas used during the over-etch process includes octafluorocyclobutane and oxygen, and the flow rate of the oxygen gas during the over-etch process is less than the flow rate of the oxygen gas during the main etch process.
7. The manufacturing method of the semiconductor device according to claim 6, characterized in that, During the main etch and the over-etch processes, a polymer is formed on the side walls and the bottom of the first trench, and the thickness of the polymer formed during the over-etch process is greater than the thickness of the polymer formed during the main etch process.
8. The manufacturing method of the semiconductor device according to claim 2, characterized in that, During the process of etching the second dielectric layer below the first trench, the bottom anti-reflection layer is also etched to remove the bottom anti-reflection layer in the second dielectric layer; and, After forming the second trench and before filling the metal layer, the patterned photoresist layer and the remaining bottom anti-reflection layer are removed.
9. The manufacturing method of the semiconductor device according to claim 1, characterized in that, A conductive layer and an etch stop layer covering the conductive layer are further formed between the substrate and the first dielectric layer, and the via also penetrates through the etch stop layer.
10. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The materials of the first dielectric layer and the third dielectric layer are both silicon oxide, and the material of the second dielectric layer is silicon nitride.