Method for manufacturing package substrate and package substrate using same

Abstract

The present invention provides a method of manufacturing a package substrate and a package substrate using the same, the package substrate according to an embodiment of the present invention comprising: a glass substrate having a first surface and a second surface facing each other; a cavity portion formed in the glass substrate; and a cavity element disposed in the cavity portion, the cavity portion including: a cavity space into which at least a portion of the cavity element is inserted; and a side wall surrounding the cavity space, in which a gap is disposed between one side surface of the cavity element and the side wall, the gap being formed by being filled with one or more types of filler materials, and the length of the gap being 50 [mu] m or less. Accordingly, the volume for filling the gap between the side wall of the cavity part and the cavity element can be reduced, the usable area of the glass substrate can be increased, the loss of the filling material can be reduced, and the effect of facilitating additional formation of the accumulation layer can be generated by reducing surface disturbance.

Description

Technical Field

[0001] The embodiments relate to a packaging substrate, a semiconductor package, a method for manufacturing a packaging substrate, a method for manufacturing a semiconductor package, etc. Background Art

[0002] In the manufacture of electronic products, the process of implementing a circuit on a semiconductor wafer is called the front-end process (FE), and the process of assembling the wafer into a state that can be used in a physical product is called the back-end process (BE). The packaging process is included in this back-end process.

[0003] Recently, the four core technologies of the semiconductor industry that can enable the rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is developing in various forms such as a line width in nanometer units below microns, more than tens of millions of cells, high-speed operation, and a large amount of heat dissipation. However, there is no corresponding perfect packaging technology to support it. Accordingly, the electrical performance of a semiconductor is determined more by the packaging technology and its electrical connection than by the performance of the semiconductor technology itself.

[0004] As materials for packaging substrates, ceramics or resins are used. In the case of a ceramic substrate such as a silicon substrate, it has a high resistance value or a high dielectric constant, making it difficult to mount high-performance high-frequency semiconductor components. In the case of a resin substrate, high-performance high-frequency semiconductor components can be relatively mounted. However, there are limitations in shortening the pitch of the wiring.

[0005] Recently, silicon or glass can be used as a high-end packaging substrate. Through holes are formed in the silicon or glass substrate, and a conductive substance is applied to the through holes, thereby shortening the wiring length between the components and the motherboard and having excellent electrical characteristics.

[0006] Moreover, a semiconductor package can generate heat during operation and also includes a heat dissipation unit for releasing such heat.

[0007] As related prior arts, for example, Korean Patent Publication No. 10-2021-0022980, Korean Patent Publication No. 10-2022-0050121, etc. are cited. Summary of the Invention

[0008] Technical Problem to be Solved

[0009] The purpose of the embodiments is to provide a method for manufacturing a packaging substrate and a packaging substrate using the same, in which, in a packaging substrate using a glass substrate, the gap between the side wall of the cavity portion and the cavity component is configured to have a smaller volume.

[0010] In addition, an object of the embodiment is to provide a method for manufacturing a packaged substrate and a packaged substrate using the same. By forming the side wall of the cavity portion obliquely to form a gap in a tapered form, surface fluctuation is reduced by methods such as reducing the loss of the filling material used to fill the gap, which is beneficial to the formation of the stacked layer.

[0011] Technical solution for solving the problem

[0012] To achieve the above object, a packaged substrate according to an embodiment includes: a glass substrate having a first surface and a second surface opposite to each other; a cavity portion formed in the glass substrate; and a cavity element disposed in the cavity portion.

[0013] The cavity portion includes: a cavity space for inserting at least a part of the cavity element; and a side wall surrounding the cavity space, and a gap is disposed between one side surface of the cavity element and the side wall.

[0014] The gap may be filled with one or more filling materials to form.

[0015] The length of the gap may be 50 μm or less.

[0016] The side wall may be formed obliquely, and the angle between the side wall and the second surface is 65 degrees or more.

[0017] In the case where the side surface is inclined, the length of the gap may be the maximum value among the distances between the side wall and one side surface of the cavity element, and the length of the gap is 50 μm or less.

[0018] The cavity portion may be a full-cavity type, in which the cavity space penetrates the glass substrate; or, the cavity portion may be a semi-cavity type, in which the cavity space is in a form recessed from the first surface or the second surface of the glass substrate.

[0019] The cavity portion may have an open surface at the opening of the cavity space and a bottom surface of the recessed portion of the cavity space or a bottom surface facing the open surface, and the area of the open surface is larger than the area of the bottom surface.

[0020] The glass substrate may include a first cavity portion and a second cavity portion.

[0021] A first cavity element may be disposed in the first cavity portion, and a second cavity element may be disposed in the second cavity portion.

[0022] When observed from a cross-section, the sum of the gaps disposed on both sides of the first cavity element and the gaps disposed on both sides of the second cavity element may be 200 μm or less.

[0023] A first cavity element and a second cavity element may be disposed in the cavity portion.

[0024] When observed from a cross-section, the sum of the gaps disposed on both sides of the first cavity element and the gaps disposed on both sides of the second cavity element may be 150 μm or less.

[0025] In addition, in order to achieve the above object, a method for manufacturing a packaging substrate according to an embodiment includes: a step of preparing a glass substrate provided with a cavity portion and a cavity element; and a step of disposing and filling the cavity element in the cavity portion.

[0026] The glass substrate has a first surface and a second surface that face each other.

[0027] The cavity portion may include: a cavity space for inserting at least a part of the cavity element; and a side wall surrounding the cavity space, a gap being disposed between one side surface of the cavity element and the side wall, and in the filling step, the gap is filled with a filling material to form a filling portion.

[0028] The cavity portion may be a full-cavity type, wherein the cavity space penetrates the glass substrate, and the step of disposing the cavity element is performed in a state where a support layer is bonded under the second surface, and the support layer is removed after the filling step.

[0029] The side wall may be formed obliquely, and the required amount of the filling material is reduced by more than 30% compared with the case where the side wall is perpendicular to the second surface.

[0030] Technical effects

[0031] According to the method for manufacturing a packaging substrate, the packaging substrate, etc. according to the embodiment, the volume for filling the gap between the side wall of the cavity portion and the cavity element can be reduced. Accordingly, the usable area of the glass substrate can be increased, the loss of the filling material can be reduced, and the surface fluctuation can be reduced, which is beneficial to the effect of additionally forming a build-up layer.

[0032] Also, by forming the side wall of the cavity portion inclinedly, etc., the volume for filling the gap between the side wall of the cavity portion and the cavity element can be reduced. Accordingly, the usable area of the glass substrate can be increased, the loss of the filling material can be reduced, and the surface fluctuation can be reduced, which is beneficial to the effect of additionally forming a build-up layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 FIG. is a conceptual diagram illustrating an example of a glass substrate of a package substrate according to an embodiment.

[0034] Figure 2A AND Figure 2B FIGS. are conceptual diagrams respectively illustrating an A-A' cross-section of a glass substrate according to an embodiment.

[0035] Figure 3 FIG. is a diagram exemplarily showing the structure of a package substrate according to an embodiment.

[0036] Figure 4A AND Figure 4B FIGS. are conceptual diagrams respectively illustrating a cross-section of a glass substrate according to another embodiment.

[0037] Figure 5A AND Figure 5B FIGS. are conceptual diagrams respectively illustrating a cross-section of a glass substrate according to another embodiment.

[0038] Figure 6A AND Figure 6B FIGS. are conceptual diagrams respectively illustrating a cross-section of a glass substrate according to another embodiment.

[0039] Figure 7A AND Figure 7B FIGS. are diagrams exemplarily showing the cross-sectional structure of a package substrate generated according to an embodiment.

[0040] DESCRIPTION OF REFERENCE NUMERALS

[0041] 100: Glass substrate; 110: Cavity portion; 120: Substrate region; 200: Package substrate; 210: Cavity element; 22: Film layer; 220: Filling portion; 225: Specific angle; 300: Upper layer; 400: Lower layer DETAILED DESCRIPTION

[0042] The following detailed description is provided to assist in a comprehensive understanding of the methods, apparatuses, and / or systems described in this specification. However, after understanding the disclosure of this application, various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described in this specification will be apparent. For example, the order of operations described in this specification is merely an example and is not limited to the operations recited in this specification. Except for operations that must be performed in a specific order, based on an understanding of the disclosure of this application, the order of operations may be changed. In addition, after understanding the disclosure of this application, the description of known features may be omitted to increase clarity and conciseness. However, the omission of these features and descriptions is not intended to acknowledge them as common knowledge.

[0043] The features described in this specification may be embodied in different forms and should not be construed as limited to the examples described in this specification. Rather, the examples described in this specification are provided only to illustrate a part of the many possible ways of implementing the methods, apparatuses, and / or systems described in this specification, which will be apparent after understanding the disclosure of this application.

[0044] Although terms such as "first," "second," and "third" may be used in this specification to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are only used to distinguish one component, part, region, layer, or section from another component, part, region, layer, or section. Thus, without departing from the teachings of the examples, the first component, part, region, layer, or section referred to in the examples described in this specification may also be referred to as the second component, part, region, layer, or section.

[0045] Throughout the specification, when an element such as a layer, region, or substrate is described as "on another element," "connected to another element," or "coupled to another element," it may be directly "on another element," "connected to another element," or "coupled to another element," or there may be one or more other elements intervening therebetween. In contrast, when an element is described as "directly on another element," "directly connected to another element," or "directly coupled to another element," there can be no other elements intervening therebetween. Similarly, expressions such as "between," "immediately between," "adjacent to," and "next to" can be interpreted as described above.

[0046] The terms used in this specification are for the purpose of describing particular examples only and are not intended to limit the disclosure. As used in this specification, the singular forms are also intended to include the plural forms unless the context clearly dictates otherwise. As used in this specification, the term "and / or" includes any one of the related listed items and any combination of any two or more of them. As used in this specification, the terms "comprises," "comprising," and "having" specify the presence of the stated features, numbers, actions, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, actions, elements, components, and / or combinations thereof. The use of the term "may" in this specification with respect to an example or embodiment (e.g., what an example or embodiment may include or implement) means that there is at least one example or embodiment in which such a feature is included or implemented, rather than all examples being limited thereto.

[0047] In this application, "B is located on A" means that B is in direct contact with A or is configured on A in such a way that another layer or structure intervenes therebetween, and thus should not be construed as being limited to B being in direct contact with A.

[0048] Unless otherwise defined, all terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention pertains. Terms such as those defined in a commonly used dictionary should be construed as having a meaning consistent with their meaning in the context of the prior art and this invention, and should not be construed in an idealized or overly formal sense unless expressly defined in this specification.

[0049] In one or more examples, the description of "A and / or B" means "A, B, or both A and B".

[0050] In one or more examples, terms such as "first," "second," "A," or "B" are used to distinguish the same terms.

[0051] In one or more examples, unless otherwise stated, singular expressions are construed to include the singular or plural meanings as interpreted in the context.

[0052] Encapsulation substrate

[0053] Figure 1 is a conceptual diagram illustrating an example of a glass substrate of an encapsulation substrate according to an embodiment. Figure 2A is a conceptual diagram illustrating an A-A' cross-section of a glass substrate according to an embodiment. Figure 2B is a conceptual diagram illustrating an A-A' cross-section of a glass substrate according to another embodiment. Hereinafter, with reference to Figures 1 to 2B a detailed description of the glass substrate included in the encapsulation substrate will be given.

[0054] The glass substrate 100 according to one or more examples includes an element region 110 and a substrate region 120 that are distinguishable from each other. The element region 110 is a region in which a cavity portion is configured, and the substrate region 120 is a region in which no cavity portion is configured. The element region 110 and the substrate region 120 may be configured adjacent to each other. The glass substrate 100 may include one element region 110 or may include two or more element regions 110. The element region may also be referred to as a cavity structure.

[0055] The glass substrate 100 has a first surface and a second surface that face each other, and the two surfaces are substantially parallel to each other, so that the glass substrate 100 has a constant thickness as a whole.

[0056] As a package substrate of a semiconductor device, a form in which a silicon substrate and an organic substrate are laminated has been conventionally applied. In the case of a silicon substrate, when applied to a high-speed circuit, parasitic elements may be generated due to the characteristics of the semiconductor, and there is a disadvantage that the power loss is relatively large. Also, in the case of an organic substrate, in order to form a more complex distribution pattern, it is necessary to increase the area, but this does not conform to the trend of manufacturing ultra-small electronic devices. In order to form a complex distribution pattern within a predetermined size, it is substantially necessary to perform pattern miniaturization, but there are substantial limitations in performing pattern miniaturization due to the characteristics of materials such as polymers applied to organic substrates.

[0057] In an embodiment, as a method for solving such problems, the glass substrate 100 is used as a support of the package substrate. And, together with the glass substrate 100, a core through-hole formed through the glass substrate 100 is adopted, thereby providing a package substrate having a shorter electrical flow length, being more miniaturized, having a faster response, and having less loss characteristics.

[0058] The glass substrate 100 is preferably a glass substrate applied in semiconductors. For example, a borosilicate glass substrate, a non-alkali glass substrate, etc. may be applied, but the present invention is not limited thereto.

[0059] The core through-hole penetrates the glass substrate 100. The core through-hole may be formed by removing a preset region of the glass substrate 100. Specifically, it may be formed by etching plate-shaped glass using physical and / or chemical methods.

[0060] Specifically, when forming the core through-hole, a method of performing chemical etching after forming defects (flaws) on the surface of the glass substrate by means of laser or the like, laser etching, etc. may be adopted, but the present invention is not limited thereto.

[0061] Based on the unit area (1 cm × 1 cm) of the glass substrate 100, the core through-holes can be arranged in numbers ranging from 100 to 3000, from 100 to 2500, or from 225 to 1024. When such pitch conditions are met, the formation of conductive layers and the like and the performance of the packaging substrate can be improved.

[0062] The cavity portion 110 may include a cavity structure.

[0063] The cavity structure refers to a structure in which a recessed portion is included in a part of the glass substrate 100, and the recessed portion is configured to be able to dispose components inside the glass substrate 100. The space formed by the recessed portion is called the cavity space.

[0064] The cavity portion 110 may include: a cavity space into which at least a part of a cavity component is inserted; side walls surrounding the cavity space; and a contact surface that selectively serves as a bottom surface.

[0065] Referring to Figure 2A and Figure 2B , a cavity portion 110 can be formed in the glass substrate 100 having a first surface and a second surface facing each other.

[0066] For example, referring to Figure 2A , the cavity portion 110 can have a space for component arrangement by penetrating through the first surface and the second surface of the glass substrate 100. Figure 2A The cavity space of the cavity portion 110 shown can be a full-cavity type penetrating through the glass substrate 100.

[0067] For example, referring to Figure 2B , the cavity portion 110 can be formed in a shape of a recessed surface with only one of the first surface or the second surface being open. The cavity portion 110 can be formed in a shape of a recessed surface with only one of the first surface or the second surface being open, so as to have a space for component arrangement. Figure 2B The cavity space of the cavity portion 110 shown can be a semi-cavity type, in which the first surface or the second surface of the glass substrate 100 is recessed.

[0068] When components are arranged in the cavity, the contact surface of the cavity portion 110 can be in direct contact with the components or in contact through another layer. The contact surface is arranged facing the opening.

[0069] The side walls of the cavity portion 110 are the walls surrounding the contact surface. That is, it can be the wall surrounding the cavity space of the cavity portion 110. When the contact surface has a quadrilateral shape, the side walls can include four surfaces.

[0070] The side wall connects the first surface of the substrate region 120 and the contact surface.

[0071] When viewed from above the opening portion, the cavity portion 110 may be substantially circular, triangular, quadrilateral, hexagonal, octagonal, cruciform, etc., and its shape is not limited.

[0072] In addition, as described above, a cavity portion may be formed in the glass substrate, and cavity elements may be disposed in the cavity portion. In this case, in order to prevent short circuits and the like in the cavity elements, a gap may be disposed between the cavity elements and the side wall on the cavity portion. A filling portion may be disposed in the gap.

[0073] The cavity elements may include active elements such as transistors or passive elements such as power transfer elements of multilayer ceramic capacitors (MLCCs).

[0074] When an active element such as a transistor is applied as the cavity element, the transistor functions to convert an electrical signal between a motherboard and a semiconductor element portion to an appropriate level, and is implemented in a form in which a transistor or the like is applied at an intersection of a package substrate, thereby providing a more efficient and high-speed semiconductor device.

[0075] Moreover, power transfer elements such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor elements. As passive power transfer elements, at least 200 or more can be applied in semiconductor elements. They can be applied in a plate shape or the like according to their form, and the number of applied power transfer elements can be changed.

[0076] When transferring power, the performance of the element is also affected by the characteristics of the conductive layer around the element. In one embodiment, non-circular core vias can be applied at positions of conductive layers that require low resistance, such as such power transfer elements.

[0077] In addition, the cavity elements may be in a form in which the elements are inserted separately, or may also be in a form embedded between insulator layers (cavity element insulating layers) such that an element group including a plurality of elements is formed with electrodes exposed and then inserted into the cavity element. In the latter case, the operation efficiency of manufacturing the package substrate can be achieved more smoothly, and it is more beneficial to make the insulating layer be located in the space between complex elements in a sufficient and highly reliable manner.

[0078] Here, depending on the pattern and size of the gap formed, there may be a significant loss of the filling material used to configure the filling portion. In the embodiment, by substantially reducing the volume of the filling portion, the surface fluctuation of the filling material can be reduced, and the formation of the build-up layer can be facilitated.

[0079] That is, in this specification, embodiments are proposed to reduce the volume of the gap in the cavity portion or to reduce the surface fluctuation. Accordingly, the usable area of the glass substrate can be increased, and the effect of reducing the loss of the filling material and facilitating the additional formation of the build-up layer can be achieved.

[0080] Figure 3 FIG. is an exemplary diagram showing the structure of a package substrate according to an embodiment. Figure 4A FIG. is a conceptual diagram for explaining a cross-section of a package substrate according to an embodiment. Figure 4B FIG. is a conceptual diagram for explaining a cross-section of a glass substrate according to another embodiment. And, Figure 5A FIG. is a conceptual diagram for explaining a cross-section of a package substrate according to another embodiment. Figure 5B FIG. is a conceptual diagram for explaining a cross-section of a glass substrate according to another embodiment.

[0081] Referring to Figure 3 , the package substrate 200 may include a glass substrate 100 having a first surface and a second surface. A cavity portion may be formed in the glass substrate 100 having the first surface and the second surface. A cavity element 210 may be disposed in the cavity portion, and a filling portion 220 may be disposed in the gap between the cavity element 210 and the sidewall of the cavity portion.

[0082] And, the package substrate 200 may selectively further include a film layer 22 located under the glass substrate 100. The film layer 22 may be bonded during the manufacturing process and removed after being used in processes such as element arrangement and filling in the cavity portion. As an example, a bonding film such as a PI tape may be applied to the film layer.

[0083] In the embodiment, after arranging the cavity elements 210 in the cavity portion, the filling portion 220 may be formed. For example, a method such as pressure lamination of the film-shaped filling portion 220 may be employed. When pressure lamination is performed in this way, the filling portion 220 sufficiently sinks into the vacant space inside the cavity portion, so that a void-free filling portion 220 can be formed. The filling portion 220 may be filled with a filling material.

[0084] One or more than two of the above-mentioned filling materials can be applied together.

[0085] Two or more than two of the above-mentioned filling materials can be applied in a way of separating spaces.

[0086] The above-mentioned filling materials can be filled in more than two times. According to the filling time point, boundary lines can be arranged on the filling materials. The boundary lines can be presented as clear boundary lines according to the differences of the materials with each other, or can be presented in a gradient form by the partial mixing of the first material and the second material near the boundary line.

[0087] An insulating material can be applied as the above-mentioned filling material.

[0088] An insulating material and a metal material can be applied together as the above-mentioned filling material.

[0089] As the above-mentioned insulating material, a polymer resin, a mixed material of a polymer resin and a filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.), an inorganic deposition layer, etc. can be applied.

[0090] Exemplarily, an acrylic resin, an epoxy resin, a modified resin thereof, etc. can be applied as the above-mentioned polymer resin, and a material applicable to an electronic device for the purpose of molding, etc. can be adopted. Exemplarily, a liquid crystal polymer (LCP), etc. can be applied.

[0091] Exemplarily, the above-mentioned mixed material can be a mixture of an acrylic resin and a filler, a mixture of an acrylic resin and an epoxy resin and a filler, a mixture of an epoxy resin and a filler, etc. As the above-mentioned filler, inorganic particles can be applied, and exemplarily, silica particles can be applied. As commercially available products, Ajinomoto Build-up Film (ABF), Epoxy Molding Compound (EMC), Modified Polyimide (MPI), etc. can be applied, but the present invention is not limited thereto.

[0092] The above-mentioned metal material can function as a conductive layer, a heat dissipation layer, etc.

[0093] Copper or an alloy of copper and titanium, chromium, nickel, etc. can be applied as the above-mentioned metal material. Or, aluminum or an alloy containing the same, etc. can be applied as the above-mentioned metal material.

[0094] In the case where the above-mentioned filling materials are filled in more than two times, boundary lines can be arranged in the form of shallow dimples or inclined surfaces at the filling part.

[0095] Refer toFigure 4A The cavity space formed in the cavity portion of the glass substrate 100 can be a full-cavity type that penetrates the glass substrate 100. The cavity portion can include a gap 280 disposed between the cavity element 210 and the side wall of the cavity portion, and a filling portion 220 can be disposed in the gap 280. For example, the width of the gap 280 can be 50 μm or less, 45 μm or less, 40 μm or less, 35 μm or less, 30 μm or less, or 25 μm or less. The width of the gap 280 can be 15 μm or more, or 20 μm or more. When the widths at the upper and lower measurement positions of each gap of the gap 280 are different from each other, the width at the widest position is regarded as the width of the gap. The encapsulation substrate 200 as other characteristics can include a film layer 22 and the like located under the second surface of the glass substrate 100, and the above-described characteristics can all be applied to the embodiments.

[0096] Refer to Figure 4B The cavity space formed in the cavity portion of the glass substrate 100 can be a semi-cavity type that is recessed from the first surface or the second surface of the glass substrate 100. The cavity portion can include: a cavity space for inserting at least a part of the cavity element 210; a side wall and a contact surface that surround the cavity space. And, the cavity portion can include a gap 280 disposed between the cavity element 210 and the side wall of the cavity portion, and a filling portion 220 can be disposed in the gap 280. For example, the width of the gap 280 can be 50 μm or less, 45 μm or less, 40 μm or less, 35 μm or less, 30 μm or less, or 25 μm or less. The width of the gap 280 can be 15 μm or more, or 20 μm or more. When the widths measured up and down for each gap of the gap 280 are different from each other, the width at the widest position is regarded as the width of the gap. The encapsulation substrate 200 as other characteristics can include a film layer 22 and the like located under the second surface of the glass substrate 100, and the above-described characteristics can all be applied to the embodiments.

[0097] This specification presents an embodiment in which a gap is formed in a tapered structure to reduce the volume of the gap in the cavity portion. For example, the cavity portion can include a gap disposed between the cavity element and the side wall, and the side wall can be inclined at a specific angle with respect to the first surface or the second surface of the glass substrate. Accordingly, the usable area of the glass substrate can be increased, the loss of the filling material can be reduced, and the surface fluctuation of the filling material can be reduced, thereby being able to produce an effect beneficial to the additional formation of a build-up layer.

[0098] Refer to Figure 5A, the cavity space formed in the cavity portion of the glass substrate 100 can be a full-cavity type that penetrates the glass substrate 100. The cavity portion can include a gap 280 disposed between the cavity element 210 and the sidewall of the cavity portion, and a filling portion 220 can be disposed in the gap 280. The sidewall can be inclined at a specific angle 225 with respect to the second surface of the glass substrate. For example, the angle 225 between the sidewall and the second surface can be 65 degrees or more, 70 degrees or more, 75 degrees or more, 80 degrees or more, 82 degrees or more, or 83 degrees or more. The angle 225 can be 86 degrees or less, or 85 degrees or less.

[0099] The cavity portion can have the following characteristics: having an open surface at the opening of the cavity space and a bottom surface of the recessed portion of the cavity space or a bottom surface facing the open surface, and the area of the open surface is larger than the area of the bottom surface.

[0100] As other characteristics, the width of the gap 280, etc., can include a film layer 22 located below the second surface of the glass substrate 100, etc., and the above-mentioned characteristics can all be applied to the embodiments.

[0101] Refer to Figure 5B , the cavity space formed in the cavity portion of the glass substrate 100 can be a semi-cavity type that is recessed in the first surface or the second surface of the glass substrate 100. The cavity portion can include: a cavity space for inserting at least a part of the cavity element 210; a sidewall and a contact surface that surround the cavity space. The cavity portion can include a gap 280 disposed between the cavity element 210 and the sidewall of the cavity portion, and a filling portion 220 can be disposed in the gap 280. The sidewall can be inclined at a specific angle with respect to the second surface of the glass substrate. For example, the angle 225 between the sidewall and the second surface can be 65 degrees or more, 70 degrees or more, 75 degrees or more, 80 degrees or more, 82 degrees or more, or 83 degrees or more. The angle 225 can be 86 degrees or less, or 85 degrees or less. As other characteristics, the width of the gap 280, etc., can all be applied to the embodiments.

[0102] A plurality of cavity elements can be disposed on the glass substrate. In this specification, an embodiment of forming a gap in a cavity portion in which a plurality of cavity elements are disposed is proposed.

[0103] Figure 6A is a conceptual diagram for explaining a cross-section of a packaging substrate according to another embodiment, Figure 6B is a conceptual diagram for explaining a cross-section of a glass substrate according to another embodiment.

[0104] Refer to Figure 6A, the cavity space formed in the cavity portion of the glass substrate 100 can be a full-cavity type that penetrates the glass substrate 100. A plurality of cavity elements 210 can be arranged in the cavity portion.

[0105] For example, the glass substrate 100 can include a first cavity portion and a second cavity portion. A first cavity element can be arranged in the first cavity portion, and a second cavity element can be arranged in the second cavity portion. The first cavity portion can include a gap 280 disposed between the first cavity element and the side wall of the first cavity portion. The second cavity portion can include a gap 280 disposed between the second cavity element and the side wall of the second cavity portion. Moreover, a gap 280 can be arranged between the first cavity portion and the second cavity portion. Refer to Figure 6A , when observed from a cross-section, gaps can be arranged on both sides of the first cavity element and both sides of the second cavity element. For example, when observed from a cross-section, the sum of the gaps arranged on both sides of the first cavity element and the gaps arranged on both sides of the second cavity element can be 200 μm or less. The sum of the gaps can be 200 μm or less, 190 μm or less, 180 μm or less, 170 μm or less, 160 μm or less, 150 μm or less, 140 μm or less, 130 μm or less, 120 μm or less, 110 μm or less, 100 μm or less, or 98 μm or less. The sum of the gaps can be 60 μm or more, 70 μm or more, or 80 μm or more. A filling portion 220 can be arranged in the gap 280.

[0106] The angle 225 between the side wall and the second surface as other characteristics can include a film layer 22 located below the second surface of the glass substrate 100, etc., and the above-mentioned characteristics can all be applied to the embodiments.

[0107] Or, for example, although not shown in Figure 6A , a first cavity element and a second cavity element can be arranged together in one cavity portion. When observed from a cross-section, the cavity portion can include the gap between the first cavity element and the second cavity element, and two gaps respectively arranged between the cavity element and the side wall. In this case, the sum of the gaps can be 150 μm or less, 140 μm or less, 130 μm or less, 120 μm or less, 100 μm or less, 90 μm or less, or 80 μm or less. The sum of the gaps can be 50 μm or more, 60 μm or more, or 70 μm or more. A filling portion 220 can be arranged in the gap 280.

[0108] The angle 225 between the side wall and the second surface as other features may include a film layer 22 located below the second surface of the glass substrate 100, etc., and the above-mentioned features can all be applied to the embodiments.

[0109] Referring to Figure 6B , the cavity space formed in the cavity portion of the glass substrate 100 can be a semi-cavity type recessed in the first surface or the second surface of the glass substrate 100. The cavity portion may include: a cavity space for inserting at least a part of the cavity element 210; a side wall and a contact surface surrounding the cavity space.

[0110] For example, the glass substrate 100 may include a cavity portion, in which a first cavity element and a second cavity element may be arranged. The cavity portion may include a gap 280 disposed between the first cavity element and the side wall of the cavity portion and a gap 280 disposed between the second cavity element and the side wall of the cavity portion. And, a gap 280 may be disposed between the first cavity element and the second cavity element. Referring to Figure 6B , when observed from a cross-section, gaps may be disposed on both sides of the first cavity element and both sides of the second cavity element. For example, when observed from a cross-section, the sum of the gaps disposed on both sides of the first cavity element and the gaps disposed on both sides of the second cavity element may be 150 μm or less. That is, the sum of the gaps may be 150 μm or less, 140 μm or less, 130 μm or less, 120 μm or less, 100 μm or less, 90 μm or less, or 80 μm or less. The sum of the gaps may be 50 μm or more, 60 μm or more, or 70 μm or more. A filling portion 220 may be disposed in the gap 280. A filling portion 220 may be disposed in the gap 280.

[0111] Although not shown in Figure 6BAs shown in the figure, the glass substrate 100 may include a first cavity portion and a second cavity portion. A first cavity element may be disposed in the first cavity portion, and a second cavity element may be disposed in the second cavity portion. The first cavity portion may include a gap 280 disposed between the first cavity element and the side walls on both sides of the first cavity portion. The second cavity portion may include a gap 280 disposed between the second cavity element and the side walls on both sides of the second cavity portion. A gap 280 may be disposed between the first cavity portion and the second cavity portion. The sum of the gaps may be 200 μm or less, 190 μm or less, 180 μm or less, 170 μm or less, 160 μm or less, 150 μm or less, 140 μm or less, 130 μm or less, 120 μm or less, 110 μm or less, 100 μm or less, or 98 μm or less. The sum of the gaps may be 60 μm or more, 70 μm or more, or 80 μm or more. A filling portion 220 may be disposed in the gap 280.

[0112] As another characteristic, the angle 225 between the side wall and the second surface, and a film layer 22 or the like located below the second surface of the glass substrate 100 may be included, and the above-described characteristics may all be applied to the embodiments.

[0113] Moreover, a packaging substrate 200 according to an embodiment includes: a glass substrate 100, an upper layer 300 located on one surface of the glass substrate 100, and a cavity portion 110 in which a cavity element can be arranged.

[0114] The packaging substrate 200 may further include: a lower layer 400 located below the other surface of the glass substrate 100.

[0115] Figures 7A to 7B This is an example of a cross-sectional structure of a packaging substrate generated according to an embodiment. In the drawings, the upper layer and the lower layer are shown schematically, omitting the display of the conductive layer inside and the structure of the insulating layer and the like.

[0116] Referring to Figure 7A , the packaging substrate 200 may include a cavity element and a glass substrate having a cavity portion including a gap. An upper layer 300 may be disposed on one surface of the glass substrate 100, and a lower layer 400 may be disposed below the other surface of the glass substrate 100. Moreover, referring to Figure 7B , the packaging substrate 200 may include a cavity element, a glass substrate having a cavity portion including a gap, and a film layer. An upper layer 300 may be disposed on one surface of the glass substrate 100, and a lower layer 400 may be disposed below the other surface of the glass substrate 100.

[0117] The upper layer 300 includes an upper distribution layer and an upper surface connection layer located above the upper distribution layer, and the uppermost surface of the upper layer 300 may be protected by a cover layer formed with an opening portion where the contact electrodes of the semiconductor element portion can directly abut.

[0118] The upper distribution layer includes: an upper insulating layer located above the first surface; an upper distribution pattern having a preset pattern, which is built in the upper insulating layer and is a conductive layer that is at least partially electrically connected to the core distribution layer.

[0119] Any material can be applied to the upper insulating layer as long as it is an insulator layer applicable to semiconductor elements or packaging substrates. For example, an epoxy resin containing fillers can be applied, but the present invention is not limited thereto.

[0120] The insulator layer can be formed by forming a coating and hardening it, or by laminating an insulator film in an unhardened or semi-hardened state on the glass substrate 100 and hardening it. At this time, if a reduced-pressure lamination method or the like is adopted, the insulator can be recessed into the space inside the core through hole, thereby enabling an efficient process.

[0121] Semiconductor device

[0122] To achieve the above object, according to an embodiment, a semiconductor device includes: a semiconductor element portion in which one or more semiconductor elements are located; a packaging substrate electrically connected to the semiconductor elements; and a mother board electrically connected to the packaging substrate, transmitting external electrical signals to the semiconductor elements and connecting them to each other.

[0123] The semiconductor element portion refers to an element installed in a semiconductor device, which is installed on the packaging substrate by using contact electrodes or the like. Specifically, as the semiconductor element portion, for example, computing elements such as CPUs and GPUs, memory elements such as memory chips, etc. can be applied, but as long as they are semiconductor elements installed in a semiconductor device, they can all be applied without limitation.

[0124] As the mother board, a printed circuit board, a printed wiring board, or the like can be applied.

[0125] According to an embodiment, even if multiple layers of insulator layers are stacked and applied, it may be difficult to substantially distinguish between the insulator layers, and the multiple insulator layers are collectively referred to as the upper insulating layer. And the core insulating layer and the upper insulating layer can use the same insulating material, and in such a case, their boundaries may not be substantially distinguished. Or, according to different embodiments, the boundaries of the insulator layers can also be generated by differently setting the pressure and temperature for hardening the multiple layers of insulator layers.

[0126] The upper distribution pattern refers to a conductive layer located within the upper insulating layer in a preset form, for example, it can be formed in a stacked layer manner. Specifically, an insulator layer can be formed, and after removing unnecessary portions of the insulator layer, a conductive layer can be formed by copper plating or the like. After selectively removing unnecessary portions of the conductive layer, an insulator layer is formed again on the conductive layer. After removing unnecessary portions again, a conductive layer is formed by plating or the like. By repeating such a process, an upper distribution pattern with a conductive layer formed in a desired pattern in the vertical or horizontal direction is formed.

[0127] Since the upper distribution pattern is located between the glass substrate 100 and the semiconductor element portion, the upper distribution pattern is formed to include a fine pattern in at least a part thereof, so as to smoothly transmit electrical signals with the semiconductor element portion and be able to sufficiently accommodate a desired complex pattern. At this time, the fine pattern means that its width and pitch can be less than 4 μm, can be 3.5 μm or less, can be 3 μm or less, can be 2.5 μm or less, can be 1 to 2.3 μm (hereinafter, the description of the fine pattern is the same).

[0128] The upper surface connection layer includes: an upper surface connection pattern, at least a part of which is electrically connected to the upper distribution pattern and is located on the upper insulating layer; an upper surface contact electrode that electrically connects the semiconductor element portion and the upper surface connection pattern. The upper surface connection pattern can be located on one surface of the upper insulating layer, or can be configured such that at least a part of it is exposed and embedded in the upper insulating layer. For example, in the case where the upper surface connection pattern is located on one surface of the upper insulating layer, the upper insulating layer can be formed by plating or the like. In the case where a part of the upper surface connection pattern is exposed and embedded in the upper insulating layer, after forming a copper plating layer or the like, a part of the insulating layer or the conductive layer can be removed by methods such as surface polishing and surface etching.

[0129] Similar to the upper distribution pattern described above, the upper surface connection pattern can include a fine pattern in at least a part thereof. Such an upper surface connection pattern including a fine pattern can electrically connect a larger number of components even in a narrow area, thereby more smoothly realizing electrical signal connection between components or with the outside, and can achieve a more integrated package.

[0130] The upper surface contact electrode can be directly connected to the semiconductor element portion using a terminal or the like, or can be connected through an element connection portion such as a solder ball as a medium.

[0131] The encapsulation substrate 200 is also connected to the mother board. The mother board can be directly connected to the core distribution pattern located on at least a part of the second surface of the glass substrate 100 by using the terminals of the mother board, or can be electrically connected through a board connection part such as a solder ball. Moreover, the core distribution pattern in contact with the mother board can also be connected to the mother board through the lower layer 400 located below the glass substrate 100.

[0132] According to an example, in the encapsulation substrate 200 located between the semiconductor element part and the mother board, except for the glass substrate, substantially no additional other substrates are adopted.

[0133] Manufacturing method of substrate for encapsulation

[0134] To achieve the above object, a manufacturing method of an encapsulation substrate according to an embodiment is proposed in this specification. For example, the manufacturing method of the encapsulation substrate according to the embodiment of this specification includes: the step of preparing a glass substrate provided with a cavity part and a cavity element; and the step of disposing and filling the cavity element in the cavity part.

[0135] The glass plate having a first surface and a second surface opposite to each other and having a cavity part formed thereon is applied as the glass substrate. A glass substrate in which through holes are also formed together with the cavity part can be applied. Since the specific description of the shape, characteristics, etc. of the cavity part is repeated with the above content, the detailed description will be omitted here.

[0136] The cavity part of the glass substrate can be formed by a defect formation process and an etching process. Defects can be formed at the positions of the glass plate where the cavity part and / or the through hole are to be formed by using a laser or the like, and it is immersed in an etching solution, so as to obtain a glass substrate having a cavity part and / or a through hole by using the difference in etching speed.

[0137] Next, the cavity element can be disposed in the cavity part. The cavity element can include an active element such as a transistor or a passive element such as a multilayer ceramic capacitor (MLCC) for power transfer.

[0138] If the cavity element is disposed in the cavity part, a gap will be formed between the cavity element and the side wall of the cavity part as described above. Since the specific description of this is repeated with the above content, the detailed description will be omitted here.

[0139] In the case where the cavity part is a full cavity, before disposing the cavity element, a support layer such as a film layer can be disposed under the second surface of the glass substrate, and the film layer can be a film having adhesiveness. In this case, it can be more beneficial to align the position of the cavity element in the cavity part which is a full cavity.

[0140] As the filling material filled in the gap, the above-described filling material can be applied. As the filling material, a material that can be hardened by methods such as ultraviolet curing or thermal curing can be exemplarily applied. Therefore, when forming the filling portion, a method of disposing the filling material in the gap by a method such as vacuum lamination and hardening the filling material by methods such as ultraviolet curing or thermal curing can be applied.

[0141] The formation of the filling portion can be performed by one or more than two filling processes.

[0142] Exemplarily, a filling material (first filling material) is used to form a first filling portion before hardening in the filling portion by first vacuum lamination or the like, and it is hardened or semi-hardened. Subsequently, the filling material (second filling material) can be used again to form a second filling portion before hardening by second vacuum lamination or the like, and it is hardened or semi-hardened again. In this case, when observed from the cross section, a boundary line can be disposed between the first filling portion and the second filling portion. Or, when the formation of the filling portion is divided into the first and second times in this way, its boundary can be observed on the filling portion. Or, forming the filling portion in more than two times can reduce the stress generated in the glass substrate, which can help to suppress the generation of warpage. Or, through filling more than two times, it is possible to substantially suppress the formation of shallow dimples and the formation of inclined surfaces on the surface of the filling portion.

[0143] In addition, an upper layer can be disposed on one surface of the encapsulation substrate, and a lower layer can be disposed under the other surface of the encapsulation substrate. As long as the formation of the upper layer and / or the lower layer is a method of forming redistribution lines, they can all be applied.

[0144] Exemplarily, the upper layer manufacturing step can be as follows.

[0145] The upper layer manufacturing step is a step of forming an upper insulating layer and an upper distribution layer including an upper distribution pattern on a core layer. The upper insulating layer can be formed by coating a resin composition for forming an insulating layer or laminating an insulating film, and it is preferably to simply apply the method of laminating an insulating film. The lamination of the insulating film can be formed by a process of laminating and hardening the insulating film. At this time, the insulating resin can be sufficiently inserted into the layer without a conductive layer inside the core through hole by adopting a vacuum lamination method. The upper insulating layer also directly abuts against the glass substrate at at least a part thereof, so an insulating layer with sufficient adhesion is applied. Specifically, it is preferable that the glass substrate and the upper insulating layer have a adhesion test value corresponding to ASTM D3359 that satisfies 4B or more.

[0146] The upper distribution pattern can be formed by repeatedly performing the following process, that is, after forming the insulating layer and forming the conductive layer in a preset pattern, etching unnecessary portions to form an etched layer of the conductive layer. When the conductive layers are formed adjacent to each other with an insulating layer in between, it can be formed by performing a plating process after forming blind vias in the insulating layer. When forming the blind vias, dry etching methods such as laser etching and plasma etching, wet etching methods using a mask layer and an etching solution, etc. can be employed.

[0147] Subsequently, although not shown, an upper surface connection layer and a cover layer can be formed.

[0148] The upper surface connection pattern and the upper surface contact electrode can also be formed by a process similar to the process of forming the upper distribution layer. Specifically, it can be formed by forming an etched layer of the insulating layer in the insulating layer and then forming a conductive layer again therein and then forming an etched layer of the conductive layer, etc., but it is also possible to apply a method of selectively forming only the conductive layer without using an etching method. The cover layer can be formed such that an opening is formed at a position corresponding to the upper surface contact electrode to expose the upper surface contact electrode and enable it to be directly connected to an element connection portion or a terminal of an element, etc.

[0149] If the upper layer is generated, a lower surface connection layer and a cover layer can be formed to perform the process of forming the lower layer. The lower distribution layer and / or the lower surface connection layer can be formed in a manner similar to the steps of forming the upper surface connection layer and the cover layer described above, and the cover layer can be selectively formed.

[0150] According to the method for manufacturing a packaging substrate according to the above-described embodiment and the packaging substrate using the same, by reducing the volume of the gap between the side wall of the cavity portion and the cavity element, the usage area of the glass substrate can be increased, the loss of the filling material can be reduced, and the surface fluctuation of the filling material can be reduced, thereby being able to produce an effect beneficial to the additional formation of a build-up layer.

[0151] As described above, this specification has been described with reference to the embodiments illustrated in the drawings, but this is only an example. Those skilled in the art should understand that various changes and modifications of the embodiments can be made therefrom. In other words, the scope of this specification is not limited to the above-described embodiments, but various changes or modifications by those skilled in the art using the basic concepts of the present embodiments defined in the appended claims all fall within the scope of the present embodiments. Therefore, the true technical protection scope of this specification should be determined according to the technical idea of the appended claims.

Claims

1. A packaging substrate, in, include: The glass substrate has a first surface and a second surface opposite to each other, a cavity portion formed in the glass substrate, and a cavity element, disposed in the cavity portion; The cavity portion comprises: a cavity space for inserting at least a portion of the cavity element, and A side wall surrounding the cavity space; A gap is arranged between one side of the cavity element and the side wall, The gap is filled with one or more filling materials. The length of the gap is 50 μm or less.

2. The packaging substrate according to claim 1, wherein: The side wall is formed obliquely, The angle between the side wall and the second surface is greater than 65 degrees, The length of the gap is the largest value among the distances between the side wall and one side surface of the cavity element.

3. The packaging substrate according to claim 1, wherein: The cavity portion is a full cavity type, wherein the cavity space penetrates the glass substrate, The cavity portion has an open surface located at the opening of the cavity space and a bottom surface facing the open surface. The area of ​​the open surface is larger than the area of ​​the bottom surface.

4. The packaging substrate according to claim 1, wherein: The cavity portion is a semi-cavity type, wherein the cavity space is in the form of a depression in the first surface or the second surface of the glass substrate. The cavity portion has an open surface located at the opening of the cavity space and a bottom surface of a recessed portion of the cavity space, The area of ​​the open surface is larger than the area of ​​the bottom surface of the recessed portion.

5. The packaging substrate according to claim 1, wherein: The glass substrate includes a first cavity portion and a second cavity portion, A first cavity element is disposed in the first cavity portion. A second cavity element is disposed in the second cavity portion. When viewed in cross section, the sum of gaps disposed on both sides of the first cavity element and gaps disposed on both sides of the second cavity element is 200 μm or less.

6. The packaging substrate according to claim 1, wherein: A first cavity element and a second cavity element are arranged in the cavity portion, When viewed in cross section, the sum of gaps disposed on both sides of the first cavity element and gaps disposed on both sides of the second cavity element is 150 μm or less.

7. A method for manufacturing a packaging substrate, in, include: a step of preparing a glass substrate having a cavity portion and a cavity element, and The step of disposing a cavity element in the cavity portion and filling the cavity portion; The glass substrate has a first surface and a second surface opposite to each other, The cavity portion comprises: a cavity space for inserting at least a portion of the cavity element, and A side wall surrounding the cavity space; A gap is arranged between one side of the cavity element and the side wall, In the filling step, the gap is filled with a filling material to form a filling portion. The length of the gap is 50 μm or less.

8. The method for manufacturing a packaging substrate according to claim 7, wherein: The cavity portion is a full cavity type, wherein the cavity space penetrates the glass substrate, The step of configuring the cavity element is performed in a state where the support layer is attached to the second surface. The support layer is removed after the filling step.

9. The method for manufacturing a packaging substrate according to claim 7, wherein: The side wall is formed obliquely, Compared with the case where the side wall is perpendicular to the second surface, the required amount of the filling material is reduced by more than 30%.

Images