Semiconductor memory device

Abstract

A semiconductor memory device includes: a first structure on a substrate and including a core region and a first peripheral circuit region; and a second structure on the first structure and including a cell array region and a second peripheral circuit region. The second structure includes: a first active pattern in each of the cell array regions and perpendicular to an upper surface of the first structure; a word line adjacent to one side of the first active pattern and extending in a first direction parallel to the upper surface of the first structure; a bit line in contact with a lower surface of the first active pattern and extending in a second direction intersecting the first direction; a second active pattern in the second peripheral circuit region and perpendicular to the upper surface of the first structure; and an anti-fuse gate electrode on one side of the second active pattern.

Description

Technical Field

[0001] The inventive concept generally relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a vertical channel transistor and a method of manufacturing the same. Background Art

[0002] When a defective unit among a plurality of unit cells of a semiconductor memory device is detected during the manufacturing process of the semiconductor memory device, the semiconductor memory device is generally discarded as a defective product. However, even if defects occur only in some of the unit cells of the semiconductor memory device, discarding the semiconductor memory device as a defective product is inefficient. The semiconductor memory device can be recovered by replacing the defective unit with a prepared redundant unit, which makes it possible to improve the yield. Summary of the Invention

[0003] An object of the inventive concept is to provide a semiconductor memory device in which electrical characteristics and integration are improved.

[0004] Problems to be solved by the inventive concept are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0005] A semiconductor memory device according to some embodiments of the inventive concept includes: a substrate; a first structure located on the substrate and including a core region and a first peripheral circuit region; and a second structure located on the first structure and including a cell array region and a second peripheral circuit region located between the cell array regions, wherein the second structure includes: a first active pattern located in each of the cell array regions and perpendicular to an upper surface of the first structure; a word line adjacent to one side of the first active pattern and extending in a first direction parallel to the upper surface of the first structure; a bit line in contact with a lower surface of the first active pattern and extending in a second direction intersecting the first direction; a second active pattern located in the second peripheral circuit region and perpendicular to the upper surface of the first structure; and an antifuse gate electrode located on one side of the second active pattern.

[0006] A semiconductor memory device according to some embodiments of the inventive concept includes: a substrate; and a first structure located on the substrate and including a cell array region and a first peripheral circuit region located between the cell array regions, wherein the first structure includes: a first word line, a first active pattern, a back gate line, a second active pattern, and a second word line, the first word line, the first active pattern, the back gate line, the second active pattern, and the second word line are arranged side by side (i.e., adjacent to each other in sequence) in a first direction parallel to the upper surface of the substrate in the cell array region; and an anti-fuse gate electrode, a third active pattern, and a first peripheral back gate electrode, the anti-fuse gate electrode, the third active pattern, and the first peripheral back gate electrode are arranged side by side in the first direction in the first peripheral circuit region, and the first active pattern, the second active pattern, and the third active pattern extend longitudinally in a third direction perpendicular to the upper surface of the substrate and in a second direction intersecting the first direction and parallel to the upper surface of the substrate.

[0007] A semiconductor memory device according to some embodiments of the inventive concept includes: a substrate; a first structure located on the substrate and including a core region and a first peripheral circuit region; and a second structure located on the first structure and including a cell array region and a second peripheral circuit region located between the cell array regions, wherein the cell array regions overlap at least partially perpendicularly with the core region, wherein the second peripheral circuit region overlaps at least partially perpendicularly with the first peripheral circuit region, the second structure includes: bit lines extending in a first direction in the cell array region; a first word line, a first gate insulating layer, a first active pattern, a back gate line, a second active pattern, and a second word line, which are arranged side by side in the first direction on the bit lines; conductive lines located in the second peripheral circuit region; an antifuse gate electrode, a second gate insulating layer, a third active pattern, and a first peripheral back gate electrode, which are arranged side by side on the conductive lines, the first active pattern, the second active pattern, and the third active pattern extend perpendicularly to the upper surface of the substrate in a third direction and longitudinally in a second direction intersecting with the first direction and parallel to the upper surface of the substrate, the first word line, the back gate line, and the second word line extend in the second direction intersecting with the first direction and parallel to the upper surface of the substrate, the first gate insulating layer has a first thickness, and the second gate insulating layer has a second thickness equal to or less than the first thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, in which like reference numerals (when used) indicate corresponding elements throughout the several views. The drawings represent non-limiting example embodiments as described herein.

[0009] Figure 1A is a block diagram of at least a part of an example semiconductor memory device including a semiconductor device according to an embodiment of the inventive concept.

[0010] Figure 1B is a schematic perspective view of at least a part of an example semiconductor memory device according to an embodiment of the inventive concept.

[0011] Figure 2 is a schematic perspective view of a semiconductor memory device according to an embodiment of the inventive concept.

[0012] Figure 3A schematic cross-sectional view taken along line A-A' of a semiconductor memory device depicted in Figure 2 in accordance with an embodiment of the inventive concept.

[0013] Figure 4 A schematic top view of a cell array region in accordance with an embodiment of the inventive concept is shown.

[0014] Figure 5A A schematic enlarged cross-sectional view of region “P1” of a semiconductor memory device depicted in Figure 3 in accordance with an embodiment of the inventive concept.

[0015] Figure 5B A detailed enlarged cross-sectional view of region “P1” of a semiconductor memory device depicted in Figure 3 in accordance with an embodiment of the inventive concept.

[0016] Figure 6 An enlarged view of region “P2” of a semiconductor memory device depicted in Figure 3 in accordance with an embodiment of the inventive concept.

[0017] Figure 7A A schematic diagram of an exemplary antifuse circuit in accordance with an embodiment of the inventive concept is shown.

[0018] Figure 7B A schematic diagram illustrating Figure 6 the programming operation of an antifuse transistor.

[0019] Figure 8 An enlarged view of region “P2” of a semiconductor memory device depicted in Figure 3 in accordance with an embodiment of the inventive concept.

[0020] Figure 9A An enlarged view of region “P2” of a semiconductor memory device depicted in Figure 3 in accordance with an embodiment of the inventive concept.

[0021] Figure 9B A schematic diagram illustrating Figure 9A the programming operation of an antifuse transistor.

[0022] Figure 10 A schematic cross-sectional view of a part of a semiconductor memory device in accordance with an embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0023] Hereinafter, with reference to the accompanying drawings, a semiconductor memory device and a method of manufacturing the same according to embodiments of the inventive concept will be described in detail. In this specification, ordinal terms such as first, second, etc. may be used herein to distinguish components performing the same / similar functions from each other, and their numbers may be changed according to the order in which they are mentioned. However, it should be understood that such ordinal terms do not aim to convey any specific order of the elements unless specifically stated.

[0024] Figure 1A is a block diagram of at least a part of an exemplary semiconductor memory device including a semiconductor device according to an embodiment of the inventive concept.

[0025] Referring to Figure 1A , according to this example, the semiconductor memory device may include a cell array region 10. Word lines WL and bit lines BL intersecting each other may be arranged in the cell array region 10. A plurality of memory cells MC may be arranged two-dimensionally or three-dimensionally in the cell array region 10. Each memory cell MC may be connected between the intersecting word line WL and bit line BL.

[0026] A core region 20 may be provided around the cell array region 10. A sub-word line driver 22 and a sense amplifier 24 may be provided in the core region 20. A peripheral circuit region 30 may be provided around the core region 20. A row decoder 32, a column decoder 34, and a control logic 36 may be provided in the peripheral circuit region 30.

[0027] The row decoder 32 may decode an externally input row address signal or a refresh address signal. The sub-word line driver 22 may perform a function of selecting a specific word line WL in response to the row address signal or the refresh address signal.

[0028] The sense amplifier 24 may detect and amplify a voltage difference between the selected bit line BL and a reference bit line according to an address decoded by the column decoder 34, and output the amplified voltage difference.

[0029] The column decoder 34 may provide a data transfer path between the sense amplifier 24 and an external device (e.g., a memory controller, not explicitly shown). The column decoder 34 may decode an externally input column address signal to select one of the bit lines BL.

[0030] The control logic 36 may generate control signals for controlling operations of writing data into or reading data from the memory cells of the cell array region 10.

[0031] Figure 1B is a schematic perspective view of at least a part of an exemplary semiconductor memory device according to an embodiment of the inventive concept.

[0032] Referring toFigure 1B , the semiconductor memory device may include a substrate 100, a first structure PS, and a second structure CS sequentially stacked in a direction (D3) perpendicular to the upper surface of the substrate 100. Different from Figure 1B , the second structure CS may be disposed between the substrate 100 and the first structure PS. The first structure PS may also be referred to as a peripheral circuit structure. The second structure CS may also be referred to as a cell structure.

[0033] The first structure PS may include Figure 1A a core region 20 and a peripheral circuit region 30. The core region 20 may include a sub-word line driver circuit SWD and a sense amplifier circuit S / A. The peripheral circuit region 30 may include a peripheral circuit PERI.

[0034] The second structure CS may include Figure 1A a cell array region 10. The second structure CS may include bit lines BL, word lines WL, and memory cells MC located between the bit lines BL and the word lines WL. The memory cells MC may be arranged two-dimensionally or three-dimensionally on a plane extending in a first direction D1 and a second direction D2 that are parallel (i.e., horizontal) to the upper surface of the substrate 100 and intersect each other. Each memory cell MC may include a selection element TR and a data storage element DS.

[0035] The selection element TR may be a field effect transistor (FET). The gate electrode of the transistor may be connected to a corresponding one of the word lines WL, and the drain / source terminals of the transistor may be connected to a corresponding one of the bit lines BL and a corresponding one of the data storage elements DS in the data storage element DS, respectively. According to an embodiment, the selection element TR of each memory cell MC may be a vertical channel transistor (VCT). The vertical channel transistor may have a structure in which the channel length extends in a direction (i.e., the third direction D3) perpendicular to the upper surface of the substrate 100.

[0036] The data storage element DS may be implemented as, for example, a capacitor, a magnetic tunnel junction pattern, or a variable resistor. In this example, a capacitor may be provided as the data storage element DS of each memory cell MC.

[0037] Figure 2 is a schematic perspective view of a semiconductor memory device according to an embodiment of the inventive concept.

[0038] Refer to Figure 2, in a semiconductor memory device, a first structure PS and a second structure CS are sequentially stacked on a substrate 100 along a third direction D3. The first structure PS may also be referred to as a peripheral circuit structure. The second structure CS may also be referred to as a cell structure. The substrate 100 may be a semiconductor substrate, a silicon-on-insulator (SOI) substrate, or an insulating substrate. The first structure PS includes first to eighth core regions Core1 to Core8 and a first peripheral circuit region Peri1 that are two-dimensionally arranged along a first direction D1 and a second direction D2. The first core region Core1, the third core region Core3, the fifth core region Core5, and the seventh core region Core7 may be disposed on a front surface of the first structure PS. The second core region Core2, the fourth core region Core4, the sixth core region Core6, and the eighth core region Core8 may be disposed on a rear surface of the first structure PS opposite to the front surface of the first structure PS along the second direction D2. The first peripheral circuit region Peri1 may be disposed between the first core region Core1, the third core region Core3, the fifth core region Core5, and the seventh core region Core7 and the second core region Core2, the fourth core region Core4, the sixth core region Core6, and the eighth core region Core8. In this example, eight core regions are disclosed, but the number of core regions is not limited thereto and may be less than 8 or greater than 9. The arrangement of the first core region Core1 to the eighth core region Core8 and the first peripheral circuit region Peri1 is not limited to Figure 2 the arrangement, and may occur differently changed.

[0039] The second structure CS includes a first cell array region Cell1 to an eighth cell array region Cell8 and a second peripheral circuit region Peri2 two-dimensionally arranged along a first direction D1 and a second direction D2. The first cell array region Cell1, the third cell array region Cell3, the fifth cell array region Cell5, and the seventh cell array region Cell7 may be disposed on the front surface of the second structure CS. The second cell array region Cell2, the fourth cell array region Cell4, the sixth cell array region Cell6, and the eighth cell array region Cell8 may be disposed on the rear surface of the second structure CS opposite to the front surface of the second structure CS along the second direction D2. The second peripheral circuit region Peri2 may be disposed between the first cell array region Cell1, the third cell array region Cell3, the fifth cell array region Cell5, the seventh cell array region Cell7 and the second cell array region Cell2, the fourth cell array region Cell4, the sixth cell array region Cell6, and the eighth cell array region Cell8. In this example, eight cell array regions are disclosed, but the number of cell array regions is not limited thereto and may be less than 8 or greater than 9. The arrangement of the first cell array region Cell1 to the eighth cell array region Cell8 and the second peripheral circuit region Peri2 is not limited to Figure 2 the arrangement of, and may be changed differently.

[0040] The first cell array region Cell1 to the eighth cell array region Cell8 may respectively vertically overlap with the first core region Core1 to the eighth core region Core8 in a third direction D3. As used herein, the term "overlap" (or "overlapping" or similar terms) is intended to broadly refer to a first element that intersects at least a portion of a second element in a vertical direction (i.e., the third direction D3), but does not require the first element and the second element to be perfectly aligned with each other in a horizontal plane (i.e., in the first direction D1 and / or the second direction D2). The first cell array region Cell1 to the eighth cell array region Cell8 may be respectively connected to the first core region Core1 to the eighth core region Core8. The second peripheral circuit region Peri2 may vertically overlap with the first peripheral circuit region Peri1. The second peripheral circuit region Peri2 may be connected to the first peripheral circuit region Peri1. Each of the first cell array region Cell1 to the eighth cell array region Cell8 may correspond to Figure 1A the cell array region 10 of. Refer to Figure 1A and Figure 1B The bit line BL, word line WL, and memory cell MC described may be disposed in each of the first cell array region Cell1 to the eighth cell array region Cell8. Refer toFigure 1A The described sub-word line driver 22 and sense amplifier 24 may be provided in each of the first core region Core1 to the eighth core region Core8. The row decoder 32, column decoder 34, and control logic circuit 36 may be provided in the first peripheral circuit region Peri1 and the second peripheral circuit region Peri2.

[0041] In this example, the antifuse circuit may be provided in the second peripheral circuit region Peri2. An antifuse is a resistive fuse element having electrical characteristics opposite to those of a fuse. The antifuse element may take the form of a transistor including a gate insulating layer and a gate electrode. Under normal conditions, the gate insulating layer of the antifuse device may be normally maintained. When a defective cell is found during inspection of the semiconductor memory device, a programming operation may be performed to apply a high voltage (breakdown voltage or fusing voltage) to the gate electrode of the antifuse device to destroy the gate insulating layer. Thus, the defective cell may be replaced with a redundant cell. Therefore, since it is not necessary to discard the semiconductor memory device, the yield can be improved.

[0042] Figure 3 is a schematic cross-sectional view taken along line A-A' of the semiconductor memory device according to an embodiment of the inventive concept. Figure 2 as shown.

[0043] Refer to Figure 2 and Figure 3 , the first structure PS and the second structure CS are sequentially stacked on the substrate 100 in a vertical direction (i.e., the third direction D3). The substrate 100 may be a semiconductor substrate, a silicon-on-insulator (SOI) substrate, or an insulating substrate. The device isolation pattern 103 may be provided on the substrate 100 to define active regions for the peripheral transistors PTR1, PTR2, and PTR3. The device isolation pattern 103 may have a single-layer or multi-layer structure of at least one of silicon oxide and silicon nitride.

[0044] The first structure PS may include a first peripheral transistor PTR1, a second peripheral transistor PTR2, and a third peripheral transistor PTR3, a lower contact plug PC1, a lower wiring PI1, and a lower insulating layer PL1 disposed on the substrate 100. Each of the first peripheral transistor PTR1, the second peripheral transistor PTR2, and the third peripheral transistor PTR3 may be in the form of a planar transistor, a fin field effect transistor (FinFET), a multi-bridge channel FET (MBCFET), a gate-all-around (GAA) transistor, or a buried channel array transistor (BCAT). Each of the first peripheral transistor PTR1, the second peripheral transistor PTR2, and the third peripheral transistor PTR3 may be connected to the lower contact plug PC1 and the lower wiring PI1. The lower insulating layer PL1 may cover the first peripheral transistor PTR1, the second peripheral transistor PTR2, the third peripheral transistor PTR3, the lower contact plug PC1, and the lower wiring PI1. A lower connection pad CCP1 is disposed on the lower insulating layer PL1. The lower connection pad CCP1 is electrically connected to the lower contact plug PC1 and the lower wiring PI1. Unless otherwise specified, the term "connected" (or "connecting", or similar terms such as "contact" or "contacting") as may be used herein is intended to refer to a physical connection and / or an electrical connection between two or more elements, and may include other intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] The lower connection pad CCP1, the lower contact plug PC1, and the lower wiring PI1 may each include a metal such as copper, aluminum, tungsten, titanium, tantalum, titanium nitride, or tantalum nitride. The lower insulating layer PL1 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, SiCN, and a porous insulator.

[0046] In each of the core regions Core1 to Core8, the first peripheral transistor PTR1 and the lower contact plug PC1 and the lower wiring PI1 connected thereto may constitute a sense amplifier 24 (see Figure 1A ). In each of the core regions Core1 to Core8, the second peripheral transistor PTR2 and the lower contact plug PC1 and the lower wiring PI1 connected thereto may constitute a sub-word line driver 22 (see Figure 1A ). The third peripheral transistor PTR3 and the lower contact plug PC1 and the lower wiring PI1 connected thereto may be disposed in the first peripheral circuit region Peri1 and may constitute a row decoder 32, a column decoder 34, and a control logic circuit 36 (see Figure 1A ).

[0047] The second structure CS may include a first upper insulating layer IL1 to a seventh upper insulating layer IL7 stacked in sequence and bit lines BL, shielding lines SHL (see Figure 4 ), word lines WL, back gate lines BGL, and capacitors CAP disposed therein. Each of the first upper insulating layer IL1 to the seventh upper insulating layer IL7 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, and porous insulators.

[0048] A first upper wiring IT1 and a first upper contact plug CT1 may be disposed in the first upper insulating layer IL1. An upper connection pad CCP2 may be disposed at a lower end portion of the first upper insulating layer IL1 and may be in contact with a lower connection pad CCP1, respectively.

[0049] Figure 4 is a schematic top view of at least a part of a cell array region according to an embodiment of the inventive concept. In Figure 3 , a first cell array region Cell1 and a second cell array region Cell2 may correspond to a cross-section taken along a line A-A' of Figure 4 .

[0050] Referring to Figures 2 to 4 , the bit lines BL and the shielding lines SHL are disposed on the first upper insulating layer IL1 in each of the first cell array region Cell1 to the eighth cell array region Cell8. The bit lines BL and the shielding lines SHL may extend in a second direction D2 and be spaced apart from each other in a first direction D1. The shielding lines SHL may be interposed between the bit lines BL. A second upper wiring IT2 may be disposed on the first upper insulating layer IL1 in a second peripheral circuit region Peri2. The bit lines BL, the shielding lines SHL, and the second upper wiring IT2 may be positioned at the same horizontal height. The bit lines BL, the shielding lines SHL, and the second upper wiring IT2 may be covered by a second upper insulating layer IL2.

[0051] Referring to Figure 3 and Figure 4 , a bit line contact plug BLC may penetrate (i.e., extend to or through) the first upper insulating layer IL1 and may connect an end portion of the bit line BL to the upper connection pad CCP2. Although not shown in Figure 3 , a shielding line contact plug SHC may penetrate the first upper insulating layer IL1 and may connect an end portion of the shielding line SHL to the upper connection pad CCP2. A word line contact plug WLC may penetrate the first upper insulating layer IL1 and a part of the second upper insulating layer IL2 and may connect an end portion of the word line WL to the first upper wiring IT1. A back gate line contact plug BGC may pass through the first upper insulating layer IL1 and a part of the second upper insulating layer IL2 and may connect an end portion of the back gate line BGL to the first upper wiring IT1.

[0052] Figure 5A of an embodiment according to the inventive concept Figure 3 Schematic enlarged view of region “P1”.

[0053] Referring to Figures 2 to 5A , in each of the first unit cell array region Cell1 to the eighth unit cell array region Cell8, the active pattern AP may penetrate the second upper insulating layer IL2 to contact the bit line BL. The active pattern AP may include a pair of first active patterns AP(1) and second active patterns AP(2) adjacent to each other in the second direction D2. The word line WL may include a pair of first word lines WL(1) and second word lines WL(2) adjacent to each other in the second direction D2. The back gate line BGL is interposed between the pair of first active patterns AP(1) and second active patterns AP(2). The word line WL and the back gate line BGL may extend in the first direction D1 as Figure 4 shown.

[0054] A third upper insulating layer IL3 is disposed on the second upper insulating layer IL2. A fourth upper insulating layer IL4 is disposed on the third upper insulating layer IL3. The storage node contact BC may penetrate the fourth upper insulating layer IL4 and the third upper insulating layer IL3, and may contact the upper end portion of the active pattern AP. Within the third upper insulating layer IL3, the storage node contact BC may have a wider width in the second direction D2 than within the fourth upper insulating layer IL4.

[0055] Figure 5B of an embodiment according to the inventive concept Figure 3 Detailed enlarged view of region “P1”.

[0056] Referring to Figure 5B , each bit line BL may include a polysilicon pattern 161 and a metal pattern 163 stacked in sequence along the third direction D3. Although not shown in Figure 5B , each shielding line SHL( Figure 4 ) may have at least one of the polysilicon pattern 161 and the metal pattern 163. With respect to the upper surface of the substrate 100 as a reference layer, the horizontal height of the upper surface of each bit line BL may be the same as or different from the horizontal height of the upper surface of each shielding line SHL in the third direction D3. With respect to the upper surface of the substrate 100 as a reference layer, the horizontal height of the lower surface of each bit line BL may be the same as or different from the horizontal height of the lower surface of each shielding line SHL in the third direction D3. The metal pattern 163 may include a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.) and a metal (e.g., tungsten, titanium, tantalum, etc.). The metal pattern 163 may include a metal silicide, such as titanium silicide, cobalt silicide, or nickel silicide.

[0057] Referring to Figure 5Aand Figure 5B ,the active pattern AP may be formed of single-crystalline semiconductor material. As an example, the active pattern AP may be formed of single-crystalline silicon. Each of the first active pattern AP(1) and the second active pattern AP(2) may have a length in a first direction D1, a width W1 in a second direction D2, and a height H1 in a third direction D3 perpendicular to the first direction D1 and the second direction D2. Each of the first active pattern AP(1) and the second active pattern AP(2) may have a substantially uniform width W1. The width W1 of the first active pattern AP(1) and the second active pattern AP(2) may be several nanometers to several tens of nanometers, but the embodiments are not limited thereto. For example, the width W1 of the first active pattern AP(1) and the second active pattern AP(2) may be 1 nm to 30 nm, more preferably 1 nm to 10 nm. The length of each of the first active pattern AP(1) and the second active pattern AP(2) may be greater than the line width of the bit line (BL).

[0058] Reference Figure 5B ,each of the first active pattern AP(1) and the second active pattern AP(2) may have a first surface S1 and a second surface S2 opposite to each other in a third direction D3 perpendicular to the first direction D1 and the second direction D2. In one example, the first surface S1 of the first active pattern AP(1) and the second active pattern AP(2) may be in contact with the polysilicon pattern 161 of the bit line BL, and when the polysilicon pattern 161 is omitted, the first surface S1 may be in contact with the metal pattern 163.

[0059] Each of the first active pattern AP(1) and the second active pattern AP(2) may have a first side SS1 and a second side SS2 opposite to each other in the second direction D2. The first side SS1 of the first active pattern AP(1) may be adjacent to the first word line WL(1), and the second side SS2 of the second active pattern AP(2) may be adjacent to the second word line WL(2).

[0060] Each of the first active pattern AP(1) and the second active pattern AP(2) may include a first dopant region SDR1 adjacent to the bit line BL, a second dopant region SDR2 adjacent to the storage node contact BC, and a channel region CHR located between the first dopant region SDR1 and the second dopant region SDR2. The first dopant region SDR1 and the second dopant region SDR2 may be regions doped with dopants in the first active pattern AP(1) and the second active pattern AP(2), and the dopant concentration in the first active pattern AP(1) and the second active pattern AP(2) may be greater than the dopant concentration in the channel region CHR.

[0061] The portion of the word line WL adjacent to the active pattern AP can be used as a gate electrode, and the first doped region SD1 and the second doped region SDR2 doped in the active pattern AP can be used as source / drain regions, so that a selection element TR or a vertical channel transistor in Figure 1B can be provided.

[0062] During the operation of the semiconductor memory device, the channel regions CHR of the first active pattern AP(1) and the second active pattern AP(2) can be controlled by the first word line WL(1) and the second word line WL(2) and the back gate line BGL, respectively. Since the first active pattern AP(1) and the second active pattern AP(2) are formed of a single crystal semiconductor material, the leakage current characteristics can be improved during the operation of the semiconductor memory device.

[0063] Reference Figure 4 and Figure 5B , the back gate lines BGL can be set to be spaced apart from each other by a specific distance in the second direction D2 on the bit line BL. The back gate lines BGL can extend in the first direction D1 across the bit line BL.

[0064] Each back gate line BGL can be disposed between a pair of the first active pattern AP(1) and the second active pattern AP(2) adjacent to each other in the second direction D2. That is, the first active pattern AP(1) can be disposed on one side of each back gate line BGL, and the second active pattern AP(2) can be disposed on the other side. The height of the back gate line BGL in the third direction D3 can be less than the heights of the first active pattern AP(1) and the second active pattern AP(2).

[0065] The back gate line BGL can have a first surface close to the bit line BL and a second surface opposite to the first surface in the third direction D3 close to the storage node contact BC. The first surface and the second surface of the back gate line BGL can be vertically spaced apart from the first surface S1 and the second surface S2 of the first active pattern AP(1) and the second active pattern AP(2).

[0066] With respect to the upper surface of the substrate 100 as a reference layer, in the third direction D3, the horizontal height of the upper surface of each back gate line BGL can be the same as or different from the horizontal height of the upper surface of each word line WL. With respect to the upper surface of the substrate 100 as a reference layer, in the third direction D3, the horizontal height of the lower surface of each back gate line BGL can be the same as or different from the horizontal height of the lower surface of each word line WL.

[0067] The back gate line BGL can be formed of, for example, doped polysilicon, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten, titanium, tantalum, etc.), a conductive metal silicide, a conductive metal oxide, or a combination thereof.

[0068] During the operation of the semiconductor memory device, a negative voltage may be applied to the back gate line BGL, and the threshold voltage of the vertical channel transistor may increase. That is, as the vertical channel transistor is miniaturized, the threshold voltage may decrease, thereby preventing deterioration of the leakage current characteristics.

[0069] The second upper insulating layer IL2 may include layers 111, 115, GOX1, GOX2, 131, 141, 143, 153, and 155 formed of an insulating material. The first insulating pattern 111 may be disposed between the first active pattern AP(1) and the second active pattern AP(2) adjacent to each other along the second direction D2. The first insulating pattern 111 may be disposed between the second dopant regions SDR2 of the first active pattern AP(1) and the second active pattern AP(2). The first insulating pattern 111 may include, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

[0070] The first back gate insulating layer GOX2 may be disposed between the back gate line BGL and the first active pattern AP(1) and the second active pattern AP(2) along the second direction D2, and may be located between the back gate line BGL and the first insulating pattern 111 in the third direction D3, respectively. The first back gate insulating layer GOX2 may include vertical portions along the third direction covering both sides of the back gate line BGL and a horizontal portion connecting these vertical portions. The horizontal portion of the first back gate insulating layer GOX2 may be closer to the storage node contact BC than the bit line BL, and may cover the second surface of the back gate line BGL.

[0071] Reference Figure 5A and Figure 5B , the first back gate insulating layer GOX2 may be formed of, for example, a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer, or a combination thereof. The first back gate insulating layer GOX2 may have a second thickness T2 in the second direction D2.

[0072] The back gate covering pattern 115 may be disposed between the bit line BL and the back gate line BGL along the third direction D3. The back gate covering pattern 115 may be formed of an insulating material, and the lower surface of the back gate covering pattern 115 may contact the polysilicon pattern 161 of the bit line BL. The back gate covering pattern 115 may be disposed between the vertical portions of the first back gate insulating layer GOX2. The thickness of the back gate covering pattern 115 between the bit lines BL may be different from the thickness of the back gate covering pattern 115 on the bit line BL.

[0073] Reference Figure 5A and Figure 5B, the first word line WL(1) and the second word line WL(2) may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. The unit gate insulating layer GOX1 may be disposed between the first word line WL(1) and the first active pattern AP(1), and between the second word line WL(2) and the second active pattern AP(2). The unit gate insulating layer GOX1 may extend in a first direction D1 to be parallel to the first word line WL(1) and the second word line WL(2). The unit gate insulating layer GOX1 may have a first thickness T1 in a second direction D2. The first thickness T1 may be the same as or different from the second thickness T2.

[0074] The unit gate insulating layer GOX1 may be formed of a silicon oxide layer, a silicon oxynitride layer, a high-k (high dielectric constant) dielectric layer having a higher dielectric constant than the silicon oxide layer, or a combination thereof. The high-k dielectric layer may be formed of a metal oxide or a metal oxynitride. For example, the high-k dielectric layer that may be used as the gate insulating layer may be formed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0075] The unit gate insulating layer GOX1 may cover a first side surface SS1 of the first active pattern AP(1) and a second side surface SS2 of the second active pattern AP(2). As used herein, the term "cover" (or "covering" or similar terms) is intended to broadly refer to an element, structure, or layer that is located on or above another element, structure, or layer, either directly or with one or more other intermediate elements, structures, or layers therebetween. The unit gate insulating layer GOX1 may have a substantially uniform thickness. Each unit gate insulating layer GOX1 may include a vertical portion VP adjacent to the first active pattern AP(1) and the second active pattern AP(2) in a third direction D3 and a horizontal portion HP protruding from the vertical portion VP in the second direction D2.

[0076] As an example, a pair of the first word line WL(1) and the second word line WL(2) may be disposed on the horizontal portion HP of each unit gate insulating layer GOX1. The unit gate insulating layers GOX1 may be spaced apart from each other and may be mirror symmetric to each other.

[0077] The second insulating pattern 143 may be disposed between the horizontal portion HP of the cell gate insulating layer GOX1 and the storage node contact BC. As an example, the second insulating pattern 143 may include silicon oxide. The first etch stop layer 131 and the second etch stop layer 141 may be disposed between the second dopant region SDR2 of the first active pattern AP(1) and the second insulating pattern 143, and between the second dopant region SDR2 of the second active pattern AP(2) and the second insulating pattern 143.

[0078] On the cell gate insulating layer GOX1, the first word line WL(1) and the second word line WL(2) may be separated from each other by a third insulating pattern 155. The third insulating pattern 155 may extend in a first direction D1 between the first word line WL(1) and the second word line WL(2). A first capping layer 153 may be disposed between the third insulating pattern 155 and the first word line WL(1), and between the third insulating pattern 155 and the second word line WL(2). The first capping layer 153 may have a substantially uniform thickness in a second direction and a third direction.

[0079] The third upper insulating layer IL3 may include an etch stop layer 210 and an interlayer insulating layer 231 stacked in sequence along a third direction D3. The storage node contact BC may penetrate (i.e., extend to or through) the interlayer insulating layer 231 and the etch stop layer 210 and be electrically connected to the first active pattern AP(1) and the second active pattern AP(2), respectively. That is, the storage node contact BC may be electrically connected to the second dopant regions SDR2 of the first active pattern AP(1) and the second active pattern AP(2), respectively. The storage node contact BC may have a lower width greater than an upper width in a second direction D2. Adjacent storage node contacts BC may be separated from each other by a fourth upper insulating layer IL4. When observed in a plan view, each storage node contact BC may have various shapes such as, for example, circular, oval, rectangular, square, diamond, hexagonal, etc., but the embodiments are not limited thereto. The storage node contacts BC are arranged in a matrix along a first direction D1 and a second direction D2. The storage node contact BC may be formed of, for example, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto.

[0080] Figure 6 is an enlarged view of “P2” in accordance with an embodiment of the inventive concept Figure 3 in

[0081] Reference Figure 3 and Figure 6, in the second peripheral circuit region Peri2, the active pattern AP can penetrate (i.e., extend to or through) the second upper insulating layer IL2 in the third direction D3 and contact the second upper wiring IT2. The active pattern AP can include a pair of third active patterns AP(3) and fourth active patterns AP(4) adjacent to each other in the second direction D2. Each of the third active pattern AP(3) and the fourth active pattern AP(4) has the same width W1 in the second direction D2 and the same height H1 in the third direction D3.

[0082] The anti-fuse gate electrode AG is disposed on a side of the third active pattern AP(3) opposite to the fourth active pattern AP(4) in the second direction D2. The peripheral back-gate electrode AB is interposed between the third active pattern AP(3) and the fourth active pattern AP(4). The read gate electrode RG is disposed on a side of the fourth active pattern AP(4) opposite to the third active pattern AP(3) in the second direction D2. Although not shown in Figure 6 but similar to Figure 5B the first active pattern AP(1) and the second active pattern AP(2), the third active pattern AP(3) and the fourth active pattern AP(4) respectively include a first dopant region SDR1 and a second dopant region SDR2 and a channel region CHR therebetween.

[0083] Refer to Figure 6 , the anti-fuse gate insulating layer GOX3 can be interposed between the anti-fuse gate electrode AG and the third active pattern AP(3). The read gate insulating layer GOX4 can be interposed between the read gate electrode RG and the fourth active pattern AP(4). The second back-gate insulating layer GOX5 can be interposed between the peripheral back-gate electrode AB and the third active pattern AP(3) and between the peripheral back-gate electrode AB and the fourth active pattern AP(4).

[0084] The anti-fuse gate electrode AG, the anti-fuse gate insulating layer GOX3 and the third active pattern AP(3) can constitute an anti-fuse transistor AF. The read gate electrode RG, the read gate insulating layer GOX4 and the fourth active pattern AP(4) can constitute a read transistor RD.

[0085] Refer to Figure 5A and Figure 6 , the anti-fuse gate insulating layer GOX3 can have a third thickness T3 in the second direction D2. The read gate insulating layer GOX4 can have a fourth thickness T4 in the second direction D2. The second back-gate insulating layer GOX5 can have a fifth thickness T5 in the second direction D2. The third thickness T3 can be the same as or different from the fourth thickness T4 and the fifth thickness T5 respectively.

[0086] The third thickness T3 of the antifuse gate insulating layer GOX3 may be equal to or less than the first thickness T1 of the cell gate insulating layer GOX1. Thus, during a programming operation in which a high voltage is applied to the gate electrode of the antifuse element, the antifuse gate insulating layer GOX3 may be liable to be destroyed, enabling the programming operation to proceed easily.

[0087] The conductive pattern 40 may be disposed on the third active pattern AP(3) and the fourth active pattern AP(4), respectively. The conductive pattern 40 may be formed of the same material as the storage node contact BC. In the third direction, with respect to the upper surface of the substrate 100 as a reference layer, the conductive pattern 40 may be positioned at the same horizontal height as the storage node contact BC and may have the same cross-section.

[0088] Referring again to Figure 3 and Figure 5A , the landing pad LP may be disposed on the storage node contact BC. When observed in a plan view, each landing pad LP may have various shapes such as circular, elliptical, rectangular, square, rhombic, or hexagonal, but the embodiments are not limited thereto. The landing pad LP may overlap the storage node contact BC completely or partially vertically. When observed in a plan view, the landing pads LP may be arranged in a matrix form along the first direction D1 and the second direction D2. Alternatively, when observed in a plan view, the landing pads LP may be arranged in a honeycomb shape. The landing pad LP may be formed of, for example, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto.

[0089] Referring to Figure 3 and Figure 6 , the third upper wiring IT3 is disposed on the conductive pattern 40 and the fourth upper insulating layer IL4. The third upper wiring IT3(1) connected to the third active pattern AP(3) may be electrically floating. The third upper wiring IT3(2) connected to the fourth active pattern AP(4) may extend to the upper surface of the fourth upper insulating layer IL4.

[0090] The second upper contact plug CT2 may penetrate (i.e., extend therein) at least a part of the first upper insulating layer IL1 to the fourth upper insulating layer IL4 and may electrically connect the third upper wiring IT3 to the first upper wiring IT1 or the upper connection pad CCP2.

[0091] Referring to Figure 3, the lower electrodes BE of the capacitor CAP can be respectively disposed on the landing pads LP. The lower electrodes BE can be respectively electrically connected to the first active pattern AP(1) and the second active pattern AP(2). Each lower electrode BE can be in a column shape or a hollow cup shape.

[0092] The lower electrodes BE can be arranged in a matrix shape or a honeycomb shape along the first direction D1 and the second direction D2. The lower electrodes BE can completely or partially overlap with the landing pads LP. The lower electrodes BE can contact all or part of the upper surface of the landing pads LP. The interval between the lower electrodes BE can be constant. The lower electrodes BE can penetrate (i.e., extend into) a part of the fifth upper insulating layer IL5 and can respectively contact the landing pads LP. The lower electrodes BE can include at least one of polysilicon doped with impurities, metal, metal oxide layer, and metal nitride layer. The lower electrodes BE can preferably include a titanium nitride layer.

[0093] The upper sidewalls of the lower electrodes BE can partially contact the support pattern SSP. The support pattern SSP can prevent the lower electrodes BE from collapsing. When observed in a plan view, the support pattern SSP can be in the shape of a plate or a net in which a plurality of holes are formed. The support pattern SSP can be formed by one layer or two or more layers. The support pattern SSP can be formed by a single layer or multiple layers of, for example, at least one of silicon nitride (SiN), silicon boron nitride (SiBN), and silicon carbon nitride (SiCN), but the embodiments are not limited thereto.

[0094] The dielectric layer DL conformally covers the lower electrodes BE and the support pattern SSP. As used herein, the term "conformally" (or "conformal" or similar terms) in the context of a material layer or a coating is intended to broadly refer to a material layer or a coating having a substantially uniform cross-sectional thickness with respect to the profile of the surface to which the material layer is applied. The dielectric layer DL covers the upper surface of the fifth upper insulating layer IL5. The dielectric layer DL can be formed as a single layer or multiple layers of, for example, a silicon oxide layer or a metal oxide layer having a higher dielectric constant than a silicon oxide layer, such as an aluminum oxide layer. The upper electrode UE can be disposed on the dielectric layer DL. The upper electrode UE can be formed of a single layer or multiple layers of at least one of a titanium nitride layer, a tungsten layer, a polysilicon layer doped with impurities, and a silicon germanium layer doped with impurities. The sidewalls of the upper electrode UE can be aligned with the sidewalls of the dielectric layer DL.

[0095] The lower electrodes BE, the dielectric layer DL, and the upper electrode UE can constitute the capacitor CAP. The capacitor CAP can correspond to Figure 1BThe data storage element DS. The capacitor CAP and the fifth upper insulating layer IL5 are covered by the sixth upper insulating layer IL6. The seventh upper insulating layer IL7 is disposed on the sixth upper insulating layer IL6. The fourth upper contact plug CT4 and the fourth upper wiring IT4 may be disposed in the seventh upper insulating layer IL7. The third upper contact plug CT3 may connect the fourth upper wiring IT4 to the third upper wiring IT3 by penetrating (i.e., extending to or through) the fifth upper insulating layer IL5 and the sixth upper insulating layer IL6.

[0096] Figure 7A is a schematic diagram showing an example anti-fuse circuit according to an embodiment of the inventive concept.

[0097] Reference Figure 7A , the anti-fuse circuit according to the inventive concept includes an anti-fuse transistor AF, a read transistor RD, and a select transistor SEL connected in series electrically. The anti-fuse circuit may be arranged two-dimensionally along a first direction D1 and a second direction D2, or three-dimensionally along a first direction D1 to a third direction D3. The anti-fuse gate electrode AG of the anti-fuse transistor AF, the read gate electrode RG of the read transistor RD, and the select gate electrode SG of the select transistor SEL may be connected to the control logic 36.

[0098] Reference Figure 6 and Figure 7A , the anti-fuse transistor AF may be electrically connected to the read transistor RD through the second upper wiring IT2. The third upper wiring IT3(1) corresponding to one terminal of the anti-fuse transistor AF may be electrically floating (i.e., not connected). Figure 7A The select transistor SEL of Figure 3 may be one of the third peripheral transistors PTR3 of

[0099] Figure 7B is a schematic diagram illustrating Figure 6 the programming operation of the anti-fuse transistor AF of

[0100] Reference Figure 7A and Figure 7B, when a defective cell is found during the inspection of a semiconductor memory device, a programming operation is performed in which a high voltage (breakdown voltage or fusing voltage) is applied from the control logic 36 to the anti-fuse gate electrode AG of the anti-fuse transistor AF. During the programming operation, a conduction voltage is applied from the control logic 36 to the read gate electrode RG of the read transistor RD and the select gate electrode SG of the select transistor SEL. Therefore, 0V at the second terminal of the select transistor SEL can be applied to the third active pattern AP(3) that serves as the channel region of the anti-fuse transistor AF. Due to the voltage difference between the anti-fuse gate electrode AG and the third active pattern AP(3), the anti-fuse gate insulating layer GOX3 can be destroyed as shown by the arrow in Figure 7B . Thus, a circuit path (i.e., a resistance path or an electrical short) is formed within the anti-fuse gate insulating layer GOX3.

[0101] After the programming operation, a read operation can be performed. During the read operation, when an electrical signal is applied to the anti-fuse gate electrode AG and the read transistor RD and the select transistor SEL are turned on, an electrical signal can be detected from the second terminal of the select transistor SEL. Therefore, the defective cell can be replaced with a redundant cell.

[0102] In the semiconductor memory device according to the inventive concept, the second peripheral circuit region Peri2 including the anti-fuse circuit can be disposed between the cell array regions Cell1 to Cell8, thereby improving the integration degree and reducing the total horizontal area of the semiconductor memory device. In addition, the anti-fuse AF and the read transistor RD can be implemented in the form of vertical channel transistors by using the same vertical active patterns AP(3) and AP(4) as the vertical active patterns AP(1) and AP(2) of the cell array regions Cell1 to Cell8. Therefore, when the horizontal area occupied by the anti-fuse circuit is reduced, the channel length can be increased. Thus, a highly integrated semiconductor memory device with improved reliability can be provided.

[0103] Figure 8 is an enlarged view of the region "P2" in Figure 3 according to an embodiment of the inventive concept.

[0104] Referring to Figure 8 , in the semiconductor memory device according to this example, the upper ends of the third active pattern AP(3) and the fourth active pattern AP(4) can be in direct contact with the third upper wiring IT3 (i.e., IT3(1) and IT3(2) respectively) without the Figure 7B conductive pattern 40. Other configurations can be the same / similar to those described with reference to Figure 7B .

[0105] Figure 9A is according to an embodiment of the inventive concept.Figure 3 An enlarged view of the region "P2".

[0106] Reference Figure 9A , according to this example, the anti-fuse gate electrode AG is disposed on one side of the third active pattern AP(3). The anti-fuse gate insulating layer GOX3 is interposed between the third active pattern AP(3) and the anti-fuse gate electrode AG. The first peripheral back gate electrode AB(1) is disposed on the other side of the third active pattern AP(3) opposite to the anti-fuse gate electrode AG in the second direction D2. The second back gate insulating layer GOX5 is interposed between the third active pattern AP(3) and the first peripheral back gate electrode AB(1). The third active pattern AP(3), the anti-fuse gate electrode AG, the anti-fuse gate insulating layer GOX3, the first peripheral back gate electrode AB(1), and the second back gate insulating layer GOX5 may form an anti-fuse transistor AF.

[0107] The read gate electrode RG is disposed on one side of the fourth active pattern AP(4). The read gate insulating layer GOX4 is interposed between the fourth active pattern AP(4) and the read gate electrode RG. The second peripheral back gate electrode AB(2) is disposed on the other side of the fourth active pattern AP(4) opposite to the read gate electrode RG in the second direction D2. The second back gate insulating layer GOX5 is interposed between the fourth active pattern AP(4) and the second peripheral back gate electrode AB(2). The second upper insulating layer IL2 is interposed between the first peripheral back gate electrode AB(1) and the read gate electrode RG. The fourth active pattern AP(4), the read gate electrode RG, the read gate insulating layer GOX4, the second peripheral back gate electrode AB(2), and the second back gate insulating layer GOX5 may form a read transistor RD.

[0108] Figure 9B is a schematic diagram illustrating Figure 9A the programming operation of the anti-fuse transistor AF of

[0109] Reference Figure 9B , during the programming operation, the same high voltage may be simultaneously applied to the anti-fuse gate electrode AG and the first peripheral back gate electrode AB(1). The anti-fuse gate insulating layer GOX3 and the second back gate insulating layer GOX5 disposed on both sides of the third active pattern AP(3) may be simultaneously damaged, thereby forming a circuit path as indicated by the corresponding arrows in Figure 9B . Two circuit paths may be formed, so that during the read operation, the current amount may increase, and the electrical signal may be well detected.

[0110] Figure 10 is a schematic cross-sectional view illustrating a part of a semiconductor memory device according to an embodiment of the inventive concept.

[0111] Reference Figure 10, in the semiconductor memory device according to the present example, the antifuse transistor AF can be disposed on the second upper wiring IT2 of the second structure CS. The read transistor RD can be positioned at the same horizontal height as the third peripheral transistor PTR3 in the first structure PS. The antifuse transistor AF according to this example can have the same structure as the antifuse transistor AF of Figure 9A . The read transistor RD can have the same structure as the third peripheral transistor PTR3. The antifuse transistor AF can be connected to the read transistor RD through the second upper wiring IT2, the first upper contact plug CT1, the first upper wiring IT1, the upper connection pad CCP2, the lower connection pad CCP1, the lower wiring PI1, and the lower contact plug PC1. Other structures can be the same as / similar to those described above.

[0112] In the semiconductor memory device according to the inventive concept, a peripheral circuit region including an antifuse circuit can be disposed between cell array regions, thereby improving integration and reducing the total horizontal area of the semiconductor memory device. Additionally, the antifuse transistor and the read transistor can be implemented in the form of vertical channel transistors by using the same type of active pattern as the vertical active pattern of the cell array region. Therefore, the horizontal area occupied by the antifuse circuit can be reduced and the channel length can be increased. Accordingly, a highly integrated semiconductor memory device with improved reliability can be provided.

[0113] Although embodiments have been described above, those skilled in the art will understand that many modifications and variations can be made without departing from the spirit and scope of the inventive concept defined in the appended claims. Therefore, the exemplary embodiments of the inventive concept should be considered illustrative rather than restrictive in all respects, and the spirit and scope of the inventive concept are indicated by the appended claims. Figures 2 to 10 The embodiments of can be combined with each other.

Claims

1. A semiconductor memory device, comprising: substrate; a first structure, the first structure being located on the substrate and comprising a core region and a first peripheral circuit region; as well as a second structure located on the first structure and including a cell array region and a second peripheral circuit region located between the cell array regions, Wherein, the second structure further includes: a first active pattern, the first active pattern being located in each of the cell array regions and being perpendicular to an upper surface of the first structure; a word line adjacent to one side of the first active pattern and extending in a first direction parallel to the upper surface of the first structure; a bit line contacting a lower surface of the first active pattern and extending in a second direction parallel to the upper surface of the first structure and intersecting the first direction; a second active pattern located in the second peripheral circuit region and perpendicular to the upper surface of the first structure; and An anti-fuse gate electrode is located at one side of the second active pattern.

2. The semiconductor memory device according to claim 1, wherein: The second structure also includes: a first gate insulating layer, the first gate insulating layer being located between the first active pattern and the word line and having a first thickness in the second direction; and a second gate insulating layer, the second gate insulating layer being located between the second active pattern and the anti-fuse gate electrode and having a second thickness in the second direction, and Wherein, the second thickness is equal to or smaller than the first thickness.

3. The semiconductor memory device according to claim 2, wherein: The second gate insulating layer is configured such that an electrical path is formed within the second gate insulating layer when a high voltage is applied to the anti-fuse gate electrode.

4. The semiconductor memory device according to claim 1, wherein: The first active pattern has the same width as the second active pattern in the second direction, and the first active pattern has the same height as the second active pattern in a third direction perpendicular to the upper surface of the first structure.

5. The semiconductor memory device according to claim 1, wherein The second structure further includes a first peripheral back-gate electrode spaced apart from the anti-fuse gate electrode, and the second active pattern is located between the first peripheral back-gate electrode and the anti-fuse gate electrode.

6. The semiconductor memory device according to claim 5, wherein: The second structure also includes: a third active pattern spaced apart from the second active pattern and perpendicular to the upper surface of the first structure, and the first peripheral back gate electrode is located between the third active pattern and the second active pattern; and A read gate electrode is spaced apart from the first peripheral back-gate electrode, and the third active pattern is located between the read gate electrode and the first peripheral back-gate electrode.

7. The semiconductor memory device according to claim 5, wherein: The second structure also includes: a third active pattern, the third active pattern being spaced apart from the second active pattern and being perpendicular to the upper surface of the first structure, and the first peripheral back gate electrode being located between the third active pattern and the second active pattern; a first upper insulating layer, the first upper insulating layer being located between the first peripheral back gate electrode and the third active pattern; a read gate electrode, the read gate electrode being located between the first upper insulating layer and the third active pattern; a second peripheral back-gate electrode, the second peripheral back-gate electrode being spaced apart from the read gate electrode, and the third active pattern being located between the second peripheral back-gate electrode and the read gate electrode; a first gate insulating layer, the first gate insulating layer being located between the anti-fuse gate electrode and the second active pattern; and A second gate insulating layer is disposed between the first peripheral back gate electrode and the second active pattern.

8. The semiconductor memory device according to claim 7, wherein: Each of the first gate insulating layer and the second gate insulating layer is configured so that when a high voltage is applied to the anti-fuse gate electrode and the first peripheral back-gate electrode, respectively, an electrical path is formed in the first gate insulating layer and the second gate insulating layer, respectively.

9. The semiconductor memory device according to claim 7, wherein: The second peripheral structure also includes: a second upper insulating layer, the second upper insulating layer being located below the bit line relative to the upper surface of the first structure; a conductive line located on the second upper insulating layer and contacting a lower surface of the second active pattern; an upper connection pad located at a lower surface of the second upper insulating layer; and an upper contact plug extending into the second upper insulating layer and electrically connecting the conductive line to the upper connection pad, and Wherein, the first structure further includes: a read transistor, the read transistor being located on the substrate; a lower insulating layer, the lower insulating layer being located on the read transistor; a lower connection pad located on an upper end portion of the lower insulating layer and contacting the upper connection pad; and A lower contact plug extends into the lower insulating layer and electrically connects the lower connection pad to one terminal of the read transistor.

10. A semiconductor memory device, comprising: substrate; as well as a first structure located on the substrate and including a cell array region and a first peripheral circuit region located between the cell array regions; Wherein, the first structure further includes: a first word line, a first active pattern, a back gate line, a second active pattern, and a second word line, wherein the first word line, the first active pattern, the back gate line, the second active pattern, and the second word line are sequentially adjacently arranged in a first direction parallel to an upper surface of the substrate in a corresponding cell array region in the cell array region; and an anti-fuse gate electrode, a third active pattern, and a first peripheral back-gate electrode, the anti-fuse gate electrode, the third active pattern, and the first peripheral back-gate electrode being arranged adjacent to each other along the first direction in the first peripheral circuit region, and The first active pattern, the second active pattern, and the third active pattern are perpendicular to the upper surface of the substrate in a third direction and extend longitudinally in a second direction intersecting the first direction and parallel to the upper surface of the substrate.

11. The semiconductor memory device according to claim 10, wherein: The first structure also includes: a first gate insulating layer located between the first active pattern and the word line and having a first thickness; and a second gate insulating layer, the second gate insulating layer being located between the third active pattern and the anti-fuse gate electrode and having a second thickness, and Wherein, the second thickness is equal to or smaller than the first thickness.

12. The semiconductor memory device according to claim 10, wherein: The first active pattern, the second active pattern, and the third active pattern have the same width in the first direction, and have the same height in the third direction perpendicular to the upper surface of the substrate.

13. The semiconductor memory device according to claim 10, further comprising a second structure located between the substrate and the first structure, in, The second structure includes a core region and a second peripheral circuit region, wherein the core regions respectively overlap at least partially vertically with the cell array regions, and The second peripheral circuit region at least partially vertically overlaps with the first peripheral circuit region.

14. The semiconductor memory device according to claim 13, wherein: The first peripheral structure also includes: a bit line contacting lower surfaces of the first active pattern and the second active pattern; an upper insulating layer, the upper insulating layer being located below the bit line in the third direction relative to the upper surface of the substrate; a conductive line located on the upper insulating layer and contacting a lower surface of the third active pattern; an upper connection pad located at a lower end of the upper insulating layer; and an upper contact plug extending into the upper insulating layer and electrically connecting the conductive line to the upper connection pad, and Wherein, the second structure further includes: a read transistor, the read transistor being located on the substrate; a lower insulating layer, the lower insulating layer being located on the read transistor; a lower connection pad located on an upper end portion of the lower insulating layer and contacting the upper connection pad; and A lower contact plug extends into the lower insulating layer and electrically connects the lower connection pad to one terminal of the read transistor.

15. The semiconductor memory device according to claim 10, wherein: The first structure also includes: a fourth active pattern spaced apart from the third active pattern and perpendicular to the upper surface of the substrate, and the first peripheral back gate electrode is located between the fourth active pattern and the third active pattern; and A read gate electrode is spaced apart from the first peripheral back-gate electrode, and the fourth active pattern is located between the read gate electrode and the first peripheral back-gate electrode.

16. The semiconductor memory device according to claim 10, wherein: The first structure also includes: a fourth active pattern, the fourth active pattern being spaced apart from the third active pattern and being perpendicular to the upper surface of the substrate, and the first peripheral back gate electrode being located between the fourth active pattern and the third active pattern; an upper insulating layer, the upper insulating layer being located between the first peripheral back gate electrode and the fourth active pattern; a read gate electrode, the read gate electrode being located between the upper insulating layer and the fourth active pattern; and A second peripheral back gate electrode is spaced apart from the read gate electrode, and the fourth active pattern is located between the second peripheral back gate electrode and the read gate electrode.

17. A semiconductor memory device, comprising: substrate; a first structure, the first structure being located on the substrate and comprising a core region and a first peripheral circuit region; as well as a second structure located on the first structure and including a cell array region and a second peripheral circuit region located between the cell array regions, The cell array regions respectively overlap the core regions at least partially vertically, wherein the second peripheral circuit region at least partially vertically overlaps with the first peripheral circuit region, Wherein, the second structure further includes: a bit line extending in a first direction parallel to an upper surface of the substrate in the cell array region; A first word line, a first gate insulating layer, a first active pattern, a back gate line, a second active pattern and a second word line, wherein the first word line, the first gate insulating layer, the first active pattern, the back gate line, the second active pattern and the second word line are sequentially arranged adjacent to each other on the bit line along the first direction; a conductive line, the conductive line being located in the second peripheral circuit region; an anti-fuse gate electrode, a second gate insulating layer, a third active pattern and a first peripheral back-gate electrode, wherein the anti-fuse gate electrode, the second gate insulating layer, the third active pattern and the first peripheral back-gate electrode are sequentially arranged adjacent to each other on the conductive line along the first direction, wherein the first active pattern, the second active pattern, and the third active pattern are perpendicular to the upper surface of the substrate in a third direction and extend longitudinally in a second direction intersecting the first direction and parallel to the upper surface of the substrate, wherein the first word line, the back gate line and the second word line extend in the second direction intersecting the first direction and parallel to the upper surface of the substrate, Wherein, the first gate insulating layer has a first thickness, and The second gate insulating layer has a second thickness that is equal to or smaller than the first thickness.

18. The semiconductor memory device according to claim 17, wherein: The second peripheral structure also includes: an upper insulating layer, the upper insulating layer being located below the bit line in the third direction relative to the upper surface of the substrate; a conductive line located on the upper insulating layer and contacting a lower surface of the second active pattern; an upper connection pad located at a lower end of the upper insulating layer; and an upper contact plug extending into the upper insulating layer and electrically connecting the conductive line to the upper connection pad, and Wherein, the first structure further includes: a read transistor, the read transistor being located on the substrate; a lower insulating layer, the lower insulating layer being located on the read transistor; a lower connection pad located on an upper end portion of the lower insulating layer and contacting the upper connection pad; and A lower contact plug extends into the lower insulating layer and electrically connects the lower connection pad to one terminal of the read transistor.

19. The semiconductor memory device according to claim 17, wherein: The second structure also includes: a fourth active pattern spaced apart from the third active pattern and perpendicular to the upper surface of the substrate, and the first peripheral back gate electrode is located between the fourth active pattern and the third active pattern; and A read gate electrode is spaced apart from the first peripheral back-gate electrode, and the fourth active pattern is located between the read gate electrode and the first peripheral back-gate electrode.

20. The semiconductor memory device according to claim 17, wherein: The second structure also includes: a fourth active pattern, the fourth active pattern being spaced apart from the third active pattern and being perpendicular to the upper surface of the substrate, and the first peripheral back gate electrode being located between the fourth active pattern and the third active pattern; an upper insulating layer, the upper insulating layer being located between the first peripheral back gate electrode and the fourth active pattern; a read gate electrode, the read gate electrode being located between the upper insulating layer and the fourth active pattern; and A second peripheral back gate electrode is spaced apart from the read gate electrode, and the fourth active pattern is located between the second peripheral back gate electrode and the read gate electrode.

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