Embedded metal wire structure and preparation method thereof

Abstract

The invention discloses an embedded power rail structure used for power distribution of a semiconductor device, the embedded power rail structure comprises a composite metal structure formed in a metal track groove, the composite metal structure comprises a first track metal structure close to the bottom of the metal track groove, and a second track metal structure close to the bottom of the metal track groove. The second track metal structure is far away from the bottom of the metal track groove, and the first track metal structure is made of a first metal material; and the material for forming the second track metal layer is a second metal material of which the resistivity is lower than that of the first metal material. The process in some embodiments of the invention is basically matched with the existing BPR process, and the resistance value is reduced by adopting the metal with lower resistivity. The invention also discloses a semiconductor device comprising the structure.

Description

Technical Field

[0001] This application relates to the field of conductor devices, and more particularly, to the structure and manufacturing method of transistors. Background Art

[0002] In order to improve the density and complexity of the back-end wiring, the technology of burying power / ground wires into the substrate, i.e., the buried power rail (BPR) technology, has been proposed. By using the BPR technology, the number of the bottom-most metal wiring lines can be reduced to 5T. In addition, the number of signal wiring lines can be maintained at 4T.

[0003] The BPR technology aims to separate the signal wiring lines from the power delivery network. The buried power rail 70 structure is formed after the active region process. The shallow trench isolation (STI) between the active regions is etched to the required depth, and then the BPR is formed. A typical BPR structure is as shown in Figure 4 、 Figure 5 On a silicon substrate 700, active regions are formed. An oxide layer 720 is provided between the active regions 710. Transistors are provided on the active regions. A front-side power distribution network and signal wiring lines 800 are provided on the front side of the substrate near the active regions. A BPR is provided at a position near the back side of the substrate and is connected to the above-mentioned power distribution network 900.

[0004] Considering the compatibility of the front-end process, the BPR metal generally uses a single tungsten metal structure. However, this structure has the following disadvantages: The BPR metal material can only be selected from metals compatible with the front-end process, with low selectivity; tungsten has a high resistivity and a complex process flow: first, tungsten is deposited, then chemical mechanical planarization (CMP) is performed to grind it flat, and finally, back-etching is performed to the required height to form the BPR metal. Summary of the Invention

[0005] The purpose of this application is to provide an improved BPR structure and corresponding processing technology.

[0006] To this end, some embodiments of this application provide a buried power rail structure for power distribution of semiconductor devices. The buried power rail structure includes a composite metal structure formed in the metal track trench. The composite metal structure includes a first track metal structure near the bottom of the metal track trench and a second track metal structure away from the bottom of the metal track trench. The material forming the first track metal structure is a first metal material; the material forming the second track metal layer is a second metal material with a resistivity lower than that of the first metal material.

[0007] In some embodiments, the first track metal structure has a groove structure, and one end of the second track metal structure is a structure complementary to the groove structure.

[0008] In some embodiments, the first material is a doped or undoped tungsten material; the second material is at least one of a doped or undoped ruthenium, molybdenum, or cobalt material.

[0009] In some embodiments, the composite metal structure further includes a third track metal structure that is further away from the bottom of the metal track trench, and the material forming the third track metal structure is a third metal material different from the second metal material.

[0010] In some embodiments, the third metal material is the same as the first metal material, or the third material is different from the first metal material.

[0011] In some embodiments, the third metal material is a metal material compatible with the previous process.

[0012] In some embodiments, the third metal material is doped or undoped tungsten.

[0013] Some other embodiments of the present application provide a method for forming the above-mentioned buried power rail structures, which includes the steps of: forming a plurality of active regions on a substrate; forming a power rail trench between the active regions; forming an insulating inner lining layer in the power rail trench; depositing a protective layer on the insulating inner lining layer; forming a first track metal layer of a first metal material on the protective layer; forming a first hard mask layer on the first track metal layer; performing an etching and retreat operation on the first hard mask layer to form a first part of the first hard mask layer on a first part of the first track metal layer at the bottom of the power rail trench so as to shield the first part of the first track metal layer; removing other parts of the first track metal layer other than the first part not covered by the first part of the hard mask layer, and then removing the first part of the first hard mask layer; filling the metal track trench by selective deposition to form a second track metal layer of a second metal material; depositing an oxide layer to fill the metal track trench and performing planarization to reach the position of the insulating inner lining layer; and then performing a shallow trench isolation recess treatment on the formed structure to remove part of the isolation material in the shallow trench isolation part to form a recess in the area of the shallow trench isolation part.

[0014] Some other embodiments of the present application provide a method for forming some of the above-mentioned buried power rail structures, which includes the steps of: forming a plurality of active regions on a substrate; forming a power rail trench between the active regions; forming an insulating inner lining layer in the power rail trench; depositing a protective layer on the insulating inner lining layer; forming a first track metal layer of a first metal material on the protective layer; forming a first hard mask layer on the first track metal layer; performing an etching back operation on the first hard mask layer to form a first part of the first hard mask layer on a first part of the first track metal layer at the bottom of the power rail trench so as to shield the first part of the first track metal layer; removing other parts of the first track metal layer except the first part covered by the first part of the hard mask layer, and then removing the first part of the first hard mask layer; filling the metal track trench by selective deposition to form a second track metal layer of a second material; forming a third track metal layer of a third metal material on the second track metal structure as a metal capping layer; forming a second hard mask layer on the third track metal layer; using an etching back process to remove parts of the second hard mask layer except a first part of the second hard mask layer in the metal track trench, and then removing the exposed third track metal layer to leave a part of the third track metal layer covered by the first part of the second hard mask layer to form the third track metal structure; removing the first part of the second hard mask layer; and filling the metal track trench with an oxide layer and performing planarization to reach the position of the oxide layer inner lining; performing a shallow trench isolation recess process on the formed structure to remove part of the isolation material in the shallow trench isolation part to form a recess in the area of the shallow trench isolation part.

[0015] Some embodiments of the present application further provide a semiconductor device, which includes any one of the above-mentioned buried power rail structures.

[0016] The beneficial effects of the present application are as follows: The processes in some embodiments of the present application are basically consistent with the existing BPR process. The metal with a lower resistivity is used, reducing the resistance value. In some embodiments, the selective deposition method has the flexibility of the process and there is no metal contamination problem for the front-end process. In some embodiments, the upper and lower ends of the BPR are made of tungsten material, and the metal filling in the middle part is ruthenium, molybdenum, cobalt or doped ruthenium, molybdenum, cobalt and other materials. Compared with the traditional BPR that uses tungsten or doped tungsten material as a whole, the resistance value is significantly reduced. Description of the Drawings

[0017] Figure 1 is a cross-sectional view showing a BPR structure according to an embodiment of the present application.

[0018] Figure 2A is a schematic diagram showing the first step of the formation process of a BPR structure according to an embodiment of the present application.

[0019] Figure 2B It is a schematic diagram showing the second step of the BPR structure formation process according to an embodiment of the present application.

[0020] Figure 2C It is a schematic diagram showing the third step of the BPR structure formation process according to an embodiment of the present application.

[0021] Figure 2D It is a schematic diagram showing the fourth step of the BPR structure formation process according to an embodiment of the present application.

[0022] Figure 2E It is a schematic diagram showing the fifth step of the BPR structure formation process according to an embodiment of the present application.

[0023] Figure 2F It is a schematic diagram showing the sixth step of the BPR structure formation process according to an embodiment of the present application.

[0024] Figure 2G It is a schematic diagram showing the seventh step of the BPR structure formation process according to an embodiment of the present application.

[0025] Figure 2H It is a schematic diagram showing the eighth step of the BPR structure formation process according to an embodiment of the present application.

[0026] Figure 2I It is a schematic diagram showing the ninth step of the BPR structure formation process according to an embodiment of the present application.

[0027] Figure 2J It is a schematic diagram showing the tenth step of the BPR structure formation process according to an embodiment of the present application.

[0028] Figure 2K It is a schematic diagram showing the eleventh step of the BPR structure formation process according to an embodiment of the present application.

[0029] Figure 2L It is a schematic diagram showing the twelfth step of the BPR structure formation process according to an embodiment of the present application.

[0030] Figure 2M It is a schematic diagram showing the thirteenth step of the BPR structure formation process according to an embodiment of the present application.

[0031] Figure 2N It is a schematic diagram showing the fourteenth step of the BPR structure formation process according to an embodiment of the present application.

[0032] Figure 2OIt is a schematic diagram showing the fifteenth step of the BPR structure formation process according to an embodiment of the present application.

[0033] Figure 2P It is a schematic diagram showing the sixteenth step of the BPR structure formation process according to an embodiment of the present application.

[0034] Figure 2M1 It is a schematic diagram showing the first step of the BPR structure formation process according to another embodiment of the present application.

[0035] Figure 2M2 It is a schematic diagram showing the second step of the BPR structure formation process according to another embodiment of the present application.

[0036] Figure 2M3 It is a schematic diagram showing the third step of the BPR structure formation process according to another embodiment of the present application.

[0037] Figure 2M4 It is a schematic diagram showing the fourth step of the BPR structure formation process according to another embodiment of the present application.

[0038] Figure 2M5 It is a schematic diagram showing the fifth step of the BPR structure formation process according to another embodiment of the present application.

[0039] Figure 3 It is a distribution diagram of the test results of the resistivity of the BPR structure according to an embodiment of the present application.

[0040] Figure 4 It is a structural diagram of a typical semiconductor device.

[0041] Figure 5 It is a structural diagram of the BPR in a typical semiconductor device. Detailed implementation manners

[0042] The following will make a detailed description of the specific implementation manners of the present application in conjunction with the accompanying drawings. It should be understood that the sizes and size relationships of the various parts of the structures in the drawings of the present application are all schematic. Unless otherwise clearly stated, the sizes and size relationships between the various parts shown in the drawings do not have any restrictive effects.

[0043] For the purpose of showing the transistor arrangement structure including a BPR with a low resistance value proposed herein, it may be useful to first understand the phenomena that may be operative in such an arrangement. The following basic information can be regarded as the basis for correctly interpreting the present disclosure. This information is provided for explanatory purposes only and should not be construed in any way as limiting the broad scope of the present disclosure and its potential applications. Although some of the following descriptions may be provided for examples implemented as FET transistors, the embodiments of the present disclosure are equally applicable to the arrangement structures of transistors employing other architectures such as nanoribbon or nanowire transistors.

[0044] As the size of IC devices continues to decrease, the process of breaking the electrical continuity of the metal gate line, commonly referred to as "metal gate cut", so as to decouple the gates of transistors on adjacent active regions in a sufficiently accurate, cost-effective manner and without inadvertently impairing the performance of the IC device, is by no means an easy task. A conventional method includes using a combination of a mask and an etching selective material (i.e., a material etched by a different etchant) to selectively etch the gate electrode material in the region where the metal gate line is to be broken. Selective etching is typically isotropic etching, which means that a given material is etched generally in all directions and may result in a significant expansion of the actual gate cut relative to the desired shape. In extreme cases, the lateral intrusion of such a gate cut may render one or more active regions inoperative.

[0045] Described herein is a transistor arrangement structure fabricated by forming a metal gate cut as an opening (e.g., a trench opening) non-selective to the gate sidewalls in an etching process capable of removing both the gate electrode material and the surrounding dielectric. Compared with the conventional methods of forming a metal gate cut, such an etching process can provide improvements in terms of precision, cost efficiency, and device performance. Additionally, if the opening of the metal gate cut is to be at least partially filled with a conductive material, such a process can be used to provide a power rail (i.e., an electrical interconnection for supplying power and / or signals to one or more transistors of the transistor arrangement structure). Providing the conductive material of the power rail in the opening between active regions instead of above the active regions can provide improvements in reducing the metal line resistance and voltage drop.

[0046] Other embodiments of the present disclosure are based on the recognition that depositing a conductive material within the opening to form a power rail and recessing such material in the portions of the power rail facing the gate stacks of various transistors can provide further improvements in reducing parasitic capacitance. Due to such recessing, the power rail can be referred to as a "buried" power rail. In some embodiments, the BPR can extend all the way through the support structure on which the transistor arrangement structure is provided, e.g., a substrate, a wafer, a chip, or a die, so that an electrical connection to the power rail can be advantageously provided from the back side of the support structure.

[0047] The descriptions provided herein apply to embodiments other than any planar or non-planar FETs, such as nanoribbon transistors, nanowire transistors, or transistors having a cross-section such as a nanoribbon / nanowire transistor but with any geometry (e.g., oval or polygon with rounded corners).

[0048] An IC structure as described herein, particularly an IC structure having one or more transistor arrangements with a low-resistance BPR as described herein, can be used to provide electrical connections for one or more components associated with the IC and / or to provide electrical connections between various such components. In various embodiments, the components associated with the IC include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. The components associated with the IC can include components mounted on the IC or components connected to the IC. The IC can be analog or digital and can be used in a variety of applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC can be used as part of a chipset to perform one or more related functions in a computer.

[0049] For purposes of explanation, some content of this application sets forth specific numbers, materials, and configurations to provide a thorough understanding of illustrative embodiments. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without specific details and / or can be practiced with only some of the aspects described in their entirety. In the description of some embodiments, well-known features are omitted or simplified so as not to make the illustrative embodiments difficult to understand.

[0050] In addition, reference is made to the accompanying drawings, which form a part hereof, and in which embodiments that can be practiced are shown by way of illustration. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure.

[0051] In the drawings, some schematic illustrations of the exemplary structures of the various devices and components described herein may be shown with exact right angles and straight lines, which is only for ease of illustration, and embodiments of these components may be curved, circular, or otherwise irregular in shape, as determined by the manufacturing processes used to fabricate semiconductor device components and which are sometimes inevitable due to such manufacturing processes. Accordingly, it should be understood that such schematic illustrations may not reflect real-life process limitations, which may result in features looking less "ideal" when inspecting any of the structures described herein using, for example, scanning electron microscope (SEM) images or transmission electron microscope (TEM) images. In images of such real structures, possible processing defects may also be visible, e.g., less straight edges of materials, tapered vias or other openings, unintentional rounding of corners, or variations in the thickness of different material layers, accidental screw dislocations, edge dislocations or combined dislocations in crystal regions, and / or accidental dislocation defects of individual atoms or atomic clusters. There may be other defects not listed herein but common in the field of device manufacturing.

[0052] Furthermore, although a certain number of given elements may be shown in some of the drawings, e.g., a certain number of BPRs, a certain number of active regions, a certain number of metal gate cuts, etc., this is only for ease of illustration, and an IC structure having one or more BPRs with low resistance values as described herein may include more or fewer than that number. Further still, the various views shown in some of the drawings are intended to illustrate the relative arrangement of the various elements therein. In other embodiments, various IC structures having one or more BPRs with low resistance values as described herein, or portions thereof, may include other elements or components not shown, e.g., transistor portions, various components that may be in electrical contact with any metal lines, etc. Inspecting the layout and mask data using, for example, an optical microscope, TEM, or SEM and reverse engineering the various components of the device to reconstruct the circuit, and / or inspecting a cross-section of the device using, for example, physical failure analysis (PFA) to detect the shape and location of the various device elements as described herein, will allow determination of the presence of one or more BPRs with low resistance values as described herein.

[0053] The various operations may be described sequentially as a number of discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations necessarily depend on the order. These operations may not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0054] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used in reference to a measurement range, the term "between" includes the end values of the measurement range.

[0055] The description uses the phrase "in an embodiment", which can refer to one or more of the same or different embodiments. Terms such as "comprising", "including", "having", etc. used in connection with the embodiments of the present disclosure are synonyms. The present disclosure may use perspective-based descriptions such as "above", "below", "top", "bottom", and "side" to explain the various features of the drawings, but these terms are for ease of discussion only and do not imply a desired or required orientation. The drawings are not necessarily drawn to scale. Unless otherwise specified, the use of ordinal adjectives "first", "second", "third", etc. to describe common objects only indicates that different instances of similar objects are being referred to and is not intended to imply that the objects so described must be in a given sequence in time, space, ranking, or in any other way.

[0056] In the following detailed description, terms commonly used by those skilled in the art will be used to describe various aspects of the illustrative embodiments to convey the substance of their work to other technicians in the art.

[0057] In another example, if used, the terms "encapsulation" and "IC encapsulation" are synonyms, the terms "die" and "IC die" are also synonyms, the term "insulate" means "electrically insulate", and the term "conduct" means "conduct electricity", unless otherwise specified. Although certain elements may be referred to in the singular in this document, such elements may include multiple sub-elements. For example, "conductive material" may include one or more conductive materials.

[0058] In another example, if used, the terms "oxide", "carbide", "nitride", etc. refer to compounds containing oxygen, carbon, nitrogen, etc. respectively, the term "high-k dielectric" refers to a material having a dielectric constant higher than that of silicon oxide, and the term "low-k dielectric" refers to a material having a dielectric constant lower than that of silicon oxide.

[0059] Furthermore, the term "connect" can be used to describe a direct electrical or magnetic connection between the things being connected without any intermediate device, while the term "couple" can be used to describe a direct electrical or magnetic connection between the things being connected, or an indirect connection through one or more passive or active intermediate devices. The term "circuit" can be used to describe one or more passive and / or active components arranged to cooperate with each other to provide a desired function.

[0060] The terms "substantially", "close to", "approximately", "near", and "about" generally refer to within + / - 20% of a target value in the context of a particular value as described herein or as known in the art. Similarly, terms indicating the orientation of various elements (e.g., "coplanar", "perpendicular", "orthogonal", "parallel", or any other angle between elements) generally refer to within + / - 5 - 20% of a target value in the context of a particular value as described herein or as known in the art.

[0061] Generally, embodiments of the present disclosure may be formed or performed on a support structure such as a semiconductor substrate, which is composed of a semiconductor material system including, for example, an N-type or P-type material system. In one embodiment, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or a silicon-on-insulator substructure. In other embodiments, the semiconductor substrate may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of Group III-V, Group II-VI, or Group IV materials. Although several examples of materials from which the substrate may be formed are described herein, any material that can be used as a basis on which a transistor arrangement structure can be built falls within the spirit and scope of the present disclosure, the transistor arrangement structure having one or more BPRs with self-aligned vias to trench contacts as described herein. In various embodiments, the substrate may include any such substrate material that provides a suitable surface for forming FET transistors.

[0062] As Figure 1 shown, the active region may extend away from the base and may be substantially perpendicular to the base. The active region may include one or more semiconductor materials, e.g., a stack of semiconductor materials, such that the uppermost portion of the active region (i.e., the portion of the active region surrounded by the gate stack) may serve as the channel region of the FET transistor. Thus, as used herein, the term "channel material" of a transistor may refer to this uppermost portion of the active region, or more generally, to any portion of one or more semiconductor materials in which a conductive channel may be formed between the source region and the drain region during operation of the transistor.

[0063] As Figure 4As shown, the STI material can surround the sides of the active region. In various embodiments, the STI material can be a low-k or high-k dielectric, including but not limited to elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Other examples of dielectric materials that can be used in the STI material can include but are not limited to silicon nitride, silicon oxide, silicon dioxide, silicon carbide, carbon-doped silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0064] Above the active region, the gate stack can surround the active region. In particular, the gate dielectric can surround the uppermost portion of the active region, and the gate electrode can surround the gate dielectric.

[0065] The gate electrode can include one or more gate electrode materials, and the choice of gate electrode material can depend on whether the FET is a P-type metal-oxide semiconductor (PMOS) transistor or an N-type metal-oxide semiconductor (NMOS) transistor. For PMOS transistors, gate electrode materials that can be used for different portions of the gate electrode can include but are not limited to ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (such as ruthenium oxide). For NMOS transistors, gate electrode materials that can be used for different portions of the gate electrode include but are not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode can include a stack of multiple gate electrode materials, where zero or more materials of the stack are work function materials and at least one material of the stack is a fill metal layer. For other purposes, other materials / layers can be included beside the gate electrode, such as to act as a diffusion barrier layer or / and an adhesion layer.

[0066] If used, the gate dielectric can include a stack of one or more gate dielectric materials. In some embodiments, the gate dielectric can include one or more high-k dielectric materials. In various embodiments, the high-k dielectric materials of the gate dielectric can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric can include but are not limited to hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process can be performed on the gate dielectric during the manufacture of the FET to improve the quality of the gate dielectric.

[0067] In some embodiments, the gate stack may be surrounded by a dielectric spacer, Figure 4 which is not specifically shown in Figure 4 . The dielectric spacer may be configured to provide separation between different FET transistors that may be provided along a single active region, e.g., different FET transistors provided along the active region, although Figure 4 only the gate stack of one such FET is shown, and to provide separation between the gate stack and source / drain contacts provided on each side of the gate stack. Such a dielectric spacer may include one or more low-k dielectric materials. Examples of low-k dielectric materials that may be used as the dielectric spacer include, but are not limited to, silicon dioxide, carbon-doped oxides, silicon nitride, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, and organosilicate glass. Other examples of low-k dielectric materials that may be used as the dielectric spacer include organic polymers such as polyimide, polynorbornene, benzocyclobutene, perfluorocyclobutane, or polytetrafluoroethylene (PTFE). Other examples of low-k dielectric materials that may be used as the dielectric spacer include silicon-based polymer dielectrics such as hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ). Other examples of low-k materials that may be used in the dielectric spacer include various porous dielectric materials such as porous silicon dioxide or porous carbon-doped silicon dioxide, where large voids or holes are created in the dielectric to reduce the total dielectric constant of the layer, since the voids may have a dielectric constant close to 1. When such a dielectric spacer is used, the lower portion of the active region may be surrounded by STI material, which may include, for example, any of the high-k dielectric materials described herein.

[0068] In some embodiments, the active region may be composed of a semiconductor material system including, for example, an N-type or P-type material system. In some embodiments, the active region may include a high-mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the active region may include a combination of semiconductor materials, where one semiconductor material is used for the channel portion and another material (sometimes referred to as a "blocking material") is used for at least a portion of the sub-active region portion of the active region. In some embodiments, both the sub-active region and the channel portion of the active region are formed of a single-crystal semiconductor such as silicon or germanium. In a first embodiment, both the sub-active region and the channel portion of the active region are formed of a compound semiconductor having a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). The sub-active region may be a binary, ternary, or quaternary III-V compound semiconductor, which is an alloy of two, three, or even four elements from Group III and Group V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth.

[0069] As Figure 2A shown, the IC structure 200 may include a plurality of active regions on a silicon substrate 100, which may extend generally parallel to each other in some embodiments. The IC structure 200 shows an example of four active regions 110, which are labeled as active regions 110-1 to 110-4, but in other embodiments, any other number of two or more active regions 110 may be implemented in the IC structure 200.

[0070] To provide the buried power rail 10, power rail trenches may be provided on the semiconductor IC. For example, power rail trenches may be formed between every two active regions, or power rail trenches may be provided every other two active regions. The power rail trenches may be, for example, the first power rail trench 140-1 and the second power rail trench 140-2. A buried power rail 10 made of a composite material is disposed within the power rail trenches. Taking the first power rail trench 140-1 as an example, a typical power rail trench is as Figure 2E shown, the power rail trench 140-1 may be etched into the silicon substrate 100. An insulating liner layer 150, such as a silicon dioxide oxide layer, is disposed between the power rail trench and the silicon substrate 100 and the insulating layer. A protective layer 160, such as a silicon nitride protective layer, is also deposited on the insulating liner layer 150.

[0071] As shown in the figure, the composite embedded power rail 10 may include a composite structure composed of two metals. Among them, the bottom surface adjacent to the silicon substrate 100 is the first track metal structure 170a formed of the first metal material as a seed metal layer. The seed metal layer is, for example, a first groove structure. The second metal material away from the bottom surface of the silicon substrate 100 forms the second track metal structure 180. The structure at the first end of the second track metal structure 180 is a structure complementary to that of the first guide rail metal structure 170a, and the two jointly fill a part of the power rail groove 140-1. Among them, the first metal material may be tungsten or tungsten doped with titanium nitride (W), and the second metal material is a material different from the first metal structure. For example, it is a material with a resistivity lower than that of the first metal material, such as ruthenium, molybdenum or cobalt, or ruthenium, molybdenum or cobalt doped with titanium nitride. In this embodiment, the first track metal structure 170a is formed in the height direction at the position where the silicon substrate 100 is located, while the second track metal structure 180 extends from the silicon substrate 100 to the insulating filling layer 120 in the height direction.

[0072] In some embodiments, the embedded power rail 10 further includes a third track metal layer 190a formed of a third metal material provided on the second track metal structure 180 as a metal capping layer. The third track metal structure 190a is a second groove structure, and the height of the second groove structure is smaller than that of the first groove structure. The third metal material may be the same metal material as the first metal material, such as tungsten or tungsten doped with titanium nitride, so as to facilitate connection with existing subsequent processing procedures. In some embodiments, the third metal material may be a metal material different from the first metal material.

[0073] The BPR structure in the embodiments of the present application is different from the traditional BPR structure. It adopts a two-layer composite structure of tungsten-low resistivity value metal or a three-layer composite structure of tungsten-low resistivity value metal-tungsten; the selection flexibility of the low resistivity metal in BPR is high, and metals such as ruthenium (Ru), molybdenum (Mo), and cobalt (Co) can be selected, which will not cause pollution to the previous process; under the same size, the overall resistance value of BPR can be effectively reduced. The resistivity here is the resistivity at the same temperature.

[0074] In addition, the process method for forming the BPR structure of the embodiments of the present application is flexible, and the metal can be filled by selective deposition.

[0075] Figures 2A to 2PThe figure shows a process diagram showing the corresponding structure of the main steps of a BPR structure IC according to an embodiment of the present application. In this embodiment, a FET transistor structure is used as the device formed by the BPR structure. In this process, a specific material and processing technology are used for explanation, but it should be understood that the materials and processes used for the BPR structure of the present application are not limited to this. The related materials described above and the processes equivalent to certain processes are also within the scope of the present application.

[0076] As Figure 2A shown, an active region 110 is formed on a silicon substrate 100, such as the first active region 110-1, the second active region 110-2, the third active region 110-3, and the fourth active region 110-4 shown in the figure; each two active regions are separated by a shallow trench, such as the first shallow trench 220-1, the second shallow trench 220-2, and the third shallow trench 220-3. A protective layer 130, such as a silicon nitride protective layer, is formed on the first to fourth active regions respectively. The protective layer 130 covers the surfaces of the four active regions and the shallow trenches between the active regions, and the thickness can be several nanometers, dozens of nanometers, or hundreds of nanometers, which is used to protect the substrate and the active regions and provide a flat surface for subsequent processing.

[0077] Then, an insulating filling material 120, such as silicon oxide, is used to fill the shallow trenches to form shallow trench isolation parts (STI), for example, Figure 2B 、 Figure 2C the first shallow trench isolation part 120-1, the second shallow trench isolation part 120-2, and the third shallow trench isolation part 120-3 shown. Subsequently, the shallow trench isolation parts are planarized, such as by performing CMP, to remove the excess silicon oxide, especially the silicon oxide 120 above the protective layer 130. As Figure 2C shown. At this time, a silicon nitride layer 310 and a photoresist layer hard mask layer 320 can be deposited to pattern the opening positions of the power rail trenches (BPR trenches), as Figure 2D shown, wherein, the first power rail trench opening 301 is formed between the first active region 110-1 and the second active region 110-2, and the second power rail trench opening 302 is formed between the third active region 110-3 and the fourth active region 110-4. After patterning the power rail trench openings 301 and 302, the power rail trenches can be etched to form the first power rail trench 140-1 and the second power rail trench 140-2. The etching depths of the two power rail trenches are determined according to requirements, for example, Figure 2E shown, the etching depths of the two power rail trenches reach half of the position of the silicon substrate 100. The etching process can use wet etching, dry etching, or a combination of both.

[0078] Taking the first power supply rail trench 140-1 as an example, after etching to form the first power supply rail trench, an insulating liner layer 150 can be formed in the first power supply rail trench by atomic layer deposition (ALD), as shown in Figure 2F ; a silicon nitride protection layer 160 is continuously deposited on the insulating liner layer 150 for the growth of the subsequent metal layer, as shown in Figure 2G ; a first tungsten track metal layer 170 is formed on the silicon nitride protection layer 160 by atomic layer deposition (ALD), as shown in Figure 2H ; a substance with better fluidity is then formed on the first tungsten track metal layer 170, such as filling a first organic dielectric layer (ODL) or a photoresist layer, as the first hard mask layer 230, as shown in Figure 2I ; then an etching and retreat operation is performed on the first organic dielectric layer or the photoresist layer to form a first part 230a of the organic dielectric layer on the first tungsten track metal layer 170 so as to shield a first part 170a of the first tungsten track metal layer below it, as shown in Figure 2J ; other parts of the first tungsten track metal layer except the first part 170a that are not covered by the first organic dielectric layer 230a are removed, as shown in Figure 2K ; then the first part 230a of the organic dielectric layer is removed to leave the first part 170a of the grooved first tungsten track metal layer 170 at the bottom of the first metal track trench 140-1. The first part 170a of the first tungsten track metal layer is the first track metal structure as the seed layer for the subsequent filling of the BPR metal layer, as shown in Figure 2L .

[0079] Figure 2M shows that after filling the metal track trench by selective deposition, a second track metal structure 180 is formed. The metal of the second track metal structure adopted can be, for example, ruthenium, molybdenum or cobalt, or ruthenium, molybdenum or cobalt doped with titanium nitride and other metals with resistivity lower than tungsten. The filling height of the second track metal structure 180 can be flexibly controlled according to needs, for example, in the direction towards the top surface of the substrate, that is, the position of the active region is reached in the extending direction of the active region. Then a silicon oxide material 250 is deposited to fill the metal track trench, as shown in Figure 2N ; and planarization is performed to reach the position of the insulating liner layer 130, as shown in Figure 2O ; then an STI recess treatment is performed on the formed structure to remove part of the silicon nitride protection layer 160 material in the shallow trench isolation part to form a recess in the area of each shallow trench isolation part. For example, the heights of the first shallow trench isolation part 120-1, the second shallow trench isolation part 120-2, and the third shallow trench isolation part 120-3 shown in Figure 2P are all reduced to a predetermined height. In this step, the parts of the shallow trench isolation part that define the first metal track trench and the second metal track trench are also removed simultaneously to form a recess.

[0080] The subsequent process is the same as the standard BPR process.

[0081] Figures 2M1 to 2M5 For another embodiment of the present application, in this embodiment, the BPR in the metal track trench includes a three-layer composite metal structure. Among them, Figures 2M1 to 2M5 The process of Figure 2M begins to develop. As Figure 2M1 shown, on the Figure 2M formed structure, a third track metal layer 190 is formed as a metal capping layer. For example, using atomic layer deposition process to deposit a tungsten metal layer as a metal capping layer on the Figure 2M structure. It should be understood that the metal used for the metal capping layer here can also be other metals, such as other metals compatible with the second track metal layer. Then, a material layer with better fluidity is deposited on the metal capping layer, such as a second organic dielectric layer or a photoresist layer 240, as the second hard mask layer, as Figure 2M2 shown; then, an etch-back process is used to remove the part of the second organic dielectric layer or the photoresist layer 240 except for the first part 240a within the metal track trench, as Figure 2M3 shown; thereafter, the metal capping layer of the exposed tungsten metal is removed, leaving only the part 190a of the third track metal layer covered by the first part 240a of the second organic dielectric layer or the photoresist layer 240 as the third track metal structure, as Figure 2M4 shown; thereafter, the first part 240a of the second organic dielectric layer or the photoresist layer 240 is removed, as Figure 2M5 shown; the subsequent process is the same as the previous embodiment, such as the process shown in Figures 2N to 2P and the BPR process after Figure 2P .

[0082] As Figure 3 shown is a comparison chart of the resistivity of molybdenum doped with titanium nitride, ruthenium doped with titanium nitride, and tungsten doped with titanium nitride. Due to the resistivity difference reaching 30%, it can be deduced from the figure that the resistance value of the composite buried power supply track composed of 84 nm molybdenum doped with titanium nitride, 72 nm ruthenium doped with titanium nitride, and 132 nm tungsten doped with titanium nitride is significantly lower than that of the buried power supply track of tungsten doped with titanium nitride of the same size.

[0083] The above exemplary manufacturing method may include Figures 2A to 2POther operations not specifically shown, such as various cleaning or planarization operations known in the art. For example, in some embodiments, the support structure and various other material layers subsequently deposited thereon may be cleaned before, after, or during any process of the methods described herein, for example to remove oxides, surface-bound organic and metal contaminants, and subsurface contaminants. In some embodiments, cleaning may be performed using, for example, chemical solutions (such as peroxides), and / or by utilizing ultraviolet (UV) radiation in combination with ozone, and / or by oxidizing the surface (such as using thermal oxidation) and then removing the oxide (such as using hydrofluoric acid (HF)). In another example, the arrangements / devices described herein may be planarized before, after, or during any process of the methods described herein, for example, to remove overlying layers or excess material. In some embodiments, planarization may be performed using wet or dry planarization processes, for example, planarization is chemical mechanical planarization (CMP), which may be understood as a process of removing the overlying layer and planarizing the surface using a polishing surface, abrasive, and slurry.

[0084] The foregoing description of the illustrated embodiments of the present disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific embodiments and examples of the disclosure have been described herein for purposes of illustration, various equivalent modifications will be apparent to those skilled in the relevant art within the scope of the disclosure. These modifications can be made to the disclosure in accordance with the foregoing specific embodiments.

Claims

1. A buried metal wire structure, which can be used for power distribution of semiconductor devices, is characterized in that: The embedded metal wire structure includes a composite metal structure formed in the metal wire trench. Among them, the composite metal structure includes a first track metal structure near the bottom of the metal wire trench and a second track metal structure away from the bottom of the metal wire trench. The material forming the first track metal structure is a first metal material; the material forming the second track metal layer is a second metal material with a resistivity lower than that of the first metal material.

2. The embedded metal wire structure according to claim 1, wherein: The first track metal structure is a metal thin film with a groove structure, and one end of the second track metal structure is a structure complementary to the groove structure.

3. The embedded metal wire structure according to claim 1, wherein: The first material is doped or undoped tungsten material; the second material is at least one of doped or undoped ruthenium, molybdenum or cobalt materials.

4. The method according to claim 3, wherein: The composite metal structure further includes a third track metal structure further away from the bottom of the metal track trench, and the material forming the third track metal structure is a third metal material different from the second metal material.

5. The embedded metal wire structure according to claim 4, wherein: The third metal material is the same as the first metal material, or the third material is different from the first metal material.

6. The embedded metal wire structure according to claim 5, wherein: The third metal material is a metal material compatible with the previous process.

7. The embedded metal wire structure according to claim 6, wherein: The third metal material is doped or undoped tungsten.

8. A method for forming the embedded metal wire structure according to any one of the above claims, characterized in that Including steps: Form a plurality of active regions separated by isolation structures on the substrate; Etch the isolation structure to form a metal wire trench; Form an insulating inner lining layer in the metal wire trench; Deposit a protective layer on the insulating inner lining layer; Form a first track metal layer of the first metal material on the protective layer; Form a first hard mask layer on the first track metal layer to shield the bottom of the first track metal layer; Remove the first track metal layer not shielded by the hard mask layer, and then remove the first hard mask layer to obtain the grooved first track metal structure; Selectively deposit a second metal material in the metal wire track trench to form the second track metal layer on the first track metal structure, and the bottom of the second track metal structure is complementary to the first track metal structure; then deposit an oxide layer to fill the metal track trench and perform planarization to reach the position of the insulating inner lining layer.

9. The method according to claim 8, wherein: Then perform an isolation recess treatment on the formed structure to remove a part of the isolation material in the isolation part to form a recess in the area where the isolation part is located.

10. A method for forming the embedded metal wire structure according to any one of claims 5 to 7 above, characterized in that, Including steps: Form a plurality of active regions on the substrate; Form a power supply guide groove between the active regions; Form an insulating inner lining layer in the power supply guide groove; Deposit a protective layer on the insulating inner lining layer; Form a first track metal layer of the first metal material on the protective layer; Form a first hard mask layer on the first track metal layer; Perform a back-etching operation on the first hard mask layer to form a first part of the first hard mask layer on the first part of the first track metal layer at the bottom of the metal wire trench to shield the first part of the first track metal layer; Remove other parts of the first track metal layer other than the first part covered by the first part of the hard mask layer, and then remove the first part of the first hard mask layer; The metal track trench is filled by selective deposition to form a second track metal layer of a second material; A third track metal layer of a third metal material is formed on the second track metal structure as a metal capping layer; A second hard mask layer is formed on the third track metal layer; By using an etching back process, a part of the second hard mask layer other than the first part of the second hard mask layer within the metal track trench is removed, and then the exposed third track metal layer is removed, so as to leave a part of the third track metal layer covered by the first part of the second hard mask layer to form the third track metal structure; The first part of the second hard mask layer is removed; and An oxide layer is filled in the metal track trench, and planarization is performed to reach the position of the oxide layer liner; The formed structure is subjected to a shallow trench isolation recess process to remove a part of the isolation material in the shallow trench isolation part to form a recess in the area of the shallow trench isolation part.

11. A semiconductor device, which includes the buried metal wire structure of claims 1 to 5.

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