Semiconductor device

Abstract

A semiconductor device includes a substrate, an upper layer, and a lower layer. The upper layer is arranged above the substrate and comprises an upper electric pattern and an alignment mark pattern which is electrically insulated from the upper electric pattern. The lower layer is arranged between the substrate and the upper layer and comprises a lower electric pattern and a dummy pattern which is electrically insulated from the lower electric pattern, the alignment mark pattern and the dummy pattern are overlapped from a top view angle, an optical contrast is formed between the alignment mark pattern and the dummy pattern, and the optical contrast is equal to or greater than 50.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an alignment mark pattern. Background Art

[0002] Semiconductor devices formed on a semiconductor substrate are generally assembled to connect to external devices and at the same time encapsulated to protect these semiconductor devices from the external environment. In particular, semiconductor devices may have a pad electrode layer for use as input / output terminals when connecting to external devices and alignment marks for use as alignment keys when assembling semiconductor devices.

[0003] Specifically, an alignment mark pattern is formed above the semiconductor substrate. Generally, the alignment mark pattern is formed within an alignment area of the device, which is formed by an insulating layer for insulation. An optical alignment device senses the contrast between the alignment area (e.g., the area surrounding the alignment mark pattern) and a part of the alignment mark pattern and aligns the semiconductor device through the contrast between the alignment area and the alignment mark pattern. However, if there are other circuit layers extending to the area directly below the alignment mark pattern under the alignment mark pattern, the contrast between the alignment area and the alignment mark pattern may be reduced, thereby generating alignment errors in these semiconductor devices. Therefore, a circuit clearance area extends from the alignment area all the way to the substrate, and the clearance area does not allow circuit wiring, but such a configuration seriously wastes the space of semiconductor devices. Summary of the Invention

[0004] Accordingly, the present invention relates to a semiconductor device having an alignment mark pattern, which can improve the space utilization rate of semiconductor devices and the design flexibility of circuit wiring.

[0005] The present invention provides a semiconductor device, including a substrate, an upper layer, and a lower layer. The upper layer is disposed above the substrate and includes an upper electrical pattern and an alignment mark pattern electrically insulated from the upper electrical pattern. The lower layer is disposed between the substrate and the upper layer and includes a lower electrical pattern and a dummy pattern electrically insulated from the lower electrical pattern, wherein, from a top-down perspective, the alignment mark pattern overlaps with the dummy pattern, there is an optical contrast between the alignment mark pattern and the dummy pattern, and the optical contrast is equal to or greater than 50.

[0006] According to an embodiment of the present invention, the upper layer includes a clearance area surrounding the alignment mark pattern, and the upper electrical pattern is disposed outside the clearance area.

[0007] According to an embodiment of the present invention, from a top-down perspective, the dummy pattern completely fills the clearance area.

[0008] According to an embodiment of the present invention, the upper electrical pattern is spaced apart from the clearance area by a gap, and the gap is equal to or greater than 5 micrometers.

[0009] According to an embodiment of the present invention, the semiconductor device further includes an interconnect structure disposed between the lower layer and the substrate, and when viewed from a top-down perspective, the interconnect circuits of a part of the interconnect structure overlap with the dummy pattern.

[0010] According to an embodiment of the present invention, the interconnect structure is electrically connected to the lower electrical pattern and electrically insulated from the dummy pattern.

[0011] According to an embodiment of the present invention, the upper electrical pattern includes pads for bonding electrical connectors, and the material of the upper layer includes aluminum or aluminum containing titanium nitride.

[0012] According to an embodiment of the present invention, the material of the lower layer includes copper.

[0013] According to an embodiment of the present invention, the upper electrical pattern includes electrical connectors, and the material of the upper layer includes gold or a multi-layer of copper / nickel / gold.

[0014] According to an embodiment of the present invention, the material of the lower layer includes aluminum.

[0015] According to an embodiment of the present invention, the alignment mark pattern is electrically insulated from the dummy pattern.

[0016] According to an embodiment of the present invention, the optical contrast is the difference between the gray-scale value of the dummy pattern and the gray-scale value of the alignment mark pattern.

[0017] According to an embodiment of the present invention, the ratio of the gray-scale value of the dummy pattern to the gray-scale value of the alignment mark pattern is equal to or greater than 1.3.

[0018] The present invention provides a semiconductor device, including a substrate, an upper layer, a lower layer, and an interconnect structure. The upper layer is disposed above the substrate and includes an upper electrical pattern and an alignment mark pattern electrically insulated from the upper electrical pattern. The lower layer is disposed between the substrate and the upper layer and includes a lower electrical pattern and a dummy pad electrically insulated from the lower electrical pattern, wherein, when viewed from a top-down perspective, the alignment mark pattern overlaps with the dummy pad. The interconnect structure is disposed between the lower layer and the substrate, wherein, when viewed from a top-down perspective, the interconnect circuits of a part of the interconnect structure overlap with the dummy pattern.

[0019] According to an embodiment of the present invention, there is an optical contrast between the alignment mark pattern and the dummy pad, and the optical contrast is equal to or greater than 50.

[0020] According to an embodiment of the present invention, when viewed from a top-down perspective, a part of the interconnect circuit overlaps with a clearance area.

[0021] Based on the above, the semiconductor device of the present invention is provided with a dummy pattern in the lower layer below the alignment mark pattern in the upper layer. Thus, the materials of the dummy pattern and the alignment mark pattern are selected in pairs so that the alignment mark pattern has an optical contrast with respect to the dummy pattern, and the optical contrast is equal to or greater than 50 and the alignment mark pattern can thus be recognized by the camera. Since the dummy pattern is disposed between the alignment mark pattern and the interconnect structure, from a top-down perspective, since the dummy pattern blocks the underlying interconnect circuits and provides sufficient optical contrast for the camera to recognize the alignment mark pattern, the interconnect circuits of some of the interconnect structures can overlap with the dummy pattern. Thus, the space utilization rate of the semiconductor device and the design flexibility of circuit routing are greatly increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, are used to explain the principles of the present invention.

[0023] Figure 1 is a cross-sectional schematic view of a semiconductor device according to some exemplary embodiments of the present invention;

[0024] Figure 2 is a top-down schematic view of the upper layer of a semiconductor device according to some exemplary embodiments of the present invention;

[0025] Figure 3 is a top-down schematic view of the lower layer of a semiconductor device according to some exemplary embodiments of the present invention;

[0026] Figure 4 is a top-down schematic view of the interconnect structure of a semiconductor device according to some exemplary embodiments of the present invention;

[0027] Figure 5 is a top-down schematic view of the upper and lower layers of a semiconductor device according to some exemplary embodiments of the present invention;

[0028] Figure 6 is a top-down schematic view of a semiconductor device according to some exemplary embodiments of the present invention;

[0029] Figure 7 is a cross-sectional schematic view of a semiconductor device according to another exemplary embodiment of the present invention;

[0030] Figure 8 is a top-down schematic view of a semiconductor device according to another exemplary embodiment of the present invention.

[0031] DESCRIPTION OF REFERENCE NUMERALS

[0032] 100, 100a: Semiconductor device

[0033] 110: Substrate

[0034] 120: Upper layer

[0035] 120a: Lower layer

[0036] 122: Upper electrical pattern

[0037] 122a: Pad (lower electrical pattern)

[0038] 1221, 1221a, 1321: dummy grid

[0039] 123: Channel

[0040] 124: Alignment mark pattern

[0041] 124a: Dummy pattern

[0042] 130: Lower layer

[0043] 130a: Interconnection structure

[0044] 132: Lower electrical pattern

[0045] 132a: Interconnection circuit

[0046] 134: Dummy pattern

[0047] 140: Interconnection structure

[0048] 142: Interconnection circuit

[0049] 144: Channel

[0050] 150: Electrical connector

[0051] 150a: Upper layer

[0052] 152a: Upper electrical pattern

[0053] 154a: Alignment mark pattern

[0054] 160: Passivation layer

[0055] d1: Gap

[0056] OP1: Opening

[0057] R1: Integrated circuit area

[0058] R2: Alignment mark area Detailed implementation mode

[0059] Reference will now be made in detail to some embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts. The terms such as "on", "above", "below", "front", "rear", "left" and "right" used herein are for the purpose of describing the directions in the drawings only and are not intended to limit the present invention. Additionally, in the discussions and claims herein, the term "on" is used with respect to two materials, one "on" the other, which means at least some contact between the materials, while "above" and "overlying" mean adjacent to the materials, but there may be one or more additional intervening materials such that physical contact is possible but not necessary. Neither "on" nor "above" implies any directionality as used herein.

[0060] Unless otherwise limited, the terms "disposed", "connected", "coupled" and "mounted" and their variants herein are used in a broad sense and encompass direct and indirect connections, couplings and mountings. Similarly, the terms "facing", "faces" and their variants herein are used in a broad sense and encompass direct and indirect facing, and "adjacent to" and its variants herein are used in a broad sense and encompass direct and indirect "adjacent to". Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0061] Figure 1 is a cross-sectional schematic view of a semiconductor device according to some exemplary embodiments of the present invention. Refer to Figure 1, in some embodiments, the semiconductor device 100 includes a substrate 110, an upper layer 120 disposed above the substrate 110, and a lower layer 130 disposed between the substrate 110 and the upper layer 120. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar component, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 110 may be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or a similar component. The insulating layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 110 may include silicon, germanium, compound semiconductors having silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide, or a combination of the above.

[0062] In some embodiments, a device layer (not shown) may be formed above the substrate 110. In some embodiments, the device layer may include an elemental semiconductor having silicon and / or germanium crystals; compound semiconductors having silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or a combination of the above. The device layer may include a plurality of doped regions according to design requirements (e.g., p-type doped wells, n-type doped wells). The doped regions include a plurality of active regions, such as regions configured for N-type metal oxide semiconductor transistors (NMOS) and P-type metal oxide semiconductor transistors (PMOS). However, the present invention is not limited thereto.

[0063] Figure 2 is a top view schematic diagram of the upper layer of a semiconductor device according to some exemplary embodiments of the present invention. Refer to Figure 1 and Figure 2, in some embodiments, the upper layer 120 is disposed above the substrate 110 and includes an upper electrical pattern 122 and an alignment mark pattern 124 that is electrically insulated from the upper electrical pattern 122. In this embodiment, the upper layer 120 is a metal layer, and the upper electrical pattern 122 includes a plurality of pads for bonding to the electrical connector 150. That is, the alignment mark pattern 124 and the upper electrical pattern 122 are formed in the same layer (horizontally) simultaneously through a patterning process, such as a lithography process or a similar process. Thus, the material of the upper layer 120 may include aluminum (Al) or aluminum containing titanium nitride (TiN), which is an aluminum pattern layer covered with an intermediate conductive layer such as a titanium nitride metal alloy. In other embodiments, the material of the alignment mark pattern 124 may include aluminum, copper, copper / nickel / gold (Cu / Ni / Au), gold, or similar materials.

[0064] Specifically, the upper layer 120 includes an integrated circuit region R1 (such as the integrated circuit region R1 shown in Figure 1 and Figure 2 ), an integrated circuit (including the upper electrical pattern 122) is formed within the integrated circuit region R1, and an alignment mark region R2 within which the alignment mark pattern 124 for alignment and positioning is formed. The alignment and positioning are, for example, during the process of mounting the semiconductor device 100 on the mounting substrate or a similar process. In this embodiment, a plurality of metal layers (including the upper electrical pattern 122, the lower electrical pattern 132, the interconnect circuit 142, etc.) are formed across multiple layers, and the alignment mark pattern 124 is formed in the same layer as the topmost metal layer among the metal layers. In certain embodiments, the upper layer 120 may further include a plurality of dummy grids 1221 for reducing stress concentration problems, which are electrically insulated from the upper electrical pattern 122 and the alignment mark pattern 124.

[0065] Referring to Figure 2 , in some embodiments, the upper layer 120 includes a clearance area, which is the part of the alignment mark region R2 that surrounds the alignment mark pattern 124, and the upper electrical pattern 122 is disposed outside the clearance area to ensure that the contrast between the alignment mark pattern 124 and the background is not interfered with by the upper electrical pattern 122. In one embodiment, the upper electrical pattern 122 is spaced apart from the clearance area of the alignment mark region R2 by a gap d1. In this embodiment, the gap d1 may be substantially equal to or greater than 5 microns. In this embodiment, the alignment mark pattern 124 is a cross-shaped mark formed at the center of the alignment mark region R2. The alignment mark region R2 may be a square region with dimensions, for example, 120 microns x 120 microns. However, the present invention is not limited thereto. The alignment mark pattern 124 may also be of various shapes, such as a deformation of the cross-shaped mark, a triangle, a circle, an irregular shape, or other suitable shapes. The alignment mark pattern 124 for aligning the semiconductor device 100 may use any shape.

[0066] Return to Figure 1 Referring back, in some embodiments, a passivation layer 160 is formed over the upper layer 120, and the passivation layer 160 has at least one opening OP1 that exposes at least a portion of the upper electrical pattern 122. In the present embodiment, the passivation layer 160 is made of a transparent material and covers the alignment mark pattern 124. However, in other embodiments, the passivation layer 160 may be non-transparent, for example, light-impermeable, and has an opening that exposes the alignment mark region R2 for subsequent alignment processes. The passivation layer 160 includes silicon oxide, silicon nitride, or any suitable dielectric material. In some embodiments, at least one electrical connector 150 is formed over the passivation layer 160 and is bonded to the upper electrical pattern 122 through the opening OP1. The electrical connector 150 may include conductive bumps having gold, multi-layered copper / nickel / gold (Cu / Ni / Au), or similar materials. In some embodiments, an under bump metal (UBM) layer may be formed within the opening 150 and between the upper electrical pattern 122 and the electrical connector 150.

[0067] Figure 3 is a top view schematic diagram of a lower layer of a semiconductor device according to some exemplary embodiments of the present invention. Referring back Figure 1 and Figure 3 , the lower layer 130 is disposed between the substrate 110 and the upper layer 120, and includes a lower electrical pattern 132 within the integrated circuit region R1 (such as the integrated circuit region R1 shown in Figure 1 and Figure 2 ) and dummy patterns 134 within the alignment mark region R2, which are electrically insulated from the lower electrical pattern 132. In some embodiments, the lower electrical pattern 132 is spaced apart from the dummy patterns 134 by a gap d1. In the present embodiment, the gap d1 may be substantially equal to or greater than 5 microns. In some embodiments, the dummy patterns 134 within the alignment mark region R2 may be dummy pads, which are solid patterns shown in Figure 2 . In the present embodiment, the lower layer 130 is the topmost metal layer in the redistribution structure below the upper layer 120, such as a pad layer. In some embodiments, the lower layer 130 may further include a plurality of dummy grids 1321 for reducing stress concentration problems, which are electrically insulated from the lower electrical pattern 132 and the alignment mark pattern 134. In the present embodiment, the dummy grids 1321 may be aligned with the dummy grids 1221, but in other embodiments, the dummy grids 1321 may not be aligned with the dummy grids 1221.

[0068] Figure 5 is a top view schematic diagram of the upper and lower layers of a semiconductor device according to some exemplary embodiments of the present invention. Referring back Figure 1 and Figure 5, in some embodiments, when viewed from the top-down perspective shown in Figure 5 , the alignment mark pattern 124 of the upper layer 120 overlaps with the dummy pattern 134 of the lower layer 130. In this embodiment, when viewed from the top-down perspective, the dummy pattern 134 completely fills the alignment mark region R2 (including the clearance region surrounding the alignment mark pattern 124). In some embodiments, the alignment mark pattern 124 and the dummy pattern 134 are electrically insulated from each other and there is no connecting channel therebetween, while as shown in Figure 1 , the upper electrical pattern 122 is electrically connected to the lower electrical pattern 132 through the channel 123.

[0069] In this embodiment, when viewed from the top-down perspective, the dummy pattern 134 that fills the alignment mark region R2 is a square pattern, and the alignment mark pattern 124 is a cross-shaped mark located at the center of the dummy pattern 134. The material of the dummy pattern 134 is different from the material of the alignment mark pattern 124. More specifically, the materials of the dummy pattern 134 and the alignment mark pattern 124 are selected in pairs so as to have an optical contrast between the alignment mark pattern 124 and the dummy pattern 134, and the optical contrast is substantially equal to or greater than 50. Thus, when the alignment mark region R2 is irradiated with light for alignment, the reflectance of the light reflected from the dummy pattern 134 is different from the reflectance of the light reflected from the alignment mark pattern 124. Since the reflectance of the light reflected from the dummy pattern 134 is different from the reflectance of the light reflected from the alignment mark pattern 124, an optical contrast between the alignment mark pattern 124 and the dummy pattern 134 is generated, and the alignment mark pattern 124 can thus be recognized by the camera. In some embodiments, the reflectance of the material of the alignment mark pattern 124 is selected to be lower than the reflectance of the material of the dummy pattern 134, and thus, the darker alignment mark pattern 124 appears on the brighter dummy pattern 134, enabling the alignment mark pattern 124 to be recognized.

[0070] By definition, the optical contrast can refer to the difference between the gray scale value of the dummy pattern 134 and the gray scale value of the alignment mark pattern 124, which can be obtained by analyzing the image captured by the camera. In other words, the difference in gray scale values represents the optical contrast between the alignment mark pattern 124 and the dummy pattern 134. In some embodiments, the materials of the dummy pattern 134 and the alignment mark pattern 124 are selected in pairs so that the ratio of the gray scale value of the dummy pattern 134 to the gray scale value of the alignment mark pattern 124 is substantially equal to or greater than 1.3.

[0071] For example, the material of the upper layer 120 (including the alignment mark pattern 124) includes aluminum (Al) or aluminum containing titanium nitride (TiN), which is an aluminum pattern layer covered with an intermediate conductive layer such as a titanium nitride metal alloy. Thus, the material of the lower layer 130 (including the dummy pattern 134) can be selected as silicon (Si). In other embodiments, when the material of the alignment mark pattern 124 includes aluminum containing titanium nitride (TiN), the material of the dummy pattern 134 can be selected as copper or a similar material. The materials of the dummy pattern 134 and the alignment mark pattern 124 are selected in pairs so that the difference between the gray scale values of the dummy pattern 134 and the alignment mark pattern 124 can be recognized by the camera for alignment.

[0072] Figure 4 is a top view schematic diagram of an interconnect structure of a semiconductor device according to some exemplary embodiments of the present invention. Figure 6 is a top view schematic diagram of a semiconductor device according to some exemplary embodiments of the present invention. Refer to Figure 1 、 Figure 4 and Figure 6 , in some embodiments, the semiconductor device 100 further includes an interconnect structure 140 disposed between the lower layer 130 and the substrate 110. As Figure 1 shown, the interconnect structure 140 is electrically connected to the lower electrical pattern 132 through at least one channel 144 and is electrically insulated from the dummy pattern 134. For example, there is no channel connecting the interconnect structure 140 and the dummy pattern 134.

[0073] In some embodiments, the interconnect structure 140 includes a plurality of interconnect circuits 142 and a plurality of channels 144 in one or more inter-metal dielectric (IMD) layers. In some embodiments, the interconnect structure 140 can be a back end of line (BEOL) intermediate structure above the device layer (including transistors). Since the dummy pattern 134 is configured to be between the alignment mark pattern 124 and the interconnect structure 140, some of the interconnect circuits 142 of the interconnect structure 140 can extend to the areas directly below the alignment mark pattern 124 and the dummy pattern 134 without interfering with the camera's recognition of the alignment mark pattern 124. In other words, from Figure 6From the top-down view shown, the interconnect circuit 142 of the partial interconnect structure 140 may overlap with the dummy pattern 134 and include the alignment mark region R2 that surrounds the clearance region of the alignment mark pattern 124. Thus, since the dummy pattern 134 blocks the underlying interconnect circuit 142 and provides sufficient optical contrast for the camera to recognize the alignment mark pattern 124, the circuit wiring of the interconnect circuit 142 of the interconnect structure 140 does not need to avoid the region directly below the alignment mark region R2. Thus, the space utilization rate of the semiconductor device 100 and the design flexibility of the circuit wiring are increased significantly.

[0074] Figure 7 is a cross-sectional schematic diagram of a semiconductor device according to another exemplary embodiment of the present invention. Figure 8 is a top-down schematic diagram of a semiconductor device according to another exemplary embodiment of the present invention. It should be noted that the semiconductor device 100a shown in Figure 7 and Figure 8 includes a plurality of features that are the same as or similar to those of the semiconductor device disclosed in the previous embodiments. For the sake of clear and simple representation, the detailed description of the same or similar features is omitted, and the same or similar reference numerals denote the same or similar components.

[0075] Referring to Figure 7 and Figure 8 , in the present embodiment, the upper layer 150a including the alignment mark pattern 154a is an electrical connection layer. That is to say, the upper layer 150a includes an upper electrical pattern 152a, which includes electrical connectors, and the alignment mark pattern 154a is electrically insulated from the upper electrical pattern 152a. In other words, the alignment mark pattern 154a and the upper electrical pattern 152a (electrical connectors) of the present embodiment are formed simultaneously in the same layer (horizontally) by a patterning process, such as a photolithography process or a similar process. Thus, the material of the upper layer 150a may include conductive bumps made of gold, multi-layer copper / nickel / gold (Cu / Ni / Au), or similar materials. The material of the alignment mark pattern 154a may actually be a metal, such as copper / nickel / silver tin (Cu / Ni / SnAg) or nickel / palladium / gold (Ni / Pd / Au).

[0076] Specifically, the upper layer 150a includes an integrated circuit region R1 (for example, as shown in Figure 1 and Figure 2In the integrated circuit region R1), a column of electrical connectors 152a (illustrated as one electrical connector 152a, but not limited thereto) is formed within the integrated circuit region R1), and an alignment mark region R2, and an alignment mark pattern 154a for alignment and positioning is formed within the alignment mark region R2). The alignment and positioning is, for example, in the process of mounting the semiconductor device 100a on the mounting substrate or a similar process. In the present embodiment, the alignment mark pattern 154a and the electrical connector 152a are formed on the same layer above the interconnect structure.

[0077] In some embodiments, the upper layer 150a includes a clearance area, which is the part of the alignment mark region R2 surrounding the alignment mark pattern 154a, and the upper electrical pattern 152a is an electrical connector and is disposed outside the clearance area to ensure that the contrast between the alignment mark pattern 154a and the background is not interfered by the upper electrical pattern 152a. In some embodiments, a passivation layer 160 is formed under the upper layer 150a, and the passivation layer 160 has at least one opening OP1, and the opening OP1 is connected to the pad 122a, and the pad 122a is referred to as a lower electrical pattern in the present embodiment. In the present embodiment, the passivation layer 160 completely covers the dummy pattern 124a under the alignment mark pattern 154a, so that the passivation layer 160 is interposed between the alignment mark pattern 154a and the dummy pattern 124a for electrical insulation. In the present embodiment, the alignment mark pattern 154a is a cross-shaped mark, which is formed at the center of the alignment mark region R2. The alignment mark region R2 may be a square region with a size of, for example, 120 microns x 120 microns. However, the present invention is not limited thereto. The alignment mark pattern 154a may also be in various shapes, such as a deformation of a cross-shaped mark, a triangle, a circle, an irregular shape, or other suitable shapes. The alignment mark pattern 154a for aligning the semiconductor device 100a may use any shape.

[0078] In some embodiments, the lower layer 120a including the dummy pattern 124a is a pad layer. That is, the lower layer 120a includes a lower electrical pattern 122a, which includes a column of pads, and the dummy pattern 124a is electrically insulated from the lower electrical pattern 122a. In other words, the dummy pattern 124a and the lower electrical pattern 122a (pads) of the present embodiment are simultaneously formed on the same layer (horizontally) by a patterning process, such as a photolithography process or a similar process.

[0079] The lower layer 120a is disposed between the substrate 110 and the upper layer 150a. In some embodiments, the lower electrical pattern 122a is separated from the dummy pattern 124a by a gap. In some embodiments, the dummy pattern 124a may be a dummy pad, which is shown in Figure 8The entity patterns in it. In some embodiments, the lower layer 120a may further include a plurality of dummy grids 1221a for reducing stress concentration problems, which are electrically insulated from the lower electrical pattern 122a and the dummy pattern 124a.

[0080] In some embodiments, from Figure 8 the top-down perspective shown, the alignment mark pattern 154a of the upper layer 150a overlaps with the dummy pattern 124a. In this embodiment, from the top-down view, the dummy pattern 124a completely fills the alignment mark region R2 (including the clearance region surrounding the alignment mark pattern 154a). In some embodiments, the alignment mark pattern 154a and the dummy pattern 124a are electrically insulated and there is no interconnected channel between them, while as Figure 7 shown, the upper electrical pattern 152a (electrical connector) is electrically connected to the lower electrical pattern (pad) 122a.

[0081] In this embodiment, the material of the dummy pattern 124a is different from the material of the alignment mark pattern 154a. More specifically, the materials of the dummy pattern 124a and the alignment mark pattern 154a are selected in pairs such that there is an optical contrast between the alignment mark pattern 154a and the dummy pattern 124a, and the optical contrast is substantially equal to or greater than 50. That is, the difference (difference value) between the gray-scale value of the alignment mark pattern 154a and the gray-scale value of the dummy pattern 124a is substantially equal to or greater than 50. Thus, when the alignment mark region R2 is irradiated with light for alignment, the reflectance of the light reflected from the dummy pattern 124a is different from the reflectance of the light reflected from the alignment mark pattern 154a. Since the reflectance of the light reflected from the dummy pattern 124a is different from the reflectance of the light reflected from the alignment mark pattern 154a, an optical contrast between the dummy pattern 124a and the alignment mark pattern 154a is generated, and the alignment mark pattern 154a can thus be recognized by the camera. In some embodiments, the reflectance of the material of the alignment mark pattern 154a is selected to be lower than the reflectance of the material of the dummy pattern 124a, and thus, the darker alignment mark pattern 154a appears on the brighter dummy pattern 124a, making the alignment mark pattern 154a recognizable. In some embodiments, the materials of the dummy pattern 124a and the alignment mark pattern 154a are selected in pairs such that the ratio of the gray-scale value of the dummy pattern 124a to the gray-scale value of the alignment mark pattern 154a is substantially equal to or greater than 1.3.

[0082] For example, the material of the upper layer 150a (including the alignment mark pattern 154a and the electrical connector 152a) includes gold, multi-layered copper / nickel / gold (Cu / Ni / Au), or similar materials. Thus, the lower layer 120a (including the dummy pattern 124a and the pad 122a) can be selected as aluminum (Al) or similar materials.

[0083] Accordingly, the semiconductor device 100a includes interconnect structures 130a, 140 disposed between the lower layer 120a and the substrate 110. As Figure 7 shown, the interconnect structure 130a is electrically connected to the lower electrical pattern 122a through at least one channel and is electrically insulated from the dummy pattern 124a. For example, there is no channel connecting the interconnect structure 130a and the dummy pattern 124a.

[0084] In some embodiments, the interconnect structures 130a, 140 include a plurality of interconnect circuits 132a, 142 and a plurality of channels in one or more intermetal dielectric layers. Since the dummy pattern 124a is configured to be between the alignment mark pattern 154a and the interconnect structures 130a, 140, some of the interconnect circuits 132a, 142 of the interconnect structures 130a, 140 can extend to the regions directly below the alignment mark pattern 154a and the dummy pattern 124a without interfering with the camera's recognition of the alignment mark pattern 154a. In other words, from Figure 8 the top-down perspective shown, some of the interconnect circuits 132a, 142 of the interconnect structures 130a, 140 can overlap with the dummy pattern 124a and the alignment mark region R2 including the clearance region surrounding the alignment mark pattern 154a.

[0085] Based on the above discussion, it can be seen that the present invention provides various advantages. However, it should be understood that not all advantages must be discussed herein, and other embodiments may provide different advantages, and specific advantages are not required for all embodiments.

[0086] In summary, the semiconductor device of the present invention has a lower dummy pattern below the alignment mark pattern on the upper layer. Accordingly, the materials of the dummy pattern and the alignment mark pattern are selected in pairs such that the alignment mark pattern has an optical contrast with respect to the dummy pattern, and the optical contrast is substantially equal to or greater than 50 and the alignment mark pattern can thus be recognized by the camera.

[0087] Since the dummy pattern is configured to be between the alignment mark pattern and the interconnect structure, from the top-down perspective, since the dummy pattern blocks the underlying interconnect circuits and provides sufficient optical contrast for the camera to recognize the alignment mark pattern, some of the interconnect circuits of the interconnect structure can overlap with the dummy pattern. Thereby, the space utilization rate of the semiconductor device and the design flexibility of the circuit wiring are greatly increased.

[0088] Those skilled in the art will recognize that they can readily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; An upper layer, disposed above the substrate and comprising an upper electrical pattern and an alignment mark pattern electrically insulated from the upper electrical pattern; as well as The lower layer is arranged between the substrate and the upper layer and includes a lower electrical pattern and a dummy pattern electrically insulated from the lower electrical pattern, wherein, from a top view, the alignment mark pattern overlaps with the dummy pattern, and there is an optical contrast between the alignment mark pattern and the dummy pattern, and the optical contrast is equal to or greater than 50.

2. The semiconductor device according to claim 1, wherein: The upper layer includes a clearance area surrounding the alignment mark pattern, and the upper electrical pattern is arranged outside the clearance area.

3. The semiconductor device according to claim 2, characterized in that From a top-down perspective, the virtual pattern completely fills the clearance area.

4. The semiconductor device according to claim 2, characterized in that The electrical pattern is separated from the clearance area by a gap, and the gap is equal to or greater than 5 micrometers.

5. The semiconductor device according to claim 1, wherein: It also includes an interconnection structure disposed between the lower layer and the substrate, and from a top view, a portion of the interconnection circuit of the interconnection structure overlaps with the dummy pattern.

6. The semiconductor device according to claim 5, characterized in that The interconnection structure is electrically connected to the lower electrical pattern and is electrically insulated from the dummy pattern.

7. The semiconductor device according to claim 1, wherein: The upper electrical pattern includes a pad for bonding an electrical connector, and the material of the upper layer includes aluminum or aluminum containing titanium nitride.

8. The semiconductor device according to claim 7, characterized in that The material of the lower layer includes copper.

9. The semiconductor device according to claim 1, wherein: The upper electrical pattern includes an electrical connector, and the material of the upper layer includes gold or multiple layers of copper / nickel / gold.

10. The semiconductor device according to claim 9, characterized in that The material of the lower layer includes aluminum.

11. The semiconductor device according to claim 1, wherein: The alignment mark pattern is electrically insulated from the dummy pattern.

12. The semiconductor device according to claim 1, wherein: The optical contrast is a difference between a grayscale value of the dummy pattern and a grayscale value of the alignment mark pattern.

13. The semiconductor device according to claim 1, wherein: A ratio of a grayscale value of the dummy pattern to a grayscale value of the alignment mark pattern is equal to or greater than 1.

3.

14. A semiconductor device, characterized in that: include: substrate; An upper layer, disposed above the substrate and comprising an upper electrical pattern and an alignment mark pattern electrically insulated from the upper electrical pattern; a lower layer disposed between the substrate and the upper layer and comprising a lower electrical pattern and a dummy pad electrically insulated from the lower electrical pattern, wherein the alignment mark pattern overlaps the dummy pad from a top view; and An interconnection structure is arranged between the lower layer and the substrate, wherein, from a top view, a portion of an interconnection circuit of the interconnection structure overlaps with the dummy pad.

15. The semiconductor device according to claim 14, characterized in that An optical contrast is provided between the alignment mark pattern and the dummy pad, and the optical contrast is equal to or greater than 50.

16. The semiconductor device according to claim 14, characterized in that The upper layer includes a clearance area surrounding the alignment mark pattern, and the upper electrical pattern is arranged outside the clearance area.

17. The semiconductor device according to claim 16, characterized in that From a top view perspective, the dummy pad completely fills the clearance area.

18. The semiconductor device according to claim 16, wherein: From a top view perspective, a portion of the interconnection circuit overlaps the clearance area.

19. The semiconductor device according to claim 14, characterized in that The interconnection structure is electrically connected to the lower electrical pattern and is electrically insulated from the dummy pattern.

20. The semiconductor device according to claim 14, wherein: The upper electrical pattern includes a pad for bonding an electrical connector, and the material of the upper layer includes aluminum or aluminum containing titanium nitride.

21. The semiconductor device according to claim 20, characterized in that The material of the lower layer includes copper.

22. The semiconductor device according to claim 14, wherein: The upper electrical pattern includes an electrical connector, and the material of the upper layer includes gold or multi-layer copper / nickel / gold.

23. The semiconductor device according to claim 22, characterized in that The material of the lower layer includes aluminum.

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