Electro-optical devices and methods based on group III-V and / or II-VI and / or IV semiconductors

Abstract

An electro-optical device based on group III-V and / or II-VI and / or IV semiconductors is provided. The electro-optical device includes a support region and a ridge structure extending from the support region. The ridge structure includes: a bottom region disposed on the support region and including at least one layer of a first semiconductor material having a first conductivity type; an intermediate region disposed on the bottom region and including an active region, in which the intermediate region further includes at least one layer of a second semiconductor material and has a trapezoidal top region having a top surface, a side surface, and an inclined surface connecting the top surface to the side surface; a capping layer disposed on the side surface and the inclined surface of the intermediate region and including at least one layer of a third semiconductor material having a higher band gap than the second semiconductor material; and a fin structure extending upwardly from the top region and including at least one layer of a fourth semiconductor material having the second conductivity type.

Description

Technical Field

[0001] The present invention provides an electro-optic device based on III-V and / or II-VI and / or group-IV semiconductors and including a ridge structure. The present invention also proposes a method for manufacturing an electro-optic device. Background Art

[0002] Semiconductor nanoridge waveguides with good current injection efficiency and / or limited non-radiative recombination are used in monolithic integrated photonic devices.

[0003] Figure 11 Examples of monolithic integrated electro-optic devices fabricated using the nanoridge engineering (NRE) method are depicted. The electro-optic device includes a III-V semiconductor material ridge structure (e.g., GaAs) grown in a narrow shallow trench isolation (STI) trench on a silicon (Si) V-groove formed in a Si support layer.

[0004] The STI trench has a high aspect ratio (i.e., the ratio of its depth to width is greater than at least 1), which has the advantage of efficiently trapping mismatch and dislocation defects during the growth of the III-V semiconductor material in the trench (hence called aspect ratio trapping, ART), and thus the III-V semiconductor ridge material growing outward, i.e., the independent ridge structure, is defect-free. The nanoridge shape on top of the STI trench can be engineered and manipulated by the applied growth conditions, and thus, this ridge integration approach is called NRE.

[0005] In Figure 11 the electro-optic device, the support layer is highly n-doped (i.e., doped with n-type impurities), and the ridge structure itself includes an n-doped III-V semiconductor material (e.g., GaAs) region disposed near the bottom of the ridge structure and in contact with the n-doped support layer in the trench.

[0006] Furthermore, the ridge structure includes a III-V semiconductor material (e.g., GaAs) region disposed at the center of the ridge structure, which is unintentionally doped (also called non-intentionally doped or NID) and contains the active region. The ridge structure also includes a p-doped III-V semiconductor material (e.g., GaAs) region disposed at the top of the ridge structure, which is in contact with the metal interface.

[0007] In the electro-optic device according to Figure 11 the ridge structure has a substantially rectangular shape, particularly in the top or upper region (i.e., the region opposite the Si support layer in the exemplary coordinate system shown in Figure 11 ).

[0008] In addition, the ridge structure includes a capping layer of a III-V material with a higher bandgap grown around the III-V semiconductor material ridge structure (especially around its wider part) relative to the previous layer (e.g., InGaP, lattice-matched to the GaAs of the ridge structure). The capping layer has a high enough conduction band and / or valence band offset to prevent at least one type of charge carrier (i.e., electrons and / or holes) from penetrating into the capping layer and reaching its surface interface with the dielectric that encapsulates the ridge structure and the capping layer.

[0009] In addition, according to Figure 11 the ridge structure includes a region near the top of the ridge structure where III-V semiconductor material has been removed by etching to form a narrower top called a metal fin or metal fin structure. Here, the purpose of the metal fin structure is to inject carriers into the active region of the ridge structure during the operation of the electro-optic device. At the same time, the optical waveguide mode is not pushed downwards but has a strong overlap with the above-mentioned metal fin and the metal-semiconductor interface. This overlap results in very strong optical absorption and hinders, for example, laser operation. To achieve laser operation in such a design, the metal fins can be replaced by a very widely spaced plug array to reduce optical losses in the metal region. Therefore, the current density in each metal plug must be very high to ensure sufficient current injection into the active region. This in turn leads to new problems such as the formation of defects in the semiconductor near the metal fin and along the interface, resulting in laser device failure. SUMMARY OF THE INVENTION

[0010] In view of the above, an object of embodiments of the present invention is to provide an improved electro-optic device. The object is to provide an electro-optic device having a ridge structure that exhibits better contact design characteristics. Another object is to reduce surface recombination by preventing the exposure of relevant semiconductor material regions, so as to maximize the charge carrier density in the active region of the electro-optic device and reduce the optical losses of the light guided in the ridge.

[0011] This object and other objects are achieved by the embodiments provided in the appended independent claims. Advantageous implementations of these embodiments are described in the dependent claims.

[0012] The embodiments are based on the following considerations. In Figure 11 the exemplary cross-section of the electro-optic device shown, an n-doped layer is arranged at the bottom of the ridge structure, while a p-doped layer is arranged at the top of the ridge structure. This means that electrons are injected into the ridge structure from the bottom, while holes are injected into the ridge structure from the top.

[0013] In addition, this is Figure 11 a key surface in the electro-optic device shown, i.e., any exposed surface on the top, for example, due to the etching of the metal fin structure. If carriers are prevented from reaching any exposed surface, surface recombination of carriers can be significantly reduced in this exemplary electro-optic device.

[0014] Accordingly, embodiments of the present invention are based on the idea of providing a trapezoidal region of a semiconductor ridge structure (e.g., made of GaAs) that encapsulates an active region and is anisotropically capped with another semiconductor material (e.g., InGaP), and importantly, the other semiconductor material covers little or no GaAs on the narrower top portion of the trapezoidal region. Additionally, the design of the ridge structure provides continuous electrical contact to the active region, where the contact can be in the form of a semiconductor fin structure placed on top of the trapezoidal region and an array of continuous metal ridges or metal plugs placed on top of the fin structure.

[0015] The present invention provides an electro-optical device based on III-V and / or II-VI and / or group-IV semiconductors, the electro-optical device including a support region and a ridge structure extending from the support region. The ridge structure includes: a bottom region including at least one layer of a first semiconductor material having a first impurity type, the bottom region being disposed on the support region; an intermediate region including at least one layer of a second semiconductor material, the intermediate region being disposed on the bottom region and including an active region, wherein the intermediate region has a trapezoidal top region having a top surface, side surfaces, and inclined surfaces connecting the top surface to the side surfaces; a capping layer including at least one layer of a third semiconductor material, the capping layer being disposed on the side surfaces and inclined surfaces of the intermediate region, wherein the third semiconductor material has a higher bandgap than the second semiconductor material; and a fin structure including at least one layer of a fourth semiconductor material having a second impurity type, the fin structure extending mainly upward from the top region of the intermediate region.

[0016] Depending on the conditions (i.e., growth conditions) for forming the ridge structure, a layer / region disposed on top of another layer / region may only partially or completely cover any exposed surface of the underlying region / layer. Additionally, the thickness of a layer / region on the surface of an underlying region / layer can be controlled, particularly relative to the thickness of a layer / region on other surfaces of the underlying region / layer.

[0017] Herein, in accordance with the manufacturing direction of the electro-optical device, e.g., by epitaxial growth, the terms "upward", "top", "above", etc. are related to the terms "downward", "bottom", "below", etc. In other words, the "lowest point" of the ridge structure is on the support region, and the support region is "below" the ridge structure. The ridge structure extends "upward" from the support region, and the fin structure is disposed "on top of" and "above" the ridge structure.

[0018] In the electro-optical device of the first aspect and herein, the "first conduction type" can be n-type or p-type, and the "second conduction type" can thus be p-type or n-type. Similarly, the "first conduction type charge carriers" can be electrons or holes, and the "second conduction type charge carriers" can thus be holes or electrons.

[0019] By shaping the top of the intermediate region of the ridge structure into a trapezoid and by providing a capping layer to cover little or no second semiconductor material on the top surface of the trapezoidal intermediate region (i.e., by providing the capping layer only on the side surfaces and the inclined surfaces of the intermediate region), good injection of carriers into the active region is allowed during operation of the electro-optic device, while maintaining sufficient surface passivation and good carrier confinement.

[0020] Furthermore, by using a higher bandgap material as the capping layer around the lower bandgap material of the intermediate region, surface passivation can be maintained and subsequent carrier injection into the active region as well as carrier confinement can be optimized.

[0021] Furthermore, this design utilizes a continuous contact ridge by forming a semiconductor fin structure on the top surface of the trapezoidal top region of the intermediate region, enabling the electro-optic device to confine current injection during operation, pull down the optical mode to reduce optical losses, increase the spacing from the metal / semiconductor interface to the optical gain region to reduce non-radiative carrier recombination and defect formation, and thereby prevent overcurrent and temperature gradients that may lead to device failure. In one example, one or more metal plugs are further arranged on the fin structure.

[0022] Furthermore, the electro-optic device can be processed in one epitaxial growth step and no regrowth is required. In addition, the integration of the electro-optic device is simplified, thereby reducing costs.

[0023] In an implementation form of the first aspect, the top surface of the intermediate region includes a {001} surface of the second semiconductor material.

[0024] In an implementation form of the first aspect, the inclined surface of the intermediate region includes a {111} surface of the second semiconductor material.

[0025] In an implementation form of the first aspect, the fin structure is directly disposed on the top surface of the intermediate region.

[0026] In an implementation form of the first aspect, the capping layer is also disposed on the top surface of the intermediate region; and the fin structure is directly disposed on the capping layer on the top surface of the intermediate region.

[0027] In an implementation form of the first aspect, the ridge structure further includes a transition layer disposed between the top surface of the intermediate region and the capping layer.

[0028] During the formation of the ridge structure, some third semiconductor material of the capping layer may also be disposed on the top surface of the intermediate region. Therefore, by growing a transition layer between the top surface of the intermediate region and the capping layer, further carrier confinement of the top surface and improved carrier injection towards the intermediate region can be achieved.

[0029] Thus, carrier injection into the active region is ensured while maintaining surface passivation and good carrier confinement.

[0030] In an implementation of the first aspect, the width of the fin structure is narrower than the width of the capping layer.

[0031] In an implementation of the first aspect, the electro-optical device further includes an electrode that makes electrical contact with the top surface of the fin structure and is configured to inject second-conductivity-type charge carriers into the ridge structure through the fin structure.

[0032] In an implementation of the first aspect, the bottom region of the ridge structure is narrower than the middle region of the ridge structure.

[0033] In an implementation of the first aspect, the active region includes one or more quantum wells and / or one or more quantum dots and / or one or more quantum wires and / or bulk material.

[0034] In an implementation of the first aspect, the first semiconductor material includes at least one of the following: doped GaAs, doped InP, doped InAs, doped GaSb, doped InGaAs, doped InGaAsSb, or doped GaAlAs.

[0035] In an implementation of the first aspect, the second semiconductor material includes at least one of the following: unintentionally doped GaAs or doped GaAs, unintentionally doped InP or doped InP, unintentionally doped InAs or doped InAs, unintentionally doped GaSb or doped GaSb, unintentionally doped InGaAs or doped InGaAs, unintentionally doped InGaAsSb or doped InGaAsSb, or unintentionally doped InGaAsP or doped InGaAsP, or unintentionally doped InGaAsN or doped InGaAsN.

[0036] In an implementation of the first aspect, the third semiconductor material includes at least one of the following: unintentionally doped AlAsSb or doped AlAsSb, unintentionally doped InGaP or doped InGaP, unintentionally doped AlGaSb or doped AlGaSb, unintentionally doped GaAlPSb or doped GaAlPSb, or unintentionally doped InAlAs or doped InAlAs, unintentionally doped GaAlAs or doped GaAlAs.

[0037] In an implementation of the first aspect, the fourth semiconductor material includes at least one of the following: doped GaAs, doped InP, doped InAs, doped GaSb, doped InGaAs, doped InGaAsSb, or doped GaAlAs.

[0038] In an implementation of the first aspect, the electro-optic device is a laser, a light-emitting diode (LED), an optical amplifier, a single-photon source, a dimming device, a saturable absorber, or an optical detector.

[0039] A second aspect of the present invention provides a method for manufacturing an electro-optic device based on III-V and / or II-VI and / or group-IV semiconductors. The method includes providing a support region; and growing a ridge structure extending from the support region by the following steps: growing a bottom region on the support region, the bottom region including at least one layer of a first semiconductor material having a first conductivity type;

[0040] growing an intermediate region on the bottom region, the intermediate region including an active region, and the intermediate region including at least one layer of a second semiconductor material, wherein the intermediate region has a trapezoidal top region having a top surface, side surfaces, and inclined surfaces connecting the top surface to the side surfaces;

[0041] growing a capping layer on the side surfaces and inclined surfaces of the intermediate region, the capping layer including at least one layer of a third semiconductor material, wherein the third semiconductor material has a higher bandgap than the second semiconductor material; and

[0042] growing a fin structure on the top region of the intermediate region, the fin structure including at least one layer of a fourth semiconductor material having a second impurity type.

[0043] In an implementation of the second aspect, the top surface of the intermediate region includes a {001} surface of the second semiconductor material.

[0044] In an implementation of the second aspect, the inclined surfaces of the intermediate region include {111} surfaces of the second semiconductor material.

[0045] In an implementation of the second aspect, the method further includes directly forming a fin structure on the top surface of the intermediate region.

[0046] In an implementation of the second aspect, the method further includes growing a capping layer on the top surface of the intermediate region; and directly forming a fin structure on the capping layer on the top surface of the intermediate region.

[0047] In an implementation of the second aspect, the method further includes forming a transition layer between the top surface of the intermediate region and the capping layer.

[0048] In an implementation of the second aspect, the width of the fin structure is narrower than the width of the capping layer.

[0049] In an implementation of the second aspect, the method further includes depositing an electrode that is in electrical contact with the top surface of the fin structure and is configured to inject second-conductivity-type charge carriers into the ridge structure through the fin structure.

[0050] In an implementation of the second aspect, the bottom region of the ridge structure is narrower than the middle region of the ridge structure.

[0051] In an implementation of the second aspect, the active region includes one or more quantum wells and / or one or more quantum dots and / or one or more quantum wires and / or bulk material.

[0052] In an implementation of the second aspect, the first semiconductor material includes at least one of the following: doped GaAs, doped InP, doped InAs, doped GaSb, doped InGaAs, doped InGaAsSb, or doped GaAlAs.

[0053] In an implementation of the second aspect, the second semiconductor material includes at least one of the following: unintentionally doped GaAs or doped GaAs, unintentionally doped InP or doped InP, unintentionally doped InAs or doped InAs, unintentionally doped GaSb or doped GaSb, unintentionally doped InGaAs or doped InGaAs, unintentionally doped InGaAsSb or doped InGaAsSb, or unintentionally doped InGaAsP or doped InGaAsP, or unintentionally doped InGaAsN or doped InGaAsN.

[0054] In an implementation of the second aspect, the third semiconductor material includes at least one of the following: unintentionally doped AlAsSb or doped AlAsSb, unintentionally doped InGaP or doped InGaP, unintentionally doped AlGaSb or doped AlGaSb, unintentionally doped GaAlPSb or doped GaAlPSb, or unintentionally doped InAlAs or doped InAlAs, unintentionally doped GaAlAs or doped GaAlAs.

[0055] In an implementation of the second aspect, the fourth semiconductor material includes at least one of the following: doped GaAs, doped InP, doped InAs, doped GaSb, doped InGaAs, doped InGaAsSb, or doped GaAlAs.

[0056] The method of the second aspect achieves the same advantages as the device of the first aspect and can be extended by the corresponding implementation for the device of the first aspect as described above.

[0057] The advantages of the solution according to the present invention can be summarized as follows:

[0058] · Maintains good carrier injection efficiency and surface passivation.

[0059] · The electro-optic device can be processed in one epitaxial growth step and no regrowth is required.

[0060] · A fin structure is obtained, which confines current injection, pulls down the optical mode to reduce optical losses, and increases the spacing from the metal / semiconductor interface to the optical gain region, thereby reducing the risk of defect formation. In addition, due to the reduced losses, it allows the use of metal ridges or metal plugs to contact the electro-optic device, thus preventing overcurrent and temperature gradients.

[0061] · Achieves simplified integration of the electro-optic device, thereby reducing costs.

[0062] · Due to the iterative process, the frame structure has flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The above aspects and implementations are explained in the following detailed description with reference to the accompanying drawings:

[0064] Figure 1 Shows a cross-section of an electro-optic device according to an embodiment of the present invention;

[0065] Figure 2a )-d) Shows examples of the trapezoidal shape of the intermediate region of an electro-optic device according to an embodiment of the present invention;

[0066] Figure 3 Shows a cross-section of an electro-optic device according to an embodiment of the present invention;

[0067] Figure 4 Shows according to Figure 3 an embodiment of the electro-optic device in a three-dimensional (3D) view;

[0068] Figure 5a )-b) Shows the results of the mode distribution and absorption region of an electro-optic device according to an embodiment of the present invention;

[0069] Figure 6 Shows a cross-section of an electro-optic device according to an embodiment of the present invention;

[0070] Figure 7 Shows a cross-section of an electro-optic device according to an embodiment of the present invention;

[0071] Figure 8Shows a method according to an embodiment of the present invention;

[0072] Figure 9 Shows an exemplary method according to an embodiment of the present invention;

[0073] Figure 10 Shows an exemplary method according to an embodiment of the present invention;

[0074] Figure 11 Shows a conventional example of a semiconductor-based ridge electro-optic device.

[0075] The elements in the drawings are not drawn to scale and may be different from real-life implementations to highlight the details of the embodiments. Detailed Description

[0076] Figure 1 Shows a cross-section of an exemplary embodiment of an electro-optic device 10 according to the present invention. The device 10 is a monolithic integrated electro-optic device and is based on III-V semiconductors and / or II-VI semiconductors and / or group-IV semiconductors.

[0077] The electro-optic device 10 can be a laser, an LED, an optical amplifier, a single-photon source, a light dimmer, a saturable absorber, or an optical detector. The electro-optic device 10 can be manufactured using a so-called nano-ridge engineering (NRE) method.

[0078] The electro-optic device 10 includes a support region 11. The support region 11 can include a substrate made of Si or Ge or SiC or any binary III-V material or any binary II-IV material. The support region 11 can include narrow STI trenches 11a formed on a V-groove in a semiconductor material substrate 11b.

[0079] In addition, the support region 11 can be an engineered substrate achieved by bonding a seed layer to a disposal substrate and processing a trench pattern, as Figure 1 shown. The engineered substrate can provide a crystal surface for epitaxial deposition of other parts of the electro-optic device 10.

[0080] The electro-optic device 10 further includes a ridge structure 12 extending from the support region 11. The ridge structure 12 can be fabricated on the support region 11 using the NRE method, that is, it can be grown in a high-aspect-ratio trench previously formed in the support region 11. The ridge structure 12 can extend on the support region 11 in a direction that enters Figure 1 the plane depicted in the cross-section shown, in which a reference coordinate system is depicted.

[0081] The ridge structure 12 includes a plurality of different regions and layers. That is, the ridge structure 12 includes a bottom region 13 disposed on the support region 11. The bottom region 13 includes at least one layer of a first semiconductor material having a first impurity type.

[0082] The bottom region 13 can be grown in the high aspect ratio trench described above. Thus, the bottom region 13 can be narrower compared to the maximum width of the ridge structure 12.

[0083] The ridge structure 12 further includes an intermediate region 14 disposed on the bottom region 13 and including an active region 15. The intermediate region 14 includes or is made of at least one layer of a second semiconductor material.

[0084] The active region 15 can emit or absorb or modulate light and can include at least one layer that includes one or more quantum wells and / or one or more quantum dots and / or one or more quantum wires and / or bulk material.

[0085] It is noted that the intermediate region 14 is formed such that it has a trapezoidal top region 16. That is, the top region 16 (or upper part) of the intermediate region 14 has two side surfaces 18, a top surface 17, and two inclined surfaces 19 connecting the top surface 17 to the side surfaces 18. Thus, the intermediate region 14 has an upper part that has a trapezoidal shape in the Figure 1 depicted cross-sectional plane, where the width of the top surface 17 (on the x-axis depicted in the Figure 1 coordinate system) is less than the total width of the intermediate region 14. The total width of the intermediate region 14 can be determined as, for example, the distance between the two side surfaces 18 (in the x-direction in the Figure 1 depicted coordinate system).

[0086] Thus, in three dimensions (3D), the top region 16 of the intermediate region 14 can have a truncated pyramid shape.

[0087] In an embodiment according to Figure 1 the top surface 17 of the intermediate region 14 can include the {001} surface of the second semiconductor material, while the inclined surfaces 19 can each include the {111} surface of the second semiconductor material.

[0088] Optionally, the side surfaces 18 can each include the {110} surface of the second semiconductor material.

[0089] As according to Figure 1As shown in the embodiment, compared with the trapezoid defined in the upper part (or top region 16), the lower part of the intermediate region 14 may have an inverted trapezoid shape, having two lower inclined surfaces and a bottom surface, wherein the lower inclined surfaces connect the bottom surface to the two side surfaces 18. Alternatively, the lower part of the intermediate region 14 may have any other shape. For example, it may have a rectangular or square shape (in two dimensions or 2D), and thus it has a cuboid box shape or a cube box shape in 3D respectively. This is not restricted in the present disclosure.

[0090] Figure 2a -d) shows four examples of the intermediate region 14, each having a trapezoid shape. Figure 2a ) and Figure 2d ) the width of the top surface 17 of the intermediate region 14 shown is greater than Figure 2b ) the top surface 17 of the intermediate region 14 shown. As Figure 2c ) shown, the top surface 17 of the intermediate region 14 is highlighted without any capping layer, which will be explained later in this text. Figure 1 and Figure 2a ) - d) The same elements in have the same reference numerals and the same functions.

[0091] Referring to Figure 1 , the ridge structure 12 further includes a capping layer 20 disposed on the side surfaces 18 and the inclined surfaces 19 of the intermediate region 14. The capping layer includes at least one layer of a third semiconductor material, wherein the third semiconductor material has a higher bandgap than the second semiconductor material.

[0092] Therefore, the {001} plane of the second semiconductor material of the intermediate layer 14 is not covered by the capping layer, that is, it remains exposed.

[0093] The ridge structure 12 further includes a fin structure 21, the fin structure 21 includes at least one layer of a fourth semiconductor material or is made of it, and the fourth semiconductor material has a second impurity type. The fin structure 21 extends upward from the top region 16 of the intermediate region 14. One or more metal plugs or metal structures may be disposed on the fin structure 21 (not shown).

[0094] In this exemplary embodiment, since the capping layer 20 is not disposed on the top surface 17 of the top region 16 of the intermediate region 14, the fin structure 21 is directly disposed on the top surface 7 of the intermediate region 14, thereby allowing good carrier injection into the active region while maintaining sufficient surface passivation and good carrier confinement.

[0095] Furthermore, the width of the fin structure 21 is narrower than the width of the capping layer 20.

[0096] As described above, the bottom region 13 can be narrower compared to the maximum width of the ridge structure 12. In other words, the bottom region 13 can be narrower compared to the total width of the middle region 14 and the width of the capping layers 20 provided on each side surface 18 of the middle region 14. Thus, the bottom region 13 can be narrower compared to the total width of the middle region 14.

[0097] The ridge structure 12 may further include at least one layer 22 of a fourth semiconductor material provided on the capping layer 20, which in turn is provided on the side surface 18 of the middle region 14, as Figure 1 shown in the embodiment of. This may be formed due to the fabrication of the fin structure 21, as will be explained later in this document, and does not limit the operation of the electro-optical device 10.

[0098] The first semiconductor material may include at least one of the following: doped GaAs, doped InP, doped InAs, doped GaSb, doped InGaAs, doped InGaAsSb, or doped GaAlAs.

[0099] The second semiconductor material of the middle region 14 may include at least one of the following: unintentionally doped GaAs or doped GaAs, unintentionally doped InP or doped InP, unintentionally doped InAs or doped InAs, unintentionally doped GaSb or doped GaSb, unintentionally doped InGaAs or doped InGaAs, unintentionally doped InGaAsSb or doped InGaAsSb, or unintentionally doped InGaAsP or doped InGaAsP, or unintentionally doped InGaAsN or doped InGaAsN.

[0100] The third semiconductor material of the capping layer 20 may include at least one of the following: unintentionally doped AlAsSb or doped AlAsSb, unintentionally doped InGaP or doped InGaP, unintentionally doped AlGaSb or doped AlGaSb, unintentionally doped GaPSb or doped GaPSb, or unintentionally doped InAlAs or doped InAlAs, unintentionally doped GaAlAs or doped GaAlAs.

[0101] The fourth semiconductor material of the fin structure 21 may include at least one of the following: doped GaAs, doped InP, doped InAs, doped GaSb, doped InGaAs, doped InGaAsSb, or unintentionally doped GaAlAs or doped GaAlAs.

[0102] As described above, the electro-optic device 10 can be a laser, an LED, an optical amplifier, a single-photon source, a light dimmer, a saturable absorber, or an optical detector. Therefore, the selection of the first semiconductor material, the second semiconductor material, the third semiconductor material, and the fourth semiconductor material depends on the desired implementation / use of the electro-optic device 10 and can be defined to ensure good waveguiding of the relevant wavelengths required for the corresponding device implementation / use.

[0103] Exemplary materials for the ridge structure 12 are shown in Table I such that the electro-optic device 10 is, for example but not limited to, a GaAs laser, an InGaAs laser, and an InP laser, or a GaSb laser.

[0104]

[0105] Table I is based on examples of semiconductor materials used in possible lasers of the electro-optic device 10.

[0106] Similarly, the respective dimensions of the bottom region 13, the middle region 14, the capping layer 20, and the fin structure 21 can vary depending on the desired use of the electro-optic device 10 and the semiconductor materials employed.

[0107] By way of example and not limitation, when the electro-optic device 10 is a GaAs / InGaAs laser, the width of the fin structure 21 can be greater than 5 nanometers (nm) and less than the maximum width of the corresponding material where the fin structure 21 does not guide waves. The upper limit of the width of the fin structure 21 for a GaAs / InGaAs laser is ∼250 nm.

[0108] Therefore, the width of the top surface 17 of the middle region 14 can be greater than or less than the width of the fin structure 21 and less than the maximum width of the middle region 14. Additionally, the width of the capping layer 20 provided on the side surfaces 18 and the inclined surfaces 19 of the middle region 14 can be above 10 nm.

[0109] Figure 3 A cross-section of an exemplary embodiment of the electro-optic device 10 according to the present invention is shown, which electro-optic device 10 is based on Figure 1 the electro-optic device shown. The same elements share the same reference numerals and have the same functions. Hereinafter, only the differences between Figure 1 and Figure 3 will be explained.

[0110] In an embodiment according to Figure 3 the electro-optic device 10, in particular the ridge structure 12, further includes an electrode 23 that electrically contacts the top surface of the fin structure 21.

[0111] The electrode 23 is configured to inject charge carriers of a second conductivity type into the ridge structure 12, in particular into the intermediate region 14, via the fin structure 21. The electrode 23 may comprise or be made of a metallic material.

[0112] In the electro-optical device 10 according to Figure 1 and Figure 3 , the first conductivity type may be n-type while the second conductivity type may be p-type. Thus, the charge carriers of the first conductivity type are electrons and the charge carriers of the second conductivity type are holes. However, these polarities may also be interchanged.

[0113] Due to the trapezoidal shape of the top region of the intermediate region 14, the fin structure 21 enables the electro-optical device 10 to confine current injection, pull down the optical mode to reduce optical losses, increase the spacing from the metal / semiconductor interface to the optically active region 15, and prevent overcurrent and temperature gradients.

[0114] Figure 4 A 3D view of the electro-optical device 10 according to an embodiment of Figure 3 is shown. Figure 3 and Figure 4 The same reference numerals are used for the same elements in and , and they have the same functions. In this example, the fin structure 21 may further comprise a second layer 21b, which may be made of a fourth semiconductor material having a second impurity type to ensure a low contact resistance.

[0115] Figure 5a ) and Figure 5b ) show exemplary simulation results of the mode profile and the absorption region obtained for the electro-optical device 10 according to the embodiments of Figure 3 and Figure 4 shown.

[0116] Figure 6 A cross-section of another exemplary embodiment of the electro-optical device 10 according to the present invention is shown, which is based on the electro-optical device shown in Figure 1 . The same elements are denoted by the same reference numerals and have the same functions. Hereinafter, only the differences between Figure 1 and Figure 6 will be explained.

[0117] In the embodiment according to Figure 6 , a capping layer 20 is also provided on the top surface 17 of the intermediate region 14. That is, the capping layer 20 covers at least partially or completely the {001} plane of the top surface 17 of the intermediate region 14.

[0118] Therefore, in order to maintain sufficient carrier injection into the intermediate region 14, the ridge structure 12 in this exemplary embodiment may further include a transition layer 24, which is disposed between the top surface 17 of the intermediate region 14 and the capping layer 20 on top thereof.

[0119] The transition layer 24 may also be inadvertently disposed on the inclined surface (19) of the intermediate region 14 (not shown) and / or on the side surface (18) of the intermediate region 14 (not shown).

[0120] The transition layer 24 may comprise or may be formed of at least one layer of a fifth semiconductor material. The fifth semiconductor material may comprise a second semiconductor material doped with impurities of a first conductivity type or a second conductivity type. By way of example but not limitation, the transition layer 24 may comprise n-doped or p-doped GaAs.

[0121] In addition, in an exemplary embodiment according to Figure 6 a fin structure 21 is disposed directly on the capping layer 20, and the capping layer 20 is disposed on the top surface 17 of the intermediate region 14.

[0122] Figure 7 A cross-section of another exemplary embodiment of the electro-optical device 10 according to the present invention is shown, and the electro-optical device 10 is based on Figure 6 the electro-optical device shown. Identical elements share the same reference numerals and have the same functions. In the following, only the differences between Figure 6 and Figure 7 will be explained.

[0123] In an embodiment according to Figure 7 the electro-optical device 10, in particular the ridge structure 12, further includes an electrode 23 that electrically contacts the top surface of the fin structure 21.

[0124] In this embodiment, the electrode 23 is configured to inject second conductivity type charge carriers into the ridge structure 12, in particular into the intermediate region 14, through the fin structure 21 and through the transition layer 24. The electrode 23 may comprise or may be made of a metallic material.

[0125] Figure 8 A method 30 for manufacturing the electro-optical device 10 according to an embodiment of the present invention is schematically shown. The method 30 includes at least the following steps: a step 31 of providing a support region 11, and a step 32 of growing a ridge structure 12 extending from the support region 11.

[0126] Step 32 may include: step 33 of growing the bottom region 13 on the support region 11, the bottom region 13 including at least one layer of a first semiconductor material having a first conductivity type; and step 34 of growing the intermediate region 14 on the bottom region 13, the intermediate region 14 including the active region 15, and the intermediate region 14 including at least one layer of a second semiconductor material, wherein the intermediate region 14 has a trapezoidal top region 16, the trapezoidal top region 16 having a top surface 17, side surfaces 18, and an inclined surface 19 connecting the top surface 17 to the side surfaces 18.

[0127] Step 32 may further include step 35 of growing a capping layer 20 on the side surfaces 18 and the inclined surface 19 of the intermediate region 14, the capping layer 20 including at least one layer of a third semiconductor material, and wherein the third semiconductor material has a higher bandgap than the second semiconductor material.

[0128] Then, step 32 may include step 36 of forming a fin structure 21 on the top region 16 of the intermediate region 14, the fin structure 21 including a fourth semiconductor material having a second conductivity type.

[0129] For example, when manufacturing the electro-optical device 10 according to an embodiment of the present invention using the NRE method, STI trenches 11a may be formed in the support region 11, and the ridge structure 12 may be epitaxially grown in the STI trenches 11a.

[0130] Figure 9 Exemplary steps of the above method 32 are schematically depicted. In step I, after forming the support region 11, the bottom region 13 may be grown on the support region 11. Then, the lower portion of the intermediate region 14 may be grown on the bottom region 13 and may be made of a second semiconductor material. The lower portion has a generally rectangular shape. For example, the side surfaces 18 of the intermediate region 14 may include respective {110} surfaces. The active region 15 may also be formed in the intermediate region 14.

[0131] Then, in step II, the trapezoidal top region 16 of the intermediate region 14 may be formed by using a facet growth rate manipulation technique called NRE. In other words, two inclined surfaces 19 may be formed to include respective {111} surfaces of the second semiconductor material, while the top surface 17 of the intermediate region 14 may be formed to include respective {001} surfaces of the second semiconductor material, wherein the inclined surfaces 19 connect the top surface 17 to the side surfaces 18.

[0132] In step III, a capping layer 20 including at least one layer of a third semiconductor material may be grown on the side surfaces 18, the inclined surface 19, and the top surface 17 of the intermediate region 14. In step IV, the capping layer 20 on the top surface 17 may be in-situ removed (e.g., by annealing or etching in the same growth chamber), thereby exposing the top surface 17.

[0133] Next, in steps V and VI, a fin structure 21 is formed by growing at least one layer 22 of a fourth semiconductor material on the intermediate structure 14 and the capping layer 20. The at least one layer 22 can then be etched to form the fin structure 21 only on the top surface 17 of the intermediate layer 14. Additionally, electrodes 23 can be formed.

[0134] Figure 10 An exemplary method is schematically depicted for the case where the capping layer 20 still exists on the top surface 17 of the intermediate region 14. According to Figure 10 step I, it is depicted that the at least one layer 22 can be grown before removing the capping layer 20. Then, in step II, a portion of the capping layer 20 may still be disposed on the top surface 17 of the intermediate layer 14.

[0135] To maintain sufficient carrier injection in the ridge structure 14, in step III, the capping layer 20 can be n-doped or p-doped. As an alternative or in addition, in steps IV and V, a transition layer 24 can be formed between the top surface 17 of the intermediate region 14 and the capping layer 20 directly thereabove. By way of example and not limitation, the transition layer 24 can be formed by fully or partially doping the top surface 17 of the trapezoidal top region 16 with a second semiconductor material. This is shown in Figure 10 step IV.

[0136] In the claims as well as in the description of the present disclosure, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single element can perform the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. An electro-optical device (10) based on III-V and / or II-VI and / or IV semiconductors, comprising: Support area (11); as well as A ridge structure (12) extending from the support region (11), wherein the ridge structure (12) comprises: - a bottom region (13), the bottom region comprising at least one layer of a first semiconductor material, the first semiconductor material having a first impurity type, the bottom region (13) being arranged on the support region (11); - an intermediate region (14) comprising at least one layer of a second semiconductor material, the intermediate region (14) being arranged on the bottom region (13) and comprising an active region (15), wherein the intermediate region (14) has a trapezoidal top region (16) having a top surface (17), a side surface (18) and an inclined surface (19) connecting the top surface (17) to the side surface (18); - a capping layer (20), the capping layer comprising at least one layer of a third semiconductor material, the capping layer (20) being arranged on the side surface (18) and the inclined surface (19) of the intermediate region (14), wherein the third semiconductor material has a higher band gap than the second semiconductor material; and - a fin structure (21), the fin structure comprising at least one layer of a fourth semiconductor material, the fin structure (21) extending mainly upwards from a top region (16) of the intermediate region (14), the fourth semiconductor material having a second impurity type.

2. The electro-optical device (10) according to claim 1, characterized in that: A top surface (17) of the intermediate region (14) comprises a {001} surface of the second semiconductor material.

3. The electro-optical device (10) according to claim 1 or 2, characterized in that: The inclined surface (19) comprises a {111} surface of the second semiconductor material.

4. The electro-optical device (10) according to any one of claims 1 to 3, characterized in that: The fin structure (21) is disposed directly on the top surface (17) of the intermediate region (14).

5. The electro-optical device (10) according to any one of claims 1 to 3, characterized in that: - the cover layer (20) is also arranged on the top surface (17) of the intermediate region (14); and The fin structure (21) is arranged directly on the capping layer (20) on the top surface (17) of the intermediate region (14).

6. The electro-optical device (10) according to claim 5, characterized in that The ridge structure (12) further comprises: - a transition layer (24) arranged between the top surface (17) of the intermediate zone (14) and the cover layer (20).

7. The electro-optical device (10) according to any one of claims 5 or 6, characterized in that: The width of the fin structure (21) is narrower than the width of the capping layer (20).

8. An electro-optical device (10) according to any one of the preceding claims, characterized in that Also includes: An electrode (23) electrically contacts a top surface of the fin structure (21) and is configured to inject charge carriers of a second conductivity type into the ridge structure (12) through the fin structure (21).

9. An electro-optical device (10) according to any one of the preceding claims, characterized in that: The bottom region (13) of the ridge structure (12) is narrower than the middle region (14).

10. An electro-optical device (10) according to any one of the preceding claims, characterized in that: The active region (15) comprises one or more quantum wells and / or one or more quantum dots and / or one or more quantum wires and / or bulk material.

11. An electro-optical device (10) according to any one of the preceding claims, characterized in that: The second semiconductor material includes at least one of the following: unintentionally doped GaAs or doped GaAs, unintentionally doped InP or doped InP, unintentionally doped InAs or doped InAs, unintentionally doped GaSb or doped GaSb, unintentionally doped InGaAs or doped InGaAs, unintentionally doped InGaAsSb or doped InGaAsSb, or unintentionally doped InGaAsP or doped InGaAsP, or unintentionally doped InGaAsN or doped InGaAsN.

12. An electro-optical device (10) according to any one of the preceding claims, characterized in that: The third semiconductor material includes at least one of the following: unintentionally doped AlAsSb or doped AlAsSb, unintentionally doped InGaP or doped InGaP, unintentionally doped AlGaSb or doped AlGaSb, unintentionally doped GaPSb or doped GaPSb, or unintentionally doped InAlAs or doped InAlAs, unintentionally doped GaAlAs or doped GaAlAs.

13. An electro-optical device (10) according to any one of the preceding claims, characterized in that: The fourth semiconductor material includes at least one of doped GaAs, doped InP, doped InAs, doped GaSb, doped InGaAs, doped InGaAsSb, or doped GaAlAs.

14. An electro-optical device (10) according to any one of the preceding claims, characterized in that , the electro-optical device is: Lasers, light emitting diodes, optical amplifiers, single photon sources, light modulators, saturable absorbers or optical detectors.

15. A method for manufacturing an electro-optical device (10) based on III-V and / or II-VI and / or IV semiconductors, the method (30) comprising: providing (31) a support area (11); A ridge structure (12) extending from the support region (11) is grown (32) by: - growing (33) a bottom region (13) on the support region (11), the bottom region (13) comprising at least one layer of a first semiconductor material having a first conductivity type; - growing (34) an intermediate region (14) on the bottom region (13), the intermediate region (14) comprising an active region (15) and the intermediate region (14) comprising at least one layer of a second semiconductor material, wherein the intermediate region (14) has a trapezoidal top region (16) having a top surface (17), a side surface (18) and an inclined surface (19) connecting the top surface (17) to the side surface (18); - growing (35) a capping layer (20) on the side surface (18) and the inclined surface (19) of the intermediate region (14), the capping layer comprising at least one layer of a third semiconductor material, wherein the third semiconductor material has a higher band gap than the second semiconductor material; as well as - growing (36) a fin structure (21) on the top region (16) of the intermediate region (14), the fin structure comprising at least one layer of a fourth semiconductor material, the fourth semiconductor material having a second impurity type.

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