GaN totem-pole bridgeless PFC converter harmonic suppression method based on adaptive virtual admittance

Abstract

The invention discloses a GaN totem-pole bridgeless PFC converter harmonic suppression method based on adaptive virtual admittance, and belongs to the technical field of converter control. The invention aims to solve the problem that LC resonance in a GaN totem-pole bridgeless PFC converter in a wide load range causes power grid voltage distortion to be converted into grid-side current harmonics. Comprising the following steps: decoupling a virtual admittance vector in a polar coordinate system, and optimizing under different load working conditions to obtain an optimal virtual admittance set; the system delay influence is compensated to ensure the robustness of the proposed method under different operation conditions; and a load power adaptive virtual admittance mechanism is constructed based on a segmented cubic Hermite interpolation method, so that suppression of network-side specific current harmonics in a wide load range is realized. The self-adaptive suppression method is used for self-adaptive suppression of the grid-side current harmonics of the GaN totem-pole bridgeless PFC converter.

Description

Technical Field

[0001] The present invention relates to a harmonic suppression method for a GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance, belonging to the technical field of converter control. Background Art

[0002] With the continuous advancement of the construction of new power systems, power quality governance faces new challenges, especially the harmonic problem. Power Factor Correction (PFC) technology can reduce the pollution of harmonic current to the power grid. Compared with other PFC converters, the totem-pole bridgeless Boost PFC converter uses the fewest components and has the smallest conduction loss. GaN devices have good reverse recovery characteristics, enabling the converter to operate in continuous conduction mode, and the peak efficiency can exceed 98.5%. Due to the fast switching speed and high switching frequency of GaN devices, more serious electromagnetic interference problems are caused, and usually two-stage EMI filters are adopted to meet the electromagnetic compatibility requirements. However, the EMI filter will generate LC resonance with the boost inductor, and coupled with the influence of parasitic parameters in the power loop and the drive loop, the totem-pole bridgeless PFC converter will introduce grid voltage distortion into the grid-side current. Therefore, it is crucial to study the grid-side current harmonic suppression strategy for GaN totem-pole bridgeless PFC converters. However, the harmonic suppression effect of the fixed virtual admittance method is strongly dependent on the converter parameters, and the suppression effect is not ideal under the conditions of input voltage harmonic frequency change and wide-range load, resulting in low adaptability. Therefore, it is necessary to establish an adaptive harmonic suppression strategy to adapt to various different operating conditions and parameter changes.

[0003] At present, the methods for suppressing grid-side current harmonics mainly include two types: harmonic compensation methods based on nonlinear control and harmonic suppression methods based on active damping. The harmonic compensation method based on nonlinear control can suppress current harmonics through the gain of the controller at the harmonic frequency, but it is relatively complex to implement. The harmonic suppression method based on active damping can be further divided into two categories: the method of adding a digital filter to the forward path and the method of adding a state variable feedforward / feedback. Among them, adding a digital filter to the forward path is essentially a series correction method, which has a large design difficulty and low adaptability. The method of adding a state variable feedforward generates a virtual admittance through the current controller, changes the frequency characteristics of the system, and thus suppresses current harmonics. When the system impedance changes or the power range is wide, the suppression effect deteriorates. Adaptive algorithms can be divided into dynamic estimation methods based on models or algorithms and direct data mapping methods according to the data processing method. The dynamic estimation methods based on models or algorithms include model reference adaptive algorithms, sliding mode observers, extended Kalman filter algorithms, recursive least squares methods, etc. This type of method generally has problems such as relying on an accurate system model and has high requirements for the performance of software and hardware devices. The direct data mapping methods mainly include the look-up table method and the fitting method. The look-up table method can quickly obtain results in a simple system, but its generality is not ideal and it is difficult to meet high-precision requirements. The fitting method is easy to implement, occupies less resources, and does not have instability problems, and can also achieve good results. Therefore, for the converter system, it is of great significance to study an adaptive suppression method for grid-side current harmonics with low cost, obvious suppression effect, and strong adaptability. Summary of the Invention

[0004] Aiming at the problem that the LC resonance in the GaN totem-pole bridgeless PFC converter under a wide load range causes the grid voltage distortion to be converted into grid-side current harmonics, the present invention provides a harmonic suppression method for a GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance.

[0005] A harmonic suppression method for a GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance of the present invention includes:

[0006] Decouple the virtual admittance vector in the polar coordinate system and optimize it under different set load powers to obtain the theoretical optimal virtual admittance set for different set load powers;

[0007] Compensate the theoretical optimal virtual admittance set based on the system delay caused by the band-pass filter in the damping distribution strategy to obtain the actual optimal virtual admittance set;

[0008] Fit the actual optimal virtual admittance set using the piecewise cubic Hermite interpolation method to obtain the optimal virtual admittance fitting curve in the full load power range;

[0009] Calculate the current load power, and determine the corresponding optimal virtual admittance through the optimal virtual admittance fitting curve; allocate the optimal virtual admittance into a reference current component and a modulation voltage component by using a damping distribution strategy, and inject them into the control loop to implement the adaptive mechanism of the virtual admittance; thereby suppressing the grid-side target current harmonics in a wide load power range.

[0010] For the harmonic suppression method of the GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance according to the present invention, the decoupling expression of the virtual admittance vector in the polar coordinate system is:

[0011]

[0012] In the formula, Y d is the virtual admittance vector, |Y d | is the virtual admittance amplitude, θ d is the virtual admittance phase angle, ω d is the harmonic frequency, and s is a complex variable.

[0013] For the harmonic suppression method of the GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance according to the present invention, the method for obtaining the theoretical optimal virtual admittance set of different set load powers is:

[0014] According to the system input admittance model of the converter system at the harmonic frequency ω d after considering non-ideal factors, with the amplitude and phase angle of the virtual admittance as independent variables and the system input admittance at the harmonic frequency as the dependent variable, take the virtual admittance amplitude and phase angle corresponding to the minimum system input admittance amplitude at the harmonic frequency as the theoretical optimal virtual admittance; repeat the test under different set load powers to obtain the theoretical optimal virtual admittance set of different set load powers.

[0015] For the harmonic suppression method of the GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance according to the present invention, the system input admittance model of the converter system at the harmonic frequency ω d after considering non-ideal factors is:

[0016]

[0017] In the formula, Y g_d is the system input admittance, Y L is the converter input admittance, Y DM is the differential-mode capacitance admittance, L DM is the differential-mode inductor in the EMI filter, R g is the equivalent resistance of the converter front-end circuit;

[0018] Y DM (s) = sC DM ,

[0019] where C DM is the differential-mode capacitance;

[0020]

[0021] where g in is the ratio of the converter input power to the effective value of the input voltage, K ib is the reciprocal of the current reference value, G ic is the transfer function of the current controller, G id is the transfer function between the s-domain form I L (s) of the converter input current and the s-domain form D(s) of the duty cycle of the PFC converter, T d is the time delay of the digital control system of the converter, 1 / V m is the gain of the PWM link, T i is the loop gain transfer function, G iv is the s-domain form I L (s) of the converter input current and the s-domain form U in (s) of the converter input voltage;

[0022] G iv (s) = 1 / (sL),

[0023] G id (s) = U dc / (sL),

[0024]

[0025] where U dc is the DC value of the converter output voltage, K is is the current feedback coefficient.

[0026] According to the harmonic suppression method of the GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance of the present invention, the method for obtaining the actual optimal virtual admittance set is as follows:

[0027] Compensate the phase angle of the virtual admittance in the theoretical optimal virtual admittance set to obtain the actual optimal virtual admittance set.

[0028] According to the harmonic suppression method of the GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance of the present invention, the method for obtaining the optimal virtual admittance fitting curve in the full load power range is as follows:

[0029] Perform piecewise cubic Hermite interpolation on the amplitudes and phase angles of all actual optimal virtual admittances to obtain the fitting curve:

[0030]

[0031] Where P L is the load power, and a k1 , a k2 , a k3 , a k4 , b k1 , b k2 , b k3 , b k4 are all undetermined fitting coefficients in the fitting curve.

[0032] According to the harmonic suppression method of the GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance of the present invention, the method for determining the optimal virtual admittance corresponding to the current load power is as follows:

[0033] Collect the input voltage u in of the converter and the input current i L of the boost inductor L in the converter, and perform AD conversion; calculate the current load power; determine the optimal virtual admittance corresponding to the current load power from the optimal virtual admittance fitting curve.

[0034] According to the harmonic suppression method of the GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance of the present invention, at the harmonic frequency ω d , the expression of the actual virtual admittance Y d (s) obtained based on the optimal virtual admittance curve is:

[0035]

[0036] According to the harmonic suppression method of the GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance of the present invention, the damping distribution strategy is as follows:

[0037] After the input voltage u in of the converter is transformed by the analog-to-digital converter ADC, the harmonic voltage u h is obtained through the band-pass filter; at the same time, after the input voltage u in of the converter is transformed by the analog-to-digital converter ADC, the phase angle value θ of the input voltage is obtained through the phase-locked loop PLL; then the sine value of the input voltage phase is solved, and the zero-crossing detection result is output through the zero-crossing detection section ZCD;

[0038] The optimal virtual admittance Y d corresponding to the current load power determined by the optimal virtual admittance fitting curve passes through the current feedback coefficient K is section to obtain the reference current component and the grid-side voltage harmonic transfer function G d1 ; at the same time, it passes through the section to obtain the modulation voltage component and the grid-side voltage harmonic transfer function G d2 ; u h passes through G d2Obtain the modulation voltage component u yh ; Meanwhile, through G d1 obtain the reference current component i yh ;

[0039] The reference voltage u ref is subtracted from the bus voltage u dc after analog-to-digital conversion, and then through the transfer function G vc of the voltage controller to obtain the output current i vco of the voltage controller; The output current i vco of the voltage controller is multiplied by the sine value of the input voltage phase to obtain the reference current i ref ; The reference current i ref is added to the reference current component i yh , and then subtract the analog-to-digital conversion result of the input current i L of the boost voltage L to obtain the error current i err , and then through the current controller to obtain the output voltage u ico ;

[0040] The output voltage u ico is added to the modulation voltage component u yh , combined with the feedforward signal d f and input to the PWM link; The PWM link combines the zero-crossing detection result to generate the control signal of the switch, and finally realizes the suppression of the grid-side current harmonics.

[0041] Advantages of the present invention: The method of the present invention relates to harmonic suppression of a GaN totem-pole bridgeless PFC converter, and can improve the problem that the LC resonance in the GaN totem-pole bridgeless PFC converter under a wide load range causes the grid voltage distortion to be converted into grid-side current harmonics. First, the virtual admittance vector is decoupled in the polar coordinate system, and optimized under different load conditions to obtain the optimal virtual admittance set. Further, the influence of system delay is compensated to ensure the robustness of the proposed method under different operating conditions. Based on the piecewise cubic Hermite interpolation method, a load power adaptive virtual admittance mechanism is constructed, thereby realizing the effective suppression of specific grid-side current harmonics under a wide load range.

[0042] The present invention applies the adaptive virtual admittance technology to the harmonic suppression of the GaN totem-pole bridgeless PFC converter, and solves the problem that the harmonic suppression effect of the traditional strategy is limited by the load range. Description of the Drawings

[0043] Figure 1 is the overall block diagram of the harmonic suppression method of the GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance according to the present invention; In the figure, i g is the grid-side current, u gis the grid-side voltage. Two GaN power device switches Q1 and Q2 form a high-frequency bridge arm, and two MOSFET switches Q3 and Q4 form a power-frequency bridge arm. C is the bus capacitor, ADC is the analog-to-digital converter, BPF is the band-pass filter, PLL is the phase-locked loop, ZCD is the zero-crossing detector, and PWM is the pulse-width modulator;

[0044] Figure 2 is a totem-pole bridgeless PFC converter topology with two-stage EMI filters; in the figure, C DM1 is the differential-mode capacitor one, C DM2 is the differential-mode capacitor two, C CM1，2 are the common-mode capacitor one and the common-mode capacitor two, C DM3 is the differential-mode capacitor three, C CM3，4 are the common-mode capacitor three and the common-mode capacitor four, L CM1，2 are the common-mode inductor one and the common-mode inductor two, L CM3,4 are the common-mode inductor three and the common-mode inductor four, L in is the boost inductor;

[0045] Figure 3 is the Bode plot of the system input admittance under different loads considering non-ideal factors;

[0046] Figure 4 is the schematic diagram of virtual admittance optimization;

[0047] Figure 5 is the comparison diagram of fitting curves obtained by high-order interpolation, piecewise linear interpolation, and piecewise cubic Hermite interpolation for the obtained virtual admittance amplitude data points;

[0048] Figure 6 is the comparison diagram of fitting curves obtained by high-order interpolation, piecewise linear interpolation, and piecewise cubic Hermite interpolation for the obtained virtual admittance phase angle data points;

[0049] Figure 7 is the schematic diagram of the dynamic test results of the adaptive virtual admittance harmonic suppression strategy;

[0050] Figure 8 is the schematic diagram of the input voltage, current waveforms, and Fourier analysis results without using the harmonic suppression strategy under a 900W load;

[0051] Figure 9 is the schematic diagram of the input voltage, current waveforms, and Fourier analysis results when using a fixed virtual admittance under a 900W load;

[0052] Figure 10 is the schematic diagram of the input voltage, current waveforms, and Fourier analysis results when using the adaptive virtual admittance harmonic suppression strategy of the present invention under a 900W load;

[0053] Figure 11 It is a comparison chart of the 17th grid-side current harmonics and current harmonic standards under three conditions: without using virtual admittance, using a fixed virtual admittance, and using an adaptive strategy at each power level. Specific implementation manners

[0054] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0055] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.

[0056] Next, the present invention will be further described in conjunction with the accompanying drawings, but it is not a limitation of the present invention.

[0057] Combined Figures 1 to 4 As shown, the present invention provides a harmonic suppression method for a GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance, including

[0058] Decouple the virtual admittance vector in the polar coordinate system and optimize it under different set load powers to obtain the theoretical optimal virtual admittance set for different set load powers;

[0059] Compensate the theoretical optimal virtual admittance set based on the system delay caused by the band-pass filter in the damping distribution strategy to obtain the actual optimal virtual admittance set;

[0060] Fit the actual optimal virtual admittance set by using the piecewise cubic Hermite interpolation method to obtain the optimal virtual admittance fitting curve in the full load power range;

[0061] Calculate the current load power, determine the corresponding optimal virtual admittance through the optimal virtual admittance fitting curve; allocate the optimal virtual admittance into a reference current component and a modulation voltage component by using the damping distribution strategy and inject them into the control loop to implement the adaptive mechanism of the virtual admittance; thereby realizing the suppression of the grid-side target current harmonics in a wide load power range.

[0062] In this implementation manner, optimization is performed under different load conditions to obtain the optimal virtual admittance set; then, the influence of system delay is compensated to ensure the robustness of the virtual admittance under different operating conditions; a load power adaptive virtual admittance mechanism is constructed based on the piecewise cubic Hermite interpolation method, thereby realizing the suppression of the grid-side target current harmonics in a wide load range.

[0063] Furthermore, combinedFigure 2 and Figure 3 As shown, study the numerical variation law of the input impedance of the research system under different load conditions. Then, decouple the virtual admittance vector in the polar coordinate system.

[0064] The expression for decoupling the virtual admittance vector in the polar coordinate system is:

[0065]

[0066] In the formula, Y d is the virtual admittance vector, |Y d | is the magnitude of the virtual admittance, θ d is the phase angle of the virtual admittance, ω d is the harmonic frequency, and s is a complex variable.

[0067] Combined with Figure 4 As shown, the method for obtaining the theoretical optimal virtual admittance set for different set load powers is:

[0068] According to the system input admittance model of the converter system at the harmonic frequency ω d after considering non-ideal factors, with the magnitude and phase angle of the virtual admittance as independent variables and the system input admittance at the harmonic frequency as the dependent variable, take the magnitude and phase angle of the virtual admittance corresponding to the minimum system input admittance magnitude at the harmonic frequency as the theoretical optimal virtual admittance; repeat the test under different set load powers to obtain the theoretical optimal virtual admittance set for different set load powers.

[0069] The system input admittance model of the converter system at the harmonic frequency ω d after considering non-ideal factors is:

[0070]

[0071] In the formula, Y g_d is the system input admittance, Y L is the converter input admittance, Y DM is the differential-mode capacitance admittance, L DM is the differential-mode inductance in the EMI filter, and R g is the equivalent resistance of the converter front-end circuit;

[0072] Y DM (s) = sC DM ,

[0073] In the formula, C DM is the differential-mode capacitance;

[0074]

[0075] In the formula, g inIt is the ratio of the converter input power to the effective value of the input voltage, K ib It is the reciprocal of the current reference value, G ic It is the transfer function of the current controller, G id It is the converter input current in the s-domain form I L (s) and the transfer function between the duty cycle s-domain form D(s) of the PFC converter, T d It is the time delay of the digital control system of the converter, 1 / V m It is the gain of the PWM link, T i It is the loop gain transfer function, G iv It is the converter input current in the s-domain form I L (s) and the converter input voltage in the s-domain form U in (s) between the transfer function;

[0076] G iv (s) = 1 / (sL),

[0077] G id (s) = U dc / (sL),

[0078]

[0079] Where U dc Is the DC value of the converter output voltage, K is Is the current feedback coefficient.

[0080] In this embodiment, the converter input admittance Y L Considers the influence of factors such as digital control system time delay, current loop bandwidth, and EMI filter.

[0081] Furthermore, the method to obtain the actual optimal virtual admittance set is:

[0082] The band-pass filter module in the damping distribution strategy will cause signal delay, which is the key factor causing the change of virtual admittance amplitude and phase angle. The change of the phase angle of the virtual admittance has a more significant impact on the 17th current harmonic. Therefore, the phase angle of the virtual admittance in the theoretical optimal virtual admittance set is compensated to obtain the actual optimal virtual admittance set.

[0083] Combined with Figure 5 And Figure 6 As shown, the method to obtain the optimal virtual admittance fitting curve in the full load power range is:

[0084] Perform piecewise cubic Hermite interpolation on the amplitude and phase angle of all actual optimal virtual admittances to obtain the fitting curve:

[0085]

[0086] where P L is the load power, and a k1 , a k2 , a k3 , a k4 , b k1 , b k2 , b k3 , b k4 are all undetermined fitting coefficients in the fitting curve.

[0087] The method for determining the optimal virtual admittance corresponding to the current load power is as follows:

[0088] Collect the input voltage u in of the converter and the input current i L of the boost inductor L in the converter, and perform AD conversion; calculate the current load power; determine the optimal virtual admittance corresponding to the current load power from the optimal virtual admittance fitting curve.

[0089] If the virtual admittance is directly superimposed on the reference current component or the modulation voltage component, the discretization is relatively complex, and due to the influence of the current loop bandwidth, the algorithm will become more complex, and at the same time, the burden on the controller will increase. Therefore, harmonic extraction is performed on the digital signal of the converter input voltage u in , and then the damping distribution strategy is adopted to distribute the virtual admittance current into the reference current component and the modulation voltage component to achieve the effect of active damping.

[0090] Finally, the obtained virtual admittance is injected into the control loop through damping distribution to realize the adaptive control of the virtual admittance, so as to achieve excellent performance under a wide load range.

[0091] At the harmonic frequency ω d , the expression of the actual virtual admittance Y d (s) obtained based on the optimal virtual admittance curve is:

[0092]

[0093] Combined with Figure 1 as shown, the damping distribution strategy in this embodiment is:

[0094] After the converter input voltage u in is transformed by the analog-to-digital converter ADC, the harmonic voltage u h is obtained through a band-pass filter; at the same time, after the converter input voltage u in is transformed by the analog-to-digital converter ADC, the input voltage phase angle value θ is obtained through the phase-locked loop PLL; then the sine value of the input voltage phase is solved, and the zero-crossing detection result is output through the zero-crossing detection link ZCD;

[0095] Optimal virtual admittance Y corresponding to the current load power determined by the optimal virtual admittance fitting curve d Through the current feedback coefficient K is The link obtains the reference current component and the grid-side voltage harmonic transfer function G d1 ; At the same time through The link obtains the modulation voltage component and the grid-side voltage harmonic transfer function G d2 ; u h Through G d2 Obtain the modulation voltage component u yh ; At the same time through G d1 Obtain the reference current component i yh ;

[0096] Reference voltage u ref After subtracting the bus voltage u dc after analog-to-digital conversion, through the transfer function G of the voltage controller vc Obtain the output current i of the voltage controller vco ; The output current i of the voltage controller vco After multiplying by the sine value of the phase of the input voltage, the reference current i ref is obtained; The reference current i ref Adding to the reference current component i yh and then subtracting the analog-to-digital conversion result of the input current i L of the boost voltage L to obtain the error current i err , and then through the current controller to obtain the output voltage u ico ;

[0097] Output voltage u ico Adding to the modulation voltage component u yh and combining with the feedforward signal d f Input to the PWM link; The PWM link combines the zero-crossing detection result to generate the control signal of the switch, and finally realizes the suppression of the grid-side current harmonics. Specific embodiment:

[0099] Next, verify the effectiveness of the harmonic suppression method of the GaN totem-pole bridgeless PFC converter based on adaptive virtual admittance proposed by the present invention on the GaN totem-pole bridgeless PFC converter experimental platform.

[0100] The parameters of the experimental platform are set as follows: grid voltage 220Vrms, grid frequency 50Hz, switching frequency 150kHz, control frequency 50kHz, boost inductor 500μH, bus capacitor 940μF, differential-mode capacitor 4μF, differential-mode inductor 80μH, common-mode capacitor 5.1μF, common-mode inductor 4mH.

[0101] To verify the effectiveness of the proposed method under dynamic variable load conditions, the dynamic test results of the load power increasing from 600 W to 1200 W and then decreasing to 900 W are as follows Figure 7 shown. As can be seen from Figure 7 , the amplitude and phase angle of the virtual admittance change adaptively with the load power, and the change trend is consistent with the Figure 5 and Figure 6 shown fitting curves. Therefore, under dynamic variable load conditions, the method of the present invention can effectively suppress the grid-side current harmonics and has good adaptability.

[0102] To further verify the effectiveness and adaptability of the method of the present invention under different load conditions, with a step of 150 W, the actual input voltage and current waveforms are respectively tested under the conditions of 0.1 - 1 times the rated power (150 W - 1500 W) without using the harmonic suppression strategy, using a fixed virtual admittance, and using the adaptive strategy, and Fourier analysis is carried out. Taking 900 W as an example, the steady-state test results are respectively as follows Figure 8 , Figure 9 and Figure 10 shown. As can be seen from Figure 8 , Figure 9 and Figure 10 , the 17th harmonic amplitudes of the grid-side current without using the harmonic suppression strategy, using a fixed virtual admittance, and using the adaptive strategy under a 900 W load are 0.2451 A, 0.0290 A, and 0.0037 A respectively, which decrease significantly in turn. The 17th harmonic of the grid-side current and the current harmonic standard in the three cases of not using the virtual admittance, using a fixed virtual admittance, and using the adaptive strategy at each power are compared and analyzed, and the comparison diagram is as follows Figure 11 shown. As can be seen from Figure 11 , the 17th harmonic of the grid-side current in the three cases decreases in turn. Before using the virtual admittance strategy, it does not meet the current harmonic standard. After using the fixed virtual admittance, it can meet the current harmonic standard, but the adaptability is not ideal under a wide load range. After introducing the adaptive strategy, the 17th current harmonic further decreases, and a good suppression effect can be maintained under different loads.

[0103] Although the present invention has been described in reference to specific embodiments herein, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed, as long as they do not deviate from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the different dependent claims and the features described herein can be combined in a manner different from that described in the original claims. It should also be understood that the features described in connection with a single embodiment can be used in other described embodiments.

Claims

1. A GaN totem pole bridgeless PFC converter harmonic suppression method based on adaptive virtual admittance, characterized in that include, The virtual admittance vector is decoupled in the polar coordinate system, and the optimal value is sought under different set load powers to obtain the theoretical optimal virtual admittance set under different set load powers; Based on the system delay caused by the bandpass filter in the damping allocation strategy, the theoretical optimal virtual admittance set is compensated to obtain the actual optimal virtual admittance set; The piecewise cubic Hermite interpolation method is used to fit the actual optimal virtual admittance set to obtain the optimal virtual admittance fitting curve in the full load power range. The current load power is calculated, and the corresponding optimal virtual admittance is determined by the optimal virtual admittance fitting curve; the optimal virtual admittance is allocated as a reference current component and a modulation voltage component using a damping allocation strategy, and injected into a control loop to realize an adaptive mechanism of virtual admittance; thereby suppressing the target current harmonics on the grid side under a wide load power range.

2. The method for harmonic suppression of GaN totem pole bridgeless PFC converter based on adaptive virtual admittance according to claim 1, characterized in that: The expression for decoupling the virtual admittance vector in the polar coordinate system is: Where Y d is the virtual admittance vector, |Y d | is the virtual admittance amplitude, θ d is the virtual admittance phase angle, ω d is the harmonic frequency, and s is a complex variable.

3. The method for harmonic suppression of GaN totem pole bridgeless PFC converter based on adaptive virtual admittance according to claim 2, characterized in that: The method to obtain the theoretical optimal virtual admittance set for different set load powers is: According to the converter system at the harmonic frequency ω after considering non-ideal factors d The system input admittance model at is proposed, with the amplitude and phase angle of the virtual admittance as independent variables, the system input admittance at the harmonic frequency as the dependent variable, and the virtual admittance amplitude and phase angle corresponding to the minimum system input admittance amplitude at the harmonic frequency are taken as the theoretical optimal virtual admittance; the test is repeated under different set load powers to obtain the theoretical optimal virtual admittance set for different set load powers.

4. The method for harmonic suppression of GaN totem pole bridgeless PFC converter based on adaptive virtual admittance according to claim 3, characterized in that: After considering non-ideal factors, the converter system is at the harmonic frequency ω d The system input admittance model at is: Where Y g_d is the system input admittance, Y L is the converter input admittance, Y DM is the differential mode capacitance admittance, L DM is the differential mode inductance in the EMI filter, R g is the equivalent resistance of the converter front-end circuit; Y DM (s)=sC DM , Where C DM is the differential mode capacitance; Where g in K is the ratio of the converter input power to the effective value of the input voltage, ib is the reciprocal of the current reference value, G ic is the current controller transfer function, G id The s-domain form of the converter input current I L The transfer function between the duty cycle (s) and the duty cycle s-domain form D(s) of the PFC converter, T d is the digital control system delay of the converter, 1 / V m is the PWM link gain, T i is the loop gain transfer function, G iv The s-domain form of the converter input current I L (s) and the converter input voltage s domain form U in (s) transfer function between; G iv (s)=1 / (sL), G id (s)=U dc / (sL), Where U dc is the DC value of the converter output voltage, K is is the current feedback coefficient.

5. The method for harmonic suppression of GaN totem pole bridgeless PFC converter based on adaptive virtual admittance according to claim 4, characterized in that: The method to obtain the actual optimal virtual admittance set is: The actual optimal virtual admittance set is obtained by compensating the phase angle of the virtual admittance in the theoretical optimal virtual admittance set.

6. The method for harmonic suppression of a GaN totem pole bridgeless PFC converter based on adaptive virtual admittance according to claim 5, characterized in that: The method to obtain the optimal virtual admittance fitting curve for the full load power range is: Perform piecewise cubic Hermite interpolation on the amplitude and phase angle of all actual optimal virtual admittances to obtain the fitting curve: Where P L is the load power, a k1 、a k2 、a k3 、a k4 、b k1 、b k2 、b k3 、b k4 are all the undetermined fitting coefficients in the fitting curve.

7. The method for harmonic suppression of GaN totem pole bridgeless PFC converter based on adaptive virtual admittance according to claim 6, characterized in that: The method to determine the optimal virtual admittance corresponding to the current load power is: Collect the converter input voltage u in and the input current i of the boost inductor L in the converter L , and perform AD conversion; The current load power is obtained by calculation; and the optimal virtual admittance corresponding to the current load power is determined by the optimal virtual admittance fitting curve.

8. The method for harmonic suppression of GaN totem pole bridgeless PFC converter based on adaptive virtual admittance according to claim 7, characterized in that: At the harmonic frequency ω d At the optimal virtual admittance curve, the actual virtual admittance Y d (s) is expressed as:

9. The method for harmonic suppression of GaN totem pole bridgeless PFC converter based on adaptive virtual admittance according to claim 8, characterized in that: The damping allocation strategy is: Converter input voltage u in After conversion by analog-to-digital converter ADC, the harmonic voltage u is obtained through bandpass filter. h ; At the same time, the converter input voltage u in After conversion by the analog-to-digital converter ADC, the input voltage phase angle value θ is obtained through the phase-locked loop PLL; then the sin value of the input voltage phase is solved, and the zero-crossing detection result is output through the zero-point detection link ZCD; The optimal virtual admittance Y corresponding to the current load power is determined by the optimal virtual admittance fitting curve d Current feedback coefficient K is The reference current component and the grid-side voltage harmonic transfer function G are obtained by d1 ; At the same time The link obtains the modulated voltage component and the grid-side voltage harmonic transfer function G d2 ;u h G d2 Get the modulation voltage component u yh ; At the same time, G d1 Get the reference current component i yh ; Reference voltage u ref The bus voltage u after analog-to-digital conversion dc After the difference is made, the transfer function G of the voltage controller vc The voltage controller output current i is obtained vco ; Voltage controller output current i vco The reference current i is obtained by multiplying the sin value of the input voltage phase ref ; Reference current i ref With the reference current component i yh After adding, subtract the input current i of the boost voltage L L The analog-to-digital conversion result is the error current i err , and then the output voltage u is obtained through the current controller ico ; Output voltage ico With the modulation voltage component u yh After addition, combined with the feedforward signal d f Input to the PWM link; the PWM link generates a switch control signal based on the zero-crossing point detection result, and finally suppresses the grid-side current harmonics.

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