PWM signal generation method, microcontroller and PWM generation circuit

Abstract

The embodiment of the invention discloses a PWM signal generation method. The generation method comprises the following steps: determining setting delay time and reset delay time of an nth PWM delay signal, and determining a first comparison result of the setting delay time and a preset clock period and a second comparison result of the reset delay time and the preset clock period, and allocating a first delay time to the delay module and allocating a first comparison threshold to the first comparator according to the first comparison result, and allocating a second delay time to the delay module and allocating a second comparison threshold to the second comparator according to the second comparison result. According to the embodiment of the invention, the method does not need to depend on a high-precision clock chip, can achieve the delay processing of the PWM signal through the fine adjustment operation on a low-cost hardware circuit, can achieve the delay of the duty ratio, can also achieve the delay of the signal period, is higher in time resolution, and is higher in precision. And more accurate and stable PWM signals can be output.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of electronic technologies, and in particular, to a method for generating a PWM signal, a microcontroller, and a PWM generation circuit. Background Art

[0002] With the rapid development of electronic technologies, digital PWM (Pulse Width Modulation) technology has been widely applied in the fields of power electronics, motor control, industrial automation, etc. When the project requires the digital pulse width modulation signal circuit to output various PWM signals, due to the problem of insufficient accuracy in the traditional digital pulse width modulation signal circuit, it cannot accurately output various PWM signals. Related technologies can accurately output various PWM signals through the programming method of a microprocessor. However, this approach requires relying on a very high clock frequency output by the chip, and the cost of such chips is relatively high, thus driving up the production cost of the digital pulse width modulation signal circuit. Summary of the Invention

[0003] An object of embodiments of the present application is to provide a method for generating a PWM signal, a microcontroller, and a PWM generation circuit, so as to solve the technical problem that related technologies need to rely on a high clock frequency to output high-precision PWM signals.

[0004] In a first aspect, an embodiment of the present application provides a method for generating a PWM signal. The generating method includes: determining the set delay time and the reset delay time of the nth PWM delay signal, where the set delay time is the time for delaying the setting to output the high level of the nth PWM delay signal, and the reset delay time is the time for delaying the reset to output the low level of the nth PWM delay signal, and n is a positive integer; determining a first comparison result between the set delay time and a preset clock period, and a second comparison result between the reset delay time and the preset clock period; allocating a first delay time to a delay module and a first comparison threshold to a first comparator according to the first comparison result, so that when the count value output by a counter to the first comparator is equal to the first comparison threshold, the first comparator outputs a set high level, and after the set high level is processed by the delay module for the first delay time, it is then transmitted to the set end of a latch, so that the latch outputs the nth high level, and the total delay time of the delay module is less than or equal to the preset clock period; allocating a second delay time to the delay module and a second comparison threshold to a second comparator according to the second comparison result, so that when the count value output by the counter to the second comparator is equal to the second comparison threshold, the second comparator outputs a reset high level, and after the reset high level is processed by the delay module for the second delay time, it is then transmitted to the reset end of the latch, so that the latch outputs the nth low level, and the nth high level and the nth low level form the nth PWM delay signal.

[0005] The PWM generation circuit provided by the embodiment of the present application can not only be compatible with the coarse adjustment situation, but also be compatible with the fine adjustment situation, and does not need to rely on a high-precision clock chip. It can perform the delay processing of the PWM signal through the fine adjustment operation on a low-cost hardware circuit. Among them, not only can the duty cycle be delayed, but also the signal period can be delayed, and the time resolution involved in the delay is relatively high, which is beneficial to output a more accurate and stable PWM signal.

[0006] Optionally, determining the set delay time of the nth PWM delay signal includes: determining a high-level delay time, where the high-level delay time is the time difference between the high level of the PWM delay signal and the high level of the PWM original signal, and multiplying n by the high-level delay time to obtain the set delay time of the nth PWM signal.

[0007] Optionally, determining the reset delay time of the nth PWM signal includes: determining a period delay time, where the period delay time is the difference between the signal period of the PWM delay signal and the signal period of the PWM original signal, and adding the set delay time and the period delay time to obtain the reset delay time of the nth PWM signal.

[0008] Optionally, the step of allocating a first delay time to the delay module according to the first comparison result includes: in response to the first comparison result indicating that the set delay time is greater than or equal to a preset clock cycle, dividing the set delay time by the preset clock cycle to obtain a first remainder, and determining the first remainder as the first delay time; in response to the first comparison result indicating that the set delay time is less than the preset clock cycle, determining the set delay time as the first delay time.

[0009] Optionally, the delay module includes a first delay unit, and the first delay unit includes a first selector and a plurality of first delay elements connected in series in sequence. The total delay time of all the first delay elements is less than or equal to the preset clock cycle. The generating method further includes: determining a first delay stage number based on the first delay time and the delay time of the first delay element, and controlling the first selector to select a corresponding number of first delay elements according to the first delay stage number, so that the corresponding number of first delay elements perform a first delay time process on the set high level.

[0010] Optionally, the step of allocating a first comparison threshold to the first comparator according to the first comparison result includes: obtaining a first local threshold of the first comparator, in response to the first comparison result indicating that the set delay time is greater than or equal to the preset clock cycle, adding a first specified value to the first local threshold to obtain a first comparison threshold, where the first specified value is the quotient obtained by dividing the set delay time by the preset clock cycle; in response to the first comparison result indicating that the set delay time is less than the preset clock cycle, determining the first local threshold as the first comparison threshold.

[0011] Optionally, the step of allocating a second delay time to the delay module according to the second comparison result includes: in response to the second comparison result indicating that the reset delay time is greater than or equal to the preset clock cycle, dividing the reset delay time by the preset clock cycle to obtain a second remainder, and determining the second remainder as the second delay time; in response to the second comparison result indicating that the reset delay time is less than the preset clock cycle, determining the reset delay time as the second delay time.

[0012] Optionally, the delay module includes a second delay unit, the second delay unit includes a second selector and a plurality of second delayers connected in series in sequence, the total delay time of all the second delayers is less than or equal to a preset clock cycle, and the generating method further includes: determining a second delay stage number based on the second remainder and the delay time of the second delayer, and controlling the second selector to select and enable the second delayers corresponding to the second delay stage number, so that the second delayers corresponding to the second delay stage number perform a second delay time process on the reset high level.

[0013] Optionally, the allocating a second comparison threshold to the second comparator according to the second comparison result includes: obtaining a second local threshold of the second comparator, in response to the second comparison result indicating that the reset delay time is greater than or equal to the preset clock cycle, adding a second specified value to the second local threshold to obtain a second comparison threshold, where the second specified value is the quotient obtained by dividing the reset delay time by the preset clock cycle, and in response to the second comparison result indicating that the reset delay time is less than the preset clock cycle, determining the second local threshold as the second comparison threshold.

[0014] Optionally, the generating method further includes: determining a current counting cycle of the counter according to the reset delay time and an original counting cycle of the counter, and in response to the count value of the counter being equal to the current counting cycle, performing a clearing operation on the counter.

[0015] In a second aspect, an embodiment of the present application provides a microcontroller, including a memory and a processor, the memory is connected to the processor, the processor is configured to execute one or more computer programs stored in the memory, and when the processor executes the one or more computer programs, the microcontroller implements the above-mentioned PWM signal generating method.

[0016] In a third aspect, an embodiment of the present application provides a PWM generating circuit, including a counter, a first comparator, a second comparator, a first delay unit, a second delay unit, a latch, and the above-mentioned microcontroller, the microcontroller is respectively communicatively connected to the counter, the first comparator, the second comparator, the first delay unit, and the second delay unit, the timer is respectively communicatively connected to the first comparator and the second comparator, the first comparator is communicatively connected to the first delay unit, the second comparator is communicatively connected to the second delay unit, a set end of the latch is communicatively connected to an output end of the first delay unit, and a reset end of the latch is communicatively connected to an output end of the second delay unit.

[0017] In a fourth aspect, an embodiment of the present application provides a digital pulse width modulation signal circuit, including the above-mentioned PWM generation circuit.

[0018] In a fifth aspect, an embodiment of the present application provides an electronic device, including the above-mentioned PWM generation circuit.

[0019] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a processor, the processor is caused to execute the above-mentioned method for generating a PWM signal.

[0020] The embodiments of the present application can achieve the following technical effects: The PWM generation circuit provided by the embodiments of the present application can not only be compatible with the coarse adjustment situation, but also be compatible with the fine adjustment situation, and does not need to rely on a high-precision clock chip. It can implement the delay processing of the PWM signal through fine adjustment operations on a low-cost hardware circuit. Among them, not only can the duty cycle be delayed, but also the signal period can be delayed, and the time resolution involved in the delay is relatively high, which is beneficial to output a more accurate and stable PWM signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 It is a schematic circuit diagram of a PWM generation circuit provided by an embodiment of the present application;

[0023] Figure 2 It is a schematic circuit diagram of a PWM generation circuit provided by another embodiment of the present application;

[0024] Figure 3 It is a schematic circuit diagram of a PWM generation circuit provided by still another embodiment of the present application;

[0025] Figure 4 It is a timing diagram of a PWM original signal and a PWM delayed signal provided by an embodiment of the present application;

[0026] Figure 5 It is a schematic flowchart of a method for generating a PWM signal provided by an embodiment of the present application;

[0027] Figure 6 It is a schematic structural diagram of a device for generating a PWM signal provided by an embodiment of the present application;

[0028] Figure 7 This is a schematic structural diagram of a microcontroller provided by an embodiment of the present application. Specific embodiments

[0029] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0030] It should be noted that if there is no conflict, the various features in the embodiments of the present application can be combined with each other, and all are within the protection scope of the present application. In addition, although functional module division is performed in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from the module division in the device or the flowchart. Furthermore, the terms "first", "second", "third", etc. used in the present application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and effects.

[0031] When the related technology needs a PWM signal with a fixed output signal period and duty cycle from a PWM generation circuit, the circuit structure of the PWM generation circuit usually includes a cyclic counter and a comparator. When the count value output by the cyclic counter to the comparator is less than the comparison threshold of the comparator, the comparator outputs a low level. When the count value output by the cyclic counter to the comparator is greater than or equal to the comparison threshold of the comparator, the comparator outputs a high level. When the count value of the cyclic counter reaches the preset count threshold, the cyclic counter automatically clears and starts counting again.

[0032] The architecture of such a PWM generation circuit is not only simple, but also runs stably and reliably. However, the time resolution that can be achieved by this method is limited by the clock period of the counter. If it is desired to finely control the signal period and duty cycle of the PWM to an accuracy of 1 nanosecond (ns), the corresponding clock frequency needs to be as high as 1 gigahertz (GHz). Further, if picosecond (ps)-level accuracy is pursued, it will lead to huge cost investment, which is unacceptable from the perspective of chip mass production.

[0033] Hereinafter, an embodiment of the present application provides a PWM generation circuit, which can be applied to a digital pulse width modulation signal circuit or an electronic device. For example, the electronic device is a switching power supply device, and the digital pulse width modulation signal circuit including the PWM generation circuit can provide a PWM signal for the switching power supply device.

[0034] Please refer toFigure 1 , the PWM generation circuit 100 includes a counter 11, a first comparator 12, a second comparator 13, a delay module 14, a latch 15, and a microcontroller 16.

[0035] The counter 11 is communicatively connected to the microcontroller 17. Among them, the counter 11 is configured with an original counting period. The microcontroller 17 sends a clock signal to the counter 11, and the counter 11 counts based on the clock signal to output a count value. In this article, the preset clock period of the clock signal is defined as c.

[0036] The first comparator 12 is communicatively connected to the counter 11 and the microcontroller 17 respectively. Specifically, the first comparator 12 includes two input terminals. One input terminal is communicatively connected to the output terminal of the counter 11, and the other input terminal is communicatively connected to the microcontroller 17. The microcontroller 17 can configure a first comparison threshold for the other input terminal of the first comparator 12 (for example, the expression of the first comparison threshold is "=0"). For example, the first comparison threshold is 0 or 1 or 2, etc. When the counter 11 starts receiving the clock signal for counting, if the first comparison threshold is 0, when the counter 11 outputs a count value i = 0, the first comparator 12 outputs a high level, and when the counter 11 outputs a count value i that is not 0, the first comparator 12 outputs a low level. For another example, if the first comparison threshold is 1, when the counter 11 outputs a count value i = 0, the first comparator 12 outputs a low level. When the counter 11 outputs a count value i = 1, the first comparator 12 outputs a high level.

[0037] The second comparator 13 is communicatively connected to the counter 11 and the microcontroller 17 respectively. Specifically, the second comparator 13 includes two input terminals. One input terminal is communicatively connected to the output terminal of the counter 11, and the other input terminal is communicatively connected to the microcontroller 17. The microcontroller 17 can configure a second comparison threshold for the other input terminal of the second comparator 13 (for example, the expression of the second comparison threshold is "=NUM"). The second comparison threshold is greater than the first comparison threshold. Exemplarily, the second comparison threshold is 5 or 6 or 7 or 8, etc.

[0038] For example, if the second comparison threshold is 8, when the counter 11 outputs a count value i = 8, the second comparator 13 outputs a high level, and when the counter 11 outputs a count value i that is not 8, the second comparator 13 outputs a low level. For another example, if the second comparison threshold is 9, when the counter 11 outputs a count value i = 8, the second comparator 13 outputs a low level. When the counter 11 outputs a count value i = 9, the first comparator 12 outputs a high level.

[0039] The delay module 14 is communicatively connected to the first comparator 12 and the second comparator 13 respectively and is also controlled by the microcontroller 17, and is used to delay and output the high levels output by the first comparator 12 and the second comparator 13 respectively. The delay module 14 provides multiple delay levels. The higher the delay level, the longer the delay time; the lower the delay level, the shorter the delay time.

[0040] The microcontroller 17 can control the delay module 14 to select the corresponding delay level to delay and output the high levels output by the first comparator 12 and the second comparator 13 respectively.

[0041] The total delay time of the delay module 14 is less than or equal to a preset clock cycle. For example, the total delay time η of the delay module 14 = k * Δt, where k is the total number of levels of the delay module 14, Δt is the delay time of each delay level, and η is the total delay time. The delay time of the high level of the PWN signal is H t = e * c + g, where e is a positive integer, g is less than c, and the expression of g can be: g = h * Δt, and h is less than k. In the embodiment of the present application, the first delay time is allocated to the delay module 14 according to the time g, and the delay level h is selected.

[0042] In the case where the delay time of the high level of the PWN signal is not an integral multiple of the clock frequency, or in the case where the delay time of the signal period of the PWN signal is not an integral multiple of the clock frequency, the embodiment of the present application can utilize the feature that "the total delay time of the delay module 14 is less than or equal to the preset clock cycle" to meet the requirement of outputting a more accurate high level time or a more accurate signal period.

[0043] In some embodiments, please refer to Figure 2 , the delay module 14 includes a first delay unit 141 and a second delay unit 142.

[0044] The first delay unit 141 is communicatively connected to the first comparator 12 and the microcontroller 16 respectively, and the output end of the first delay unit 141 is communicatively connected to the set end S of the latch 15. The microcontroller 16 configures the first delay time for the first delay unit 141. When the count value output by the counter 11 is equal to the first comparison threshold of the first comparator 12, the first comparator 12 outputs a high level to the first delay unit 141, and the first delay unit 141 performs a delay process on the high level for the first delay time and finally outputs it to the set end S of the latch 15.

[0045] The second delay unit 142 is communicatively connected to the second comparator 13 and the microcontroller 16 respectively, and the output end of the second delay unit 142 is communicatively connected to the reset end R of the latch 15. The microcontroller 16 configures a second delay time for the second delay unit 142. When the count value output by the counter 11 is equal to the second comparison threshold of the second comparator 13, the second comparator 13 outputs a high level to the second delay unit 142, and the second delay unit 142 delays the high level for the second delay time and finally outputs it to the reset end R of the latch 15.

[0046] In some embodiments, please refer to Figure 3 , the first delay unit 141 includes a plurality of first delayers 1411 and a first selector 1412. The plurality of first delayers 1411 are connected in series in sequence. The first selector 1412 is a multi-selector, for example, the first selector 1412 is a 64-to-1 selector. The first selector 1412 includes a plurality of channel input ends and an output end. One channel input end is communicatively connected to the output end of a first delayer 1411, and the output end of the first selector 1412 is communicatively connected to the set end S of the latch 15.

[0047] The microcontroller 16 selects a corresponding number of first delayers 1411 according to the delay stage number to delay and output the high level output by the first comparator 12. Among them, the delay time of each first delayer is the same, and the sum of the delay times of the plurality of first delayers 1411 is the total delay time. The total delay time is less than the preset clock cycle, and the delay stage number multiplied by the delay time of the first delayer 1411 is equal to the first delay time.

[0048] In some embodiments, please continue to refer to Figure 3 , the second delay unit 142 includes a plurality of second delayers 1421 and a second selector 1422. The plurality of second delayers 1421 are connected in series in sequence. The second selector 1422 is a multi-selector, for example, the second selector 1422 is a 64-to-1 selector. The second selector 1422 includes a plurality of channel input ends and an output end. One channel input end is communicatively connected to the output end of a second delayer 1421, and the output end of the second selector 1422 is communicatively connected to the reset end R of the latch 15.

[0049] The microcontroller 16 selects a corresponding number of second delayers 1421 according to the delay stage number to delay and output the high level output by the first comparator 12. Among them, the delay time of each second delayer 1421 is the same, and the sum of the delay times of the plurality of second delayers 1421 is the total delay time. The total delay time is less than the preset clock cycle, and the delay stage number multiplied by the delay time of the first delayer 1411 is equal to the first delay time.

[0050] The latch 15 can be any type of latch. Exemplarily, the latch 15 includes an SR latch, a D flip-flop, a JK latch, etc.

[0051] The microcontroller 16 is capable of controlling the above-mentioned devices to work together to generate a PWM signal.

[0052] To elaborate in detail on the working principle of the PWM generation circuit provided in the embodiments of the present application, the embodiments of the present application are combined with the attached Figure 4 to make a detailed description thereof. It can be understood that the "delay" described in the embodiments of the present application is based on the situation of "no delay", and the situation of "no delay" is the situation where the first delay unit and the second delay unit do not participate in the generation of the PWM signal. In this article, the situation of "the first delay unit and the second delay unit do not participate in the generation of the PWM signal" is defined as the coarse adjustment situation. The situation of "delay" is the situation where the first delay unit and the second delay unit participate in the generation of the PWM signal. In this article, the situation of "the first delay unit and the second delay unit participate in the generation of the PWM signal" is defined as the fine adjustment situation. First, the first comparison threshold of the first comparator is "=0", and the second comparison threshold of the second comparator is "=NUM".

[0053] ① The embodiments of the present application are combined with the attached Figure 4 to make an explanation of the coarse adjustment situation:

[0054] As Figure 4 shown, the counter is triggered by the rising edge of the 3rd clock signal to start counting. When the count value of the counter is 0, the first comparator outputs a high level. The microcontroller 16 does not control the first selector 1412 to select any one of the first delayers 1411, but directly controls the first selector 1412 to directly output the high level output by the first comparator. At this time, the high level is regarded as the original set signal S(n). The original set signal S(n) is applied to the set terminal S of the latch 15, and the latch 15 outputs a high level and latches the high level.

[0055] When the count value of the counter is NUM at the falling edge of the 4th clock signal, the second comparator outputs a high level. The microcontroller 16 does not control the second selector 1422 to select any one of the second delayers 1421, but directly controls the second selector 1422 to directly output the high level output by the second comparator. At this time, the high level is regarded as the original reset signal R(n). The original reset signal R(n) is applied to the reset terminal R of the latch 15, and the latch 15 outputs a low level and latches the low level.

[0056] When the count value of the counter reaches the preset count threshold at the 6th clock signal, the counter starts to clear. So far, the latch 15 has been able to output a complete PWM original signal origin_pwm.

[0057] When the rising edge of the 7th clock signal arrives, the counter starts counting, outputs a count value of 0, and outputs the next PWM original signal origin_pwm according to the above process.

[0058] ② The embodiments of the present application will be described in conjunction with the attached Figure 4 An explanation of the fine-tuning situation will be given:

[0059] First, the set delay time is Nα, and the reset delay time is Nα + β, where α is the time difference between the high levels of two adjacent PWM signals. In Figure 4 , α is 0.5c (i.e., half of the clock period). β is the difference in the signal periods of two adjacent PWM signals. In Figure 4 , β is 0.5c (i.e., half of the clock period).

[0060] As Figure 4 shown, the counter is triggered by the rising edge of the 3rd clock signal to start counting. When the count value of the counter is 0, the first comparator outputs a high level. The microcontroller 16 needs to control the first delay unit 141 to perform a first delay time processing of 1*α, that is, control the first selector 1412 to select the corresponding number of first delayers 1411 for the first delay time processing. After the high level output by the first comparator passes through the first delay time processing, it is then output to the set terminal S of the latch 15. At this time, the high level is regarded as the delayed set signal S_P(n). The delayed set signal S_P(n) is applied to the set terminal S of the latch 15, and the latch 15 outputs a high level and latches the high level.

[0061] When the count value of the counter at the falling edge of the 4th clock signal is NUM, the second comparator outputs a high level. The microcontroller 16 needs to control the second delay unit 142 to perform a second delay time processing of 1*α + β (i.e., 1c), that is, control the first selector 1412 to select the corresponding number of second delayers 1411 for the second delay time processing. Or, since the second delay time is a complete clock cycle, the microcontroller 16 does not need to control the second delay unit 142 to work, but increases the second comparison threshold of the second comparator by the natural number 1, which can also equivalently achieve the delay. After the high level output by the second comparator passes through the delay processing, it is then output to the reset terminal R of the latch 15. At this time, the high level is regarded as the delayed reset signal R_P(n). The delayed reset signal R_P(n) is applied to the reset terminal R of the latch 15, and the latch 15 outputs a low level and latches the low level.

[0062] When the count value of the counter reaches the preset count threshold at the 7th clock signal, the counter starts to clear. So far, the latch 15 has been able to output a complete PWM delay signal delay_pwm.

[0063] When the rising edge of the 8th clock signal arrives, the counter starts counting, outputs the count value 0, and outputs the next PWM delay signal delay_pwm according to the above process.

[0064] Furthermore, from Figure 4 it can be seen that the first original set signal S(n) and the first delayed set signal S_P(n) differ by 1 α, the second original set signal S(n) and the second delayed set signal S_P(n) differ by 2 α, the third original set signal S(n) and the third delayed set signal S_P(n) differ by 3 α, and so on.

[0065] Similarly, the first original reset signal R(n) and the first delayed reset signal R_P(n) differ by (α + β), the second original reset signal R(n) and the second delayed reset signal R_P(n) differ by (2*α + β), the third original reset signal R(n) and the third delayed reset signal R_P(n) differ by (3*α + β), and so on.

[0066] The PWM generation circuit provided by the embodiments of the present application can not only be compatible with the coarse adjustment situation, but also be compatible with the fine adjustment situation, and does not need to rely on a high-precision clock chip. It can perform delay processing on the PWM signal through fine adjustment operations on a low-cost hardware circuit. Among them, it can not only delay the duty cycle, but also delay the signal period. The time resolution involved in the delay is relatively high, which is beneficial to output a more accurate and stable PWM signal.

[0067] Next, the embodiments of the present application provide a method for generating a PWM signal. Here, the PWM signal can be the PWM original signal origin_pwm described in the above embodiments when one condition is met, and can be the PWM delay signal delay_pwm described in the above embodiments when another condition is met.

[0068] Please refer to Figure 5 , the method for generating a PWM signal includes steps S51 to S54.

[0069] The embodiments of the present application execute step S51 to determine the set delay time and reset delay time of the nth PWM signal.

[0070] The set delay time is the time for delaying the set to output the high level of the nth PWM signal, and n is a positive integer. As Figure 4As shown in the figure, for the first PWM delay signal delay_pwm, relative to the first PWM original signal origin_pwm, in the embodiments of the present application, the first selector is controlled to select a corresponding number of first delay elements to delay the high level output by the first comparator for a delay time (0.5c). Only then can the latch output the high level of the first PWM delay signal delay_pwm. Therefore, the delay time 0.5c is the set delay time. For the second PWM delay signal delay_pwm, relative to the second PWM original signal origin_pwm, in the embodiments of the present application, the first selector is controlled to select a corresponding number of first delay elements to delay the high level output by the first comparator for a delay time (a preset clock cycle c), or increase the second comparison threshold of the second comparator by the natural number 1 to equivalently achieve the delay. Only then can the latch output the high level of the second PWM delay signal delay_pwm. Therefore, the delay time c is the set delay time.

[0071] Determining the set delay time of the nth PWM signal includes the following steps: determining the high-level delay time, which is the time difference between the high level of the PWM delay signal and the high level of the PWM original signal, and multiplying n by the high-level delay time to obtain the set delay time of the nth PWM signal. Exemplarily, the time difference between the high level of the PWM delay signal and the high level of the PWM original signal is α, the high-level delay time is α, and the set delay time is nα.

[0072] For example, for the first PWM delay signal, the set delay time P of the first PWM delay signal is 1α. For another example, for the second PWM delay signal, the set delay time P of the second PWM delay signal is 2α. And so on.

[0073] The reset delay time is the time for delaying the reset to output the low level of the nth PWM signal. Determining the reset delay time of the nth PWM signal includes the following steps: determining the period delay time, which is the difference between the signal period of the PWM delay signal and the signal period of the PWM original signal, and adding the set delay time and the period delay time to obtain the reset delay time of the nth PWM signal. For example, the difference between the signal period of the PWM delay signal and the signal period of the PWM original signal is β, the period delay time is β, and the reset delay time is nα + β.

[0074] For example, for the first PWM delay signal, the reset delay time W of the first PWM delay signal is 1α + β. For another example, for the second PWM delay signal, the reset delay time W of the second PWM delay signal is 2α + β. And so on.

[0075] The embodiment of the present application executes step S52 to determine the first comparison result between the set delay time and the preset clock period, and the second comparison result between the reset delay time and the preset clock period.

[0076] The first comparison result includes a first type of result and a second type of result. The first type of result is used to indicate that the set delay time is greater than or equal to the preset clock period. The second type of result is used to indicate that the set delay time is less than the preset clock period. Determining the first comparison result between the set delay time and the preset clock period includes the following steps: in response to the set delay time being greater than or equal to the preset clock period, generating the first type of result; in response to the set delay time being less than the preset clock period, generating the second type of result.

[0077] The second comparison result includes a third type of result and a fourth type of result. The third type of result is used to indicate that the reset delay time is greater than or equal to the preset clock period. The fourth type of result is used to indicate that the reset delay time is less than the preset clock period. Determining the second comparison result between the reset delay time and the preset clock period includes the following steps: in response to the reset delay time being greater than or equal to the preset clock period, generating the third type of result; in response to the reset delay time being less than the preset clock period, generating the fourth type of result.

[0078] The embodiment of the present application executes step S53 to allocate a first delay time to the delay module and a first comparison threshold to the first comparator according to the first comparison result, so that when the count value output by the counter to the first comparator is equal to the first comparison threshold, the first comparator outputs a set high level. After the set high level is processed by the delay module for the first delay time, it is then transmitted to the set end of the latch, so that the latch outputs the nth high level, and the total delay time of the delay module is less than or equal to the preset clock period.

[0079] As Figure 4 shown, for the first PWM delay signal delay_pwm, the first delay time is α. The counter is triggered by the rising edge of the 3rd clock signal to start counting. When the count value of the counter is 0, the first comparator outputs a set high level. The microcontroller needs to control the first delay unit to perform a first delay time processing of 1*α. If α = u*Δt, the microcontroller controls the first selector to select u first delayers to perform the first delay time processing. The set high level output by the first comparator is processed for the first delay time and then output to the set end S of the latch. At this time, the set high level is regarded as the delayed set signal S_P(n). The delayed set signal S_P(n) is applied to the set end S of the latch, and the latch outputs a high level and latches the high level.

[0080] Allocating a first delay time to the delay module according to the first comparison result includes the following steps: In response to the first comparison result indicating that the set delay time is greater than or equal to the preset clock cycle, dividing the set delay time by the preset clock cycle to obtain a first remainder, and determining the first remainder as the first delay time; in response to the first comparison result indicating that the set delay time is less than the preset clock cycle, determining the set delay time as the first delay time.

[0081] For example, if the set delay time p = nα is greater than or equal to the preset clock cycle c, the embodiment of the present application obtains the first delay time according to the following formula: p÷c = nα÷c = x....d1, where x is the quotient obtained by dividing the set delay time by the preset clock cycle, and d1 is the first remainder, and the first remainder d1 is used as the first delay time.

[0082] For another example, if the set delay time p = nα is less than the preset clock cycle c, the embodiment of the present application directly uses the set delay time as the first delay time.

[0083] The delay module includes a first delay unit, and the first delay unit includes a first selector and a plurality of first delay elements connected in series in sequence. The total delay time of all the first delay elements is less than or equal to the preset clock cycle. The generation method further includes the following steps: determining a first delay stage number based on the first delay time and the delay time of the first delay element, and controlling the first selector to select a corresponding number of first delay elements according to the first delay stage number, so that the corresponding number of first delay elements perform a first delay time process on the set high level.

[0084] If the delay time of each first delay element is Δt, the first delay stage number z1 = y÷Δt, where z1 is the first delay stage number and y is the first delay time. The embodiment of the present application selects z1 first delay elements to perform a first delay time process on the set high level.

[0085] Allocating a first comparison threshold to the first comparator according to the first comparison result includes the following steps: obtaining a first local threshold of the first comparator, in response to the first comparison result indicating that the set delay time is greater than or equal to the preset clock cycle, adding a first specified value to the first local threshold to obtain a first comparison threshold, where the first specified value is the quotient obtained by dividing the set delay time by the preset clock cycle; in response to the first comparison result indicating that the set delay time is less than the preset clock cycle, determining the first local threshold as the first comparison threshold.

[0086] For example, the first local threshold of the first comparator is 0. If the set delay time p = nα is greater than or equal to the preset clock period c, as shown below: p÷c = nα÷c = x....d1, where x is the quotient obtained by dividing the set delay time by the preset clock period. In the embodiment of the present application, 0 + x = x, that is, the first comparison threshold is x.

[0087] For another example, if the set delay time p = nα is less than the preset clock period c, the embodiment of the present application directly uses 0 as the first comparison threshold.

[0088] The embodiment of the present application executes step S54, and allocates a second delay time to the delay module and a second comparison threshold to the second comparator according to the second comparison result, so that when the count value output by the counter to the second comparator is equal to the second comparison threshold, the second comparator outputs a reset high level. After the reset high level is processed by the delay module for the second delay time, it is then transmitted to the reset terminal of the latch, so that the latch outputs the nth low level, and the nth high level and the nth low level form the nth PWM delay signal.

[0089] Allocating a second delay time to the delay module according to the second comparison result includes the following steps: in response to the second comparison result indicating that the reset delay time is greater than or equal to the preset clock period, dividing the reset delay time by the preset clock period to obtain a second remainder, and determining the second remainder as the second delay time; in response to the second comparison result indicating that the reset delay time is less than the preset clock period, determining the reset delay time as the second delay time.

[0090] For example, if the reset delay time W = nα + β is greater than or equal to the preset clock period c, the embodiment of the present application obtains the second delay time according to the following formula, as shown below: W÷c = (nα + β)÷c = m....d2, where m is the quotient obtained by dividing the reset delay time by the preset clock period, and d2 is the second remainder. The second remainder d2 is used as the second delay time.

[0091] For another example, if the reset delay time W = nα + β is less than the preset clock period c, the embodiment of the present application directly uses the reset delay time as the second delay time.

[0092] The delay module includes a second delay unit. The second delay unit includes a second selector and a plurality of second delayers connected in series in sequence. The total delay time of all the second delayers is less than or equal to the preset clock period. The generation method further includes the following steps: determining the second delay stage based on the second delay time and the delay time of the second delayers, and controlling the second selector to select and connect the number of second delayers corresponding to the second delay stage, so that the number of second delayers corresponding to the second delay stage processes the reset high level for the second delay time.

[0093] The second delay level z2 = γ÷Δt, where z2 is the second delay level and γ is the second delay time. In the embodiments of the present application, z2 second delay devices are selected to process the set high level for the second delay time.

[0094] Allocating a second comparison threshold for the second comparator according to the second comparison result includes the following steps: obtaining the second local threshold of the second comparator, in response to the second comparison result indicating that the reset delay time is greater than or equal to the preset clock cycle, adding a second specified value to the second local threshold to obtain the second comparison threshold, where the second specified value is the quotient obtained by dividing the reset delay time by the preset clock cycle, and in response to the second comparison result indicating that the reset delay time is less than the preset clock cycle, determining the second local threshold as the second comparison threshold.

[0095] For example, the second local threshold of the second comparator is NUM. If the reset delay time W = nα + β is greater than or equal to the preset clock cycle c, as follows: W÷c = (nα + β)÷c = m....d2, where m is the quotient obtained by dividing the reset delay time by the preset clock cycle, and in the embodiments of the present application, the second comparison threshold NUM = NUM + m.

[0096] For another example, if the reset delay time W = nα + β is less than the preset clock cycle c, in the embodiments of the present application, the second local threshold NUM is directly used as the second comparison threshold.

[0097] It can be understood that in some embodiments, in the delay scenario, the original counting cycle of the counter can continue to be used in the embodiments of the present application. In some embodiments, in the delay scenario, the current counting cycle of the counter can be determined according to the reset delay time and the original counting cycle of the counter. In response to the count value of the counter being equal to the current counting cycle, a clear operation is performed on the counter. For example, the current counting cycle T' = T + nα + β of the counter, where T' is the current counting cycle and T is the original counting cycle. When the count value of the counter is equal to the current counting cycle, the counter performs a clear operation.

[0098] To elaborate on the working principle of the PWM signal generation method provided by the embodiments of the present application, the following examples are provided for illustration in the embodiments of the present application, specifically as follows:

[0099] A1. When starting to work, the current counting cycle of the counter is updated to T' = T + nα + β, where the first comparison threshold is 0 and the second comparison threshold is NUM.

[0100] A2. The counter starts to work, and the arrival of each clock cycle causes the count value of the counter to increase.

[0101] ① In the case where n*α is greater than or equal to c and nα + β is greater than or equal to c:

[0102] Since the quotient of α divided by c is 1, the first comparison threshold is updated to 1, and the first remainder of α divided by c is divided by the delay time Δt of the first delay element to obtain the first delay stage number. Finally, the first selector is controlled to select and enable a plurality of first delay elements corresponding to the first delay stage number.

[0103] Since the quotient of (nα + β) divided by c is 1, the second comparison threshold is updated to NUM + 1, and the second remainder of (nα + β) divided by c is divided by the delay time Δt of the second delay element to obtain the second delay stage number. Finally, the second selector is controlled to select and enable a plurality of second delay elements corresponding to the second delay stage number.

[0104] When the count value of the counter is 0, both the first comparator and the second comparator output a low level.

[0105] When the next clock cycle arrives, the count value of the counter is 1, and the output of the first comparator is set to a high level. After passing through a plurality of first delay elements corresponding to the first delay stage number for the first delay time processing, the set high level is applied to the set terminal of the latch, so that the latch outputs a high level and latches the high level.

[0106] As the clock signal is continuously input to the counter, when the count value of the counter is NUM + 1, the output of the second comparator is reset to a high level. After passing through a plurality of second delay elements corresponding to the second delay stage number for the second delay time processing, the reset high level is applied to the reset terminal of the latch, so that the latch outputs a low level and latches the low level.

[0107] As the clock signal is continuously input to the counter, when the count value of the counter reaches the current counting cycle, the counter performs a clear operation, and the first comparison threshold, the second comparison threshold, and the counting cycle of the counter are restored to the initial state, continue to generate the next PWM signal, and return to A1.

[0108] ② In the case where n * α is greater than or equal to c and nα + β is less than c:

[0109] Since the quotient of α divided by c is 1, the first comparison threshold is updated to 1, and the first remainder of α divided by c is divided by the delay time Δt of the first delay element to obtain the first delay stage number. Finally, the first selector is controlled to select and enable a plurality of first delay elements corresponding to the first delay stage number.

[0110] Keep the second comparison threshold unchanged at NUM, and divide (nα + β) by the delay time Δt of the second delay element to obtain the second delay stage number. Finally, the second selector is controlled to select and enable a plurality of second delay elements corresponding to the second delay stage number.

[0111] When the count value of the counter is 0, both the first comparator and the second comparator output a low level.

[0112] When the next clock cycle arrives, the count value of the counter is 1, and the output of the first comparator is set to a high level. After the high level is delayed for the first delay time through multiple first delay elements corresponding to the first delay stage number, it is then applied to the set terminal of the latch, so that the latch outputs a high level and latches the high level.

[0113] As the clock signal continuously inputs to the counter, when the count value of the counter is NUM, the output of the second comparator is reset to a high level. After the high level is delayed for the second delay time through multiple second delay elements corresponding to the second delay stage number, it is then applied to the reset terminal of the latch, so that the latch outputs a low level and latches the low level.

[0114] As the clock signal continuously inputs to the counter, when the count value of the counter reaches the current counting cycle, the counter performs a clearing operation, and restores the first comparison threshold, the second comparison threshold, and the counting cycle of the counter to the initial state, continues to generate the next PWM signal, and returns to A1.

[0115] ③ In the case where n*α is less than c and nα + β is greater than or equal to c:

[0116] Keep the first comparison threshold unchanged at 0, and divide n*α by the delay time Δt of the first delay element to obtain the first delay stage number. Finally, control the first selector to select and connect multiple first delay elements corresponding to the first delay stage number.

[0117] Since the quotient of (nα + β) divided by c is 1, update the second comparison threshold to NUM + 1, and divide the second remainder of (nα + β) divided by c by the delay time Δt of the second delay element to obtain the second delay stage number. Finally, control the second selector to select and connect multiple second delay elements corresponding to the second delay stage number.

[0118] When the count value of the counter is 0, the output of the first comparator is set to a high level. After the high level is delayed for the first delay time through multiple first delay elements corresponding to the first delay stage number, it is then applied to the set terminal of the latch, so that the latch outputs a high level and latches the high level.

[0119] As the clock signal continuously inputs to the counter, when the count value of the counter is NUM + 1, the output of the second comparator is reset to a high level. After the high level is delayed for the second delay time through multiple second delay elements corresponding to the second delay stage number, it is then applied to the reset terminal of the latch, so that the latch outputs a low level and latches the low level.

[0120] As the clock signal is continuously input into the counter, when the count value of the counter reaches the current counting period, the counter performs a clearing operation, and restores the first comparison threshold, the second comparison threshold, and the counting period of the counter to their initial states, continues to generate the next PWM signal, and returns to A1.

[0121] ④ In the case where n*α is less than c and nα + β is less than c:

[0122] Keep the first comparison threshold unchanged at 0, divide n*α by the delay time Δt of the first delay element to obtain the first delay stage number, and finally control the first selector to select and enable multiple first delay elements corresponding to the first delay stage number.

[0123] Keep the second comparison threshold unchanged at NUM, divide (nα + β) by the delay time Δt of the second delay element to obtain the second delay stage number, and finally control the second selector to select and enable multiple second delay elements corresponding to the second delay stage number.

[0124] When the count value of the counter is 0, the first comparator outputs a set high level. After the set high level is processed by the first delay time through multiple first delay elements corresponding to the first delay stage number, it is then applied to the set terminal of the latch, so that the latch outputs a high level and latches the high level.

[0125] When the next clock cycle arrives, the count value of the counter is 1, the first comparator outputs a set high level. After the set high level is processed by the first delay time through multiple first delay elements corresponding to the first delay stage number, it is then applied to the set terminal of the latch, so that the latch outputs a high level and latches the high level.

[0126] As the clock signal is continuously input into the counter, when the count value of the counter is NUM, the second comparator outputs a reset high level. After the reset high level is processed by the second delay time through multiple second delay elements corresponding to the second delay stage number, it is then applied to the reset terminal of the latch, so that the latch outputs a low level and latches the low level.

[0127] As the clock signal is continuously input into the counter, when the count value of the counter reaches the current counting period, the counter performs a clearing operation, and restores the first comparison threshold, the second comparison threshold, and the counting period of the counter to their initial states, continues to generate the next PWM signal, and returns to A1.

[0128] The PWM signal generation method provided by the embodiments of the present application can achieve control effects of high precision, high stability, and fast response with relatively low hardware costs, and significantly improve the precision and performance of PWM.

[0129] It should be noted that in the above various embodiments, there is not necessarily a certain order among the above steps. Those of ordinary skill in the art can understand from the description of the embodiments of the present application that in different embodiments, the above steps can have different execution orders, that is, they can be executed in parallel, or they can be executed alternately, and so on.

[0130] As another aspect of the embodiments of the present application, the embodiments of the present application provide a PWM signal generation device. Among them, the PWM signal generation device can be a software module, and the software module includes several instructions, which are stored in a memory, and a processor can access the memory and call the instructions for execution to complete the PWM signal generation method described in the above various embodiments.

[0131] In some embodiments, the PWM signal generation device can also be built by hardware devices. For example, the PWM signal generation device can be built by one or more than two chips, and each chip can work in coordination with each other to complete the PWM signal generation method described in the above various embodiments. For another example, the PWM signal generation device can also be built by various logic devices, such as being built by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a single-chip microcomputer, an ARM (Acorn RISC Machine), or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components.

[0132] Please refer to Figure 6 , the PWM signal generation device 600 includes a delay time determination module 61, a comparison result determination module 62, a first delay module 63, and a second delay module 64.

[0133] The delay time determination module 61 is used to determine the set delay time and the reset delay time of the nth PWM delay signal. The set delay time is the time for delaying the set to output the high level of the nth PWM delay signal, and the reset delay time is the time for delaying the reset to output the low level of the nth PWM delay signal, where n is a positive integer. The comparison result determination module 62 is used to determine the first comparison result between the set delay time and the preset clock cycle, and the second comparison result between the reset delay time and the preset clock cycle. The first delay module 63 is used to allocate a first delay time to the delay module and a first comparison threshold to the first comparator according to the first comparison result, so that when the count value output by the counter to the first comparator is equal to the first comparison threshold, the first comparator outputs a set high level. After the set high level is processed by the delay module for the first delay time, it is then transmitted to the set end of the latch, so that the latch outputs the nth high level. The total delay time of the delay module is less than or equal to the preset clock cycle. The second delay module 64 is used to allocate a second delay time to the delay module and a second comparison threshold to the second comparator according to the second comparison result, so that when the count value output by the counter to the second comparator is equal to the second comparison threshold, the second comparator outputs a reset high level. After the reset high level is processed by the delay module for the second delay time, it is then transmitted to the reset end of the latch, so that the latch outputs the nth low level. The nth high level and the nth low level form the nth PWM delay signal.

[0134] The embodiment of the present application does not need to rely on a high-precision clock chip, and can realize the delay processing of the PWM signal through fine-tuning operations on a low-cost hardware circuit. Among them, not only can the duty cycle be delayed, but also the signal period can be delayed, and the time resolution involved in the delay is relatively high, which is beneficial to output a more accurate and stable PWM signal.

[0135] In some embodiments, the delay time determination module 61 is specifically used to: determine the high-level delay time, where the high-level delay time is the time difference between the high level of the PWM delay signal and the high level of the PWM original signal, and multiply n by the high-level delay time to obtain the set delay time of the nth PWM signal.

[0136] In some embodiments, the delay time determination module 61 is also specifically used to: determine the period delay time, where the period delay time is the difference between the signal period of the PWM delay signal and the signal period of the PWM original signal, and add the set delay time and the period delay time to obtain the reset delay time of the nth PWM signal.

[0137] In some embodiments, the first delay module 63 is specifically configured to: in response to the first comparison result indicating that the set delay time is greater than or equal to the preset clock cycle, divide the set delay time by the preset clock cycle to obtain a first remainder, and determine the first remainder as the first delay time; in response to the first comparison result indicating that the set delay time is less than the preset clock cycle, determine the set delay time as the first delay time.

[0138] In some embodiments, the delay module includes a first delay unit, and the first delay unit includes a first selector and a plurality of first delay elements connected in series in sequence. The total delay time of all the first delay elements is less than or equal to the preset clock cycle. The first delay module 63 is specifically configured to: determine a first delay stage number based on the first delay time and the delay time of the first delay element, and control the first selector to select and enable a number of first delay elements corresponding to the first delay stage number, so that the number of first delay elements corresponding to the first delay stage number perform a first delay time process on the set high level.

[0139] In some embodiments, the first delay module 63 is specifically configured to: obtain a first local threshold of the first comparator; in response to the first comparison result indicating that the set delay time is greater than or equal to the preset clock cycle, accumulate a first specified value on the basis of the first local threshold to obtain a first comparison threshold, where the first specified value is the quotient obtained by dividing the set delay time by the preset clock cycle; in response to the first comparison result indicating that the set delay time is less than the preset clock cycle, determine the first local threshold as the first comparison threshold.

[0140] In some embodiments, the second delay module 64 is specifically configured to: in response to the second comparison result indicating that the reset delay time is greater than or equal to the preset clock cycle, divide the reset delay time by the preset clock cycle to obtain a second remainder, and determine the second remainder as the second delay time; in response to the second comparison result indicating that the reset delay time is less than the preset clock cycle, determine the reset delay time as the second delay time.

[0141] In some embodiments, the delay module includes a second delay unit, and the second delay unit includes a second selector and a plurality of second delay elements connected in series in sequence. The total delay time of all the second delay elements is less than or equal to the preset clock cycle. The second delay module 64 is specifically configured to: determine a second delay stage number based on the second remainder and the delay time of the second delay element, and control the second selector to select and enable a number of second delay elements corresponding to the second delay stage number, so that the number of second delay elements corresponding to the second delay stage number perform a second delay time process on the reset high level.

[0142] In some embodiments, the second delay module 64 is specifically configured to: obtain the second local threshold of the second comparator, in response to the second comparison result indicating that the reset delay time is greater than or equal to the preset clock cycle, accumulate a second specified value on the basis of the second local threshold to obtain a second comparison threshold, where the second specified value is the quotient obtained by dividing the reset delay time by the preset clock cycle, and in response to the second comparison result indicating that the reset delay time is less than the preset clock cycle, determine the second local threshold as the second comparison threshold.

[0143] In some embodiments, the second delay module 64 is specifically configured to: determine the current counting cycle of the counter according to the reset delay time and the original counting cycle of the counter, and in response to the count value of the counter being equal to the current counting cycle, perform a clear operation on the counter.

[0144] It should be noted that the above PWM signal generation device can execute the PWM signal generation method provided by the embodiments of the present application, and has the corresponding functional modules and beneficial effects for executing the method. For technical details not described in detail in the embodiments of the PWM signal generation device, reference may be made to the PWM signal generation method provided by the embodiments of the present application.

[0145] See Figure 7 , Figure 7 FIG. 13 is a schematic structural diagram of a microcontroller provided by an embodiment of the present application. The microcontroller 700 includes one or more processors 71 and a memory 72. The memory 72 is connected to one or more processors 71, for example, connected to the processor 71 through a bus.

[0146] The processor 71 is configured to support the microcontroller to execute the corresponding functions in the methods in the above method embodiments. The processor may be a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof. The above hardware chip may be an application specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The above PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0147] The memory 72 is used to store program codes and the like. The memory may include volatile memory (VM), such as random access memory (RAM); the memory may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD) or solid-state drive (SSD); the memory may further include a combination of the above types of memories.

[0148] The memory 72 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the method for generating PWM signals in the embodiments of the present application. The processor executes various functional applications and data processing of the method for generating PWM signals and the device for generating PWM signals by running the non-volatile software programs, instructions, and modules stored in the memory, that is, realizes the functions of each module or unit of the method for generating PWM signals and the device for generating PWM signals provided in the above method embodiments.

[0149] The memory 72 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function. The data storage area can store data created according to the use of the device for generating PWM signals. In some embodiments, the memory may optionally include a memory remotely set relative to the processor, and these remote memories can be connected to the device for generating PWM signals through a network. Examples of the above networks include but are not limited to the Internet, intranet, local area network, mobile communication network, and combinations thereof.

[0150] The one or more modules are stored in the memory and, when executed by the one or more processors, execute the method for generating PWM signals in any of the above method embodiments. For example, execute the method steps described in the above method embodiments and realize the functions of the modules described in the above device embodiments.

[0151] The embodiments of the present application further provide a computer-readable storage medium. The computer-readable storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a microcontroller, the microcontroller is caused to execute the method as described in the foregoing embodiments.

[0152] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above various methods. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0153] The above-disclosed are only the preferred embodiments of the present application. Of course, the scope of rights of the present application cannot be limited thereby. Therefore, equivalent changes made according to the claims of the present application still fall within the scope covered by the present application.

Claims

1. A method for generating a PWM signal, characterized in that: The generation method comprises: Determine a set delay time and a reset delay time of the nth PWM delay signal, wherein the set delay time is a time for delaying the setting to output a high level of the nth PWM delay signal, and the reset delay time is a time for delaying the resetting to output a low level of the nth PWM delay signal, where n is a positive integer; Determine a first comparison result of the set delay time and a preset clock cycle, and a second comparison result of the reset delay time and a preset clock cycle; Allocating a first delay time to the delay module and a first comparison threshold to the first comparator according to the first comparison result, so that when the count value output by the counter to the first comparator is equal to the first comparison threshold, the first comparator outputs a set high level, and the set high level is processed by the delay module for the first delay time and then transmitted to the set end of the latch, so that the latch outputs an nth high level, and the total delay time of the delay module is less than or equal to a preset clock cycle; A second delay time is allocated to the delay module and a second comparison threshold is allocated to the second comparator according to the second comparison result, so that when the count value output by the counter to the second comparator is equal to the second comparison threshold, the second comparator outputs a reset high level, and the reset high level is processed by the delay module for the second delay time and then transmitted to the reset end of the latch, so that the latch outputs an nth low level, and the nth high level and the nth low level form the nth PWM delay signal.

2. The generation method according to claim 1, characterized in that: The step of determining the setting delay time of the nth PWM delay signal comprises: Determine a high level delay time, where the high level delay time is a time difference between a high level of a PWM delay signal and a high level of a PWM original signal; Multiply n by the high level delay time to obtain the setting delay time of the nth PWM signal.

3. The generation method according to claim 1, characterized in that: The step of determining the reset delay time of the nth PWM signal comprises: Determine a period delay time, where the period delay time is a difference between a signal period of the PWM delay signal and a signal period of the PWM original signal; The set delay time is added to the cycle delay time to obtain a reset delay time of the nth PWM signal.

4. The generation method according to claim 1, characterized in that: The allocating a first delay time to the delay module according to the first comparison result includes: In response to the first comparison result indicating that the set delay time is greater than or equal to a preset clock cycle, the set delay time is divided by the preset clock cycle to obtain a first remainder, and the first remainder is determined to be a first delay time; In response to the first comparison result indicating that the set delay time is less than a preset clock period, the set delay time is determined to be a first delay time.

5. The generation method according to claim 4, characterized in that: The delay module includes a first delay unit, the first delay unit includes a first selector and a plurality of first delayers connected in series in sequence, the total delay time of all the first delayers is less than or equal to a preset clock cycle, and the generation method further includes: determining a first delay level based on the first delay time and the delay time of the first delayer; The first selector is controlled to select the first delay devices whose number corresponds to the first delay stage, so that the first delay devices whose number corresponds to the first delay stage process the set high level for a first delay time.

6. The generation method according to claim 1, characterized in that: The allocating a first comparison threshold to the first comparator according to the first comparison result includes: Obtaining a first local threshold of the first comparator; In response to the first comparison result indicating that the set delay time is greater than or equal to a preset clock cycle, a first specified value is accumulated on the basis of the first local threshold to obtain a first comparison threshold, where the first specified value is a quotient obtained by dividing the set delay time by the preset clock cycle; In response to the first comparison result indicating that the set delay time is less than a preset clock period, the first local threshold is determined as a first comparison threshold.

7. The generation method according to claim 1, characterized in that: The allocating a second delay time to the delay module according to the second comparison result includes: In response to the second comparison result indicating that the reset delay time is greater than or equal to a preset clock cycle, the reset delay time is divided by the preset clock cycle to obtain a second remainder, and the second remainder is determined to be a second delay time; In response to the second comparison result indicating that the reset delay time is less than a preset clock period, the reset delay time is determined to be a second delay time.

8. The generation method according to claim 7, characterized in that: The delay module includes a second delay unit, the second delay unit includes a second selector and a plurality of second delayers connected in series in sequence, the total delay time of all the second delayers is less than or equal to a preset clock cycle, and the generation method further includes: determining a second delay stage based on the second remainder and a delay time of the second delayer; The second selector is controlled to select the second delay devices whose number corresponds to the second delay stage, so that the second delay devices whose number corresponds to the second delay stage process the reset high level for a second delay time.

9. The generation method according to claim 1, characterized in that: The allocating a second comparison threshold to the second comparator according to the second comparison result includes: obtaining a second local threshold of the second comparator; In response to the second comparison result indicating that the reset delay time is greater than or equal to the preset clock cycle, a second specified value is accumulated on the basis of the second local threshold to obtain a second comparison threshold, where the second specified value is a quotient obtained by dividing the reset delay time by the preset clock cycle; In response to the second comparison result indicating that the reset delay time is less than a preset clock period, the second local threshold is determined as a second comparison threshold.

10. The generation method according to any one of claims 1 to 9, characterized in that: Also includes: Determining a current counting period of the counter according to the reset delay time and the original counting period of the counter; In response to the count value of the counter being equal to the current count cycle, a clearing operation is performed on the counter.

11. A microcontroller, characterized in that: It comprises a memory and a processor, wherein the memory is connected to the processor, and the processor is used to execute one or more computer programs stored in the memory. When the processor executes the one or more computer programs, the microcontroller implements the method for generating a PWM signal as described in any one of claims 1 to 10.

12. A PWM generation circuit, characterized in that: It includes a counter, a first comparator, a second comparator, a first delay unit, a second delay unit, a latch and a microcontroller as described in claim 11, wherein the microcontroller is respectively communicated with the counter, the first comparator, the second comparator, the first delay unit and the second delay unit, the timer is respectively communicated with the first comparator and the second comparator, the first comparator is communicated with the first delay unit, the second comparator is communicated with the second delay unit, the set end of the latch is communicated with the output end of the first delay unit, and the reset end of the latch is communicated with the output end of the second delay unit.

13. A digital pulse width modulation signal circuit, characterized in that: Comprising the PWM generating circuit as claimed in claim 12.

14. An electronic device, characterized in that: Comprising the PWM generating circuit as claimed in claim 12.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the processor executes the method for generating a PWM signal according to any one of claims 1 to 10.

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