Delay-locked loop system and memory

Abstract

According to the delay-locked loop system and the memory provided by the invention, the clock loss detection circuit is added on the basis of the circuit structure of the original delay-locked loop system to detect whether the clock feedback node of the DLL loop loses the clock or not, the scheme is simple and easy to implement, and when the clock loss detection circuit detects the clock loss, the delay-locked loop system can be used for detecting whether the clock feedback node of the DLL loop loses the clock or not. The DLL loop is enabled to freeze the current delay line length (namely, the delay line length is not adjusted temporarily), the DCC loop is enabled to adjust the duty ratio of the output clock signal of the DLL loop to a set value, the DLL loop is enabled to recover to work until the clock loss detection circuit detects that no clock loss exists, freezing of the delay line length is relieved (namely, the delay line length is unfrozen), and the DLL loop is enabled to return to the set value until the clock loss detection circuit detects that no clock loss exists. Therefore, the length of the delay line is continuously adjusted so as to complete the locking of the DLL loop, so that the locking of the DLL loop can be smoothly completed when the working condition of the memory is very poor.

Description

Technical Field

[0001] The present invention relates to the field of memories, and particularly to a delay locked loop system and a memory. Background Art

[0002] Memory chips such as DRAM (Dynamic Random Access Memory) usually have a Delay Locked Loop (DLL) inside to achieve synchronization of internal and external clock signals (i.e., aligning the phases of internal and external clock signals).

[0003] However, when the operating conditions of the memory chip are very poor (for example, when operating under extreme conditions such as low voltage and ss process corner where the working speeds of NMOS and PMOS are both slow), if the duty cycle of the external clock signal received by the DLL is very poor (for example, the duty cycle deviates from 50%), then at the initial stage of the DLL's locking operation, clock loss may occur on the DLL loop, resulting in the DLL being unable to complete the phase alignment of internal and external clock signals. Summary of the Invention

[0004] The purpose of the present invention is to provide a delay locked loop system and a memory, which can detect whether clock signal loss occurs at the clock feedback node of the DLL loop, and ensure that the DLL loop can complete locking smoothly.

[0005] To achieve the above purpose, the present invention provides a delay locked loop system, which includes:

[0006] A DLL loop for aligning the phase of the input clock signal it receives with the output clock signal it outputs;

[0007] A DCC loop coupled to the DLL loop and used to adjust the duty cycle of the output clock signal;

[0008] A clock loss detection circuit coupled to the clock feedback node of the DLL loop and used to detect whether there is clock loss at the clock feedback node during the locking process of the DLL loop. When it detects that there is clock loss at the clock feedback node, it freezes the current delay line length of the DLL loop, and at the same time makes the DCC loop adjust the duty cycle of the output clock signal to a set value. And, after it is detected again that the clock feedback node no longer has clock loss, it releases the freezing of the delay line length of the DLL loop to adjust the delay line length to complete the locking of the DLL loop.

[0009] Optionally, the DLL loop includes a DLL controller for generating a corresponding status signal according to the period of the input clock signal, and the clock loss detection circuit includes:

[0010] A reset signal generation circuit, coupled to the DLL controller and configured to generate a corresponding reset signal according to the status signal;

[0011] A clock edge detection circuit, coupled to the output terminal of the reset signal generation circuit and the clock feedback node, and configured to be reset according to the reset signal, and during the period after the reset ends until the next time the status signal becomes valid, detect the number of rising edges or falling edges of the feedback clock signal fed back by the clock feedback node, and output a corresponding indication signal according to the detection result, wherein when the indication signal is valid, it indicates that there is a situation of lost clock at the clock feedback node;

[0012] A thaw signal generation circuit, coupled to the DLL controller and the clock edge detection circuit, and configured to generate a valid thaw signal to the DLL controller when both the indication signal and the status signal are valid, so that the DLL controller releases the freezing of the length of its delay line to adjust the delay line length to complete the locking of the DLL loop.

[0013] Optionally, the status signal becomes valid once every N Tck, and the length of each valid period is 1 Tck, where Tck is the period of the input clock signal, and N is a set value determined by the mode register setting or the trimming setting determined according to the pre-factory test.

[0014] Optionally, a state machine is provided inside the DLL controller, the N value is stored in the state machine, and the state machine outputs the status signal based on the N value and the Tck.

[0015] Optionally, the reset signal has a delay relative to the status signal.

[0016] Optionally, the reset signal generation circuit includes a delay element, an inverter, and a NOR logic circuit; the input terminal of the delay element and the first input terminal of the NOR logic circuit both receive the status signal; the output terminal of the delay element is coupled to the input terminal of the inverter, the output terminal of the inverter is coupled to the second input terminal of the NOR logic circuit, and the output terminal of the NOR logic circuit outputs the reset signal.

[0017] Optionally, the clock edge detection circuit includes a trigger chain formed by cascading a plurality of triggers. The clock terminals of each trigger are coupled to the clock feedback node, the reset terminals of each trigger are coupled to the output terminal of the reset signal generation circuit, the input terminal of the trigger at the first stage is coupled to a power supply voltage, and the output terminal of the trigger at the last stage outputs the indication signal. The trigger chain is configured to detect whether the number of rising edges or falling edges of the feedback clock signal output by the clock feedback node is greater than or equal to a set threshold during the period from the end of reset to the next validity of the status signal. If so, the valid indication signal is output.

[0018] Optionally, the thaw signal generation circuit includes an AND logic circuit. The first input terminal of the AND logic circuit receives the status signal, and the second input terminal of the AND logic circuit is coupled to the output terminal of the clock edge detection circuit to receive the indication signal. The AND logic circuit is configured to perform an AND logic operation on the status signal and the indication signal to output a valid thaw signal when both the indication signal and the status signal are valid.

[0019] Optionally, the DLL loop includes:

[0020] A delay line for delaying the input clock signal and outputting it. The length of the delay line determines the delay amount of the DLL loop for the external clock signal.

[0021] A replica delay circuit with its input terminal coupled to the output terminal of the DCC loop and its output terminal being the clock feedback node. The replica delay circuit is configured to feedback and output the clock signal output by the DCC loop.

[0022] A phase detector coupled to the output terminal of the replica delay circuit and configured to compare the phases between the input clock signal and the feedback clock signal output by the replica delay circuit.

[0023] Wherein, the DLL controller is further coupled to the phase detector and the delay line, and is configured to adjust the delay amount of the delay line according to the comparison result of the phase detector during the locking process of the DLL loop to complete the locking of the DLL loop.

[0024] Optionally, the DCC loop includes:

[0025] A DCC adjustment circuit for adjusting the duty cycle of the output clock signal.

[0026] A DCC detection circuit for detecting the duty cycle of the clock signal output by the DCC adjustment circuit.

[0027] A DCC controller, coupled to the DCC detection circuit, and configured to control the duty cycle adjustment amount of the DCC adjustment circuit according to the detection result of the DCC detection circuit.

[0028] Optionally, the delay locked loop system further includes:

[0029] An input buffer, whose output terminal is coupled to the DLL loop, and is configured to receive an externally input clock signal, output it as the input clock signal, and provide it to the DLL loop;

[0030] A clock tree, whose input terminal is coupled to the output terminal of the DLL loop, and is configured to distribute the output clock signal to other circuits inside the delay locked loop system;

[0031] An output buffer, whose input terminal is coupled to the output terminal of the clock tree, and is configured to delay and output the clock signal output by the clock tree.

[0032] Based on the same inventive concept, the present invention further provides a memory, which includes the delay locked loop system as described in the present invention.

[0033] Compared with the prior art, the technical solution of the present invention adds a clock loss detection circuit to detect whether there is a clock loss at the clock feedback node of the DLL loop on the basis of the original circuit structure of the delay locked loop system. The solution is simple and easy to implement. When the clock loss detection circuit detects a clock loss, the DLL loop freezes the current delay line length (i.e., temporarily does not adjust the delay line length), and the DCC loop adjusts the duty cycle of the output clock signal of the DLL loop to a set value until the clock loss detection circuit detects that there is no clock loss, and then the DLL loop resumes operation, releases the freeze on the delay line length (i.e., unfreezes the delay line length), so as to continue to adjust the delay line length to complete the locking of the DLL loop. Thus, even when the working conditions of the memory (or the system chip of the memory) are very poor, it can be ensured that the DLL loop can successfully complete the locking. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0035] Figure 1 is a schematic structural diagram of an existing delay locked loop system.

[0036] Figure 2 is a schematic structural diagram of the delay locked loop system according to an embodiment of the present invention.

[0037] Figure 3It is a schematic structural diagram of a replica delay circuit in a delay-locked loop system according to an embodiment of the present invention.

[0038] Figure 4 It is a schematic structural diagram of a clock loss detection circuit in a delay-locked loop system according to an embodiment of the present invention.

[0039] Figure 5 It is a schematic structural diagram of an example of a reset signal generation circuit in a clock loss detection circuit of a delay-locked loop system according to an embodiment of the present invention.

[0040] Figure 6 It is a schematic structural diagram of an example of a clock edge detection circuit in a clock loss detection circuit of a delay-locked loop system according to an embodiment of the present invention.

[0041] Figure 7 It is a schematic structural diagram of an example of a phase sampling trigger circuit in a clock loss detection circuit of a delay-locked loop system according to an embodiment of the present invention.

[0042] Figure 8 It is a schematic diagram of signal timing in a clock loss detection circuit of a delay-locked loop system according to an embodiment of the present invention. Detailed implementation manners

[0043] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some well-known technical features are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals represent the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, it can be directly connected to the other element, or there may be intervening elements. In contrast, when an element is referred to as "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0044] The circuit structure of an existing delay-locked loop system is as Figure 1As shown in the figure, it includes a clock receiver 10, an input buffer 11, a DLL loop 12, a DCC (Duty Cycle Corrector) loop 13, a clock tree 14, an output buffer 15, and a clock output terminal 16. The DLL loop 12 includes a delay line 121, a phase detector 123, a DLL controller 122, and a replica delay circuit 124. The DCC loop 13 includes a DCC adjustment circuit 131, a DCC detection circuit 132, and a DCC controller 133.

[0045] Among them, the input terminal of the input buffer 11 is coupled to the clock receiver 10 to receive an external clock signal Clk, delay it, and output it as a clock signal Clk_rcv. The input terminal of the delay line 121 receives the clock signal Clk_rcv, delays it, and outputs it as a clock signal Clk_out, which is provided to the DCC adjustment circuit 131. The DCC adjustment circuit 131 adjusts the clock signal Clk_out under the control of the DCC controller 133 and then outputs it as a clock signal Lf_clk. The DCC detection circuit 132 detects the duty cycle of the clock signal Lf_clk. The DCC controller 133 generates a corresponding control signal DCC_ctrl (also called control code Dcc code) according to the duty cycle detection result of the DCC detection circuit 132 to control the duty cycle adjustment amount of the DCC adjustment circuit 131. The replica delay circuit 124 feeds back the clock signal Lf_clk output by the DCC adjustment circuit 131 to the phase detector 123 (the output terminal of the replica delay circuit 124 is the clock feedback node of the DLL loop). The phase detector 123 compares the phase of the clock signal Clk_rcv output by the input buffer 11 and the feedback clock signal Clk_fb output by the replica delay circuit 124. The DLL controller 122 generates a control signal DLL Ctrl (also called control code Dll code) according to the phase comparison result of the phase detector 123, thereby controlling the delay amount of the delay line 121. When the phase detector 123 detects that the phases of Clk_rcv and Clk_fb are the same, and the duty cycle of Clk_fb reaches the set value (50%), the phase of the external clock signal Clk input at the clock input terminal 10 and the internal clock signal DQS output at the clock output terminal 16 are aligned, and the duty cycle of the internal clock signal DQS reaches the set value (50%). At this time, the DLL loop 12 is locked.

[0046] When the duty cycle of the external clock signal Clk input at the clock input terminal 10 deviates from 50% due to reasons such as extreme working conditions (it can also be said that the chip working conditions are very poor), the following problems will occur in the above scheme:

[0047] 1. In the initial stage of the DLL loop 12 being locked, since the transmission path of the clock signal in the DLL loop 12 is very long, after being transmitted through the DLL loop 12, there is an easy problem of duty cycle loss. If the DCC adjustment circuit 131 has not started to adjust the duty cycle or the adjustment amount of the duty cycle is very small, the duty cycle of the clock signal Lf_clk output by the DCC adjustment circuit 131 will deviate from 50%. For example, the duty of the external clock signal Clk input at the clock input terminal 10 is 45%, and the duty of the clock signal Lf_clk output by the DCC adjustment circuit 131 is 40%. When the clock signal Lf_clk output by the DCC adjustment circuit 131 is further transmitted to the replica delay circuit 124 and output as the feedback clock signal Clk_fb, due to the longer clock transmission path, more duty loss occurs. As a result, the feedback clock signal Clk_fb output by the replica delay circuit 124 may be a high level or a low level for a period of time, that is, the feedback clock signal Clk_fb output by the replica delay circuit 124 has a clock loss situation.

[0048] 2. When the feedback clock signal Clk_fb output by the replica delay circuit 124 has a clock loss situation, the phase detector 123 will still compare the phase of the clock signal Clk_rcv output by the input buffer 11 and the feedback clock signal Clk_fb output by the replica delay circuit 124 and output a comparison result of "0" or "1". Since the feedback clock signal Clk_fb is in a clock loss state (i.e., a high level or a low level for a period of time) at this time, the phase comparison result PD of the phase detector 123 cannot accurately reflect the phase difference between the internal and external clock signals. If the DLL controller adjusts the length of the delay line 121 (i.e., the magnitude of the delay amount) according to the wrong phase comparison result PD output by the phase detector 123, the situation where the DLL loop 12 cannot align the phases of the internal and external clock signals will occur, that is, the DLL loop 12 cannot complete the locking at this time.

[0049] To solve the above problems, the present invention proposes a delay locked loop system and a memory, which adds a clock loss detection circuit (feedback monitor) on the basis of the existing delay locked loop system. Thus, during the DLL loop locking process, the clock loss detection circuit detects whether there is a clock loss at the clock feedback node of the DLL loop. If a clock loss is detected, the current delay line length of the DLL loop (i.e., the current delay amount of the DLL loop) is frozen, and at the same time, the DCC loop continues to work, and the duty cycle of the output clock signal output by the DCC loop is adjusted to a set value (e.g., 50%), until the clock loss detection circuit no longer detects a clock loss at the clock feedback node of the DLL loop, then the DLL loop releases the freezing of the delay line length (i.e., unfreezes the delay line length). At this time, the DLL loop can complete the locking by continuing to adjust its delay line length.

[0050] The technical solutions proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0051] Please refer to Figure 2 , an embodiment of the present invention provides a delay locked loop system, which at least includes a DLL loop 22, a DCC loop 23, and a clock loss detection circuit 27.

[0052] Among them, the DLL loop 22 is used to align the phase of the input clock signal Clk_rcv and its output output clock signal Clk_out, so as to synchronize the external clock signal Clk received by the clock receiving end 20 with the internal clock signal DQS output by the clock output end 26.

[0053] The DCC loop 23 is coupled to the output end of the DLL loop 22 and is used to adjust the duty cycle of the output clock signal Clk_out output by the DLL loop 22, so as to output a clock signal Lf_clk with a duty cycle reaching a set value (e.g., reaching 50%).

[0054] The clock loss detection circuit 27 is coupled to the clock feedback node of the DLL loop 22 and is used to detect whether there is a clock loss at the clock feedback node of the DLL loop 22 during the locking process of the DLL loop 22 (i.e., to detect whether there is a clock loss at Clk_fb). When it is detected that there is a clock loss at the clock feedback node of the DLL loop 22, the clock loss detection circuit 27 generates a corresponding freeze signal (such as an invalid LCYC1D_DLL), causing the DLL loop 22 to freeze the current length of its delay line 221. At the same time, the DCC loop 22 adjusts the duty cycle of the output clock signal clk_out it receives to a set value and then outputs it as the clock signal Lf_clk (i.e., at this time, the duty cycle of the clock signal Lf_clk output by the DCC loop 22 reaches the set value). Moreover, after it is detected again that there is no clock loss at the clock feedback node of the DLL loop 22, the DLL loop 22 releases the freezing of the length of its delay line 221, so that it can continue to adjust the length of the delay line 221 until the DLL loop 22 completes locking.

[0055] Please refer to Figure 2 , optionally, the DLL loop 22 includes a DLL controller 222, and the DLL controller 22 is used to generate a corresponding status signal LCYC0D_PRE according to the period of the input clock signal Clk_rcv (this period is also the period of the external clock signal Clk). As an example, the status signal LCYC0D_PRE is valid once every N Tck, and the length of each valid period is 1 Tck. At this time, the period of the status signal LCYC0D_PRE is N*Tck, where Tck is the period of the input clock signal Clk_rcv, the value of N is a preset value, and N is an integer greater than 1. In one embodiment, the value of N is determined according to the corresponding MRS (Model Register Set) setting of the delay locked loop system or the trim set determined by pre-factory testing. In one embodiment, the trim set is set by burning an electronic fuse (efuse) before leaving the factory. In one embodiment, there is a state machine (not shown) inside the DLL controller, and the value of N is stored in this state machine, and this state machine outputs the status signal LCYC0D_PRE based on the value of N and the Tck. In another embodiment, this state machine can not only store the value of N, but also generate and store a control code DLL code for adjusting the length of the delay line of the DLL loop 22 during the locking process of the DLL loop 22.

[0056] Please refer to Figure 2 and Figure 4 , optionally, the clock loss detection circuit 27 includes a reset signal generation circuit 271, a clock edge detection circuit 272, and a thaw signal generation circuit 273.

[0057] Among them, the reset signal generation circuit 271 is coupled to the DLL controller 222 and is configured to generate a corresponding reset signal RST according to the status signal LCYC0D_PRE output by the DLL controller 222. In one example, the reset signal generation circuit 271 performs corresponding logical operation processing on the status signal LCYC0D_PRE to generate the reset signal RST. Optionally, the reset signal RST has a delay relative to the status signal LCYC0D_PRE. For example, the rising edge of the reset signal RST is aligned with the falling edge of the status signal LCYC0D_PRE.

[0058] The clock edge detection circuit 272 is coupled to the output terminal of the reset signal generation circuit 271 and the clock feedback node of the DLL loop 22 (i.e., the output terminal of the replica delay circuit 224), and is configured to be reset according to the reset signal RST to clear the number of detected edges before, and, during the period after the reset ends until the status signal LCYC0D_PRE becomes valid again (i.e., Figure 8 within the time period between the falling edge of the reset signal RST in and the next rising edge of the status signal LCYC0D_PRE), detect the number of rising edges or falling edges of the feedback clock signal Clk_fb output by the clock feedback node of the DLL loop 22, and output a corresponding indication signal LCYC_gating according to the detection result, where, when the indication signal LCYC_gating is valid (e.g., active high), it indicates that there is no clock loss in the clock signal Clk_fb output by the clock feedback node of the DLL loop 22.

[0059] The thaw signal generation circuit 273 is coupled to the DLL controller 222 and the clock edge detection circuit 272, and is configured to generate a valid thaw signal LCYC1D_DLL and output it to the DLL controller 222 when both the indication signal LCYC_gating and the status signal LCYC0D_PRE are valid, so that the DLL controller 222 releases the freezing of the length of its delay line according to the valid thaw signal LCYC1D_DLL, thereby continuing to adjust the length of the delay line 221 and successfully completing the locking of the DLL loop 22. As an example, after the valid thaw signal LCYC1D_DLL is transmitted to the DLL controller 222, the state machine (not shown) in the DLL controller 222 continues to sample the phase comparison result PD output by the phase detector 223 in the DLL loop 22, update the control code DLL code therein, thereby adjusting the length of the delay line 221. In one embodiment, when the thaw signal LCYC1D_DLL is valid, it indicates that the DLL controller 222 samples the phase comparison result PD output by the phase detector 223.

[0060] It should be understood that the reset signal generation circuit 271, the clock edge detection circuit 272, and the thaw signal generation circuit 273 can all be implemented by any suitable circuit design capable of realizing their functions, and the present invention does not make specific limitations thereto.

[0061] As an example, please refer to Figure 5 , the reset signal generation circuit 271 includes a delay element delay, an inverter INV, and a NOR logic circuit NOR. Among them, the input terminal of the delay element delay and the first input terminal of the NOR logic circuit NOR are both coupled to the corresponding terminals of the DLL controller 222 to receive the status signal LCYC0D_PRE output by the DLL controller 222. The output terminal of the delay element delay is coupled to the input terminal of the inverter INV, the output terminal of the inverter INV is coupled to the second input terminal of the NOR logic circuit NOR, and the output terminal of the NOR logic circuit NOR outputs the reset signal RST. The delay element delay can be implemented by any suitable circuit design such as an RC delay circuit, and the NOR logic circuit NOR can be implemented by any suitable circuit design such as a NOR gate.

[0062] As an example, please refer to Figure 6 , the clock edge detection circuit includes a trigger chain formed by cascading m flip-flops DFF1 to DFFm. The clock terminals (i.e., the Clk terminals) of each of the flip-flops DFF1 to DFFm are all coupled to the clock feedback node of the DLL loop 22 (such as the output terminal of the replica delay circuit 224) to receive the feedback clock signal Clk_fb. The reset terminals Reset of each of the flip-flops DFF1 to DFFm are all coupled to the output terminal of the reset signal generation circuit 271 to receive the reset signal RST (such as active high). The input terminal D of the first-stage flip-flop DFF1 is coupled to a power supply voltage (not shown), and the output terminal Q of the last-stage flip-flop DFFm outputs an indication signal LCYC_gating. This trigger chain is used to detect whether the number of rising edges or falling edges of the feedback clock signal Clk_fb is greater than or equal to a set threshold k during the period from the end of the reset to the next valid state of the status signal LCYC0D_PRE (such as active high) (i.e., Figure 8 the period between the falling edge of the reset signal RST in

[0063] In one embodiment, the flip - flops DFF1 to DFFm are D - type flip - flops. The status signal LCYC0D_PRE is valid once every N Tck, and the length of each valid period is 1 Tck. Here, Tck is the period of the input clock signal Clk_rcv. In this case, it is necessary to satisfy k = m and m < N - 1. At this time, (N - 1)*Tck is the actual detection time period, that is, (N - 1)*Tck is the time between two high levels of the status signal LCYC0D_PRE.

[0064] When the reset signal RST is valid (for example, active high), each of the flip - flops DFF1 to DFFm is reset, and the output of the Q output terminal of each flip - flop is cleared. During the period from when the reset signal RST changes from valid to invalid (i.e., the reset ends) until the next status signal LCYCOD_PRE becomes valid, if the number of rising edges (or falling edges) of the clock signal Clk_fb output by the replication delay circuit 224 is greater than or equal to the set threshold k (for example, k is equal to the number m of the flip - flops DFF1 to DFFm), the indication signal LCYC_gating is set to valid (for example, "1"). If the number of rising edges (or falling edges) of Clk_fb detected is less than the set threshold k, the indication signal LCYC_gating is set to invalid (for example, "0") until the next reset signal RST is valid (for example, active high).

[0065] It should be understood that the number m of flip - flops in the flip - flop chain can be set by the user or the circuit designer, and the present invention does not make specific limitations in this regard. In addition, Figure 6 the flip - flops in are shown by taking D - type flip - flops as an example. However, in other embodiments of the present invention, they can also be replaced with any other suitable type of flip - flops to construct the required flip - flop chain. Alternatively, in other embodiments of the present invention, any other suitable signal edge detection circuit and counting circuit can be used to construct the clock edge detection circuit 272, and the present invention does not make specific limitations in this regard.

[0066] As an example, please refer to Figure 7, the thaw signal generation circuit 273 includes an AND logic circuit. The first input terminal of the AND logic circuit is coupled to the corresponding terminal of the DLL controller 222 to receive the status signal LCYC0D_PRE output by the DLL controller 222. The second input terminal of the AND logic circuit is coupled to the output terminal of the clock edge detection circuit 272 (i.e., the output terminal Q of the last-stage flip-flop DFFm) to receive the indication signal LCYC_gating. The AND logic circuit is used to perform an AND logic operation on the status signal LCYC0D_PRE and the indication signal LCYC_gating, and when both the indication signal LCYC_gating and the status signal LCYC0D_PRE are valid, output a valid thaw signal LCYC1D_DLL (for example, active high). Among them, the AND logic circuit can be implemented by any suitable circuit design such as an AND gate, and the present invention does not make specific limitations on this.

[0067] Please combine with Figures 2 to 8 , the thaw signal LCYC1D_DLL, the reset signal RST, and the indication signal LCYC_gating are all low-level invalid in the initial state or the default state. The working timing of the clock loss detection circuit 27 in this embodiment is as follows:

[0068] First, the state machine of the DLL controller 222 outputs the status signal LCYC0D_PRE, and its period is N * Tck.

[0069] In the time period from t1 to t2, when the status signal LCYC0D_PRE changes from low level to high level, the reset signal generation circuit 271 in the clock loss detection circuit 27 generates a reset signal RST whose rising edge has a delay relative to the rising edge of the status signal LCYC0D_PRERST. During the high-valid stage of the reset signal RST, the clock edge detection circuit 272 in the clock loss detection circuit 27 is reset. After the reset ends until t2 (i.e., Figure 8During the period from the first falling edge of the reset signal RST to the second rising edge of the status signal LCYC0D_PRE, if the clock edge detection circuit 272 detects that the number of rising edges (or falling edges) of the feedback clock signal Clk_fb at the clock feedback node of the DLL loop is <m, it is determined that there is a clock loss. At this time, the indication signal LCYC_gating remains low to indicate that the feedback clock signal Clk_fb has lost a clock. As a result, the thawing signal LCYC1D_DLL output by the thawing signal generation circuit 273 is still low and invalid, and the state machine in the DLL controller 222 freezes the current length of the delay line 221 (i.e., no longer updates the control code DLL code). The DCC loop 23 adjusts the duty cycle of the output clock signal Clk_out of the DLL loop 22 and adjusts the duty cycle of the output clock signal Lf_clk to the set value (e.g., 50%).

[0070] At time t2, the status signal LCYC0D_PRE changes from low to high again.

[0071] During the time period from t2 to t3, the reset signal RST changes from low to high again. During the high-valid phase of the reset signal RST, the clock edge detection circuit 272 in the clock loss detection circuit 27 is reset again, so that the clock edge detection circuit 272 re-counts the edges of the clock signal Clk_fb. During the period from the end of the reset to t3 (i.e., from the second falling edge of the reset signal RST to the third rising edge of the status signal LCYC0D_PRE), if the clock edge detection circuit 272 detects that the number of rising edges (or falling edges) of the feedback clock signal Clk_fb at the clock feedback node of the DLL loop is greater than or equal to m, it is determined that there is no clock loss. At this time, the indication signal LCYC_gating is set to high to indicate that the feedback clock signal Clk_fb no longer loses a clock.

[0072] At time t3, the status signal LCYC0D_PRE becomes active high, and at the same time, the indication signal LCYC_gating is active high. The thaw signal LCYC1D_DLL output by the thaw signal generation circuit 273 becomes active high level. The DLL controller 222 resumes operation, and the state machine inside it thaws the length of the delay line 221 (i.e., starts to continue updating the control code DLL code), so as to continue to adjust the length of the delay line 221. At the same time, the DCC loop 23 adjusts the duty cycle of the output clock signal Clk_out of the DLL loop 22. Finally, the locking of the DLL loop 22 is completed, that is, finally the DLL loop 22 can make the clock signal Clk received by the clock receiving end 10 phase-align with the signal DQS output by the clock output end 26, realizing the synchronization of the internal and external clock signals of the delay locked loop system. In addition, due to the action of the DCC loop 23, the duty cycle of the internal clock signal DQS output by the clock output end 26 is a set value (for example, 50%).

[0073] In one example, the falling edge of the thaw signal LCYC1D_DLL can be triggered by the falling edge of the status signal LCYC0D_PRE.

[0074] Optionally, please refer to Figure 2 , the delay locked loop system of this embodiment further includes a clock receiving end (Clk pad) 20, an input buffer (Receiver, RCV) 21, a clock tree (clk tree) 24, an output buffer (OCD) 25, and a clock output end (DQS pad) 26.

[0075] Among them, the clock receiving end 20 is an external pin of a chip such as a memory like DRAM, and it receives an external clock signal Clk input externally (that is, a clock signal outside the delay locked loop system, which can come from a host or a controller outside the memory chip). The output end of the input buffer 21 is coupled to the input end of the DLL loop 22. The input buffer 21 delays the clock signal Clk received by the clock receiving end 20 and outputs it as an input clock signal Clk_rcv to provide to the DLL loop 22.

[0076] The input end of the clock tree 24 is coupled to the output end of the DCC loop 23, and the clock tree 24 is configured to distribute the clock signal Lf_clk output by the DCC loop 23 to other circuits inside the delay locked loop system.

[0077] The input end of the output buffer 25 is coupled to the output end of the clock tree 24, and the output buffer 25 is configured to delay the clock signal output by the clock tree 24 and output it as an internal clock signal DQS, and provide it to the clock output end 26.

[0078] It should be understood that in the delay-locked loop system of this embodiment, modules such as the input buffer 21, the DLL loop 22, the DCC loop 23, the clock tree 24, and the output buffer 25 can be implemented using any suitable conventional design in the art. In addition, in this embodiment, the clock loss detection circuit 27 is regarded as a circuit external to the DLL loop 22, indicating that the addition of the clock loss detection circuit 27 does not greatly modify the internal circuit of the DLL loop 22. However, the clock loss detection circuit 27 can also be regarded as an internal circuit of the DLL loop 22, thereby obtaining an improved DLL loop 22 different from the existing DLL loop 22.

[0079] Please continue to refer to Figure 2 , optionally, in addition to the DLL controller 222, the DLL loop 22 further includes a delay line 221, a phase detector 223, and a replica delay circuit 224.

[0080] Please continue to refer to Figure 2 , the input end of the delay line 221 serves as the input end of the DLL loop 22 (or the clock input node of the DLL loop 22) and is coupled to the output end of the input buffer 21. The output end of the delay line 221 serves as the output end of the DLL loop 22 (or the clock output node of the DLL loop 22) and is coupled to the input end of the DCC loop 23. The length of the delay line 221 can be adjusted under the control of the DLL controller 222 to complete the locking of the DLL loop 22. Thus, the delay line 221 receives the input clock signal Clk_rcv, delays the input clock signal Clk_rcv by a corresponding delay amount, and outputs it as the output clock signal Clk_out to the input end of the DCC loop 23.

[0081] The replica delay circuit 224 is a replica circuit corresponding to the input buffer 21, the clock tree 24, and the output buffer 25, and it can replicate (or simulate) the delay amount except for the delay amount of the delay line 221 on the path from the input buffer 21 to the output buffer 25. Please refer to Figure 3, the replica delay circuit 224 may include an output buffer replica circuit 224a, a clock tree replica circuit 224b, and an input buffer replica circuit 224c. Among them, the input terminal of the output buffer replica circuit 224a is coupled to the output terminal of the 221DCC loop 23 (or referred to as the clock output node of the DCC loop 23), and is used to delay the output clock signal Clk_out output by the delay line 221 by the delay amount of the output buffer 25 and then output it. The input terminal of the clock tree replica circuit 224b is coupled to the output terminal of the input buffer replica circuit 224c, and is used to delay the clock signal output by the output buffer replica circuit 224a by the delay amount of the clock tree 24 and then output it. The input terminal of the input buffer replica circuit 224c is coupled to the output terminal of the clock tree replica circuit 224b. The output terminal of the input buffer replica circuit 224c serves as the clock feedback node of the DLL loop 22 and is coupled to an input terminal of the phase detector 223 and the input terminal of the clock loss detection circuit 27. The input buffer replica circuit 224c is used to delay the clock signal output by the clock tree replica circuit 224b by the delay amount of the input buffer 21 and then output it. The output terminal of the input buffer replica circuit 224c is the clock feedback node of the DLL loop 22, and the clock signal output by it serves as the feedback clock signal Clk_fb output by the replica delay circuit 224, which is provided to the clock loss detection circuit 27 and the phase detector 223.

[0082] Please refer to Figure 2 , the phase detector 223 is configured to compare the phases between the input clock signal Clk_rcv output by the input buffer 21 and the feedback clock signal Clk_fb output by the replica delay circuit 224.

[0083] Please refer to Figure 2 , the DLL controller 222 is not only coupled to the output terminal of the phase detector 223 and the control terminal of the delay line 221, but also coupled to the clock loss detection circuit 27. The DLL controller 222 is configured to freeze the current delay line length (i.e., freeze the current DLL control code DLL code, so as to temporarily not adjust the length of the delay line 221, or temporarily no longer adjust the delay amount of the delay line 221) when the clock loss detection circuit 27 detects that there is a clock loss at the clock feedback node of the DLL loop 22 (i.e., detects that the feedback clock signal Clk_fb has a clock loss), and, after the clock loss detection circuit 27 re-detects that there is no clock loss at the clock feedback node of the DLL loop 22 (i.e., detects that the feedback clock signal Clk_fb no longer has a clock loss), resume (or unfreeze) the adjustment of the delay line length, so as to continue to adjust the length (i.e., the delay amount) of the delay line 221 according to the phase comparison result PD of the phase detector 223 until the DLL loop 22 is locked.

[0084] Please continue to refer toFigure 2 , optionally, the DCC loop 23 includes a DCC adjustment circuit 231, a DCC controller 233, and a DCC detection circuit 232. Among them, the input end of the DCC detection circuit 232 is coupled to the output end of the DCC adjustment circuit 231, the output end of the DCC detection circuit 232 is coupled to the input end of the DCC controller 233, the output end of the DCC controller 233 is coupled to the control end of the DCC adjustment circuit 231, the input end of the DCC adjustment circuit 231 is coupled to the output end of the delay line 221, and the output end of the DCC adjustment circuit 231 is coupled to the input end of the clock tree 24. The DCC detection circuit 232 is configured to detect the duty cycle of the clock signal Lf_clk output by the DCC adjustment circuit 231; the DCC controller 233 is configured to control the duty cycle adjustment amount of the DCC adjustment circuit 231 according to the duty cycle detection result of the DCC detection circuit 232; the DCC adjustment circuit 231 adjusts the duty cycle of the output clock signal Clk_out output by the delay line 221 under the control of the DCC controller 233 and then outputs a clock signal Lf_clk with a duty cycle reaching a set value (for example, 50%), for example, the duty cycle of the clock signal Lf_clk output by the DCC adjustment circuit 231 is adjusted to 50%.

[0085] In summary, for the delay locked loop system of the present invention, compared with Figure 1 the circuit structure of the original delay locked loop system shown, it only adds a clock loss detection circuit, which is used to detect whether there is a clock loss at the clock feedback node of the DLL loop. The solution is simple and easy to implement. When the clock loss detection circuit detects a clock loss, the DLL loop freezes the current delay line length (that is, temporarily does not adjust the delay line length), and the DCC loop adjusts the duty cycle of the output clock signal of the DLL loop to a set value until the clock loss detection circuit detects that there is no clock loss, and then the DLL loop resumes operation to adjust the delay line length until the DLL loop is locked. Thus, even when the working conditions of the memory (or rather, the system chip of the memory) are very poor, it can ensure that the DLL loop can be successfully locked.

[0086] The delay locked loop system described in the present invention can be applied to any memory that needs to set a delay locked loop. Based on this, please refer to Figures 2 to 8 , an embodiment of the present invention further provides a memory, which includes the delay locked loop system described in the present invention.

[0087] Since this memory adopts the delay locked loop system of the present invention, it can ensure that the DLL loop can be successfully locked even when the working conditions are very poor.

[0088] Optionally, this memory is a DRAM memory.

[0089] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the technical solution of the present invention.

Claims

1. A delay locked loop system, characterized in that, Comprising: A DLL loop for phase-aligning an input clock signal received thereby with an output clock signal output therefrom; A DCC loop coupled to the DLL loop and for adjusting a duty cycle of the output clock signal; A clock loss detection circuit coupled to a clock feedback node of the DLL loop and for detecting whether there is a clock loss at the clock feedback node during a locking process of the DLL loop. When it is detected that there is a clock loss at the clock feedback node, the DLL loop is caused to freeze a current delay line length thereof, and at the same time, the DCC loop is caused to adjust the duty cycle of the output clock signal to a set value. Also, after it is redetected that the clock feedback node no longer has a clock loss, the DLL loop is caused to unfreeze the delay line length thereof to adjust the delay line length so that the DLL loop completes locking.

2. The delay-locked loop system according to claim 1, wherein, The DLL loop includes a DLL controller for generating a corresponding status signal according to a period of the input clock signal, and The clock loss detection circuit includes: A reset signal generation circuit coupled to the DLL controller and for generating a corresponding reset signal according to the status signal; A clock edge detection circuit coupled to an output end of the reset signal generation circuit and the clock feedback node, and for resetting according to the reset signal, and during a period from the end of the reset to the next validity of the status signal, detecting a number of rising edges or falling edges of a feedback clock signal output from the clock feedback node and outputting a corresponding indication signal according to a detection result, wherein when the indication signal is valid, it indicates that there is no clock loss at the clock feedback node; A thaw signal generation circuit coupled to the DLL controller and the clock edge detection circuit and for generating a valid thaw signal to the DLL controller when both the indication signal and the status signal are valid, so that the DLL controller unfreezes the delay line length thereof to adjust the delay line length so that the DLL loop completes locking.

3. The delay-locked loop system according to claim 2, wherein The status signal is valid once every N Tck, and a length of each valid period is 1 Tck, where Tck is a period of the input clock signal, and N is a set value determined by setting a corresponding mode register or a trimming setting determined according to a pre-factory test.

4. The delay locked loop system according to claim 3, wherein A state machine is provided inside the DLL controller, the N value is stored in the state machine, and the state machine outputs the status signal based on the N value and the Tck.

5. The delay locked loop system according to claim 2, wherein The reset signal has a delay relative to the status signal.

6. The delay-locked loop system according to any one of claims 2-5, characterized in that The reset signal generation circuit includes a delay element, an inverter and a NOR logic circuit; an input end of the delay element and a first input end of the NOR logic circuit both receive the status signal; an output end of the delay element is coupled to an input end of the inverter, an output end of the inverter is coupled to a second input end of the NOR logic circuit, and an output end of the NOR logic circuit outputs the reset signal.

7. The delay-locked loop system according to any one of claims 2-5, characterized in that, The clock edge detection circuit includes a trigger chain formed by cascading a plurality of triggers. The clock terminals of each trigger are coupled to the clock feedback node, and the reset terminals of each trigger are coupled to the output terminal of the reset signal generation circuit. The input terminal of the first-stage trigger is coupled to a power supply voltage, and the output terminal of the last-stage trigger outputs the indication signal. The trigger chain is configured to detect whether the number of rising edges or falling edges of the feedback clock signal output by the clock feedback node is greater than or equal to a set threshold during the period from the end of reset to the next valid state signal. If so, it outputs a valid indication signal.

8. The delay locked loop system according to any one of claims 2-5, characterized in that The thaw signal generation circuit includes an AND logic circuit. The first input terminal of the AND logic circuit receives the state signal, and the second input terminal of the AND logic circuit is coupled to the output terminal of the clock edge detection circuit to receive the indication signal. The AND logic circuit is configured to perform an AND logic operation on the state signal and the indication signal to output a valid thaw signal when both the indication signal and the state signal are valid.

9. The delay locked loop system according to claims 2-5, characterized in that, The DLL loop further includes: A delay line for delaying the input clock signal and outputting it. The length of the delay line determines the delay amount of the DLL loop for the external clock signal. A replica delay circuit with its input terminal coupled to the output terminal of the DCC loop and its output terminal being the clock feedback node. The replica delay circuit is configured to feedback and output the clock signal output by the DCC loop. A phase detector coupled to the output terminal of the replica delay circuit and configured to compare the phases between the input clock signal and the feedback clock signal output by the replica delay circuit. Wherein, the DLL controller is further coupled to the phase detector and the delay line, and is configured to adjust the delay amount of the delay line according to the comparison result of the phase detector during the locking process of the DLL loop to complete the locking of the DLL loop.

10. The delay locked loop system according to claim 1, wherein The DCC loop includes: A DCC adjustment circuit for adjusting the duty cycle of the output clock signal. A DCC detection circuit for detecting the duty cycle of the clock signal output by the DCC adjustment circuit. A DCC controller coupled to the DCC detection circuit and configured to control the duty cycle adjustment amount of the DCC adjustment circuit according to the detection result of the DCC detection circuit.

11. The delay locked loop system according to claim 1, wherein, It further includes: An input buffer with its output terminal coupled to the DLL loop and configured to receive an externally input clock signal and output it as the input clock signal and provide it to the DLL loop. A clock tree with its input terminal coupled to the output terminal of the DLL loop and configured to distribute the output clock signal to other circuits inside the delay locked loop system. An output buffer with its input terminal coupled to the output terminal of the clock tree and configured to delay and output the clock signal output by the clock tree.

12. A memory, characterized in that, It includes the delay locked loop system according to any one of claims 1-11.

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