Two-wire system Ethernet-based clock synchronization method and system with redundancy mechanism

Abstract

The invention relates to a clock synchronization method and system with a redundancy mechanism and based on a two-wire system Ethernet. Firstly, whether the system is in a master clock state or a slave clock state is determined according to a local clock quality level. The clock synchronization system in the master clock state controls the two clock synchronization processing modules, converts a clock synchronization message into a twisted pair electric signal by using a two-wire system Ethernet chip, and performs clock synchronization with other clock systems in the slave state in the control network; the two clock synchronization processing modules of the clock synchronization system in the slave clock state respectively calculate transmission delay and clock skew with the clock synchronization system in the master clock state, and the redundancy decision module selects the optimal clock skew to adjust a local clock. According to the invention, decision making is carried out on the clock skew calculated by the two independent clock synchronization modules, so that the system can still carry out high-precision clock synchronization when any one of the clock synchronization modules fails, and the stability of clock synchronization between systems in a control network is improved.

Description

Technical Field

[0001] The present invention relates to a clock synchronization method and system based on two-wire Ethernet with a redundancy mechanism, and belongs to the field of communication technologies. Background Art

[0002] In industrial control systems, time synchronization is a key factor to ensure the efficient and stable operation of the system. Industrial control systems usually involve the collaborative work of multiple devices, sensors, and controllers. These components are distributed in different geographical locations and need to complete data acquisition, processing, and transmission tasks at precise time points. And through a unified time reference, the system can accurately record the time sequence of events, which is convenient for fault diagnosis, performance analysis, and quality traceability. Therefore, the industrial control system has an extremely urgent need for a high-precision and highly reliable time synchronization system.

[0003] Currently, the traditional solution is to adopt the PTP high-precision clock synchronization method. Each device node in the industrial control network synchronizes time with the master clock node in the network through clock synchronization messages based on Ethernet, so as to achieve a high time synchronization accuracy at the microsecond level. However, with the expansion of the network scale of the industrial control system, the distance between the node devices in the network and the master clock node has exceeded the 100-meter distance in the standard Ethernet application. And by using the method of adding network switches to expand the control network, although the overall transmission distance can be increased, adding network switches will increase the complexity of the control network on the one hand, resulting in a decrease in clock synchronization accuracy, and on the other hand, it will additionally increase equipment, thus increasing the networking cost of the industrial control network.

[0004] To solve the above problems, this paper proposes a clock synchronization method and system based on two-wire Ethernet with a redundancy mechanism, that is, using two-wire Ethernet instead of standard Ethernet to realize the transmission of clock synchronization messages between node devices. Compared with standard Ethernet, the transmission range of two-wire Ethernet approaching one kilometer far exceeds the 100-meter transmission distance of standard Ethernet, and two-wire Ethernet uses twisted pairs for data transmission, and the cost is also much lower than that of Ethernet transmission cables. In addition, by adopting a redundant synchronization mechanism, the stability of the overall synchronization system is improved. Thus, high-precision and low-cost clock synchronization is achieved between node devices in a large-scale, multi-node, and long-distance complex control network. Summary of the Invention

[0005] Aiming at the above deficiencies existing in the prior art, the technical problem to be solved by the present invention is to provide a clock synchronization method and system based on two-wire Ethernet with a redundancy mechanism, which is mainly used to achieve low-cost and high-precision time synchronization between node devices in a large-scale multi-node complex industrial control network.

[0006] The clock synchronization method based on two-wire Ethernet with a redundancy mechanism includes the following steps:

[0007] After all the clock synchronization systems in the control network are initialized, management messages containing local clock quality level information are respectively transmitted into the corresponding control network, and the clock synchronization system with the highest local clock level in the control network is set to the master clock state, while other clock synchronization systems are set to the slave clock state;

[0008] When the clock synchronization system is in the master clock state, for each clock processing unit, the clock synchronization processing module controls the MAC controller module to send Sync messages into the control network. The timestamp function module records the time t1 when the Sync message is sent and transmits it to the clock synchronization processing module through the MAC controller; the clock synchronization processing module adds the timestamp t1 to the Follow-up message and then controls the MAC controller module to send it into the control network; when the MAC controller module receives the Delay-Req message sent by the clock synchronization system in the slave clock state in the control network, the timestamp function module records the time t4 when the Delay-Req message is received, and the clock synchronization processing module controls the MAC controller module to send the Dela-Resp message containing the timestamp t4 to the clock synchronization system that sent the Delay-Req message; the clock synchronization processing module periodically sends heartbeat messages to the redundancy decision module; then the redundancy decision module transmits the status signals of the clock synchronization processing module in the two clock processing units to the main control unit;

[0009] When the clock synchronization system is in the slave clock state, for each clock processing unit, after the MAC controller module receives the Sync message, the timestamp function module records the time t2 when the Sync message is received and transmits it to the clock synchronization module. Then, after the MAC controller module receives the Follow-up message, the clock synchronization processing module reads the timestamp t1 in the Follow-up message and controls the MAC controller module to send the Delay-Req message. The timestamp function module records the time t3 when the MAC controller module sends the Delay-Req message. After the clock synchronization processing module extracts the timestamp t4 in the Delay-Resp message received by the MAC controller module, according to the clock deviation calculation formula in the IEEE1588 clock synchronization protocol, it calculates the time deviation from the master clock and transmits it to the redundancy decision module; the redundancy decision module makes a decision on the time deviations calculated by the clock synchronization processing module in the two clock processing units and selects the optimal clock deviation to adjust the local clock.

[0010] After all the clock synchronization systems are initialized, the master control unit controls the clock synchronization processing modules of the two clock processing units to generate management messages containing local clock level information, and then forms Ethernet data frames with the management messages through the corresponding MAC controller modules. The two-wire Ethernet chip converts the Ethernet data frames containing local clock quality level information into twisted-pair signals and sends them into the corresponding control network.

[0011] The clock synchronization system is initially defaulted to the master clock state. After receiving the management message containing local clock level information sent by other clock synchronization systems, it compares the local clock quality level with the clock quality level in the message. If the clock quality level in the received management message is greater than the clock quality level of the current clock synchronization system, the current clock synchronization system converts from the master clock state to the slave clock state. If the clock quality level in the received management message is less than the clock quality level of this system, the current clock synchronization system continues to be in the master clock state.

[0012] When the clock quality level in the management message received by the clock synchronization system is the same as the clock quality level of the current clock synchronization system, it compares the time information of the local clock with the time information in the management message. If the time information in the management message is greater than the time information of the local clock, the current clock synchronization system converts from the master clock state to the slave clock state, otherwise the current clock synchronization system continues to be in the master clock state.

[0013] The redundancy decision module makes a decision on the time deviation calculated by the clock synchronization processing modules in the two clock processing units, and selects the optimal clock deviation to adjust the local clock, specifically as follows: when the clock synchronization system is in the slave clock state, if only one clock synchronization processing module synchronizes time with the clock synchronization system in the master clock state in the control network, it selects the clock deviation calculated by this clock synchronization processing module from the clock synchronization system in the master clock state to adjust the local clock. If both clock synchronization processing modules are normally synchronizing time with the clock synchronization systems in the master clock state in their respective control networks, it selects the clock deviation calculated by the clock synchronization processing module with a smaller clock synchronization transmission delay to adjust the local clock.

[0014] The redundant decision module makes a decision on the time deviation calculated by the clock synchronization processing module in the two-way clock processing unit, and selects the optimal clock deviation to adjust the local clock. It also includes: when the clock synchronization system is in the slave clock state, if the redundant decision module finds that the clock synchronization processing module corresponding to adjusting the local clock deviation fails and cannot calculate the clock deviation from the clock synchronization system in the master clock state, the redundant decision module automatically switches to select the clock deviation calculated by the other clock synchronization processing module to adjust the local clock; when the failed clock synchronization processing module resumes normal operation, the redundant decision module still selects the clock deviation calculated by the clock synchronization processing module that was working normally before the failure to adjust the local clock from the clock synchronization system in the master clock state.

[0015] A clock synchronization system based on two-wire Ethernet with a redundancy mechanism, including two-way clock processing units and a redundant decision module;

[0016] The clock processing unit includes:

[0017] A MAC control module, which is used to extract the time synchronization frame from the data frame received through the two-wire Ethernet chip and transmit it to the time synchronization processing module, and assemble the data message transmitted by the time synchronization processing module into a data frame and transmit it to the two-wire Ethernet chip;

[0018] A timestamp function module, which is used to record and store the timestamp information of the time synchronization message received and sent by the MAC control module, and add timestamp information to the corresponding position of the time synchronization message;

[0019] A clock synchronization processing module, which is used to send and process clock synchronization messages according to the IEEE1588 clock synchronization protocol process according to the state of the clock synchronization system; when the clock synchronization system is in the master clock state, the clock synchronization processing module controls the MAC controller module to send the Dela-Resp message containing timestamp t4 to the clock synchronization system that sent the Delay-Req message, and periodically sends a heartbeat message to the redundant decision module; when the clock synchronization system is in the slave clock state, it transmits the calculated time deviation and transmission delay between the local system and the clock synchronization system in the master clock state to the redundant decision module.

[0020] The redundant decision module, when the clock synchronization system is in the master clock state, the redundant decision module is responsible for monitoring the working status of the two-way clock synchronization processing module; when the clock synchronization system is in the slave clock state, the redundant decision module is responsible for making a decision on the clock deviation calculated by the two-way clock synchronization processing module and selecting the optimal clock deviation to adjust the local clock.

[0021] The clock synchronization processing module is used for,

[0022] When the clock synchronization system is in the master clock state, it controls the MAC controller module to send Sync messages to the control network; the clock synchronization processing module adds the timestamp t1 to the Follow-up message and then controls the MAC controller module to send it into the control network; the clock synchronization processing module controls the MAC controller module to send the Dela-Resp message containing the timestamp t4 to the clock synchronization system that sent the Delay-Req message; the clock synchronization processing module periodically sends heartbeat messages to the redundancy decision module;

[0023] When the clock synchronization system is in the slave clock state, the clock synchronization processing module reads and records the timestamp t1 in the Follow-up message, and controls the MAC controller module to send Delay-Req messages; after the clock synchronization processing module extracts the timestamp t4 in the Delay-Resp message received by the MAC controller module, it calculates the time deviation from the master clock according to the clock deviation calculation formula in the IEEE1588 clock synchronization protocol, and transmits it to the redundancy decision module;

[0024] The timestamp function module is used for,

[0025] When the clock synchronization system is in the master clock state, it records the time t1 when the Sync message is sent, and transfers it to the clock synchronization processing module through the MAC controller; the timestamp function module records the time t4 when the Delay-Req message is received;

[0026] When the clock synchronization system is in the slave clock state, the timestamp function module records the time t2 when the Sync message is received and transfers it to the clock synchronization module; the timestamp function module records the time t3 when the MAC controller module sends the Delay-Req message;

[0027] The MAC controller module is used for,

[0028] When the clock synchronization system is in the master clock state, it receives the Delay-Req message sent by the clock synchronization system in the slave clock state in the control network;

[0029] When the clock synchronization system is in the slave clock state, the MAC controller module receives the Sync message and the Follow-up message;

[0030] The redundancy decision module is used for,

[0031] When the clock synchronization system is in the slave clock state, if there is only one clock synchronization processing module that synchronizes time with the clock synchronization system in the master clock state within the control network, then select the clock deviation between the clock synchronization processing module's calculated value and the clock synchronization system in the master clock state to adjust the local clock; if both clock synchronization processing modules are normally synchronizing time with the clock synchronization systems in the master clock state within their respective control networks, then select the clock deviation calculated by the clock synchronization processing module with a smaller clock synchronization transmission delay to adjust the local clock.

[0032] When the clock synchronization system is in the slave clock state, when it is found that the clock synchronization processing module corresponding to adjusting the local clock deviation fails and cannot calculate the clock deviation between the clock synchronization system in the master clock state, automatically switch to select the clock deviation between the clock synchronization system in the master clock state calculated by the other clock synchronization processing module to adjust the local clock; when the failed clock synchronization processing module resumes normal operation, still select the clock deviation between the clock synchronization system in the master clock state calculated by the clock synchronization processing module that was working normally before the failure to adjust the local clock.

[0033] The clock synchronization system based on two-wire Ethernet with a redundancy mechanism further includes: a two-wire Ethernet chip, which is used to receive the energy signal and data signal on the control network's twisted pair, and after separating and extracting the data signal and energy signal, send them to the MAC control module and power supply module within the clock synchronization system respectively, and convert the data packet formed by the MAC control module into a twisted pair electrical signal and send it to the control network.

[0034] The two-wire Ethernet chips, MAC control modules, timestamp function modules, and time synchronization processing modules of each clock synchronization system all adopt dual-channel redundancy, and there is no data interaction between the channels.

[0035] The present invention has the following beneficial effects and advantages:

[0036] 1. High time synchronization accuracy. On the one hand, the present invention selects the system with the highest local clock quality level as the master clock system within the control network by comparing the management messages containing the local clock quality level sent by each clock synchronization system within the control network; on the other hand, it adopts the hardware timestamp technology to add a hardware timestamp to the clock synchronization message when the clock synchronization message enters the MAC layer of the clock synchronization system, improving the recording accuracy of the timestamp information during the clock synchronization process, thereby improving the synchronization accuracy between the clock synchronization systems within the control network.

[0037] 2. High reliability. The present invention applies redundancy management technology. When a clock synchronization processing module in a clock synchronization system in the slave clock state fails, or the corresponding control network fails, resulting in the clock synchronization system being unable to synchronize the clock with the master clock system, the redundancy decision module in the clock synchronization system can switch in real time to select the clock deviation value calculated by another clock synchronization processing module to adjust the local clock, thereby ensuring the reliability of clock synchronization between clock synchronization systems in the control network.

[0038] 3. Low cost. The method of the present invention uses a two-wire Ethernet for the transmission of clock synchronization messages. Compared with the cable transmission of a standard Ethernet, the twisted pair used in the two-wire Ethernet has a longer effective transmission distance and a lower cost per unit transmission distance of the transmission cable, which can reduce the number of hardware network switches in the control network. In addition, this method uses the system with the highest clock quality level in the control network as the master clock, without the need to additionally use high-precision master clock devices, thereby reducing the networking cost of the control network. Brief Description of the Drawings

[0039] Figure 1 is the overall structural block diagram of the clock synchronization system in a specific implementation example of the method of the present invention;

[0040] Figure 2 is the control network structure diagram of the clock synchronization system in a specific implementation example of the method of the present invention;

[0041] Figure 3 is the flowchart of the IEEE1588 clock synchronization protocol;

[0042] Figure 4 is the record table of the transmission delay and clock deviation calculated by the B clock synchronization module of the clock synchronization system;

[0043] Figure 5 is the comparison diagram of the second pulse output signals of clock synchronization system A and clock synchronization system B. Detailed Implementation Manner

[0044] The present invention will be further described in detail below with reference to the drawings and embodiments.

[0045] The clock synchronization system in the control network first determines whether the system is in the master clock state or the slave clock state according to the local clock quality level. The clock synchronization system in the master clock state controls two clock synchronization processing modules, and respectively converts the clock synchronization message into a twisted pair electrical signal by using a two-wire Ethernet chip to perform clock synchronization with other clock systems in the slave state within the control network; for the two clock synchronization processing modules of the clock synchronization system in the slave clock state, they respectively calculate the transmission delay and clock deviation from the clock synchronization system in the master clock state, and the redundant decision module selects the optimal clock deviation to adjust the local clock, so as to achieve stable, reliable and high-precision clock synchronization among the clock synchronization systems in the control network. By designing a redundant decision module to make decisions on the clock deviations calculated by two independent clock synchronization modules, the present invention ensures that the system can still perform high-precision clock synchronization when any one of them fails, improving the stability of clock synchronization among systems in the control network; by using the twisted pair transmission of two-wire Ethernet to replace the standard Ethernet cable transmission, the complexity of the network deployment of the control network clock synchronization system is reduced, and the overall cost is reduced while ensuring the clock synchronization accuracy among systems.

[0046] A clock synchronization method based on two-wire Ethernet with a redundancy mechanism, comprising the following steps:

[0047] After the clock synchronization system in the control network is initialized, it respectively transmits management messages containing local clock quality level information into the control network, and sets the clock synchronization system with the highest local clock level in the network to be in the master clock state, and other clock synchronization systems to be in the slave clock state.

[0048] When the clock synchronization system is in the master clock state, the clock synchronization processing module controls the MAC controller module to send a Sync message into the control network. The timestamp function module records the time t1 when the Sync message is sent and transfers it to the clock synchronization processing module. The clock synchronization processing module adds the timestamp t1 to the Follow-up message and then controls the MAC controller module to send it into the control network; when the MAC controller module receives a Delay-Req message sent by the clock synchronization system in the slave clock state in the network, the timestamp function module records the time t4 when the Delay-Req message is received. The clock synchronization processing module controls the MAC controller module to send a Dela-Resp message containing the timestamp t4 to the clock synchronization system that sent the Delay-Req message; the clock synchronization processing module periodically sends a heartbeat message to the redundant decision module, and then the redundant decision module transmits the status signals of the two clock synchronization processing modules to the main control unit.

[0049] When the clock synchronization system is in the slave clock state, after the MAC controller module receives the Sync message, the timestamp function module records the reception time t2 of the Sync message and transmits it to the clock synchronization module. Then, after the MAC controller module receives the Follow-up message, the clock synchronization processing module reads and records the timestamp t1 in the Follow-up message, and controls the MAC controller module to send a Delay-Req message. The timestamp function module records the transmission time t3 of the Delay-Req message by the MAC controller module. After the clock synchronization processing module extracts the timestamp t4 in the Delay-Resp message received by the MAC controller module, according to the clock deviation calculation formula in the IEEE1588 clock synchronization protocol, it calculates the time deviation from the master clock and transmits it to the redundancy decision module. The redundancy decision module makes a decision on the time deviations calculated by the two clock synchronization processing modules and selects the optimal clock deviation to adjust the local clock.

[0050] Transmitting the management message containing the local clock quality level information to the control network means that the master control unit controls the clock synchronization processing module to generate a management message containing the local clock level information, and then the MAC controller module assembles the management message into an Ethernet data frame. The two-wire Ethernet chip converts the Ethernet data frame containing the local clock quality level information into a twisted pair signal and then sends it into the control network.

[0051] The clock synchronization system is initially defaulted to the master clock state. After the clock synchronization system receives the management message containing the local clock level information sent by other nodes, it compares the local clock quality level with the clock quality level in the message. If the clock quality level in the received management message is higher than the clock quality level of this system, then this clock synchronization system switches from the master clock state to the slave clock state; if the clock quality level in the received management message is lower than the clock quality level of this system, then this clock synchronization system continues to be in the master clock state.

[0052] When the clock quality level in the management message received by the clock synchronization system is the same as the clock quality level of this system, it compares the time information of the local clock with the time information in the management message. If the time information in the management message is greater than the time information of the local clock, then this clock synchronization system switches from the master clock state to the slave clock state; otherwise, the clock synchronization system continues to be in the master clock state.

[0053] The clock synchronization system redundancy decision module makes a decision on the time deviation calculated by the two clock synchronization processing modules. That is, if only one clock synchronization processing module synchronizes time with the clock synchronization system in the master clock state within the control network, the clock deviation between the clock synchronization processing module and the clock synchronization system in the master clock state calculated by this module is selected to adjust the local clock. If both clock synchronization processing modules are normally synchronized with the clock synchronization systems in the master clock state within their respective control networks, the clock deviation calculated by the clock synchronization processing module with a smaller clock synchronization transmission delay is selected to adjust the local clock.

[0054] For the redundancy switching mechanism, when the redundancy decision module finds that the clock synchronization processing module corresponding to adjusting the local clock deviation fails and cannot calculate the clock deviation from the clock synchronization system in the master clock state, the redundancy decision module automatically switches to select the clock deviation between the other clock synchronization processing module and the clock synchronization system in the master clock state to adjust the local clock. When the failed clock synchronization processing module returns to normal, the redundancy decision module still selects the clock deviation between the clock synchronization processing module that was working properly before the failure and the clock synchronization system in the master clock state to adjust the local clock.

[0055] A clock synchronization system based on two-wire Ethernet with a redundancy mechanism includes:

[0056] A two-wire Ethernet chip, which is used to receive the energy signal and data signal on the control network's twisted pair wires, and after separating and extracting the data signal and energy signal, send them to the MAC control module and the power supply module respectively, and convert the data packet formed by the MAC control module into a twisted pair electrical signal and send it to the control network.

[0057] The MAC control module is used to extract the time synchronization frame from the data frame received from the two-wire Ethernet chip and transmit it to the time synchronization processing module, and form the data packet transmitted by the time synchronization processing module into a data frame and transmit it to the two-wire Ethernet chip.

[0058] The timestamp function module is used to record and store the timestamp information of the time synchronization packets received and sent by the MAC control module, and add timestamp information at the corresponding position of the time synchronization packet.

[0059] The clock synchronization processing module is used to send and process clock synchronization packets according to the IEEE1588 clock synchronization protocol process according to the state of the clock synchronization system. When the clock synchronization system is in the master clock state, it regularly sends heartbeat packets to the redundancy decision module. When the clock synchronization system is in the slave clock state, it transmits the calculated time deviation and transmission delay between the local system and the clock synchronization system in the master clock state to the redundancy decision module.

[0060] The redundant decision-making module is responsible for monitoring the working status of the two clock synchronization processing modules when the clock synchronization system is in the master clock state; when the clock synchronization system is in the slave clock state, the redundant decision-making module is responsible for making a decision on the clock deviations calculated by the two clock synchronization processing modules and selecting the optimal clock deviation to adjust the local clock.

[0061] For each clock synchronization system, the two-wire Ethernet chip, MAC control module, timestamp function module, and time synchronization processing module all adopt dual redundancy, and there is no data interaction between the channels.

[0062] Figure 1 It is the overall structural block diagram of the specific implementation example of the time synchronization system in the method of the present invention. Below, in combination with the overall structural block diagram of the specific implementation example of the time synchronization system, each component module of the clock synchronization system will be specifically introduced.

[0063] Two-wire Ethernet chip: Since the overall control network uses twisted-pair technology for data transmission and simultaneously transmits data and power on the two-wire Ethernet twisted pair, the two-wire Ethernet chip is mainly responsible for receiving the data signal and energy signal transmitted on the control network twisted pair, transmitting the received data signal to the MAC control module for further data parsing, transmitting the energy signal to the power supply module to provide power for the stable operation of the system, and converting the Ethernet data frame formed by the MAC control module into a two-wire Ethernet signal and transmitting it to the control network twisted pair. There are two two-wire Ethernet chips in a single clock synchronization system. The two-wire Ethernet chip A is connected to control network A, and the two-wire Ethernet B is connected to control network B. They are independent of each other and do not perform data interaction. The two-wire Ethernet chip selects the ADIN1100 chip of ADI Company, which has the advantages of low power consumption, strong anti-interference ability, and mature technology, meeting the requirements of the system for the two-wire Ethernet chip.

[0064] The MAC control module, timestamp function module, time synchronization processing module, redundant decision-making module, and main control unit of the clock synchronization system are all implemented on the embedded processor MCU. In this implementation example, the RT1064 microprocessor of NXP Company is selected. This type of microprocessor uses the ARM Cortex-M7 core, has the characteristics of high performance and low latency, and the rich on-chip resources support the functional design and development of the above modules. In addition, there are 2 MAC controllers extended on the RT1064 microprocessor chip, which can simplify the design and implementation difficulty of the clock synchronization system of this method. Below, the MAC control module, timestamp function module, time synchronization processing module, and redundant decision-making module will be specifically introduced respectively.

[0065] MAC Control Module: Centered around the MAC controller of the RT1064 microprocessor, it adopts a dual-channel redundant structure. MAC Control Module A and MAC Control Module B respectively receive data signals in Control Network A and Control Network B through two-wire Ethernet chip A and two-wire Ethernet chip B, and extract the time synchronization frames from the data frames received from the two-wire Ethernet chips and transmit them to Time Synchronization Processing Module A and Time Synchronization Processing Module B; when MAC Control Module A and MAC Control Module B respectively receive the clock synchronization messages sent by the corresponding time synchronization processing modules, they assemble the clock synchronization messages into Ethernet data frames and transmit them to the corresponding two-wire Ethernet chips.

[0066] Timestamp Function Module: Timestamp Function Module A and Timestamp Function Module B are respectively responsible for recording the moments when the corresponding MAC control modules receive the clock synchronization messages, storing and transmitting the sending moments to the corresponding clock synchronization processing modules in the form of timestamp information, and recording and storing the moments when the corresponding MAC control modules send the clock synchronization messages, and adding the sending moments to the corresponding positions of the clock synchronization messages in the form of timestamps.

[0067] Clock Synchronization Processing Module: The functions of the clock synchronization processing module vary slightly according to the different states of the clock synchronization system. When the clock synchronization system is in the master clock state, Clock Synchronization Processing Module A and Clock Synchronization Processing Module B respectively send Sync messages and Follow-up messages regularly according to the IEEE clock synchronization protocol, process the Delay-Req messages received through their respective control networks, and promptly reply to the Delay-Resp messages to the corresponding clock synchronization systems in the slave clock state. Then Clock Synchronization Processing Module A and Clock Synchronization Processing Module B regularly send the operating states of their respective clock synchronization processing modules to the Redundancy Decision Module; when the clock synchronization system is in the slave clock state, after Clock Synchronization Processing Module A and Clock Synchronization Processing Module B receive the Sync messages and Follow-up messages sent by the clock synchronization systems in the master clock state within their respective control networks, they send Delay-Req messages to the clock synchronization systems in the master clock state within their respective control networks, and then after receiving the replied Delay-Resp messages, calculate according to the timestamp information in the clock synchronization messages and the time information recorded and stored by the timestamp function module using the transmission delay and clock offset calculation formulas in the IEEE1588 clock synchronization protocol, and transmit the transmission delay and clock offset calculated by their respective clock synchronization processing modules to the Redundancy Decision Module for processing.

[0068] Redundant decision-making module: When the clock synchronization system is mainly in the master clock state, the redundant decision-making module is mainly responsible for monitoring the working states of the two clock synchronization processing modules and notifying the main control unit; when the clock synchronization system is in the slave clock state, if only one of the two clock synchronization processing modules is normally performing the clock synchronization process, the redundant decision-making module selects the clock deviation calculated by the normally operating clock synchronization processing module as the adjustment value to adjust the local clock; if both clock synchronization processing modules are working normally, according to the transmission delay calculated by the clock synchronization processing module, the clock deviation calculated by the clock synchronization processing module with a smaller transmission delay is selected to adjust the local clock.

[0069] Figure 2 It is a control network structure diagram of the implementation example clock synchronization system constructed for specifically introducing the method of the present invention. First, there are three clock synchronization systems A, B, and C in the control network. The two-wire Ethernet chips A of the three clock synchronization systems are connected together by twisted pairs to form control network A, and the two-wire Ethernet chips B of the clock synchronization systems are connected together by twisted pairs to form control network B; The clock synchronization system A uses a GPS timing system as the clock source, and according to the IEEE clock synchronization protocol standard, the clock quality level of the clock synchronization system A is 6. The clock synchronization system B uses a high-precision crystal oscillator as the clock source, and the clock quality level is 248. The clock synchronization system C uses Internet timing as the clock source, and the clock quality level is 13. Next, the working process of the clock synchronization system of the method of the present invention will be specifically introduced.

[0070] First, after the clock synchronization systems A, B, and C are successfully initialized, all clock synchronization systems default to the master clock state and send management messages containing the clock quality levels of their own systems to the other two clock synchronization systems in the control network. The smaller the clock quality level value, the higher the clock quality level, and the higher the accuracy and credibility of the clock source. Therefore, after receiving the management message containing the clock quality level of their own system sent by the clock synchronization system A, the clock synchronization systems B and C adjust the state of their own systems from the master clock state to the slave clock state. Then the clock synchronization system A starts to perform clock synchronization with the clock synchronization systems B and C. Below, taking the clock synchronization process between the clock synchronization system A and the clock synchronization system B in the control network A as an example, it will be specifically introduced in combination with Figure 3 the IEEE1588 clock synchronization protocol flow chart shown.

[0071] The clock synchronization processing module A of the clock synchronization system A in the master clock state forms a Sync message every 2S according to the IEEE clock synchronization protocol standard and transmits it to the MAC control module A. The MAC control module A assembles the Sync message into an Ethernet data frame and sends it to the two-wire Ethernet chip A. The two-wire Ethernet chip A converts the Ethernet data frame into a twisted pair signal and transmits it to the control network A. The timestamp function module A records the moment t1 when the Ethernet data frame leaves the MAC control module and notifies the time synchronization processing module A. After receiving the moment t1, the time synchronization processing module A forms a Follow-up message, adds the moment t1 to the corresponding position in the Follow-up message, and then sends it to the MAC control module A. After the MAC control module A assembles the Follow-up message into an Ethernet frame, it sends it to the control network A through the two-wire Ethernet chip A.

[0072] The two-wire Ethernet chip A of the clock synchronization system B in the slave clock state, after receiving the twisted pair signal containing the Sync message sent by the clock synchronization system A in the control network A, converts and parses it to transmit the Ethernet frame containing the Sync message to the MAC control module A. The MAC control module transmits the Sync message in the Ethernet frame to the clock synchronization processing module A. The timestamp function module A records the moment t2 when the MAC control module receives the Ethernet frame containing the Sync message and notifies the clock synchronization processing module A. Then, after the two-wire Ethernet chip A of the clock synchronization system B receives the twisted pair signal containing the Follow-up message, it converts and parses it to transmit the Ethernet frame containing the Follow-up message to the MAC control module A. The MAC control module A transmits the Follow-up message to the clock synchronization module A. The clock synchronization processing module A extracts the moment t1 in the message and stores it. Then, the clock synchronization processing module A forms a Delay-Req message and sends it to the control network A through the two-wire Ethernet chip A according to the above process. The timestamp function module A records the moment t3 when the Ethernet data frame containing the Delay-Req message leaves the MAC control module and notifies the clock synchronization processing module A.

[0073] After receiving the twisted pair signal containing the Delay-Req message, the two-wire Ethernet chip A of the clock synchronization system A converts and parses it, and transmits the Ethernet frame containing the Delay-Req message to the MAC control module A. The MAC control module A extracts the Delay-Req message and sends it to the clock synchronization processing module A. The timestamp function module A records the moment t4 when the MAC control module receives the Ethernet frame containing the Delay-Req message, and notifies the clock synchronization processing module A. After receiving the moment t4, the time synchronization processing module A constructs a Delay-Resp message, adds the moment t4 to the corresponding position in the Delay-Resp message, and then transmits it to the control network A according to the previous sending process of the clock synchronization message.

[0074] After receiving the twisted pair signal containing the Delay-Resp message, the two-wire Ethernet chip A of the clock synchronization system B processes it according to the processing flow of receiving the Follow-up message. The clock synchronization processing module extracts and stores the moment t4 in the Delay-Resp message. At this time, the clock synchronization processing module of the clock synchronization system B has obtained the timestamps t1, t2, t3, and the moment t4 of the clock synchronization process, and calculates the transmission delay delay between the clock synchronization system B and the clock synchronization system A according to the Figure 3 formula for transmission delay and clock deviation in A and the clock deviation offset A , and then the clock synchronization processing module B of the clock synchronization system B transmits the transmission delay delay A and the clock deviation offset A to the redundancy decision module for decision-making.

[0075] For the clock synchronization system A in the master clock state, the clock synchronization processing module A and the clock synchronization processing module B of the system will regularly send heartbeat messages to the redundancy decision module of the clock synchronization system A, and the redundancy decision module will notify the main control unit of the state of the system clock synchronization processing module. For the clock synchronization system B in the slave clock state, the clock synchronization processing module A and the clock synchronization processing module B of the system will transmit the calculated transmission delay and clock deviation to the redundancy decision module of the system. If the redundancy decision module only receives the transmission delay and clock deviation calculated by one clock synchronization processing module, the redundancy decision module selects the clock deviation calculated by this clock synchronization processing module to adjust the local clock; if the redundancy decision module receives the transmission delay and clock deviation sent by two clock synchronization processing modules, as shown in this implementation example, the clock synchronization processing module A and B of the clock synchronization system B perform clock synchronization with the clock synchronization system A through the control networks A and B respectively, then the redundancy decision module makes a decision based on the average transmission delay calculated by the two clock synchronization processing modules.

[0076] As shown Figure 4 in the figure, they are the transmission delay and clock deviation calculated by the clock synchronization processing module A and the clock synchronization processing module B during continuous operation for a period of time. Since the transmission delay will not fluctuate significantly after the systems in the control network work stably, in this embodiment, the first 10 transmission delays calculated by the clock synchronization module are selected for the calculation of the average delay. The average transmission delay between the clock synchronization processing module A of the clock synchronization system B and the clock synchronization processing module A of the clock synchronization system A is 1.63 μs, and the average transmission delay between the clock synchronization processing module B of the clock synchronization system B and the clock synchronization processing module B of the clock synchronization system A is 0.89 μs. Therefore, the redundancy decision module of the clock synchronization system B selects the clock deviation calculated by the clock synchronization processing module B to adjust the local clock. The local clock is not adjusted before the redundancy decision module makes a decision. Therefore, the clock deviation between the clock synchronization processing module of the clock synchronization system B and the clock synchronization system A is about 500 microseconds. Figure 5 A screenshot of the PPS second pulse signals output by the clock synchronization system A and the clock synchronization system B. From Figure 5 it can be found that after the local clock is adjusted by the redundancy decision module of the clock synchronization system B, the clock deviation between the clock synchronization system B and the clock synchronization system A has been reduced to about -100 ns - 200 ns, thus verifying the accuracy and effectiveness of the clock synchronization of the method of the present invention.

Claims

1. A clock synchronization method based on two-wire Ethernet with a redundancy mechanism, characterized in that: The following steps are involved: After all clock synchronization systems in the control network are initialized, they transmit management messages containing local clock quality level information to the corresponding control networks respectively, and set the clock synchronization system with the highest local clock level in the control network to be in the master clock state, and the other clock synchronization systems to be in the slave clock state; When the clock synchronization system is in the master clock state, for each clock processing unit, the clock synchronization processing module controls the MAC controller module to send a Sync message to the control network, and the timestamp function module records the time t1 when the Sync message is sent, and transmits it to the clock synchronization processing module through the MAC controller; The clock synchronization processing module controls the MAC controller module to send the message to the control network after adding the timestamp t1 to the Follow-up message; when the MAC controller module receives the Delay-Req message sent by the clock synchronization system in the slave clock state in the control network, the timestamp function module records the time t4 when the Delay-Req message is received, and the clock synchronization processing module controls the MAC controller module to send the Dela-Resp message containing the timestamp t4 to the clock synchronization system that sent the Delay-Req message; the clock synchronization processing module periodically sends heartbeat messages to the redundancy decision module; Then the redundancy decision module transmits the status signals of the clock synchronization processing modules in the two clock processing units to the main control unit; When the clock synchronization system is in the slave clock state, for each clock processing unit, after the MAC controller module receives the Sync message, the timestamp function module records the time t2 of receiving the Sync message and transmits it to the clock synchronization module. Then, after the MAC controller module receives the Follow-up message, the clock synchronization processing module reads the timestamp t1 recorded in the Follow-up message, and controls the MAC controller module to send a Delay-Req message. The timestamp function module records the time t3 when the MAC controller module sends the Delay-Req message. After the clock synchronization processing module extracts the timestamp t4 in the Delay-Resp message received by the MAC controller module, it calculates the time deviation from the master clock according to the clock deviation calculation formula in the IEEE1588 clock synchronization protocol, and transmits it to the redundancy decision module; The redundancy decision module makes a decision on the time deviation calculated by the clock synchronization processing modules in the two clock processing units, and selects the optimal clock deviation to adjust the local clock.

2. The clock synchronization method based on two-wire Ethernet with a redundancy mechanism according to claim 1, characterized in that: After all the clock synchronization systems are initialized, the main control unit controls the clock synchronization processing modules of the two clock processing units to generate management messages containing local clock level information, and then composes the management messages into Ethernet data frames through the corresponding MAC controller modules. The two-wire Ethernet chip converts the Ethernet data frames containing local clock quality level information into twisted pair signals and sends them to the corresponding control network.

3. The clock synchronization method based on two-wire Ethernet with a redundancy mechanism according to claim 1, characterized in that: The clock synchronization system is initially in the master clock state by default. After receiving the management message containing the local clock level information sent by other clock synchronization systems, it compares the local clock quality level with the clock quality level in the message; If the clock quality level in the received management message is greater than the clock quality level of the current clock synchronization system, the current clock synchronization system is converted from the master clock state to the slave clock state; If the clock quality level in the received management message is lower than the clock quality level of the current system, the current clock synchronization system continues to be in the master clock state.

4. The clock synchronization method based on two-wire Ethernet with a redundancy mechanism according to claim 1, characterized in that: When the clock quality level in the management message received by the clock synchronization system is the same as the clock quality level of the current clock synchronization system, the time information of the local clock is compared with the time information in the management message; if the time information in the management message is greater than the time information of the local clock, the current clock synchronization system is converted from the master clock state to the slave clock state, otherwise the current clock synchronization system continues to be in the master clock state.

5. The clock synchronization method based on two-wire Ethernet with a redundancy mechanism according to claim 1, characterized in that: The redundant decision module makes a decision on the time deviation calculated by the clock synchronization processing modules in the two clock processing units, and selects the optimal clock deviation to adjust the local clock, specifically as follows: when the clock synchronization system is in the slave clock state, if there is only one clock synchronization processing module that performs time synchronization with the clock synchronization system in the master clock state in the control network, then the clock deviation calculated by the clock synchronization processing module with the clock synchronization system in the master clock state is selected to adjust the local clock; if both clock synchronization processing modules are normally synchronized with the clock synchronization systems in the master clock state in their respective control networks, then the clock deviation calculated by the clock synchronization processing module with the smaller clock synchronization transmission delay is selected to adjust the local clock.

6. The clock synchronization method based on two-wire Ethernet with a redundancy mechanism according to claim 1, characterized in that: The redundant decision module makes a decision on the time deviation calculated by the clock synchronization processing modules in the two clock processing units, selects the optimal clock deviation to adjust the local clock, and also includes: when the clock synchronization system is in a slave clock state, when the redundant decision module finds that the corresponding clock synchronization processing module for adjusting the local clock deviation fails and cannot calculate the clock deviation with the clock synchronization system in the master clock state, the redundant decision module automatically switches to select the clock deviation calculated by another clock synchronization processing module with the clock synchronization system in the master clock state to adjust the local clock; when the clock synchronization processing module with the failure returns to normal, the redundant decision module still selects the clock deviation calculated by the clock synchronization processing module that works normally before the failure is recovered with the clock synchronization system in the master clock state to adjust the local clock.

7. A clock synchronization system based on two-wire Ethernet with a redundant mechanism, characterized in that: It includes two clock processing units and a redundant decision module; The clock processing unit comprises: The MAC control module is used to extract the time synchronization frame from the data frame received through the two-wire Ethernet chip and transmit it to the time synchronization processing module, and assemble the data message transmitted by the time synchronization processing module into a data frame and transmit it to the two-wire Ethernet chip; The timestamp function module is used to record and store the timestamp information of the time synchronization messages received and sent by the MAC control module, and to add the timestamp information to the corresponding position of the time synchronization message; The clock synchronization processing module is used to send and process clock synchronization messages according to the IEEE1588 clock synchronization protocol process based on the state of the clock synchronization system; when the clock synchronization system is in the master clock state, the clock synchronization processing module controls the MAC controller module to send the Dela-Resp message containing the timestamp t4 to the clock synchronization system that sends the Delay-Req message, and regularly sends heartbeat messages to the redundancy decision module; when the clock synchronization system is in the slave clock state, the calculated time deviation and transmission delay between the system and the clock synchronization system in the master clock state are transmitted to the redundancy decision module. Redundancy decision module: When the clock synchronization system is in the master clock state, the redundant decision module is responsible for monitoring the working status of the two clock synchronization processing modules; when the clock synchronization system is in the slave clock state, the redundant decision module is responsible for making decisions on the clock deviations calculated by the two clock synchronization processing modules and selecting the optimal clock deviation to adjust the local clock.

8. The clock synchronization system based on two-wire Ethernet with a redundancy mechanism according to claim 7, characterized in that: The clock synchronization processing module is used to: When the clock synchronization system is in the master clock state, the MAC controller module is controlled to send Sync messages to the control network; The clock synchronization processing module adds the timestamp t1 to the Follow-up message and controls the MAC controller module to send it to the control network; the clock synchronization processing module controls the MAC controller module to send the Dela-Resp message containing the timestamp t4 to the clock synchronization system that sends the Delay-Req message; the clock synchronization processing module periodically sends a heartbeat message to the redundancy decision module; When the clock synchronization system is in the slave clock state, the clock synchronization processing module reads the timestamp t1 recorded in the Follow-up message and controls the MAC controller module to send the Delay-Req message; after the clock synchronization processing module extracts the timestamp t4 in the Delay-Resp message received by the MAC controller module, it calculates the time deviation from the master clock according to the clock deviation calculation formula in the IEEE1588 clock synchronization protocol and transmits it to the redundancy decision module; The timestamp function module is used to: When the clock synchronization system is in the master clock state, the time t1 when the Sync message is sent is recorded and transmitted to the clock synchronization processing module through the MAC controller; The timestamp function module records the time t4 when the Delay-Req message is received; When the clock synchronization system is in the slave clock state, the timestamp function module records the time t2 of receiving the Sync message and transmits it to the clock synchronization module; The timestamp function module records the time t3 when the MAC controller module sends the Delay-Req message; The MAC controller module is used to: When the clock synchronization system is in the master clock state, it receives a Delay-Req message sent by the clock synchronization system in the slave clock state in the control network; When the clock synchronization system is in the slave clock state, the MAC controller module receives Sync messages and Follow-up messages; The redundancy decision module is used to: When the clock synchronization system is in the slave clock state, if there is only one clock synchronization processing module that performs time synchronization with the clock synchronization system in the master clock state in the control network, the clock deviation calculated by the clock synchronization processing module with the clock synchronization system in the master clock state is selected to adjust the local clock; if both clock synchronization processing modules are normally performing time synchronization with the clock synchronization systems in the master clock state in their respective control networks, the clock deviation calculated by the clock synchronization processing module with the smaller clock synchronization transmission delay is selected to adjust the local clock; When the clock synchronization system is in the slave clock state, when it is found that the corresponding clock synchronization processing module for adjusting the local clock deviation fails and cannot calculate the clock deviation with the clock synchronization system in the master clock state, it automatically switches to select another clock synchronization processing module to calculate the clock deviation with the clock synchronization system in the master clock state to adjust the local clock; when the faulty clock synchronization processing module returns to normal, the clock synchronization processing module that works normally before the fault is recovered still selects the clock deviation with the clock synchronization system in the master clock state to adjust the local clock.

9. The clock synchronization system based on two-wire Ethernet with a redundancy mechanism according to claim 7, characterized in that: Also includes: The two-wire Ethernet chip is used to receive energy signals and data signals on the twisted pair of the control network, separate and extract the data signal from the energy signal, and send them to the MAC control module and power supply module in the clock synchronization system respectively, and convert the data message formed by the MAC control module into a twisted pair electrical signal and send it to the control network.

10. The clock synchronization system based on two-wire Ethernet with a redundancy mechanism according to claim 7, characterized in that: The two-wire Ethernet chip, MAC control module, time stamp function module and time synchronization processing module of each clock synchronization system all adopt dual-path redundancy, and no data interaction is performed between the paths.

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