Real-time optical communication signal processing method and device based on FPGA

Abstract

The invention discloses a real-time optical communication signal processing method and device based on an FPGA in the technical field of optical communication, and the method comprises the steps: generating a first three-dimensional chaotic sequence and a second three-dimensional chaotic sequence through a Logistic-Lorenz cascade chaotic model according to a secret key initial value based on a first iteration number and a second iteration number; generating an encrypted sequence according to the first three-dimensional chaotic sequence and the second three-dimensional chaotic sequence; performing XOR encryption on the original data by using the encryption sequence to obtain encrypted data; binary conversion is carried out on the key initial value, the first iteration times and the second iteration times, and after expansion, serial splicing is carried out to form a synchronous frame header; and the synchronous frame header and the encrypted data are modulated by the PAM4 and then enter an optical fiber for transmission.

Description

Technical Field

[0001] This application belongs to the field of optical communication technology, and particularly relates to a real-time optical communication signal processing method and device based on FPGA. Background Art

[0002] With the continuous growth of transmission capacity, achieving uninterrupted, low-latency authentication and security of data has also become a key issue. For secure transmission, encryption at the physical layer can encrypt data signals at high speed and low latency with minimal impact on the system. Among the recently reported physical layer encryption methods, digital chaotic encryption has attracted extensive interest due to its ergodicity, pseudo-randomness, and high sensitivity to initial values. In addition, digital chaotic encryption is operated by digital signal processing (DSP), so it can be easily incorporated into signal generation to economically and effectively improve data security. However, in existing schemes, the initial value of the chaotic system is simply assumed to be a key pre-shared between two legal communication parties. Therefore, key distribution in digital chaotic encryption schemes remains a substantial problem.

[0003] Currently, in the field of optical communication, quantum key distribution (QKD) is the only reliable technology that theoretically provides absolute security. Once an eavesdropper accesses the quantum channel, it will be unconditionally detected due to the irreproducibility of single photons. However, the implementation of quantum key distribution significantly increases the cost and complexity of system design. Other key distribution technologies using the characteristics of optical channel links have been proposed, such as phase fluctuations in large-scale Mach-Zehnder interferometers (MZIs), mode mixing in multimode fibers, and phase fluctuations between orthogonally polarized modes (OPMs) in delay interferometers (DIs). However, these methods require additional equipment and will change the structure of optical communication nodes, which is incompatible with traditional fiber optic transmission systems.

[0004] At the same time, the structure of traditional chaotic encryption systems is relatively simple, and hardware implementation leads to accuracy loss, resulting in a reduction in the initial value sensitivity of the chaotic system, making it vulnerable to attacks and causing encryption failures. Summary of the Invention

[0005] Objective: In view of at least one of the above technical problems, this application provides a real-time optical communication signal processing method and device based on FPGA, which uses a multi-cascaded chaotic model for encryption, cascades the Lorenz and Logistic chaotic models, and solves the problems of data transmission security and key distribution by writing key information into the synchronization header and superimposing the key signal and the encrypted signal for transmission.

[0006] The technical solution adopted by this application is as follows:

[0007] In a first aspect, the present application provides a real-time optical communication signal processing method based on FPGA, including:

[0008] Based on the first iteration number and the second iteration number, generate a first three-dimensional chaotic sequence through a Logistic-Lorenz cascaded chaotic model according to the initial key value and a second three-dimensional chaotic sequence ;

[0009] According to the first three-dimensional chaotic sequence and the second three-dimensional chaotic sequence generate an encryption sequence;

[0010] Use the encryption sequence to perform exclusive-or encryption on the original data to obtain encrypted data;

[0011] Perform binary conversion and extension on the initial key value, the first iteration number, and the second iteration number, and then serially splice them to form a synchronization header;

[0012] After modulating the synchronization header and the encrypted data together by PAM4, transmit them into the optical fiber.

[0013] In a second aspect, the present application provides a real-time optical communication signal processing device based on FPGA, including a processor and a storage medium;

[0014] The storage medium is used to store instructions;

[0015] The processor is used to operate according to the instructions to execute the method according to the first aspect.

[0016] In a third aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method according to the first aspect is implemented.

[0017] Beneficial effects: The real-time optical communication signal processing method and device based on FPGA provided by the present application have the following advantages: The Logistic-Lorenz chaotic cascaded model is utilized to generate two groups of three-dimensional chaotic sequences according to different iteration numbers. Among the two groups of three-dimensional chaotic sequences generated by the Logistic-Lorenz chaotic cascaded model for and The system performs sequence scrambling and bit width selection, and uses the chaotic sequence after sequence scrambling and bit width selection to generate an encryption sequence to scramble the original signal, which greatly improves the security performance of the system. In addition, the above method designs a key control module, which can update the encryption sequence or the key according to the real-time change of the chaotic system state quantity and the number of iterations. At the same time, the key information is used as the synchronization frame header, which can be superimposed and transmitted simultaneously with the chaotic encryption signal. The receiving end can extract the key information from the synchronization frame header part of the superimposed signal by step-by-step decoding.

[0018] The multi-cascade chaos model is used for encryption. The Lorenz and Logistic chaos models are cascaded. By writing the key information into the synchronization frame header, the key signal is superimposed and transmitted with the encrypted signal, thereby solving the security problem of data transmission and the key distribution problem. It also improves the pseudo-random characteristics of the chaotic sequence and increases the key space. In addition, real-time digital signal processing is used instead of offline digital signal processing. The real-time digital signal processing system can respond to the input signal immediately, with low processing delay, and can achieve "transmission and processing". It can also monitor the input signal in real time and provide instant feedback and adjustment as needed. This is very important for coping with changing environmental and channel conditions in communication to maintain communication quality and stability. The high parallel characteristics of the field programmable gate array (FPGA) make it particularly suitable for complex DSP algorithms, thereby achieving efficient parallel computing. The low latency characteristics enable it to process the transmitted data in real time, which is suitable for applications with high real-time requirements. The high flexibility allows it to implement different DSP algorithms through reconfiguration. Compared with traditional processors, FPGA has lower power consumption in executing DSP algorithms. The above characteristics make FPGA widely used in the field of digital signal processing.

[0019] The present application provides a real-time optical communication signal processing method based on FPGA with good real-time performance and high security, which makes full use of the real-time performance and high parallelism of FPGA. The key uses the chaotic system to generate a chaotic sequence, and uses the Logistic-Lorenz cascade chaotic model to select two iterations to generate two sets of chaotic sequences. and , and according to The chaotic sequence used is selected to perform chaotic encryption on the data. The key signal is used as the frame header and PAM4 modulated and transmitted simultaneously with the encrypted signal. At the receiving end of the system, the legitimate user can demodulate the key signal from the received signal, and then decrypt the encrypted signal with the initial key to restore the original signal. When the state quantity and number of iterations of the chaotic system at the sending end change, the receiving end takes out the synchronization frame header part in the received data and extracts the key information, so that the sending end can continuously update the key and achieve uninterrupted identity authentication during the decryption process of the legitimate receiving end. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic flowchart of a real-time optical communication signal processing method based on FPGA according to an embodiment of the present application;

[0021] Figure 2 It is a schematic diagram of an L-L chaotic sequence generator based on FPGA according to an embodiment of the present application;

[0022] Figure 3 It is a schematic diagram of the bifurcation of the Logistic chaotic map according to an embodiment of the present application;

[0023] Figure 4 It is a schematic diagram of the phase of the Lorenz chaotic model according to an embodiment of the present application;

[0024] Figure 5 It is a schematic diagram of the phase of the Logistic-Lorenz chaotic model according to an embodiment of the present application;

[0025] Figure 6 It is a schematic diagram of the principle of generating an encryption sequence according to an embodiment of the present application;

[0026] Figure 7 and Figure 8 They are respectively schematic diagrams of the waveforms of the transmitter signal and the receiver signal according to an embodiment of the present application. Specific Embodiments

[0027] The present application will be further described below with reference to the accompanying drawings and embodiments. The following embodiments are only used to more clearly illustrate the technical solutions of the present application, and should not be used to limit the protection scope of the present application.

[0028] In the description of the present application, the meaning of several is more than one, the meaning of multiple is more than two, greater than, less than, exceeding, etc. are understood as not including the number itself, and above, below, within, etc. are understood as including the number itself. If there is a description of first and second, it is only for the purpose of distinguishing technical features and should not be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence of the indicated technical features.

[0029] In the description of the present application, the description referring to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0030] The term "and / or" is merely a description of the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0031] Example 1: This example provides a real-time optical communication signal processing method based on FPGA, as Figure 1 shown, including:

[0032] S1. Based on the first iteration number and the second iteration number, generate a first three-dimensional chaotic sequence and a second three-dimensional chaotic sequence according to the initial key value through the Logistic-Lorenz cascaded chaotic model and a second three-dimensional chaotic sequence ;

[0033] S2. Generate an encryption sequence according to the first three-dimensional chaotic sequence and the second three-dimensional chaotic sequence ;

[0034] S3. Use the encryption sequence to perform exclusive-OR encryption on the original data to obtain encrypted data;

[0035] S4. Perform binary conversion and extension on the initial key value, the first iteration number, and the second iteration number, and then serially splice them to form a synchronization frame header;

[0036] S5. Together with the synchronization frame header and the encrypted data, pass through PAM4 modulation and then enter optical fiber transmission.

[0037] In this application, the chaotic system adopts the Logistic-Lorenz cascaded chaotic model. Since it finally needs to be implemented on FPGA hardware, the chaotic model needs to be discretized.

[0038] The Logistic map is a relatively simple one-dimensional chaotic system:

[0039]

[0040] where x is the variable of the Logistic map; . are the variables after the nth and (n + 1)th iterations, and μ is called the bifurcation parameter; when 3.5699456 < μ ≤ 4, the Logistic map has chaotic properties, as Figure 3 shown in the bifurcation diagram of the Logistic chaotic map.

[0041] The Lorenz map is a three-dimensional nonlinear dynamics discrete chaotic map system that is currently widely used, and its mathematical model is:

[0042]

[0043] where: A, B, and C are system parameters, A = 10, B = 28, and C = 8 / 3 are typical parameters, 、 、 are the system state variables x 、y 、z derivatives with respect to time t. Figure 4 is the phase diagram of the Lorenz chaotic model.

[0044] To facilitate the implementation of a continuous chaotic system using an FPGA, the Euler algorithm can be used to discretize the above equation, resulting in the following discretized equation:

[0045]

[0046] where n is the number of iterations. When the time step is small enough, for example, taking = 0.001 s, the above two systems have the same dynamic characteristics, and the corresponding discrete equation at this time is:

[0047]

[0048] It can be seen from the formula that floating-point numbers are used in the calculation, but in a hardware system, floating-point numbers are difficult to calculate. Therefore, based on the FPGA system (hardware), this application uses equivalent transformation to change the floating-point iteration process of the chaotic sequence into a fixed-point iteration process. The specific operation is to quantize the three-dimensional chaotic model and substitute the corresponding initial key into the chaotic system in the form of fixed-point numbers to generate a chaotic pseudorandom sequence. Considering from the perspective of hardware implementation, the base of exponential quantization mainly uses 2, so multiplication can be implemented by shifting. Due to the requirement of calculation accuracy, 24-bit quantization is adopted in this scheme, that is, 2 24 , in the hardware language, it is calculated by shifting 24 bits to the left, and multiplying the system state variables and parameters by 2 24 and retaining the integer part to obtain:

[0049]

[0050] At this time, the operand width is 24 bits. Therefore, zeros are padded to the high bits of the operand to expand it to 32 bits. Considering that during the multiplication operation, the result may be wider than the operand width and some precision will be lost during the quantization process, using a larger width to store intermediate results during the multiplication operation, such as 64 bits or 96 bits, helps to maintain the precision of the intermediate results. By maintaining a larger width, this precision loss can be minimized through appropriate rounding and truncation in subsequent processing, and the final result is truncated to 32 bits.

[0051] The Logistic-Lorenz cascaded chaotic model takes the output of Logistic as the input of the Lorenz chaotic model, and performs the discretization and floating-point parameter fixed-point conversion steps according to the above steps to obtain the Logistic-Lorenz cascaded chaotic model.

[0052] Therefore, in some embodiments, the Logistic-Lorenz cascaded chaotic model is expressed as:

[0053]

[0054] where x 、y and z are the system state variables; n is the number of iterations; A, B, and C are the system parameters, is the time step. As Figure 5 shown is the phase schematic diagram of the Logistic-Lorenz cascaded chaotic model.

[0055] As Figure 2 shown is the L-L chaotic sequence generator based on FPGA in this embodiment. The Logistic-Lorenz cascaded chaotic model first uses the Logistc chaotic model to generate a one-dimensional chaotic sequence, takes it as the input of the Lorenz chaotic model and generates a three-dimensional chaotic sequence through the Lorenz chaotic model, and based on the FPGA system (hardware), uses equivalent transformation to change the floating-point iteration process of the chaotic sequence into a fixed-point iteration process. The specific operation is to quantize the chaotic model and substitute the corresponding initial key into the chaotic system in the form of fixed-point numbers to generate a chaotic pseudorandom sequence.

[0056] For the original data, this application uses the FPGA to generate a pseudorandom binary sequence as the original data, and uses the chaotic sequence generated by the above Logistic-Lorenz chaotic model to perform bit scrambling on the original data. The specific scrambling steps are as follows.

[0057] In some embodiments, in step S2, according to the first three-dimensional chaotic sequence and the second three-dimensional chaotic sequence Generate an encrypted sequence, including:

[0058] Extract the lower five bits from as the first counter cnt1 and the second counter cnt2 respectively;

[0059] Concatenate and to form a 64-bit first sequence ch1_data_buf1, and concatenate and to form a 64-bit second sequence ch1_data_buf2;

[0060] According to the value of the first counter cnt1, continuously extract 32-bit data from the first sequence ch1_data_buf1 starting from the cnt1-th bit to obtain a third sequence; according to the value of the second counter cnt2, continuously extract 32-bit data from the second sequence ch1_data_buf2 starting from the cnt2-th bit to obtain a fourth sequence;

[0061] Concatenate the fourth sequence and the third sequence as the encrypted sequence. As Figure 6 shown is the schematic diagram of the principle of generating the encrypted sequence in this embodiment.

[0062] In some embodiments, in this step S3, use the encrypted sequence to perform exclusive-or encryption on the original data to obtain encrypted data, including:

[0063] ;

[0064] Wherein, represents the original data in binary form, represents the encrypted sequence, represents the encrypted data after exclusive-or encryption, represents the exclusive-or operation.

[0065] After generating the encrypted sequence and performing exclusive-or encryption on the original data, the present application then uses the key information as the synchronization frame header to communicate together with the encrypted data. The key information includes the key initial value and the number of iterations of the chaotic system.

[0066] In some embodiments, in this step S4, perform binary conversion, expansion on the key initial value, the first number of iterations, and the second number of iterations, and then serially concatenate them to form the synchronization frame header, including:

[0067] Multiply the key initial value by 2 24 and then convert it into binary form, and convert the first number of iterations and the second number of iterations into binary forms respectively;

[0068] Zero-pad the high-order bits of the bit widths of the initial key value in binary form, the first iteration count in binary form, and the second iteration count in binary form to 24 bits, obtaining a 24-bit initial key value, a 24-bit first iteration count, and a 24-bit second iteration count;

[0069] Serial concatenate the 24-bit initial key value, the 24-bit first iteration count, and the 24-bit second iteration count to form a synchronization header.

[0070] Taking the Logistic-Lorenz cascaded chaotic model as an example, assume the initial key values are 0.001, 0.002, and 0.02; the first iteration count is 99; the second iteration count is 123. Assume , , , , . Multiply it by 2 according to the quantization specification above 24 After that, , , . Convert it to binary to get , , , , . For the convenience of unifying the bit width and separating the key information, this application stipulates that the bit width of the key information is zero-padded at the high-order bits to be extended to 24 bits, , , , , , and serial concatenate them to form a synchronization header.

[0071] Furthermore, serial concatenating the 24-bit initial key value, the 24-bit first iteration count, and the 24-bit second iteration count to form a synchronization header includes:

[0072] ;

[0073] Wherein, is the synchronization header, , , are the three 24-bit numbers of the initial key value; is the 24-bit first iteration count; is the 24-bit second iteration count.

[0074] Verification Example: This application uses an FPGA chip of xczu15eg-ffvb1156-2-i, and connects the DAC module of AD9744 and the ADC module of AD9434 through the LVDS DDR interface. An intensity modulation direct detection system is adopted. On the FPGA development board at the transmitting end, the chaotic sequence generated by the Logistic-Lorenz cascaded chaotic model is used to perform exclusive OR encryption on the key and data, and then it is converted from digital to analog through AD9744. After being amplified by an electrical amplifier, it is input into a Mach-Zehnder modulator for intensity modulation and the signal is loaded onto the optical carrier generated by the laser source. After the signal is transmitted through a single-mode optical fiber, a variable optical attenuator (VOA) is used to adjust the received optical power, and a photodetector is used to receive the optical signal and perform photoelectric conversion. Subsequently, AD9434 is used to perform analog-to-digital conversion on the electrical signal, and then the correct key is obtained through DSP processing in the FPGA development board to decrypt and demodulate the encrypted PAM4 signal and calculate the bit error rate.

[0075] When ensuring the accuracy of the key, this application performs final decryption on the decrypted data. After the initial signal is serially-parallel converted and then PAM4 demapped, it is compared with the original generated bit information at the beginning. Figure 7 and Figure 8 are respectively the waveform schematic diagrams of the transmitting-end signal and the receiving-end signal in this embodiment. It can be seen that the receiving end can accurately extract the correct key information for demodulation.

[0076] Embodiment 2: Based on Embodiment 1, this embodiment provides a real-time optical communication signal processing device based on FPGA, including a processor and a storage medium;

[0077] The storage medium is used to store instructions;

[0078] The processor is used to operate according to the instructions to execute the method described in Embodiment 1.

[0079] Embodiment 3: Based on Embodiment 1, this embodiment provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in Embodiment 1 is implemented.

[0080] Embodiment 4: Based on Embodiment 1, this embodiment provides a computer device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the method described in Embodiment 1 is implemented.

[0081] Embodiment 5: Based on Embodiment 1, this embodiment provides a computer program product, including a computer program, and when the computer program is executed by a processor, the method described in Embodiment 1 is implemented.

[0082] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0083] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices produce a device for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0084] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction device that implements the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0085] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0086] The above are only the preferred embodiments of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A real-time optical communication signal processing method based on FPGA, characterized in that: include: Based on the first iteration number and the second iteration number, the first three-dimensional chaotic sequence is generated through the Logistic-Lorenz cascade chaotic model according to the initial value of the key. and the second three-dimensional chaotic sequence ; According to the first three-dimensional chaotic sequence and the second three-dimensional chaotic sequence Generate an encrypted sequence; Using the encryption sequence to XOR encrypt the original data to obtain encrypted data; The initial value of the key, the first iteration number and the second iteration number are converted into binary, expanded and serially spliced ​​to form a synchronization frame header; The synchronization frame header and encrypted data are modulated by PAM4 and then transmitted through the optical fiber.

2. The method according to claim 1, characterized in that The Logistic-Lorenz cascade chaos model is expressed as: ； Among them, x ,y and z is the system state quantity, x is the variable of Logistic mapping; n is the number of iterations; A, B and C are system parameters, is the time step.

3. The method according to claim 2, characterized in that A=10, B=28, C=8 / 3.

4. The method according to claim 1, characterized in that: The initial key values ​​are 0.001, 0.002 and 0.02; the first iteration number is 99; the second iteration number is 123.

5. The method according to claim 1, characterized in that According to the first three-dimensional chaotic sequence and the second three-dimensional chaotic sequence Generate an encryption sequence, including: from Extract the lower five bits as the first counter cnt1 and the second counter cnt2 respectively; will and Splice to form a 64-bit first sequence ch1_data_buf1, and Spliced ​​together to form a 64-bit second sequence ch1_data_buf2; According to the value of the first counter cnt1, 32 bits of data are continuously taken out from the first sequence ch1_data_buf1 starting from the cnt1th bit to obtain a third sequence; according to the value of the second counter cnt2, 32 bits of data are continuously taken out from the second sequence ch1_data_buf2 starting from the cnt2th bit to obtain a fourth sequence; The fourth sequence and the third sequence are concatenated as the encrypted sequence.

6. The method according to claim 1, characterized in that The encrypted data is obtained by XOR-encrypting the original data using the encryption sequence, including: ； in, Represents raw data in binary form, represents an encrypted sequence, Indicates the encrypted data after XOR encryption. Represents the exclusive-or operation.

7. The method according to claim 1, characterized in that The initial key value, the first iteration number, and the second iteration number are converted into binary, expanded, and serially concatenated to form a synchronization frame header, including: Multiply the initial key value by 2 24 Then convert it into binary form, convert the first iteration number and the second iteration number into binary form respectively; The bit widths of the initial key value in binary form, the first iteration number in binary form, and the second iteration number in binary form are respectively padded with zeros to be extended to 24 bits, so as to obtain a 24-digit number of the initial key value, a 24-digit number of the first iteration number, and a 24-digit number of the second iteration number; The 24-digit initial key value, the 24-digit first iteration number, and the 24-digit second iteration number are serially concatenated to form a synchronization frame header.

8. The method according to claim 7, characterized in that The 24-digit initial key value, the 24-digit first iteration number, and the 24-digit second iteration number are serially concatenated to form a synchronization frame header, including: ； in, is the synchronization frame header, , , Three 24-digit numbers for the initial key value; The 24-digit number for the first iteration; A 24-digit number for the second iteration.

9. A real-time optical communication signal processing device based on FPGA, characterized in that: including processor and storage medium; The storage medium is used to store instructions; The processor is configured to operate according to the instructions to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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