Data exchange method

Abstract

The invention belongs to the technical field of data exchange, and discloses a data exchange method, which is applied to a data exchange device, and the data exchange device comprises a main control module, an exchange module and a plurality of receiving modules. The method comprises the following steps: a first receiving module receives multiple pieces of time slice data of a first peripheral, and analyzes and recombines each piece of time slice data with a predetermined identifier based on an exchange instruction to obtain insertion data comprising a destination address; determining a first transmission link according to the switching instruction and the destination address, and sending the first transmission link to a switching module; the switching module determines a second transmission link according to the switching instruction and the destination address, and sends the switching instruction to the main control module or the second receiving module through the second transmission link; and the second receiving module determines a corresponding output node and a second peripheral according to the destination address, unpacks the inserted data and sends the unpacked inserted data to the second peripheral. According to the invention, the method can achieve the recognition and processing of the inserted data of the peripheral, and the receiving and output of the time slice data at different rates.

Description

Technical Field

[0001] This application relates to the technical field of data exchange, and in particular, to a data exchange method. Background Art

[0002] Currently, the mainstream video switching matrices are all based on the circuit switching technology of CrossPoint chips. However, the CrossPoint chips can only achieve data switching and cannot insert and extract link data, resulting in poor flexibility of data exchange and difficulty in meeting various communication requirements between peripherals and switches. Moreover, the input and output node bandwidths of the CrossPoint chips are the same, and different-rate data exchange cannot be achieved simultaneously. When the CrossPoint chips are actually applied, circuit modules such as signal scaling usually need to be added between peripherals to achieve rate modulation of the received and output signals and ensure communication with different peripherals. However, this not only increases the cost of data exchange but also brings more workload to hardware debugging. Therefore, the existing switching methods have problems in that data insertion and different-rate data exchange cannot be achieved. Summary of the Invention

[0003] This application provides a data exchange method that can identify and process inserted data of peripherals and receive and output peripheral data at different rates.

[0004] In a first aspect, this application provides a data exchange method applied to a data exchange device. The data exchange device includes a main control module, a switching module, and multiple receiving modules designed based on an FPGA chip. The method includes:

[0005] A first receiving module receives multiple time-slice data of a first peripheral, parses and reorganizes each time-slice data with a predetermined identifier based on a switching instruction to obtain inserted data including a destination address and having a first bandwidth;

[0006] The first receiving module determines a first transmission link according to the switching instruction and the destination address, and sends the inserted data to the switching module through the first transmission link;

[0007] The switching module determines a second transmission link according to the switching instruction and the destination address in the inserted data, and sends the inserted data to the main control module or a second receiving module through the second transmission link;

[0008] The second receiving module determines a corresponding output node and a second peripheral according to the destination address in the inserted data, unpacks the inserted data according to the bandwidth of the output node, and sends it to the second peripheral.

[0009] Further, the method further includes:

[0010] The first receiving module aggregates the time slice data without the predetermined identifier into the switching data of the second bandwidth;

[0011] The first receiving module determines the third transmission link based on the switching instruction and the switching data, and sends the switching data to the switching module through the third transmission link;

[0012] The switching module determines the fourth transmission link based on the switching instruction and the switching data, and sends the switching data to the third receiving module through the fourth transmission link;

[0013] The third receiving module determines the corresponding output node and the third peripheral according to the switching data and the switching instruction, unpacks the switching data according to the bandwidth of the output node, and sends it to the third peripheral.

[0014] Further, the first bandwidth is less than the second bandwidth.

[0015] Further, the method further includes:

[0016] Before sending the insertion data, the first receiving module determines whether the flag signal bit in the insertion data is valid; if valid, the insertion data is sent to the switching module through the first transmission link.

[0017] Further, the predetermined identifier is a preset preamble in the time slice data, and the preset preamble includes 5 hexadecimal characters.

[0018] Further, the first receiving module receives multiple time slice data of the first peripheral, parses and reorganizes the time slice data with the predetermined identifier based on the switching instruction, and obtains the insertion data with the first bandwidth including the destination address, including:

[0019] The first receiving module receives multiple time slice data of the first peripheral, parses the time slice data with the predetermined identifier, and determines whether there is a preset master address therein; if so, it is used as the destination address, and the time slice data with the predetermined identifier is reorganized to obtain the insertion data with the first bandwidth including the preset master address.

[0020] Further, the time slice data includes the first peripheral serial number of the first peripheral;

[0021] The first receiving module receives multiple time slice data of the first peripheral, parses and reorganizes the time slice data with the predetermined identifier based on the switching instruction, and obtains the insertion data with the first bandwidth including the destination address, further including:

[0022] When the preset master address does not exist, the first receiving module searches for the second peripheral serial number corresponding to the first peripheral serial number in the exchange instruction, uses the second peripheral serial number as the destination address, and reorganizes the time slice data with a predetermined identifier to obtain inserted data including the second peripheral serial number and having a first bandwidth.

[0023] Further, the above first receiving module determines the first transmission link according to the exchange instruction and the destination address, including: when the destination address is the preset master address, the first receiving module determines the master uplink according to the exchange instruction and uses it as the first transmission link.

[0024] Further, the above first receiving module determines the first transmission link according to the exchange instruction and the destination address, and further includes:

[0025] When the destination address is the second peripheral serial number, the first receiving module determines the target uplink according to the exchange instruction and uses it as the first transmission link.

[0026] Further, the method further includes:

[0027] The master control module receives the custom data and the downlink address of the custom data, and sends the custom data and the downlink address to the exchange module;

[0028] The exchange module determines the downlink transmission link according to the downlink address and the exchange instruction, and sends the custom data to the fourth receiving module through the downlink transmission link.

[0029] Further, after receiving the custom data, the master control module further includes:

[0030] Judging whether the flag signal bit in the custom data is valid;

[0031] If it is valid, send the custom data and the downlink address to the exchange module.

[0032] Further, the custom data includes a signaling code, and inquiry information, upgrade instructions or device management information that correspond one-to-one with the signaling code.

[0033] Further, the inquiry information includes node temperature inquiry information, peripheral temperature inquiry information, the number of peripheral connections or the peripheral device type.

[0034] Further, the upgrade instructions include FPGA firmware upgrade instructions or SOC firmware upgrade instructions.

[0035] Further, the device management information includes link signal quality, the number of link disconnections or link connection status.

[0036] Further, the method further includes:

[0037] When the fourth receiving module parses the custom data as an inquiry message, it generates feedback data based on the custom data and the preset master control address, and sends it to the switching module through the master control uplink.

[0038] After receiving the feedback data through the master control uplink, the switching module sends it to the master control module.

[0039] Furthermore, the method further includes:

[0040] When the fourth receiving module parses the custom data as an upgrade instruction or device management information, it executes the custom data, and generates an acknowledgment message and sends it to the switching module after the execution is completed.

[0041] Furthermore, the sum of the first bandwidth and the second bandwidth is equal to the bandwidth of each transmission link.

[0042] Furthermore, when the bandwidth of each transmission link is 10G, the first bandwidth is 2G and the second bandwidth is 8G.

[0043] Furthermore, the bandwidth of the output nodes of each receiving module includes 1G, 2.5G, and 5G.

[0044] In summary, compared with the prior art, the beneficial effects brought by the technical solution provided by the embodiment of the present application at least include:

[0045] A data exchange method provided by an embodiment of the present application. First, by performing the identification of a predetermined identifier on the multiple time slice data of the received peripheral device, the determination of the inserted data of the peripheral device is realized, and considering the possible different functions or purposes of the inserted data of the peripheral device, the destination address and the transmission link of the inserted data are determined separately, realizing various communication requirements of the peripheral device; secondly, by packing the time slice data into the inserted data of the first bandwidth and then unpacking and outputting, the design of the unpacking mechanism can support the expansion of the bandwidth of the input and output nodes, realizing the input and output of the peripheral device data of various different rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a flowchart of a data exchange method provided by an exemplary embodiment of the present application.

[0047] Figure 2 It is a schematic diagram of inserted data and exchanged data provided by an exemplary embodiment of the present application.

[0048] Figure 3 It is a structural diagram of a data exchange device provided by an exemplary embodiment of the present application.

[0049] Figure 4 It is a structural diagram of a data exchange device provided by another exemplary embodiment of the present application. Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0051] All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0052] In the description of the present application, the terms "first", "second", "third", "fourth", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", "third", etc. may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0053] Please refer to Figure 1 , the embodiment of the present application provides a data exchange method, which is applied to a data exchange device. The data exchange device includes a main control module, a switching module, and a plurality of receiving modules designed based on an FPGA chip. The method includes:

[0054] Step S11, the first receiving module receives a plurality of time slice data of the first peripheral device, parses and reorganizes each time slice data with a predetermined identifier based on a switching instruction, and obtains inserted data including a destination address and having a first bandwidth.

[0055] Among them, the time slice data is data transmitted by the peripheral device to the receiving module in the form of time slice insertion; specifically, the peripheral device can choose to insert data into a time slice without a predetermined identifier to achieve simple data exchange, or insert the data into a time slice with a preset identifier and send it to the connected receiving module to indicate that the data is of the inserted nature, and address detection needs to be performed to determine whether it is data sent up to the main control module, and the corresponding transmission link is used for transmission. Taking a 10clk cycle as an example, assume that only the time slices of the middle 8 clk are actual channel data without a predetermined identifier, while the time slices of the other 2 clk are inserted data with a predetermined identifier, that is, the peripheral device inserts the message data to be transmitted in 2 clk.

[0056] Among them, the predetermined identifier can be a preset preamble in the time slice data, and the preset preamble includes 5 hexadecimal characters. For example: forms such as 0x55+0x55+0x55+0x5d+0xd5, 0x45+0x90+0x85+0x6d+0x9f, 0x33+0x07+0x55+0x5e+0xf5, etc.; if a preset preamble appears in the time slice data, it is determined that there is a predetermined identifier.

[0057] The exchange instruction is sent from the host computer to the exchange module through the main control module, and then sent from the exchange module to each receiving module; the exchange principle is a multi-level lookup table, and the lookup table is an N*N matrix table, which stores the transmission links between peripherals with communication connection relationships, and the main control uplink separately set to make the inserted data go up to the main control module; therefore, according to the destination address of the inserted data, it can be determined which transmission link the data of the first peripheral needs to take to reach the destination address.

[0058] Step S12, the first receiving module determines the first transmission link according to the exchange instruction and the destination address, and sends the inserted data to the exchange module through the first transmission link.

[0059] Specifically, considering the existence of exchange data without a predetermined identifier, the value of the first bandwidth can be set to be less than the bandwidth of each transmission link to avoid transmission conflicts with the exchange data.

[0060] Step S13, the exchange module determines the second transmission link according to the exchange instruction and the destination address in the inserted data, and sends the inserted data to the main control module or the second receiving module through the second transmission link.

[0061] Specifically, if the destination address of the inserted data is the main control module, the second transmission link is the data transmission link between the exchange module and the main control module. If the destination address is the second peripheral serial number, the target downlink to reach the second peripheral needs to be found in the exchange instruction as the second transmission link, and the inserted data is sent to the second receiving module connected to the second peripheral.

[0062] Step S14, the second receiving module determines the corresponding output node and the second peripheral according to the destination address in the inserted data, unpacks the inserted data according to the bandwidth of the output node, and sends it to the second peripheral.

[0063] Among them, the second receiving module and the first receiving module can be the same or different receiving modules, which specifically depends on which receiving module the second peripheral is connected to when the destination address of the first peripheral is the second peripheral.

[0064] Specifically, the unpacking mechanism of the present application can unpack the inserted data of the first bandwidth at the rate of the output node, and send the obtained several unpacked data to the second peripheral device through the output node in sequence.

[0065] The above embodiment provides a data exchange method. First, by performing predetermined identification on multiple time slice data received from the peripheral device, the judgment of the inserted data of the peripheral device is realized. Taking into account the different functions or purposes that the inserted data of the peripheral device may have, the destination address and transmission link of the inserted data are determined separately to realize various communication needs of the peripheral device. Secondly, by packaging the time slice data into the inserted data of the first bandwidth and then unpacking it for output, the design of the unpacking mechanism can support the expansion of the bandwidth of the input and output nodes, and realize the input and output of peripheral data at multiple different rates.

[0066] In some embodiments, the method further comprises:

[0067] Step S21: The first receiving module aggregates the time slice data without a predetermined identifier into exchange data of a second bandwidth.

[0068] Among them, the first bandwidth is smaller than the second bandwidth; in view of the fact that in actual use, the demand for inserting data is usually smaller than the demand for exchanging data, most of the bandwidth of the transmission link is provided to the exchanging data of the second bandwidth, and a small part of the bandwidth is reserved for the inserting data of the first bandwidth, so as to ensure that the resources of the transmission link are not wasted as much as possible.

[0069] Step S22: The first receiving module determines a third transmission link based on the exchange instruction and the exchange data, and sends the exchange data to the exchange module through the third transmission link.

[0070] Step S23: The exchange module determines a fourth transmission link based on the exchange instruction and the exchange data, and sends the exchange data to the third receiving module through the fourth transmission link.

[0071] Step S24: the third receiving module determines the corresponding output node and the third peripheral device according to the exchange data and the exchange instruction, unpacks the exchange data according to the bandwidth of the output node, and sends the data to the third peripheral device.

[0072] In a specific implementation process, multiple time slice data received within a time period may all have a predetermined identifier or may not have one. Therefore, the insertion data and the exchange data are not necessarily transmitted at the same time, and may also be transmitted separately in batches.

[0073] The exchange instruction is sent by the main control module to the switching module in real time and then sent by the switching module to each receiving module. Therefore, when inserting data and exchanging data are transmitted, if they are not transmitted simultaneously, different exchange instructions may be used, resulting in the time slice data of the first peripheral being sent to different peripherals successively even if they are all from the first peripheral.

[0074] In the above situation, the third transmission link may be the same as the first transmission link; the third receiving module and the second receiving module may be the same receiving module, that is, the second transmission link and the fourth transmission link may be the same link.

[0075] Considering that there is a situation where inserting data and exchanging data are transmitted simultaneously, the transmission link can be set as the sum of the first bandwidth and the second bandwidth to solve the situation where a certain transmission link transmits both exchange data and inserting data simultaneously.

[0076] In some embodiments, the method further includes:

[0077] Before the first receiving module sends the inserted data, it determines whether the flag signal bit in the inserted data is valid; if it is valid, the inserted data is sent to the switching module through the first transmission link.

[0078] Specifically, please refer to Figure 2 the packed exchange data and inserted data in: The first row represents the control signaling flag bit, that is, the signaling code: the signaling code 0x00 represents a data packet without a predetermined identifier, and the corresponding nodes D0 - D7 below it are the packed exchange data, and each square contains 1 byte of data; while the signaling codes 0x01 and 0xFE are the start and stop flag bits of the inserted data; the data in the signaling code 0x01 includes the start flag byte S, the data packet length bytes len0 to len7, and also includes misc_data, ctrl_data, and the valid flag; under the signaling code 0xfe, there are msg_data and the stop flag T; misc_data, ctrl_data, and msg_data can be filled with inserted data such as device management, firmware upgrade, and communication protocol packets between devices; other unused fields can also be added under the signaling code 0xFE as needed, but the corresponding signaling code needs to be changed accordingly.

[0079] The peripheral can define that the valid signal in the time slice data indicates whether these inserted data are valid. For example, the peripheral can define Figure 2 in the valid byte, the lowest 3 bits bit respectively indicate misc_data_valid, ctrl_data_valid, msg_data_valid. When the flag signal bit valid bit is 1, the corresponding byte is valid; when it is 0, the corresponding byte is invalid and the data packet is discarded.

[0080] Through the recognition of whether the flag bit in the data is valid in the above embodiments, the validity of the inserted data can be judged, avoiding the waste of bandwidth resources caused by transmitting invalid data.

[0081] In some embodiments, the first receiving module receives multiple time-slot data of the first peripheral device, parses and reorganizes each time-slot data with a predetermined identifier based on the exchange instruction, and obtains inserted data including the destination address and having a first bandwidth, including:

[0082] The first receiving module receives multiple time-slot data of the first peripheral device, parses each time-slot data with a predetermined identifier, and judges whether a preset master control address exists therein; if it exists, it uses it as the destination address, and reorganizes each time-slot data with a predetermined identifier to obtain inserted data including the preset master control address and having a first bandwidth.

[0083] Further, the time-slot data includes the first peripheral device number of the first peripheral device.

[0084] The above first receiving module receives multiple time-slot data of the first peripheral device, parses and reorganizes each time-slot data with a predetermined identifier based on the exchange instruction, and obtains inserted data including the destination address and having a first bandwidth, further including:

[0085] When the preset master control address does not exist, the first receiving module searches for the second peripheral device number corresponding to the first peripheral device number in the exchange instruction, uses the second peripheral device number as the destination address, and reorganizes each time-slot data with a predetermined identifier to obtain inserted data including the second peripheral device number and having a first bandwidth.

[0086] Specifically, the exchange instruction uses 4-bit binary data to represent the interface number of the receiving module, and 6-bit binary data to represent the number of the peripheral device. For example, 0001_000001_0010_000010 is used to represent the connection between the first peripheral device of the first receiving module and the second peripheral device of the second receiving module; the connection between each other pair of peripheral devices is represented by a 20-bit data. If a maximum of 1024 connection states are reserved, an array of 1024 dimensions is formed, and each number is represented by 20-bit data.

[0087] Therefore, after receiving the time-slot data of the first peripheral device, the second peripheral device number having a connection relationship with the first peripheral device and the number of the second receiving module where the second peripheral device is located can be found in the exchange instruction according to the number of the first peripheral device, and the first transmission link and the second transmission link defined in the exchange instruction for data exchange between the first peripheral device and the second peripheral device can be obtained.

[0088] In some embodiments, the above first receiving module determines the first transmission link according to the exchange instruction and the destination address, including:

[0089] When the destination address is the preset master address, the first receiving module determines the master uplink according to the switching instruction and uses it as the first transmission link. The switching module and each receiving module have stored the preset master address in advance, and the switching instruction stores the master uplink that should be used when the data with the transmission destination address of each receiving module being the master module arrives at the switching module.

[0090] The master uplink is a dedicated link for data going up to the master module, different from the link used for data with other destination addresses being peripherals. Only the inserted data with the destination address being the preset master address can pass through the master uplink.

[0091] Furthermore, the above-mentioned first receiving module determining the first transmission link according to the switching instruction and the destination address further includes:

[0092] When the destination address is the second peripheral serial number, the first receiving module determines the target uplink according to the switching instruction and uses it as the first transmission link. If the preset master address exists in the time slice data, there is no need to search for the switching instruction, and it is directly packed into inserted data and sent to the switching module through the master uplink; otherwise, the data needs to be sent to the switching module according to the target uplink specified in the switching instruction for reaching the second peripheral.

[0093] In some embodiments, the method further includes:

[0094] The master module receives the custom data and the downlink address of the custom data, and sends the custom data and the downlink address to the switching module; the switching module determines the downlink transmission link according to the downlink address and the switching instruction, and sends the custom data to the fourth receiving module through the downlink transmission link.

[0095] Among them, the custom data includes a signaling code, and the inquiry information, upgrade instruction or device management information that corresponds one-to-one with the signaling code. The inquiry information includes node temperature inquiry information, peripheral temperature inquiry information, the number of peripheral connections or the type of peripheral device; the upgrade instruction includes an FPGA firmware upgrade instruction or an SOC firmware upgrade instruction; the device management information includes link signal quality, the number of link disconnections or link connection status.

[0096] In some embodiments, after receiving the custom data, the master module further includes:

[0097] Judge whether the flag signal bit in the custom data is valid.

[0098] If it is valid, send the custom data and the downlink address to the switching module.

[0099] Specifically, the packaging forms of both the custom data and the inserted data are Figure 2As shown, therefore, it is possible to determine whether the received custom data is valid and whether it needs to be discarded by detecting the corresponding flag signal bit (valid bit) in the custom data.

[0100] In some embodiments, the method further includes:

[0101] When the fourth receiving module parses the custom data as an inquiry message, it generates feedback data based on the custom data and a preset master address, and sends it to the switching module through the master uplink;

[0102] After receiving the feedback data through the master uplink, the switching module sends it to the master module.

[0103] For example, if the inquiry message asks about the interface temperature of the fourth receiving module, then after receiving the inquiry message, the fourth receiving module obtains the interface temperature value, and takes the received temperature value and the preset master address as feedback information and sends it up to the master module.

[0104] In some embodiments, the method further includes:

[0105] When the fourth receiving module parses the custom data as an upgrade instruction or device management information, it executes the custom data, and after the execution is completed, generates an acknowledgment message and sends it to the switching module.

[0106] Specifically, the format of the custom data is the same as the format of the inserted data shown in Figure 2 Therefore, after the custom data reaches the corresponding fourth receiving module, it is also necessary to perform reverse unpacking on the custom data. The misc_data, ctrl_data, and msg_data parsed out need to be repackaged. For example, misc_data needs to buffer the byte data in each slice, repackage it in the form of a fifo, and perform corresponding operations according to the custom protocol, including but not limited to device management, firmware upgrade, communication between devices, etc. After each operation is completed, generate the corresponding ACK message and repackage it into the original link.

[0107] The above embodiments implement the function of inserting custom data into peripherals, enabling the present application to not only support data exchange and insertion between peripherals and insertion of peripherals into the master module, but also enable the master module to insert data into any peripheral, further improving the flexibility and applicability of the data exchange method of the present application.

[0108] In some embodiments, data is transmitted between the switching module and the master module through low-voltage differential signals.

[0109] Among them, the low-voltage differential signal is LVDS (Low-Voltage Differential Signaling) communication.

[0110] Further, data is transmitted between each receiving module and its connected peripheral devices through leaf nodes, and data is transmitted between the receiving module and the switching module through branch nodes. Please refer to Figure 4 , where the receiving module receives the time slice data of each peripheral device through the leaf node. The rates of the leaf nodes of different receiving modules can be different, specifically not limited to 1 Gbps, 2.5 Gbps, or 5 Gbps; however, the inserted data after packaging is all of the first bandwidth, and the switched data is all of the second bandwidth.

[0111] In specific implementation, the receiving module sends the data to the switching module through the branch node. The sum of the first bandwidth and the second bandwidth is equal to the bandwidth of each transmission link; when the bandwidth of each transmission link is 10 G, the first bandwidth is 2 G, and the second bandwidth is 8 G. The bandwidths of the output nodes of each receiving module include 1 G, 2.5 G, and 5 G.

[0112] For example, the branch node always reserves 10 G of bandwidth. 8 G of bandwidth is used to access the time slice data without a predetermined identifier of the leaf node, and 2 G of bandwidth is used to insert the time slice data with an additional predetermined identifier.

[0113] Taking Figure 2 the switched data and the inserted data as an example, they are aggregated into a 10 G branch node in the leafswitch, where the switched data 0x00 occupies 8 G of bandwidth, and the inserted data 0x01 + 0xfe occupies 2 G of bandwidth.

[0114] Taking a specific example to illustrate the execution process of inserting data from the first peripheral device to the second peripheral device in the present application:

[0115] Suppose the first receiving module is externally connected to 48 1 G peripheral devices downstream and has 4 10 G links connected to the switching module upstream; the second receiving module is externally connected to 48 1 G peripheral devices downstream and has 4 10 G links connected to the switching module upstream.

[0116] If the first peripheral device of the first receiving module needs to send a message to the second peripheral device of the second receiving module, the main control module first needs to connect the peripheral device numbers of the two peripheral devices in the switching instruction: use 4-bit binary data to represent the interface number of the receiving module, and use 6-bit binary data to represent the peripheral device number. Thus, 0001_000001_0010_000010 can be used to represent the connection between the first peripheral device of the first receiving module and the second peripheral device of the second receiving module. The connection between each other pair of peripheral devices is represented by a 20-bit data. If a maximum of 1024 connection states are reserved, a 1024-dimensional array is formed, and each number is represented by 20-bit data.

[0117] The first receiving module needs to first parse the time slice data of the first peripheral device, extract the message data with a predetermined identifier to be inserted, mark its own channel signal, and find the serial numbers of the second peripheral device and the second receiving module corresponding to the first peripheral device according to the switching instruction, pack the serial numbers and the message data, and insert them into the 2G redundant time gap slice in the uplink 10G signal.

[0118] The switching module receives the first 10G link data of the first receiving module, parses the inserted data according to the valid signal, parses the serial numbers of the second receiving module and the second peripheral device that the inserted data needs to be forwarded to, and finds the first 10G link of the second receiving module according to the switching instruction to insert the data; the second receiving module parses the inserted data of the first 10G link, and finds the output node of the second peripheral device according to the serial number of the second peripheral device in the switching instruction to insert the data, and the whole process is completed.

[0119] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0120] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it cannot be understood as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A data exchange method, characterized in that, Applied to a data exchange device, the data exchange device includes a main control module, a switching module, and a plurality of receiving modules designed based on an FPGA chip. The method includes: The first receiving module receives a plurality of time-slot data from a first peripheral device, parses and reorganizes each of the time-slot data with a predetermined identifier based on a switching instruction, and obtains inserted data including a destination address and having a first bandwidth. The first receiving module determines a first transmission link according to the switching instruction and the destination address, and sends the inserted data to the switching module through the first transmission link. The switching module determines a second transmission link according to the switching instruction and the destination address in the inserted data, and sends the inserted data to the main control module or the second receiving module through the second transmission link. The second receiving module determines a corresponding output node and a second peripheral device according to the destination address in the inserted data, unpacks the inserted data according to the bandwidth of the output node, and sends it to the second peripheral device.

2. The data exchange method according to claim 1, characterized in that It further includes: The first receiving module aggregates each of the time-slot data without a predetermined identifier into switching data with a second bandwidth. The first receiving module determines a third transmission link based on the switching instruction and the switching data, and sends the switching data to the switching module through the third transmission link. The switching module determines a fourth transmission link based on the switching instruction and the switching data, and sends the switching data to the third receiving module through the fourth transmission link. The third receiving module determines a corresponding output node and a third peripheral device according to the switching data and the switching instruction, unpacks the switching data according to the bandwidth of the output node, and sends it to the third peripheral device.

3. The data exchange method according to claim 2, characterized in that The first bandwidth is less than the second bandwidth.

4. The data exchange method according to claim 1, characterized in that It further includes: Before sending the inserted data, the first receiving module determines whether the flag signal bit in the inserted data is valid; if it is valid, the inserted data is sent to the switching module through the first transmission link.

5. The data exchange method according to claim 1, wherein The predetermined identifier is a preset preamble in the time-slot data, and the preset preamble includes 5 hexadecimal characters.

6. The data exchange method according to claim 1, wherein The first receiving module receives a plurality of time-slot data from a first peripheral device, parses and reorganizes each of the time-slot data with a predetermined identifier based on a switching instruction, and obtains inserted data including a destination address and having a first bandwidth, including: The first receiving module receives a plurality of time-slot data from a first peripheral device, parses each of the time-slot data with a predetermined identifier, and determines whether a preset main control address exists therein; if it exists, it is used as the destination address, and each of the time-slot data with a predetermined identifier is reorganized to obtain inserted data including the preset main control address and having a first bandwidth.

7. The data exchange method according to claim 6, wherein The time-slot data includes a first peripheral device number of the first peripheral device; the first receiving module receives a plurality of time-slot data from a first peripheral device, parses and reorganizes each of the time-slot data with a predetermined identifier based on a switching instruction, and obtains inserted data including a destination address and having a first bandwidth. It further includes: When the preset master address does not exist, the first receiving module searches for a second peripheral serial number corresponding to the first peripheral serial number in the switching instruction, uses the second peripheral serial number as the destination address, and reorganizes each piece of time slice data with a predetermined identifier to obtain inserted data including the second peripheral serial number and having a first bandwidth.

8. The data exchange method according to claim 7, wherein The first receiving module determines a first transmission link according to the switching instruction and the destination address, including: When the destination address is the preset master address, the first receiving module determines a master uplink according to the switching instruction and uses it as the first transmission link.

9. The data exchange method according to claim 8, wherein The first receiving module determines a first transmission link according to the switching instruction and the destination address, and further includes: When the destination address is the second peripheral serial number, the first receiving module determines a target uplink according to the switching instruction and uses it as the first transmission link.

10. The data exchange method according to claim 8, characterized in that, It further includes: The master control module receives custom data and a downlink address of the custom data, and sends the custom data and the downlink address to the switching module; The switching module determines a downlink transmission link according to the downlink address and the switching instruction, and sends the custom data to the fourth receiving module through the downlink transmission link.

11. The data exchange method according to claim 10, wherein After receiving the custom data, the master control module further includes: Judging whether the flag signal bit in the custom data is valid; If it is valid, the custom data and the downlink address are sent to the switching module.

12. The data exchange method according to claim 10, wherein The custom data includes a signaling code, and inquiry information, upgrade instructions, or device management information that corresponds one-to-one with the signaling code.

13. The data exchange method according to claim 12, wherein The inquiry information includes node temperature inquiry information, peripheral temperature inquiry information, the number of peripheral connections, or the peripheral device type.

14. The data exchange method according to claim 12, wherein The upgrade instructions include FPGA firmware upgrade instructions or SOC firmware upgrade instructions.

15. The data exchange method according to claim 14, wherein The device management information includes link signal quality, the number of link disconnections, or link connection status.

16. The data exchange method according to claim 13, wherein It further includes: When the fourth receiving module parses the custom data as inquiry information, it generates feedback data according to the custom data and the preset master address, and sends it to the switching module through the master uplink; After receiving the feedback data through the master uplink, the switching module sends it to the master control module.

17. The data exchange method according to claim 15, wherein, It further includes: When the fourth receiving module parses the custom data as upgrade instructions or device management information, it executes the custom data, and generates an acknowledgment message and sends it to the switching module after the execution is completed.

18. The data exchange method according to claim 2, wherein The sum of the first bandwidth and the second bandwidth is equal to the bandwidth of each transmission link.

19. The data exchange method according to claim 18, characterized in that, When the bandwidth of each transmission link is 10G, the first bandwidth is 2G and the second bandwidth is 8G.

20. The data exchange method according to claim 1, wherein The bandwidth of the output nodes of each receiving module includes 1G, 2.5G, and 5G.

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