Illuminating system and illuminating method

Abstract

The invention is suitable for the technical field of lighting, and provides a lighting system and a lighting method.The system comprises a light controller, a plurality of parallel transcoding chips and a plurality of display circuits, and the light controller is connected with the parallel transcoding chips and used for sending control signals to the parallel transcoding chips; the plurality of parallel transcoding chips are respectively connected with the display circuit and are used for receiving a control signal sent by the light controller and forwarding the received control signal to the connected display circuit; and the plurality of display circuits are used for receiving the control signals forwarded by the parallel transcoding chips and displaying the control signals according to the control signals. The damaged parallel transcoding chips or display circuits in the lighting system can be directly replaced in a targeted manner, and other parallel transcoding chips or display circuits are not influenced, so that the reliability of the lighting system is ensured.

Description

Technical Field

[0001] This application belongs to the technical field of lighting, and in particular, relates to a lighting system and a lighting method. Background Art

[0002] Existing light-emitting diode (LED) landscape lighting systems are usually series systems that use a return-zero (RZ) code protocol to cascade chips, or parallel systems that use a DMX512 protocol to cascade chips. Among them, the return-zero (RZ) code protocol is a digital signal encoding method in which the signal level returns to the zero level within each bit period. The digital multiplex with 512 pieces of information (DMX512) protocol is an industrial standard released by the American Institute of Lighting Control, which is specifically used for stage lighting control design to achieve digital communication between lighting controllers and lighting equipment. Precise adjustment of parameters such as brightness, color, and movement of lighting equipment is achieved through digital signal control.

[0003] The series system of RZ code protocol cascaded chips uses the RZ code protocol and has a simple single-wire connection. However, if a certain cascaded chip in the system suddenly malfunctions, all subsequent cascaded chips will be out of control. Therefore, the series system of RZ code protocol cascaded chips has a low cost but poor reliability. The parallel system of DMX512 protocol cascaded chips uses differential DMX512 two-wire parallel connection. Any abnormality in the system does not affect the application of other chips, and it has high reliability. However, this system requires multiple wires such as DMX512 protocol differential wires, address wires, power supply wires, and ground wires for connection, and its cost is relatively high.

[0004] Therefore, in existing LED landscape lighting systems, how to improve maintenance efficiency and reduce maintenance costs while ensuring system reliability has become an urgent problem to be solved. Summary of the Invention

[0005] Embodiments of this application provide a lighting system and a lighting method, which can solve the technical problem that in existing LED landscape lighting systems, it is impossible to balance system reliability, maintenance efficiency, and maintenance cost.

[0006] In a first aspect, embodiments of this application provide a lighting system, including: a lighting controller, a plurality of parallel transcoding chips, and a plurality of display circuits, where

[0007] The lighting controller is connected to the plurality of parallel transcoding chips and is configured to send control signals to the plurality of parallel transcoding chips;

[0008] Multiple of the parallel transcoding chips are respectively connected to the display circuit, and are configured to receive the control signal sent by the lighting controller and forward the received control signal to the connected display circuit;

[0009] Multiple of the display circuits are configured to receive the control signal forwarded by the parallel transcoding chips and perform display according to the control signal.

[0010] In a possible implementation manner of the first aspect, the lighting controller is a multi-channel digital transmission DMX512 protocol controller, the parallel transcoding chip is a DMX512 protocol parallel transcoding chip, and the display circuit includes a DMX512 protocol display circuit or a return-to-zero code protocol display circuit, where,

[0011] The DMX512 protocol parallel transcoding chip includes a first signal receiving end and a second signal receiving end, and is configured to receive the control signal sent by the DMX512 protocol controller;

[0012] The DMX512 protocol parallel transcoding chip further includes a first signal transcoding end and a second signal transcoding end, and is configured to forward the control signal to the DMX512 protocol display circuit through the first signal transcoding end or forward the control signal to the return-to-zero code protocol display circuit through the second signal transcoding end.

[0013] In a possible implementation manner of the first aspect, the DMX512 protocol parallel transcoding chip further includes a transcoding address output end and a cascaded transcoding end, where,

[0014] The transcoding address output end of the DMX512 protocol parallel transcoding chip is connected to the cascaded transcoding end of the next-level cascaded DMX512 protocol parallel transcoding chip through a third resistor, and is configured to forward the control signal to the next-level cascaded DMX512 protocol parallel transcoding chip.

[0015] In a possible implementation manner of the first aspect, the DMX512 protocol parallel transcoding chip includes a transcoding adaptive decoding module, a transcoding address parsing module, a transcoding data parsing module, a transcoding parameter parsing module, and a first memory, where,

[0016] The transcoding adaptive decoding module is configured to perform adaptive transmission rate decoding on the control signal to obtain decoded data;

[0017] The transcoding address parsing module is connected to the transcoding adaptive decoding module, and is configured to perform address parsing on the decoded data to obtain address data, store the address data in the first memory, and send the address data to the next-level cascaded DMX512 protocol parallel transcoding chip through the transcoding address output end;

[0018] The transcoding data parsing module, connected to the transcoding adaptive decoding module, is used to perform display analysis on the decoded data to obtain transcoding display data, and forward the transcoding display data to the DMX512 protocol display circuit through the first signal transcoding end or forward the transcoding display data to the return-to-zero code protocol display circuit through the second signal transcoding end;

[0019] The transcoding parameter parsing module, connected to the transcoding adaptive decoding module, is used to perform parameter analysis on the decoded data to obtain parameter data, store the parameter data in the first memory, and forward the parameter data to the DMX512 protocol display circuit through the first signal transcoding end or forward the parameter data to the return-to-zero code protocol display circuit through the second signal transcoding end.

[0020] In a possible implementation manner of the first aspect, the DMX512 protocol parallel transcoding chip further includes a second memory, where,

[0021] The second memory is used to store the transcoding display data and circularly forward the transcoding display data to the first signal transcoding end or the second signal transcoding end.

[0022] In a possible implementation manner of the first aspect, the DMX512 protocol controller includes: a first signal sending end and a second signal sending end, where,

[0023] The first signal sending end of the DMX512 protocol controller is connected to the first signal receiving end of the DMX512 protocol parallel transcoding chip through a first resistor;

[0024] The second signal sending end of the DMX512 protocol controller is connected to the second signal receiving end of the DMX512 protocol parallel transcoding chip through a second resistor.

[0025] In a possible implementation manner of the first aspect, the DMX512 protocol display circuit includes: a plurality of DMX512 protocol cascaded display chips, a transcoding resistor, a plurality of output resistors, and a plurality of cascaded input resistors, where,

[0026] The first display receiving end of the DMX512 protocol cascaded display chip is connected to the first signal transcoding end of the DMX512 protocol parallel transcoding chip through the transcoding resistor to receive the control signal forwarded by the DMX512 protocol parallel transcoding chip;

[0027] The first display output terminal of the DMX512 protocol cascaded display chip is connected to the first cascaded address terminal of the next cascaded DMX512 protocol cascaded display chip after being connected in series with the output resistor and the cascaded input resistor, and forwards the control signal to the next cascaded DMX512 protocol cascaded display chip.

[0028] In a possible implementation manner of the first aspect, the DMX512 protocol cascaded display chip includes: a DMX512 adaptive decoding module, a DMX512 data parsing module, a DMX512 parameter parsing module, a DMX512 address parsing module, a DMX512 correction module, and a third memory, where

[0029] The DMX512 adaptive decoding module is configured to perform adaptive transmission rate decoding on the transcoded display data to obtain DMX512 protocol display data;

[0030] The DMX512 data parsing module is connected to the DMX512 adaptive decoding module and is configured to parse the DMX512 protocol display data to obtain DMX512 protocol parsing data, and send the DMX512 protocol parsing data to the DMX512 correction module;

[0031] The DMX512 parameter parsing module is connected to the DMX512 adaptive decoding module and is configured to perform parameter analysis on the DMX512 protocol display data to obtain DMX512 protocol parameter data, store the DMX512 protocol parameter data in the third memory, and send the DMX512 protocol parameter data to the color display terminal of the DMX512 protocol cascaded display chip;

[0032] The DMX512 address parsing module is connected to the DMX512 adaptive decoding module and is configured to perform address parsing on the DMX512 protocol display data to obtain DMX512 protocol address data, store the DMX512 protocol address data in the third memory, and forward the DMX512 protocol address data to the next cascaded DMX512 protocol cascaded display chip through the first display output terminal of the DMX512 protocol cascaded display chip;

[0033] The DMX512 correction module is connected to the DMX512 data parsing module and is configured to perform gamma correction on the DMX512 protocol parsing data to obtain corrected DMX512 protocol parsing data, and send the corrected DMX512 protocol parsing data to the color display terminal of the DMX512 protocol cascaded display chip, so that the color display terminal of the DMX512 protocol cascaded display chip performs display according to the corrected DMX512 protocol parsing data.

[0034] In a possible implementation of the first aspect, the return-to-zero code protocol display circuit includes a plurality of cascaded return-to-zero code protocol display chips, where,

[0035] The second display receiving end of the cascaded return-to-zero code protocol display chip is connected to the second signal transcoding end of the DMX512 protocol parallel transcoding chip to receive the control signal forwarded by the DMX512 protocol parallel transcoding chip;

[0036] The second display output end of the cascaded return-to-zero code protocol display chip is connected to the second display receiving end of the next cascaded return-to-zero code protocol display chip to forward the control signal to the next cascaded return-to-zero code protocol display chip.

[0037] In a possible implementation of the first aspect, the cascaded return-to-zero code protocol display chip includes: a return-to-zero code adaptive decoding module, a return-to-zero code data parsing module, a return-to-zero code forwarding module, and a return-to-zero code correction module, where,

[0038] The return-to-zero code adaptive decoding module is configured to perform adaptive transmission rate decoding on the transcoded display data to obtain return-to-zero code protocol display data;

[0039] The return-to-zero code data parsing module is connected to the return-to-zero code adaptive decoding module and is configured to parse the return-to-zero code protocol display data to obtain return-to-zero code protocol parsing data, and send the return-to-zero code protocol parsing data to the return-to-zero code correction module;

[0040] The return-to-zero code forwarding module is connected to the return-to-zero code adaptive decoding module and is configured to send the return-to-zero code protocol display data to the second display output end of the cascaded return-to-zero code protocol display chip, so that the second display output end of the cascaded return-to-zero code protocol display chip forwards the return-to-zero code protocol display data to the next cascaded return-to-zero code protocol display chip;

[0041] The return-to-zero code correction module is connected to the return-to-zero code data parsing module and is configured to perform gamma correction on the return-to-zero code protocol parsing data to obtain corrected return-to-zero code protocol parsing data, and send the corrected return-to-zero code protocol parsing data to the color display end of the cascaded return-to-zero code protocol display chip, so that the color display end of the cascaded return-to-zero code protocol display chip performs display according to the corrected return-to-zero code protocol parsing data.

[0042] In a second aspect, an embodiment of the present application provides an illumination method applied to a parallel transcoding chip in the illumination system as described in any one of the first aspects. The method includes:

[0043] Receive the control signal sent by the lighting controller;

[0044] Perform transcoding processing on the control signal to obtain transcoded data;

[0045] Forward the transcoded data to the connected display circuit so that the display circuit performs display according to the transcoded data.

[0046] In a possible implementation manner of the second aspect, the lighting controller is a multi-channel digital transmission DMX512 protocol controller, the parallel transcoding chip is a DMX512 protocol parallel transcoding chip, and the display circuit includes a DMX512 protocol display circuit or a return-to-zero code protocol display circuit. The method includes:

[0047] When the display circuit is the DMX512 protocol display circuit, connect the first signal transcoding terminal of the DMX512 protocol parallel transcoding chip to the DMX512 protocol display circuit, and forward the received control signal sent by the DMX512 protocol controller to the DMX512 protocol display circuit through the first signal transcoding terminal;

[0048] When the display circuit is the return-to-zero code protocol display circuit, connect the second signal transcoding terminal of the DMX512 protocol parallel transcoding chip to the return-to-zero code protocol display circuit, and forward the received control signal sent by the DMX512 protocol controller to the return-to-zero code protocol display circuit through the second signal transcoding terminal.

[0049] In a possible implementation manner of the second aspect, the method further includes:

[0050] In the case of cascading the first preset number of DMX512 protocol parallel transcoding chips, store all the control signals including the address data of the current DMX512 protocol parallel transcoding chip in the second memory of the current DMX512 protocol parallel transcoding chip, and circularly forward the control signals to multiple DMX512 protocol cascaded display chips in the DMX512 protocol display circuit connected to the current DMX512 protocol parallel transcoding chip or multiple return-to-zero code protocol cascaded display chips in the return-to-zero code protocol display circuit connected to the current DMX512 protocol parallel transcoding chip according to the configuration requirements.

[0051] In a possible implementation manner of the second aspect, the method further includes:

[0052] In the case of cascading the second preset number of DMX512 protocol cascaded display chips in the DMX512 protocol display circuit or cascading the second preset number of return-to-zero code protocol cascaded display chips in the return-to-zero code protocol display circuit,

[0053] Forward all the control signals containing the address data of the current DMX512 protocol transcoding chip infinitely to multiple DMX512 protocol cascaded display chips in the DMX512 protocol display circuit connected to the current DMX512 protocol transcoding chip or multiple return-to-zero code protocol cascaded display chips in the return-to-zero code protocol display circuit connected to the current DMX512 protocol transcoding chip until the last DMX512 protocol cascaded display chip in the DMX512 protocol display circuit or the last return-to-zero code protocol cascaded display chip in the return-to-zero code protocol display circuit receives the control signal.

[0054] In a third aspect, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the lighting method described in any one of the above is implemented.

[0055] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the lighting method described in any one of the above is implemented.

[0056] In a fifth aspect, an embodiment of the present application provides a computer program product, and when the computer program product runs on a terminal device, the terminal device is caused to execute the lighting method described in any one of the first aspects above.

[0057] The beneficial effects of the embodiments of the present application compared with the prior art are as follows:

[0058] An embodiment of the present application provides a lighting system, which includes a lighting controller, multiple parallel transcoding chips, and multiple display circuits. Among them, the lighting controller is connected to the multiple parallel transcoding chips and is used to send control signals to the multiple parallel transcoding chips; the multiple parallel transcoding chips are respectively connected to the display circuits and are used to receive the control signals sent by the lighting controller and forward the received control signals to the connected display circuits; the multiple display circuits are used to receive the control signals forwarded by the parallel transcoding chips and perform display according to the control signals. For the damaged parallel transcoding chips or display circuits in the lighting system, targeted replacement can be directly carried out without affecting other parallel transcoding chips or display circuits, thereby ensuring the reliability of the lighting system. Description of the Drawings

[0059] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for use in the embodiments or the description of the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0060] Figure 1 It is a schematic structural diagram of a series system of a general return-to-zero code protocol cascaded chip provided by an embodiment of the present application;

[0061] Figure 2 It is a schematic structural diagram of a series system of a general break-point resume return-to-zero code cascaded chip provided by an embodiment of the present application;

[0062] Figure 3 It is a schematic structural diagram of a parallel system of a general DMX512 protocol cascaded chip provided by an embodiment of the present application;

[0063] Figure 4 It is a schematic structural diagram of a lighting system provided by an embodiment of the present application;

[0064] Figure 5 It is a schematic structural diagram of a lighting system composed of a DMX512 protocol parallel transcoding chip and a DMX512 protocol display circuit provided by an embodiment of the present application;

[0065] Figure 6 It is a schematic structural diagram of a lighting system composed of a DMX512 protocol parallel transcoding chip and a return-to-zero code protocol display circuit provided by an embodiment of the present application;

[0066] Figure 7 It is a schematic structural diagram of a DMX512 protocol parallel transcoding chip provided by an embodiment of the present application;

[0067] Figure 8 It is a schematic structural diagram of a DMX512 protocol cascaded display chip provided by an embodiment of the present application;

[0068] Figure 9 It is a schematic structural diagram of a return-to-zero code protocol cascaded display chip provided by an embodiment of the present application;

[0069] Figure 10 It is a schematic flowchart of a lighting method provided by an embodiment of the present application;

[0070] Figure 11 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0071] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system architectures, technologies, etc. are presented to provide a thorough understanding of the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from obscuring the description of the present application.

[0072] It should be understood that when used in the specification of the present application and the appended claims, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0073] It should also be understood that the term "and / or" as used in the specification of the present application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0074] As used in the specification of the present application and the appended claims, the term "if" can be interpreted as "when" or "once" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrase "if determined" or "if detected [the described condition or event]" can be interpreted as meaning "once determined" or "in response to determining" or "once detected [the described condition or event]" or "in response to detecting [the described condition or event]" depending on the context.

[0075] In addition, in the description of the specification of the present application and the appended claims, the terms "first", "second", "third", etc. are only used for differentiating descriptions and cannot be understood as indicating or implying relative importance.

[0076] The reference to "one embodiment" or "some embodiments" or the like described in the specification of the present application means that a specific feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having", and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0077] The LED landscape lighting system is a lighting system that takes LED (light-emitting diode) technology as the core, combines the requirements of landscape design, and enhances the shaping of the night environment of modern cities and scenic spots through light and shadow art. The core lies in the intelligent control and artistic design of the LED light source to achieve the balance between the dynamic presentation of environmental aesthetics and functional requirements.

[0078] As Figure 1 shown, Figure 1 is a schematic structural diagram of a series system of a general return-to-zero code protocol cascaded chip provided by an embodiment of the present application. As Figure 1 shown in, the series system of the general return-to-zero code protocol cascaded chip uses the return-to-zero code protocol and includes three connecting lines: the return-to-zero code DIN1 data line, the VDD power supply line, and the GND ground line. The connection is simple and the cost is low. However, if a certain cascaded chip in the system suddenly fails, all subsequent cascaded chips will be out of control. Therefore, the series system of the return-to-zero code protocol cascaded chip has a low cost but poor reliability.

[0079] Although, a series system of break-point resume transmission return-to-zero code cascaded chips has been developed subsequently. As Figure 2 shown, Figure 2 is a schematic structural diagram of a series system of a general break-point resume transmission return-to-zero code cascaded chip provided by an embodiment of the present application. As Figure 2 shown in, the series system of the general break-point resume transmission return-to-zero code cascaded chip includes four connecting lines: the return-to-zero code DIN1 data line, the spare return-to-zero code DIN2 data line, the VDD power supply line, and the GND ground line. One more line is added on the basis of the series system of the general return-to-zero code protocol cascaded chip. Although the reliability of the system is improved, if two consecutive cascaded chips in the system suddenly fail, all subsequent cascaded chips will still be out of control. The reliability of the series system of the break-point resume transmission return-to-zero code cascaded chip has been improved, but the reliability is average.

[0080] As Figure 3 shown, Figure 3 is a schematic structural diagram of a parallel system of a general DMX512 protocol cascaded chip provided by an embodiment of the present application. Figure 3 shown in, the parallel system of the general DMX512 protocol cascaded chip uses differential DMX512 two-wire parallel connection and includes five connecting lines: the DMX512 protocol differential DA line and DB line, the address line, the VDD power supply line, and the GND ground line. The cost is relatively high. However, any abnormality in the system does not affect the application of other chips, and the reliability is high.

[0081] However, in an LED landscape lighting system, a series system of return-to-zero code protocol cascaded chips or a parallel system of DMX512 protocol cascaded chips usually cascades many display chips. When the LED landscape lighting system has been applied for a period of time and a certain display chip malfunctions and needs to be replaced, the replacement process is rather troublesome and the maintenance cost is high. Therefore, in an LED landscape lighting system, how to improve the maintenance efficiency and reduce the maintenance cost under the condition of ensuring the system reliability has become an urgent problem to be solved. Corresponding to the above problems, a lighting system provided by an embodiment of the present application can reduce the maintenance cost and improve the maintenance efficiency under the condition of ensuring the system reliability.

[0082] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of a lighting system provided by an embodiment of the present application. Figure 4 In

[0083] the lighting system 1 includes: a lighting controller 10, a plurality of parallel transcoding chips 20, and a plurality of display circuits 30, wherein,

[0084] the lighting controller 10 is connected to the plurality of parallel transcoding chips 20 and is configured to send control signals to the plurality of parallel transcoding chips 20.

[0085] The plurality of parallel transcoding chips 20 are respectively connected to a display circuit 30 and are configured to receive the control signals sent by the lighting controller and forward the received control signals to the connected display circuit 30.

[0086] As Figure 4 in

[0087] the lighting system 1 is an integrated whole device or device combination designed, constructed, and integrated to achieve specific lighting functions, and can meet the lighting requirements in different scenarios, such as providing appropriate brightness, color, etc. In this embodiment, the lighting system 1 can be an LED landscape lighting system.

[0088] The parallel transcoding chip 20 mainly performs conversion and encoding processing on the received signals. In this lighting system 1, the control signals sent by the lighting controller 10 may have specific protocols or encoding methods, and the display circuit 30 may not be able to directly recognize and process these control signals. In this embodiment, the parallel transcoding chip 20 can decode and analyze the control signals sent by the lighting controller 10, and then, according to the requirements of the display circuit, re-encode them into a format suitable for the display circuit 30 to receive and process, and then forward the converted signals to the corresponding display circuit 30 to ensure that the control signals can be correctly interpreted and executed in the display circuit 30, so as to achieve the expected lighting effect. In this embodiment, the parallel transcoding chip 20 adopts a parallel connection method, that is, each parallel transcoding chip 20 is directly connected to the lighting controller 10, and each parallel transcoding chip 20 is independent of each other and does not affect each other. It should be understood that the lighting controller 10 can send control signals to multiple parallel transcoding chips 20 at the same time, each parallel transcoding chip 20 can receive the complete signal, and the working state of each parallel transcoding chip 20 will not be interfered by the failure or other working states of other parallel transcoding chips, thereby improving the reliability and stability of the system.

[0089] The display circuit 30 is a component in the lighting system 1 responsible for realizing the lighting effect. The display circuit 30 can receive the control signals forwarded by the parallel transcoding chip 20 and control its own light-emitting state according to these control signals. The display circuit 30 includes a series of light-emitting elements (such as LED lamp beads). By adjusting parameters such as the current and voltage of these light-emitting elements, their brightness, color and other characteristics can be controlled, so as to convert the display information expressed by the control signals into an actual visible lighting effect. Specifically, when the control signal sent by the lighting controller is to increase the brightness, the parallel transcoding chip receives the control signal, decodes and converts the control signal, and sends the converted control signal to the display circuit. After receiving the converted control signal, the display circuit correspondingly increases the current provided to the light-emitting elements, so that the light-emitting elements emit brighter light.

[0090] In this embodiment, in this lighting system 1, the lighting controller 10 can be connected in parallel with multiple parallel transcoding chips 20, and each parallel transcoding chip 20 can be connected to a display circuit 30.

[0091] It can be understood that an embodiment of the present application provides an illumination system, which includes a lighting controller, a plurality of parallel transcoding chips, and a plurality of display circuits. Among them, the lighting controller is connected to the plurality of parallel transcoding chips and is used to send control signals to the plurality of parallel transcoding chips; the plurality of parallel transcoding chips are respectively connected to the display circuits and are used to receive the control signals sent by the lighting controller and forward the received control signals to the connected display circuits; the plurality of display circuits are used to receive the control signals forwarded by the parallel transcoding chips and perform displays according to the control signals. For the damaged parallel transcoding chips or display circuits in the illumination system, targeted replacement can be directly carried out, which will not affect other parallel transcoding chips or display circuits, thus ensuring the reliability of the illumination system.

[0092] Please refer to Figure 5 and Figure 6 , Figure 5 which is a schematic structural diagram of an illumination system composed of a DMX512 protocol parallel transcoding chip and a DMX512 protocol display circuit provided by an embodiment of the present application. Figure 6 which is a schematic structural diagram of an illumination system composed of a DMX512 protocol parallel transcoding chip and a return-to-zero code protocol display circuit provided by an embodiment of the present application. As Figure 5 and Figure 6 shown in

[0093] the lighting controller 10 is a multi-channel digital transmission DMX512 protocol controller 11, the parallel transcoding chip 20 is a DMX512 protocol parallel transcoding chip 21, and the display circuit 30 includes a DMX512 protocol display circuit 31 or a return-to-zero code protocol display circuit 32. Among them,

[0094] the DMX512 protocol parallel transcoding chip 21 includes a first signal receiving end UA and a second signal receiving end UB, which are used to receive the control signals sent by the DMX512 protocol controller 11.

[0095] The multi-channel digital transmission DMX512 protocol is a standard communication protocol widely used in fields such as stage lighting and building lighting. It stipulates the transmission format, timing, and electrical characteristics of digital signals between the controller and the controlled devices. In this embodiment, the lighting controller 10 can be a DMX512 protocol controller 11, which is used to generate control signals conforming to the DMX512 protocol according to a preset program or externally input information, and send these control signals to the parallel transcoding chip 20, thereby controlling lighting parameters such as the brightness and color of the display circuit 30 to achieve diverse lighting effects.

[0096] The parallel transcoding chip 20 can be a DMX512 protocol parallel transcoding chip 21, that is, a parallel transcoding chip designed and optimized for the DMX512 protocol. It can decode the signal format of the DMX512 protocol sent by the DMX512 protocol controller 11 and convert it into other protocol formats or signal formats adapted to the requirements of different display circuits.

[0097] The display circuit 30 can be a DMX512 protocol display circuit 31 or a return-to-zero code protocol display circuit 32. The DMX512 protocol display circuit 31 is a display circuit capable of directly recognizing and processing DMX512 protocol signals, usually used in lighting scenarios with high requirements for signal processing and precise control of multiple parameters. The return-to-zero code protocol display circuit 32 is a display circuit that communicates using the return-to-zero code protocol. The return-to-zero code protocol is a digital signal encoding method, and the signal returns to the zero level within each symbol interval to represent different data in this way. The return-to-zero code protocol display circuit 32 is usually suitable for some specific lighting application scenarios and has characteristics such as low cost and simple implementation.

[0098] The DMX512 protocol is designed based on the RS-485 interface and uses the DA line and the DB line (i.e., the data positive line and the data negative line) to transmit differential voltage signals. The DMX512 protocol parallel transcoding chip 21 includes a first signal receiving end UA and a second signal receiving end UB. Among them, the first signal receiving end UA and the second signal receiving end UB are interface terminals on the DMX512 protocol parallel transcoding chip 21 for receiving control signals. That is, the DMX512 protocol parallel transcoding chip 21 receives the RS-485 differential voltage signal (i.e., the control signal) sent by the DMX512 protocol controller 11 through the first signal receiving end UA and the second signal receiving end UB to ensure that the signal can enter the chip accurately for processing.

[0099] The DMX512 protocol parallel transcoding chip 21 further includes a first signal transcoding terminal DMXO and a second signal transcoding terminal RZO. The first signal transcoding terminal DMXO is an interface terminal on the DMX512 protocol parallel transcoding chip 21 for outputting signals conforming to the DMX512 protocol; the second signal transcoding terminal RZO is an interface terminal on the DMX512 protocol parallel transcoding chip 21 for outputting signals conforming to the return-to-zero code protocol.

[0100] Specifically, the DMX512 protocol parallel transcoding chip 21 can perform transcoding processing on the control signal received from the DMX512 protocol controller 11 according to the type of the display circuit. For example Figure 5 In the case where the subsequent connection of the DMX512 protocol parallel transcoding chip 21 is a DMX512 protocol display circuit 31, at this time, the first signal transcoding terminal DMXO of the DMX512 protocol parallel transcoding chip 21 is connected to the DMX512 protocol display circuit 31, and the second signal transcoding terminal RZO is left floating. Then, the DMX512 protocol parallel transcoding chip 21 forwards the control signal to the corresponding DMX512 protocol display circuit 31 through the first signal transcoding terminal DMXO; for example Figure 6 In the case where the subsequent connection of the DMX512 protocol parallel transcoding chip 21 is a return-to-zero code protocol display circuit 32, at this time, the second signal transcoding terminal RZO of the DMX512 protocol parallel transcoding chip 21 is connected to the return-to-zero code protocol display circuit 32, and the first signal transcoding terminal DMXO is left floating. Then, the DMX512 protocol parallel transcoding chip 21 converts the control signal into a return-to-zero code protocol signal through the second signal transcoding terminal RZO and forwards it to the corresponding return-to-zero code protocol display circuit 32, thus realizing the conversion and adaptation between different protocol signals, enabling the DMX512 protocol controller to control different types of display circuits.

[0101] It should be noted that other IIC protocols, etc. can also be used in the lighting system in this embodiment, and no specific limitation is made thereto.

[0102] In a possible implementation manner, the DMX512 protocol parallel transcoding chip 21 further includes a transcoding address output terminal UAO and a cascaded transcoding terminal UADFI, where

[0103] The transcoding address output terminal UAO of the DMX512 protocol parallel transcoding chip 21 is connected to the cascaded transcoding terminal UADFI of the next cascaded DMX512 protocol parallel transcoding chip 22 through the third resistor R UAO for forwarding the control signal to the next cascaded DMX512 protocol parallel transcoding chip 22.

[0104] For example Figure 5Among them, the transcoding address output terminal UAO is an interface terminal on the DMX512 protocol parallel transcoding chip 21 for outputting address information, and can send chip status to the subsequent cascaded DMX512 protocol parallel transcoding chip 22. For example, when the chip status is 0, it means the chip address can be configured; when the chip status is 1, it means the chip address cannot be configured, etc.

[0105] The cascaded transcoding terminal UADFI is an interface terminal on the DMX512 protocol parallel transcoding chip 21 for receiving signals from the previous cascaded chip (such as the DMX512 protocol parallel transcoding chip 21), including control signals, address information, etc.

[0106] Specifically, in a large lighting system that needs to control multiple display circuits, a single DMX512 protocol parallel transcoding chip often cannot meet the requirements, and multiple DMX512 protocol parallel transcoding chips need to be cascaded to work. At this time, the transcoding address output terminal UAO and the cascaded transcoding terminal UADFI can enable multiple DMX512 protocol parallel transcoding chips to be connected to each other and work together. That is, the transcoding address output terminal UAO of the current DMX512 protocol parallel transcoding chip 21 is connected to the cascaded transcoding terminal UADFI of the next cascaded DMX512 protocol parallel transcoding chip 22 through the third resistor R UAO , connecting the current DMX512 protocol parallel transcoding chip 21 to the next cascaded DMX512 protocol parallel transcoding chip 22. Then, connect the first signal receiving terminal UA and the second signal receiving terminal UB of the next cascaded DMX512 protocol parallel transcoding chip 22 to the DMX512 protocol controller 11, and forward the control signal to the DMX512 protocol display circuit 31 through the first signal transcoding terminal DMXO of the next cascaded DMX512 protocol parallel transcoding chip 22 or forward the control signal to the return-to-zero code protocol display circuit 32 through the second signal transcoding terminal RZO of the next cascaded DMX512 protocol parallel transcoding chip 22.

[0107] During signal transmission, due to possible differences in the input and output impedances of different chips, direct connection may cause problems such as signal reflection and distortion. Also, abnormal conditions such as overvoltage, overcurrent, or static electricity in the circuit may cause damage to the chip ports. Therefore, by setting the third resistor R UAO can play a role in impedance matching and protecting the chip ports, reduce signal reflection, enable the signal to be transmitted to the next cascaded DMX512 protocol parallel transcoding chip stably and accurately, and improve the quality and reliability of signal transmission. As Figure 5 In, in order to further protect the chip ports and the stability of the signal, a resistor R can also be connected in series between the third resistor R UAO and the cascaded transcoding terminal UADFI of the next cascaded DMX512 protocol parallel transcoding chip.ADFI 。

[0108] It should be noted that in this embodiment, the cascaded lower-level DMX512 protocol parallel transcoding chip 22 and the DMX512 protocol parallel transcoding chip 21 are DMX512 protocol parallel transcoding chips of the same structure and type.

[0109] Please refer to Figure 7 , Figure 7 which is a schematic structural diagram of a DMX512 protocol parallel transcoding chip provided by an embodiment of the present application. As shown in Figure 7 , the DMX512 protocol parallel transcoding chip 21 includes a transcoding adaptive decoding module 211, a transcoding address parsing module 212, a transcoding data parsing module 213, a transcoding parameter parsing module 214, and a first memory 215, where

[0110] The transcoding adaptive decoding module 211 is configured to perform adaptive transmission rate decoding on the control signal to obtain decoded data.

[0111] The transcoding address parsing module 212 is connected to the transcoding adaptive decoding module 211, and is configured to perform address parsing on the decoded data to obtain address data, store the address data in the first memory 215, and send the address data to the cascaded lower-level DMX512 protocol parallel transcoding chip 22 through the transcoding address output terminal UAO.

[0112] The transcoding data parsing module 213 is connected to the transcoding adaptive decoding module 211, and is configured to perform display analysis on the decoded data to obtain transcoded display data, and forward the transcoded display data to the DMX512 protocol display circuit 31 through the first signal transcoding terminal DMXO or forward the transcoded display data to the return-to-zero code protocol display circuit 32 through the second signal transcoding terminal RZO.

[0113] The transcoding parameter parsing module 214 is connected to the transcoding adaptive decoding module 211, and is configured to perform parameter analysis on the decoded data to obtain parameter data, store the parameter data in the first memory 215, and forward the parameter data to the DMX512 protocol display circuit 31 through the first signal transcoding terminal DMXO or forward the parameter data to the return-to-zero code protocol display circuit 32 through the second signal transcoding terminal RZO.

[0114] As shown in Figure 7 , the DMX512 protocol parallel transcoding chip 21 mainly includes the following several modules, namely, a transcoding adaptive decoding module 211, a transcoding address parsing module 212, a transcoding data parsing module 213, and a transcoding parameter parsing module 214. The transcoding address parsing module 212, the transcoding data parsing module 213, and the transcoding parameter parsing module 214 are respectively connected to the transcoding adaptive decoding module 211.

[0115] Among them, the transcoding adaptive decoding module 211 can perform adaptive transmission rate decoding on the input control signal to obtain corresponding decoded data. The transcoding address parsing module 212 can parse the decoded data to obtain address data, and then write / read the address data into / from the first memory 215 through the control logic of the read-only memory, that is, the ROM CONTROL module. After parsing the address data, the address data can also be sent to the cascaded DMX512 protocol parallel transcoding chip 22 at the next level through the transcoding address output terminal UAO (i.e., the address output module).

[0116] The transcoding data parsing module 213 can perform display analysis on the decoded data to obtain transcoding display data, that is, the data that needs to be displayed subsequently. After obtaining the transcoding display data, the transcoding display data can be forwarded to the DMX512 protocol display circuit 31 through the first signal transcoding terminal DMXO (i.e., the DMX512 decoding and forwarding module), or the transcoding display data can be forwarded to the return-to-zero code protocol display circuit 32 through the second signal transcoding terminal RZO (i.e., the return-to-zero code decoding and forwarding module).

[0117] The transcoding parameter parsing module 214 can perform parameter analysis on the decoded data to obtain parameter data, that is, set parameters such as current adjustment amplitude, self-channel addressing, and automatic addressing. At this time, the parameter data can be stored in the first memory 215; when forwarding the transcoding display data, the parameter data in the first memory 215 is read simultaneously and forwarded to the DMX512 protocol display circuit 31 through the first signal transcoding terminal or to the return-to-zero code protocol display circuit 32 through the second signal transcoding terminal RZO.

[0118] The first memory 215 is an electrically erasable programmable read-only memory, which can be used to store address data and parameter data.

[0119] It should be noted that in the lighting system of this embodiment, when encountering situations such as corners, increasing the current and brightness by multiple chips, when it is necessary to increase or reduce the number of cascaded display chips in the subsequent display circuit 30, or change the number of channels of the subsequent display chips, the address data that needs to be configured is no longer a fixed increasing value but a changing value. Therefore, self-channel addressing is introduced in the DMX512 protocol parallel transcoding chip 21, and the self-channel addressing technology is integrated into the DMX512 protocol parallel transcoding chip 21. According to the number of channels and the number of chips of the display chips controlled by the DMX512 protocol parallel transcoding chip 21, etc., the DMX512 protocol parallel transcoding chip 21 automatically increases the corresponding address.

[0120] Furthermore, the DMX512 protocol parallel transcoding chip 21 further includes a second memory 216, among which,

[0121] A second memory 216 for storing transcoded display data and cyclically forwarding the transcoded display data to a first signal transcoding terminal DMXO or a second signal transcoding terminal RZO.

[0122] It should be noted that after obtaining the transcoded display data, the transcoded display data can be stored in the second memory 216, and the cyclical forwarding of the transcoded display data to the first signal transcoding terminal DMXO or the second signal transcoding terminal RZO can be achieved. At the same time, infinite forwarding can also be performed. Among them, the second memory 216 is a random access memory.

[0123] It should be noted that in Figure 7 wherein, the first signal receiving terminal UA and the second signal receiving terminal UB are RS-485 differential signal reading and writing circuit modules, and transmit the control signal to the transcoding adaptive decoding module 211. The cascaded transcoding terminal UADFI is a write address identification module, which judges the input of the chip address to judge whether it is the write address state of this chip, etc. UOSC is an oscillator; UPOR is a power-on reset, a reset operation automatically triggered when power is applied, which ensures the initial state of the internal circuit of the chip after power-on reset; UVCC clamping is a clamping circuit for the power supply voltage. When the system power supply is greater than 5V (such as 24V), UVCC clamping can ensure that the working voltage of the chip is 5V, ensure that the working voltage of the chip is within a safe range, and prevent overvoltage from damaging the circuit.

[0124] In a possible implementation manner, the DMX512 protocol controller 11 includes: a first signal sending terminal CA and a second signal sending terminal CB, wherein,

[0125] The first signal sending terminal CA of the DMX512 protocol controller 11 is connected to the first signal receiving terminal UA of the DMX512 protocol parallel transcoding chip 21 through a first resistor R A

[0126] The second signal sending terminal CB of the DMX512 protocol controller 11 is connected to the second signal receiving terminal UB of the DMX512 protocol parallel transcoding chip 21 through a second resistor R B

[0127] Such as Figure 4 wherein, the first signal sending terminal CA and the second signal sending terminal CB of the DMX512 protocol controller 11. The first signal sending terminal CA and the second signal sending terminal CB are interface terminals on the DMX512 protocol controller 11 for sending control signals (RS-485 differential voltage signals). Connect the first signal sending terminal CA of the DMX512 protocol controller 11 to the first signal receiving terminal UA of the DMX512 protocol parallel transcoding chip 21 through a first resistor R A and, connect the second signal sending terminal CB of the DMX512 protocol controller 11 to the second signal receiving terminal UB of the DMX512 protocol parallel transcoding chip 21 through a second resistor R​​B Connect the second signal sending end CB of the DMX512 protocol controller 11 to the second signal receiving end UB of the DMX512 protocol parallel transcoding chip 21. That is, the DMX512 protocol controller 11 sends a control signal to the first signal receiving end UA of the DMX512 protocol parallel transcoding chip 21 through the first signal sending end CA, and sends a control signal to the second signal receiving end UB of the DMX512 protocol parallel transcoding chip 21 through the second signal sending end CB. Through the above connection, the transmission of the control signal can be realized.

[0128] In a possible implementation, the DMX512 protocol display circuit 31 includes: a plurality of DMX512 protocol cascaded display chips 311, a transcoding resistor R C , a plurality of output resistors R AO and a plurality of cascaded input resistors R ADF , where

[0129] The first display receiving end XA of the DMX512 protocol cascaded display chip 311 is connected to the first signal transcoding end DMXO of the DMX512 protocol parallel transcoding chip 21 through the transcoding resistor R C to receive the control signal forwarded by the DMX512 protocol parallel transcoding chip 21.

[0130] The first display output end XAO of the DMX512 protocol cascaded display chip 311 is connected to the first cascaded address end XADFI of the next cascaded DMX512 protocol cascaded display chip 312 after being connected in series with the output resistor R AO and the cascaded input resistor R ADF to forward the control signal to the next cascaded DMX512 protocol cascaded display chip 312.

[0131] As Figure 5 shown, multiple DMX512 protocol cascaded display chips 311 can be cascaded in the DMX512 protocol display circuit 31. The first display receiving end XA is an interface terminal on the DMX512 protocol cascaded display chip 311 for receiving control signals, and it is connected to the first signal transcoding end DMXO of the DMX512 protocol parallel transcoding chip 21 through the transcoding resistor R C to receive the control signal forwarded by the DMX512 protocol parallel transcoding chip 21.

[0132] The first display output end XAO is an interface terminal on the DMX512 protocol cascaded display chip 311 for outputting address information, and can send the chip status to the subsequent next cascaded DMX512 protocol cascaded display chip 312. This first display output end XAO is connected in series with the output resistor R AO and the cascaded input resistor R ADFAfter being connected in series, connect to the first display receiving end XA of the next cascaded DMX512 protocol cascaded display chip 312, so as to forward the control signal to the next cascaded DMX512 protocol cascaded display chip 312.

[0133] Among them, the transcoding resistor R C , multiple output resistors R AO and multiple cascaded input resistors R ADF are all set to play the role of impedance matching and protecting the chip ports. By setting these resistors, signal reflection can be reduced, so that the signal can be stably and accurately transmitted to the next cascaded DMX512 protocol cascaded display chip, thereby improving the quality and reliability of signal transmission.

[0134] Specifically, in a large lighting system with various display requirements, a single DMX512 protocol cascaded display chip often cannot meet the needs, and multiple DMX512 protocol cascaded display chips need to be cascaded for lighting display. At this time, the first display output end XAO and the first cascaded address end XADFI can enable multiple DMX512 protocol cascaded display chips to be connected to each other and work together. That is, the first display output end XAO of the current DMX512 protocol cascaded display chip 311 passes through the output resistor R AO , cascaded input resistor R ADF in series and is connected to the first cascaded address end XADFI of the next cascaded DMX512 protocol cascaded display chip 312, so as to connect the previous DMX512 protocol cascaded display chip 311 to the next cascaded DMX512 protocol cascaded display chip 312; then, the first display receiving end XA of the next cascaded DMX512 protocol cascaded display chip 312 is connected to the first signal transcoding end DMXO of the DMX512 protocol parallel transcoding chip 21 through the transcoding resistor R C to receive the control signal forwarded by the first signal transcoding end DMXO of the DMX512 protocol parallel transcoding chip 21. Among them, the DMX512 protocol cascaded display chip 311 and the next cascaded DMX512 protocol cascaded display chip 312 are DMX512 protocol cascaded display chips of the same structure and type.

[0135] Such as Figure 5 In, UGND represents the ground end in the DMX512 protocol parallel transcoding chip 21, and UVDD represents the power voltage end in the DMX512 protocol parallel transcoding chip 21; XGND represents the ground end in the DMX512 protocol cascaded display chip 311, and XVDD represents the power voltage end in the DMX512 protocol cascaded display chip 311. Such as Figure 6In it, DGND represents the ground terminal in the return-to-zero code protocol cascaded display chip 321, and DVDD represents the power supply voltage terminal in the return-to-zero code protocol cascaded display chip 321.

[0136] Please refer to Figure 8 , Figure 8 which is a schematic structural diagram of a DMX512 protocol cascaded display chip provided by an embodiment of the present application. Figure 8 In it, the DMX512 protocol cascaded display chip 311 includes: a DMX512 adaptive decoding module 313, a DMX512 data parsing module 314, a DMX512 parameter parsing module 315, a DMX512 address parsing module 316, a DMX512 correction module 317, and a third memory 318, where

[0137] The DMX512 adaptive decoding module 313 is used to perform adaptive transmission rate decoding on the transcoded display data to obtain DMX512 protocol display data.

[0138] The DMX512 data parsing module 314 is connected to the DMX512 adaptive decoding module 313 and is used to parse the DMX512 protocol display data to obtain DMX512 protocol parsed data, and send the DMX512 protocol parsed data to the DMX512 correction module 317.

[0139] The DMX512 parameter parsing module 315 is connected to the DMX512 adaptive decoding module 313 and is used to perform parameter analysis on the DMX512 protocol display data to obtain DMX512 protocol parameter data, store the DMX512 protocol parameter data in the third memory 318, and send the DMX512 protocol parameter data to the color display terminal of the DMX512 protocol cascaded display chip.

[0140] The DMX512 address parsing module 316 is connected to the DMX512 adaptive decoding module 313 and is used to perform address parsing on the DMX512 protocol display data to obtain DMX512 protocol address data, store the DMX512 protocol address data in the third memory 318, and forward the DMX512 protocol address data to the next cascaded DMX512 protocol cascaded display chip 312 through the first display output terminal XAO of the DMX512 protocol cascaded display chip 311.

[0141] The DMX512 calibration module 317, connected to the DMX512 data parsing module 314, is used to perform gamma calibration on the DMX512 protocol parsed data, obtain the calibrated DMX512 protocol parsed data, and send the calibrated DMX512 protocol parsed data to the color display terminals RGBW of the DMX512 protocol cascaded display chip 311, so that the color display terminals RGBW of the DMX512 protocol cascaded display chip 311 display according to the calibrated DMX512 protocol parsed data.

[0142] It should be noted that in the lighting system, the DMX512 protocol parallel transcoding chip meets the adaptive decoding of 200K to 2MHZ. At the same time, there are oscillation deviations and the like during the production process of this chip, resulting in frequency deviations of the forwarded data. Therefore, it is required that the display chips in the subsequent display circuit (i.e., the DMX512 protocol cascaded display chip and the return-to-zero code protocol cascaded display chip) also have the adaptive decoding function to ensure correct data decoding and achieve the preset LED display function. The first byte of data in the DMX512 protocol is used for self-alignment, which can achieve the adaptive decoding function of 200K to 2MHZ. In the standard return-to-zero code protocol, there is no dedicated data for self-alignment. Generally, the transmission rate of the 800K return-to-zero code is used. Therefore, in the return-to-zero code protocol cascaded display chip, the first bit of data is designed to define the return-to-zero code transmission rate, and the data is not decoded at this time; after a certain time delay of the return-to-zero code data, the data is decoded according to the determined return-to-zero code transmission rate to achieve the function of adaptively decoding the return-to-zero code data.

[0143] As Figure 8 shown in, the DMX512 protocol cascaded display chip 311 mainly includes the following modules, namely the DMX512 adaptive decoding module 313, the DMX512 data parsing module 314, the DMX512 parameter parsing module 315, the DMX512 address parsing module 316, and the DMX512 calibration module 317. The DMX512 data parsing module 314, the DMX512 parameter parsing module 315, and the DMX512 address parsing module 316 are respectively connected to the DMX512 adaptive decoding module 313, and the DMX512 calibration module 317 is connected to the DMX512 data parsing module 314. Among them, the DMX512 adaptive decoding module 313 can perform adaptive transmission rate decoding on the transcoded display data forwarded by the DMX512 protocol parallel transcoding chip 22 to obtain the corresponding DMX512 protocol display data.

[0144] The DMX512 address resolution module 316 can resolve the DMX512 protocol display data to obtain the DMX512 protocol address data. Then, through the control logic of the read-only memory, i.e., the ROM CONTROL module, the address data can be written / read into the third memory 318. After resolving the DMX512 protocol address data, the address data can also be sent to the cascaded DMX512 protocol cascaded display chip 312 through the first display output terminal XAO (i.e., the address output module).

[0145] The DMX512 data parsing module 314 can parse the DMX512 protocol display data to obtain the DMX512 protocol parsing data, i.e., the data to be displayed subsequently (such as brightness, color). After obtaining the DMX512 protocol parsing data, the DMX512 protocol parsing data can be sent to the DMX512 correction module 317. After receiving the DMX512 protocol parsing data, the DMX512 correction module 317 performs gamma correction on the DMX512 protocol parsing data, such as correcting 8-bit (256 levels of luminance) to 16-bit (65536 levels of luminance), so as to obtain the corrected DMX512 protocol parsing data. Finally, the corrected DMX512 protocol parsing data is sent to the color display terminal RGBW (i.e., the port for controlling the display of different color luminances) of the DMX512 protocol cascaded display chip 311. At this time, the color display terminal RGBW of the DMX512 protocol cascaded display chip 311 can display according to the corrected DMX512 protocol parsing data, that is, lighting is achieved according to the control signal.

[0146] The DMX512 parameter parsing module 315 can perform parameter analysis on the DMX512 protocol display data to obtain the DMX512 protocol parameter data, i.e., set the parameters, such as current adjustment amplitude, self-channel addressing, automatic addressing, etc. At this time, the DMX512 protocol parameter data can be stored in the third memory 318; while sending the corrected DMX512 protocol parsing data to the color display terminal RGBW of the DMX512 protocol cascaded display chip 311, the DMX512 protocol parameter data in the third memory 318 is read, so that the color display terminal RGBW can display according to the corrected DMX512 protocol parsing data and the DMX512 protocol parameter data. The third memory 318 is an electrically erasable programmable read-only memory, which can be used to store the DMX512 protocol address data and the DMX512 protocol parameter data.

[0147] It should be noted that in Figure 8Among them, the first display receiving end XA and another display receiving end XB are the signal reading and writing circuit modules, which transmit the transcoded display data to the DMX512 adaptive decoding module 313. In this embodiment, only the first display receiving end XA is connected to the first signal transcoding end DMXO of the DMX512 protocol parallel transcoding chip 21. The first cascade address end XADFI is the write address identification module, which judges the input of the chip address to determine whether it is the write address state of this chip, etc. XOSC is the oscillator; XPOR is the power-on reset, a reset operation automatically triggered when power is applied, ensuring the initial state of the internal circuit of the chip after power-on reset; XVCC clamping is the clamping circuit of the power supply voltage, ensuring that the operating voltage of the chip is within a safe range to prevent overvoltage from damaging the circuit.

[0148] In a possible implementation manner, the return-to-zero code protocol display circuit 32 includes multiple return-to-zero code protocol cascade display chips 321, where

[0149] The second display receiving end DIN of the return-to-zero code protocol cascade display chip 321 is connected to the second signal transcoding end RZO of the DMX512 protocol parallel transcoding chip 21 to receive the control signal forwarded by the DMX512 protocol parallel transcoding chip 21.

[0150] The second display output end DOUT of the return-to-zero code protocol cascade display chip 321 is connected to the second display receiving end DIN of the next cascaded return-to-zero code protocol cascade display chip 322 to forward the control signal to the next cascaded return-to-zero code protocol cascade display chip 322.

[0151] As Figure 6 shown in, multiple return-to-zero code protocol cascade display chips 321 can be cascaded in the return-to-zero code protocol display circuit 32, and each return-to-zero code protocol cascade display chip 321 is connected in series. The second display receiving end DIN is the interface terminal on the return-to-zero code protocol cascade display chip 321 for receiving the control signal, which is connected to the second signal transcoding end RZO of the DMX512 protocol parallel transcoding chip 21, thereby receiving the control signal forwarded by the DMX512 protocol parallel transcoding chip 21.

[0152] The second display output end DOUT is the interface terminal on the return-to-zero code protocol cascade display chip 321 for outputting address information, and can send the chip status to the subsequent next cascaded return-to-zero code protocol cascade display chip 322. The second display output end DOUT can be directly connected to the second display receiving end DIN of the next cascaded return-to-zero code protocol cascade display chip 322, thereby forwarding the control signal to the next cascaded return-to-zero code protocol cascade display chip 322. Among them, the return-to-zero code protocol cascade display chip 321 and the next cascaded return-to-zero code protocol cascade display chip 322 are return-to-zero code protocol cascade display chips of the same structure and type.

[0153] Please refer to Figure 9 , Figure 9 which is a schematic structural diagram of a return-to-zero code protocol cascaded display chip provided by an embodiment of the present application. Figure 9 In

[0154] the return-to-zero code adaptive decoding module 323 is configured to perform adaptive transmission rate decoding on the transcoded display data to obtain the return-to-zero code protocol display data.

[0155] The return-to-zero code data parsing module 324, connected to the return-to-zero code adaptive decoding module 323, is configured to parse the return-to-zero code protocol display data to obtain the return-to-zero code protocol parsed data, and send the return-to-zero code protocol parsed data to the return-to-zero code correction module 326.

[0156] The return-to-zero code forwarding module 325, connected to the return-to-zero code adaptive decoding module 323, is configured to send the return-to-zero code protocol display data to the second display output terminal DOUT of the return-to-zero code protocol cascaded display chip 321, so that the second display output terminal DOUT of the return-to-zero code protocol cascaded display chip 321 forwards the return-to-zero code protocol display data to the next-level return-to-zero code protocol cascaded display chip 322.

[0157] The return-to-zero code correction module 326, connected to the return-to-zero code data parsing module 324, is configured to perform gamma correction on the return-to-zero code protocol parsed data to obtain the corrected return-to-zero code protocol parsed data, and send the corrected return-to-zero code protocol parsed data to the color display terminal RGB of the return-to-zero code protocol cascaded display chip 321, so that the color display terminal RGB of the return-to-zero code protocol cascaded display chip 321 performs display according to the corrected return-to-zero code protocol parsed data.

[0158] As Figure 9 in

[0159] the return-to-zero code protocol cascaded display chip 321 mainly includes the following modules, namely, the return-to-zero code adaptive decoding module 323, the return-to-zero code data parsing module 324, the return-to-zero code forwarding module 325, and the return-to-zero code correction module 326. The return-to-zero code data parsing module 324 and the return-to-zero code forwarding module 325 are respectively connected to the return-to-zero code adaptive decoding module 323, and the return-to-zero code correction module 326 is connected to the return-to-zero code data parsing module 324.

[0160] The return-to-zero code forwarding module 325 can send the return-to-zero code protocol display data to the second display output terminal DOUT of the return-to-zero code protocol cascaded display chip 321, so that the second display output terminal DOUT of the return-to-zero code protocol cascaded display chip 321 forwards the return-to-zero code protocol display data to the next-level return-to-zero code protocol cascaded display chip 322.

[0161] The return-to-zero code data parsing module 324 can parse the return-to-zero code protocol display data to obtain the return-to-zero code protocol parsed data, that is, the data to be displayed subsequently (such as brightness, color). After obtaining the return-to-zero code protocol parsed data, the return-to-zero code protocol parsed data can be sent to the return-to-zero code correction module 326. After receiving the return-to-zero code protocol parsed data, the return-to-zero code correction module 326 performs gamma correction on the return-to-zero code protocol parsed data to obtain the corrected return-to-zero code protocol parsed data. Finally, the corrected return-to-zero code protocol parsed data is sent to the color display terminal RGB of the return-to-zero code protocol cascaded display chip 321 (that is, the port used to control the display of different color brightness). At this time, the color display terminal RGB of the return-to-zero code protocol cascaded display chip 321 can display according to the corrected return-to-zero code protocol parsed data, that is, the lighting is realized according to the control signal.

[0162] It should be noted that in Figure 9 , DOSC is an oscillator; DPOR is a power-on reset, a reset operation automatically triggered when power is on, which ensures the initial state of the internal circuit of the chip after power-on reset; the DVCC clamp is a clamping circuit for the power supply voltage, which ensures that the operating voltage of the chip is within a safe range and prevents overvoltage from damaging the circuit.

[0163] It should be noted that in the lighting system of this embodiment, if a certain DMX512 protocol parallel transcoding chip is damaged, the damaged DMX512 protocol parallel transcoding chip can be simply replaced, and the system data can be reconfigured, and then the data of the subsequent cascaded DMX512 protocol parallel transcoding chips can be reconfigured by methods such as self-channel addressing and automatic addressing; if the DMX512 protocol cascaded display chip in the DMX512 protocol display circuit or the return-to-zero code protocol cascaded display chip in the return-to-zero code protocol display circuit is damaged, the entire display chip can also be directly replaced, and then the data of the subsequent cascaded chips can be reconfigured by methods such as self-channel addressing and automatic addressing. Thereby, the reliability of the system can be ensured, the maintenance efficiency can be improved, and the system cost can be reduced. Especially for the lighting system composed of the DMX512 protocol parallel transcoding chip and the return-to-zero code protocol display circuit in Figure 6 , only three connecting wires are required, which can make the circuit board narrower and further reduce the production cost.

[0164] Corresponding to a lighting system in the above embodiment, Figure 10The flowchart shows a lighting method provided by an embodiment of the present application. For ease of explanation, only the parts related to the embodiments of the present application are shown. As Figure 10 In this case, the lighting method is applied to the parallel transcoding chip in the lighting system as described in any of the above. The method includes:

[0165] S101. Receive the control signal sent by the lighting controller.

[0166] S102. Perform transcoding processing on the control signal to obtain transcoded data.

[0167] S103. Forward the transcoded data to the connected display circuit so that the display circuit can perform display according to the transcoded data.

[0168] It should be noted that this method can be applied to the parallel transcoding chip in the lighting system. In this embodiment, the parallel transcoding chip can receive the control signal sent by the lighting controller, convert and encode the received control signal according to the preset rules, generate the transcoded data suitable for the subsequent display circuit to receive and process, and then accurately forward the transcoded data to the display circuit. In the lighting system, multiple parallel transcoding chips can interact with the lighting controller in a parallel connection manner to solve the problem of signal format incompatibility between different devices and achieve efficient and stable signal transmission.

[0169] The lighting controller is the core control component of the lighting system, which integrates control logic and communication modules inside. It can generate corresponding control information according to the user's operation and send these control signals to the controlled lighting devices or related forwarding devices (such as parallel transcoding chips) to achieve precise control of the lights. The control signal is the specific information generated and sent by the lighting controller to control the lighting devices. The control signal is usually transmitted using a specific coding format and communication protocol (such as DMX512 protocol, return-to-zero code protocol, etc.), and it contains various instructions and parameters required to control the lighting devices. For example, the control signal may be to indicate adjusting the brightness of the lights in a certain area to 50%, setting the color to red, or starting a certain flashing mode, etc.

[0170] The transcoded data is the data obtained after the parallel transcoding chip performs transcoding processing on the control signal sent by the lighting controller. The purpose of the transcoding processing is to convert the original control signal into a format suitable for the display circuit to receive and process, so that the display circuit can correctly parse and execute the corresponding display operations.

[0171] The display circuit can be understood as a lighting device or a circuit part directly connected to the lighting device, which can receive the transcoding signal and display or drive the lighting device to display. The display circuit can be integrated inside a single lighting device or a centralized control circuit shared by multiple lighting devices. The display circuit includes a series of light-emitting components (such as LED lamp beads). By adjusting parameters such as the current and voltage of these light-emitting components, their brightness, color and other characteristics can be controlled, so as to convert the display information expressed by the control signal into an actual visible lighting effect. Specifically, when the control signal sent by the lighting controller is to increase the brightness, the parallel transcoding chip receives the control signal, decodes and converts the control signal to obtain transcoding data, and sends the converted transcoding data to the display circuit. After receiving the converted transcoding data, the display circuit correspondingly increases the current provided to the light-emitting components, so that the light-emitting components emit brighter light.

[0172] It can be understood that the embodiments of the present application provide an illumination method, which includes receiving a control signal sent by a lighting controller; performing transcoding processing on the control signal to obtain transcoding data; and forwarding the transcoding data to the connected display circuit so that the display circuit displays according to the transcoding data. This method can ensure the reliability of the system. At the same time, it can also improve the system maintenance efficiency and reduce the system maintenance cost.

[0173] In a possible implementation manner, the lighting controller is a multi-channel digital transmission DMX512 protocol controller, the parallel transcoding chip is a DMX512 protocol parallel transcoding chip, and the display circuit includes a DMX512 protocol display circuit or a return-to-zero code protocol display circuit. The method includes:

[0174] When the display circuit is a DMX512 protocol display circuit, connect the first signal transcoding terminal of the DMX512 protocol parallel transcoding chip to the DMX512 protocol display circuit, and forward the received control signal sent by the DMX512 protocol controller to the DMX512 protocol display circuit through the first signal transcoding terminal.

[0175] When the display circuit is a return-to-zero code protocol display circuit, connect the second signal transcoding terminal of the DMX512 protocol parallel transcoding chip to the return-to-zero code protocol display circuit, and forward the received control signal sent by the DMX512 protocol controller to the return-to-zero code protocol display circuit through the second signal transcoding terminal.

[0176] It should be noted that the lighting controller can be a DMX512 protocol controller, the parallel transcoding chip can be a DMX512 protocol parallel transcoding chip, and the display circuit can be a DMX512 protocol display circuit or a return-to-zero code protocol display circuit. The DMX512 protocol display circuit is a display circuit that can directly identify and process DMX512 protocol signals, and is usually used in lighting scenarios with high requirements for signal processing and precise control of multiple parameters. The return-to-zero code protocol display circuit is a display circuit that communicates using the return-to-zero code protocol. The return-to-zero code protocol display circuit is usually suitable for some specific lighting application scenarios and has characteristics such as low cost and simple implementation.

[0177] Specifically, the DMX512 protocol parallel transcoding chip includes a first signal transcoding terminal and a second signal transcoding terminal. When the requirements of the lighting system are high reliability, precise control, etc., the display circuit can be a DMX512 protocol display circuit. At this time, connect the first signal transcoding terminal of the DMX512 protocol parallel transcoding chip to the DMX512 protocol display circuit, and forward the control signal sent by the DMX512 protocol controller received through the first signal transcoding terminal to the DMX512 protocol display circuit. When the requirements of the lighting system are low cost, simple implementation, etc., and the display circuit can be a return-to-zero code protocol display circuit, at this time, connect the second signal transcoding terminal of the DMX512 protocol parallel transcoding chip to the return-to-zero code protocol display circuit, and forward the control signal sent by the DMX512 protocol controller received through the second signal transcoding terminal to the return-to-zero code protocol display circuit.

[0178] It should be understood that in this embodiment, the MX512 protocol parallel transcoding chip can transcode the control signal sent by the DMX512 protocol controller received according to the type of the display circuit and forward it to the display circuit, thereby realizing the conversion and adaptation between different protocol signals, and enabling the DMX512 protocol controller to control different types of display circuits.

[0179] In a possible implementation manner, the method further includes:

[0180] In the case of cascading a first preset number of DMX512 protocol parallel transcoding chips, store all control signals containing the address data of the current DMX512 protocol parallel transcoding chip in the second memory of the current DMX512 protocol parallel transcoding chip, and cyclically forward the control signals to multiple DMX512 protocol cascaded display chips in the DMX512 protocol display circuit connected to the current DMX512 protocol parallel transcoding chip or multiple return-to-zero code protocol cascaded display chips in the return-to-zero code protocol display circuit connected to the current DMX512 protocol parallel transcoding chip according to the configuration requirements.

[0181] Specifically, when a first preset number of DMX512 protocol parallel transcoding chips are cascaded in the lighting system, such as when more than 100 DMX512 protocol parallel transcoding chips are cascaded, for the 4096-byte data of the DMX512 protocol, the data allocated to each display chip is less than 40 bytes. Then, the cascaded number of display chips in the corresponding display circuit is less than 10. However, in practical applications, usually the cascaded number of display chips in the display circuit is greater than 10. The display chips need to increase the current to increase the brightness, or the display chips need to output cyclic data such as LED effects in a flowing water manner. At this time, the transmitted data needs to be cyclically output. Correspondingly, the DMX512 protocol parallel transcoding chips need functions such as data storage and cyclic forwarding. After the DMX512 protocol parallel transcoding chip reads the address data related to this chip, it stores all the subsequent configuration required data in the second memory in the DMX512 protocol parallel transcoding chip, and cyclically forwards the stored data to the subsequent display chips (i.e., multiple cascaded display chips of the DMX512 protocol or multiple cascaded display chips of the return-to-zero code protocol) according to the configuration of the DMX512 protocol parallel transcoding chip. Among them, the first preset number is a preset value, which is not limited in this embodiment.

[0182] In a possible implementation manner, when a second preset number of DMX512 protocol cascaded display chips are cascaded in the DMX512 protocol display circuit or a second preset number of return-to-zero code protocol cascaded display chips are cascaded in the return-to-zero code protocol display circuit, the method further includes:

[0183] Infinitely forward all control signals including the address data of the current DMX512 protocol transcoding chip to multiple DMX512 protocol cascaded display chips in the DMX512 protocol display circuit connected to the current DMX512 protocol transcoding chip or multiple return-to-zero code protocol cascaded display chips in the return-to-zero code protocol display circuit connected to the current DMX512 protocol transcoding chip until the last DMX512 protocol cascaded display chip in the DMX512 protocol display circuit or the last return-to-zero code protocol cascaded display chip in the return-to-zero code protocol display circuit receives the control signal.

[0184] Specifically, in the lighting system, when the second preset number of DMX512 protocol cascaded display chips are cascaded in the DMX512 protocol display circuit or the second preset number of return-to-zero code protocol cascaded display chips are cascaded in the return-to-zero code protocol display circuit, if there are more than 100 DMX512 protocol cascaded display chips or return-to-zero code protocol cascaded display chips, at this time, the DMX512 protocol transcoding chip needs an infinite data forwarding function. That is, after the current DMX512 protocol transcoding chip reads the address data of this chip, it forwards all subsequent data related to this chip infinitely to the DMX512 protocol cascaded display chips or the return-to-zero code protocol cascaded display chips until the last DMX512 protocol cascaded display chip in the DMX512 protocol display circuit or the return-to-zero code protocol cascaded display chip in the return-to-zero code protocol display circuit receives the data. This function is suitable for application scenarios where the number of cascaded DMX512 protocol cascaded display chips or return-to-zero code protocol cascaded display chips is relatively large. Among them, the second preset number is a preset value, which is not limited in this embodiment.

[0185] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0186] The embodiment of the present application also provides an electronic device, such as Figure 11 shown Figure 11 is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Referring to Figure 11 , the electronic device 4 of this embodiment includes: a memory 41, a processor 42, and a computer program stored in the memory 41 and executable on the processor 42. When the processor 42 executes the computer program, it implements the steps in any of the above lighting method embodiments.

[0187] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it can implement the steps in the above various method embodiments.

[0188] The embodiment of the present application provides a computer program product. When the computer program product runs on a mobile terminal, it enables the mobile terminal to implement the steps in the above various method embodiments when executed.

[0189] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-mentioned embodiment methods of this application, a computer program can be used to instruct the relevant hardware to complete. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the photographing device / terminal device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disc, etc. In some jurisdictions, according to legislation and patent practice, the computer-readable medium cannot be an electrical carrier signal and a telecommunication signal.

[0190] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0191] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0192] In the embodiments provided in this application, it should be understood that the disclosed device / network device and method can be implemented in other ways. For example, the device / network device embodiments described above are only illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical, mechanical or other form.

[0193] The unit described as a separation component may or may not be physically separated. The component shown as a unit may or may not be a physical unit, that is, it may be located in one place or may be distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0194] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A lighting system, characterized in that: include: A lighting controller, a plurality of parallel transcoding chips and a plurality of display circuits, wherein: The lighting controller is connected to the plurality of parallel transcoding chips and is used to send control signals to the plurality of parallel transcoding chips; The plurality of parallel transcoding chips are respectively connected to the display circuit, and are used to receive the control signal sent by the light controller, and forward the received control signal to the connected display circuit; The plurality of display circuits are used to receive the control signal forwarded by the parallel transcoding chip and perform display according to the control signal.

2. The lighting system according to claim 1, characterized in that The lighting controller is a multi-channel digital transmission DMX512 protocol controller, the parallel transcoding chip is a DMX512 protocol parallel transcoding chip, and the display circuit includes a DMX512 protocol display circuit or a return-to-zero code protocol display circuit, wherein: The DMX512 protocol parallel transcoding chip includes a first signal receiving end and a second signal receiving end, which are used to receive the control signal sent by the DMX512 protocol controller; The DMX512 protocol parallel transcoding chip also includes a first signal transcoding end and a second signal transcoding end, which are used to forward the control signal to the DMX512 protocol display circuit through the first signal transcoding end or to forward the control signal to the return-to-zero code protocol display circuit through the second signal transcoding end.

3. The lighting system according to claim 2, characterized in that The DMX512 protocol parallel transcoding chip also includes a transcoding address output terminal and a cascade transcoding terminal, wherein: The transcoding address output end of the DMX512 protocol parallel transcoding chip is connected to the cascade transcoding end of the next cascaded DMX512 protocol parallel transcoding chip through a third resistor, and is used to forward the control signal to the next cascaded DMX512 protocol parallel transcoding chip.

4. The lighting system according to claim 3, characterized in that The DMX512 protocol parallel transcoding chip includes: a transcoding adaptive decoding module, a transcoding address parsing module, a transcoding data parsing module, a transcoding parameter parsing module and a first memory, wherein: The transcoding adaptive decoding module is used to perform adaptive transmission rate decoding on the control signal to obtain decoded data; The transcoding address resolution module is connected to the transcoding adaptive decoding module, and is used to perform address resolution on the decoded data to obtain address data, store the address data in the first memory, and send the address data to the next cascaded DMX512 protocol parallel transcoding chip through the transcoding address output terminal; The transcoded data parsing module is connected to the transcoded adaptive decoding module, and is used to perform display analysis on the decoded data to obtain transcoded display data, and forward the transcoded display data to the DMX512 protocol display circuit through the first signal transcoding end or forward the transcoded display data to the return-to-zero code protocol display circuit through the second signal transcoding end; The transcoding parameter parsing module is connected to the transcoding adaptive decoding module, and is used to perform parameter analysis on the decoded data to obtain parameter data, store the parameter data in the first memory, and forward the parameter data to the DMX512 protocol display circuit through the first signal transcoding end or forward the parameter data to the return-to-zero code protocol display circuit through the second signal transcoding end.

5. The lighting system according to claim 4, characterized in that The DMX512 protocol parallel transcoding chip also includes a second memory, wherein: The second memory is used to store the transcoded display data, and cyclically forward the transcoded display data to the first signal transcoding end or the second signal transcoding end.

6. The lighting system according to claim 5, characterized in that The DMX512 protocol controller includes: a first signal sending end and a second signal sending end, wherein: The first signal sending end of the DMX512 protocol controller is connected to the first signal receiving end of the DMX512 protocol parallel transcoding chip through a first resistor; The second signal sending end of the DMX512 protocol controller is connected to the second signal receiving end of the DMX512 protocol parallel transcoding chip through a second resistor.

7. The lighting system according to claim 6, characterized in that The DMX512 protocol display circuit includes: a plurality of DMX512 protocol cascade display chips, a transcoding resistor, a plurality of output resistors and a plurality of cascade input resistors, wherein: The first display receiving end of the DMX512 protocol cascade display chip is connected to the first signal transcoding end of the DMX512 protocol parallel transcoding chip through the transcoding resistor, and receives the control signal forwarded by the DMX512 protocol parallel transcoding chip; The first display output end of the DMX512 protocol cascade display chip is connected to the first cascade address end of the next cascaded DMX512 protocol cascade display chip through being connected in series with the output resistor and the cascade input resistor, and forwards the control signal to the next cascaded DMX512 protocol cascade display chip.

8. The lighting system according to claim 7, characterized in that The DMX512 protocol cascade display chip includes: a DMX512 adaptive decoding module, a DMX512 data parsing module, a DMX512 parameter parsing module, a DMX512 address parsing module, a DMX512 correction module and a third memory, wherein: The DMX512 adaptive decoding module is used to perform adaptive transmission rate decoding on the transcoded display data to obtain DMX512 protocol display data; The DMX512 data parsing module is connected to the DMX512 adaptive decoding module, and is used to parse the DMX512 protocol display data to obtain DMX512 protocol parsing data, and send the DMX512 protocol parsing data to the DMX512 correction module; The DMX512 parameter parsing module is connected to the DMX512 adaptive decoding module, and is used to perform parameter analysis on the DMX512 protocol display data to obtain DMX512 protocol parameter data, store the DMX512 protocol parameter data in a third memory, and send the DMX512 protocol parameter data to the color display end of the DMX512 protocol cascade display chip; The DMX512 address resolution module is connected to the DMX512 adaptive decoding module, and is used to perform address resolution on the DMX512 protocol display data to obtain DMX512 protocol address data, store the DMX512 protocol address data in the third memory, and forward the DMX512 protocol address data to the next cascaded DMX512 protocol cascade display chip through the first display output end of the DMX512 protocol cascade display chip; The DMX512 correction module is connected to the DMX512 data parsing module, and is used to perform gamma correction on the DMX512 protocol parsing data to obtain the corrected DMX512 protocol parsing data, and send the corrected DMX512 protocol parsing data to the color display end of the DMX512 protocol cascade display chip, so that the color display end of the DMX512 protocol cascade display chip displays according to the corrected DMX512 protocol parsing data.

9. The lighting system according to claim 6, characterized in that The return-to-zero code protocol display circuit includes a plurality of return-to-zero code protocol cascade display chips, wherein: The second display receiving end of the return-to-zero code protocol cascade display chip is connected to the second signal transcoding end of the DMX512 protocol parallel transcoding chip to receive the control signal forwarded by the DMX512 protocol parallel transcoding chip; The second display output terminal of the return-to-zero code protocol cascade display chip is connected to the second display receiving terminal of the next cascade return-to-zero code protocol cascade display chip, and forwards the control signal to the next cascade return-to-zero code protocol cascade display chip.

10. The lighting system according to claim 9, characterized in that The return-to-zero code protocol cascade display chip includes: a return-to-zero code adaptive decoding module, a return-to-zero code data parsing module, a return-to-zero code forwarding module and a return-to-zero code correction module, wherein: The return-to-zero code adaptive decoding module is used to perform adaptive transmission rate decoding on the transcoded display data to obtain return-to-zero code protocol display data; The return-to-zero code data parsing module is connected to the return-to-zero code adaptive decoding module, and is used to parse the return-to-zero code protocol display data to obtain return-to-zero code protocol parsing data, and send the return-to-zero code protocol parsing data to the return-to-zero code correction module; The return-to-zero code forwarding module is connected to the return-to-zero code adaptive decoding module and is used to send the return-to-zero code protocol display data to the second display output end of the return-to-zero code protocol cascade display chip, so that the second display output end of the return-to-zero code protocol cascade display chip forwards the return-to-zero code protocol display data to the next cascade return-to-zero code protocol cascade display chip; The return-to-zero code correction module is connected to the return-to-zero code data parsing module, and is used to perform gamma correction on the return-to-zero code protocol parsing data to obtain corrected return-to-zero code protocol parsing data, and send the corrected return-to-zero code protocol parsing data to the color display end of the return-to-zero code protocol cascade display chip, so that the color display end of the return-to-zero code protocol cascade display chip displays according to the corrected return-to-zero code protocol parsing data.

11. A lighting method, characterized in that: A parallel transcoding chip used in a lighting system according to any one of claims 1 to 10, wherein the method comprises: Receive control signals sent by the lighting controller; Performing transcoding processing on the control signal to obtain transcoded data; The transcoded data is forwarded to a connected display circuit so that the display circuit performs display according to the transcoded data.

12. The lighting method according to claim 11, characterized in that: The lighting controller is a multi-channel digital transmission DMX512 protocol controller, the parallel transcoding chip is a DMX512 protocol parallel transcoding chip, the display circuit includes a DMX512 protocol display circuit or a return-to-zero code protocol display circuit, and the method includes: When the display circuit is the DMX512 protocol display circuit, the first signal transcoding end of the DMX512 protocol parallel transcoding chip is connected to the DMX512 protocol display circuit, and the control signal received from the DMX512 protocol controller is forwarded to the DMX512 protocol display circuit through the first signal transcoding end; When the display circuit is the return-to-zero code protocol display circuit, the second signal transcoding end of the DMX512 protocol parallel transcoding chip is connected to the return-to-zero code protocol display circuit, and the control signal received from the DMX512 protocol controller is forwarded to the return-to-zero code protocol display circuit through the second signal transcoding end.

13. The lighting method according to claim 12, characterized in that: The method further comprises: In the case where a first preset number of the DMX512 protocol parallel transcoding chips are cascaded, all the control signals including the address data of the current DMX512 protocol parallel transcoding chip are stored in the second memory of the current DMX512 protocol parallel transcoding chip, and the control signals are cyclically forwarded to multiple DMX512 protocol cascaded display chips in the DMX512 protocol display circuit connected to the current DMX512 protocol parallel transcoding chip or multiple return-to-zero code protocol cascaded display chips in the return-to-zero code display circuit connected to the current DMX512 protocol parallel transcoding chip according to configuration requirements.

14. The lighting method according to claim 12, characterized in that: The method further comprises: In the case where a second preset number of DMX512 protocol cascade display chips are cascaded in the DMX512 protocol display circuit or a second preset number of return-to-zero code protocol cascade display chips are cascaded in the return-to-zero code display circuit, All the control signals containing the address data of the current DMX512 protocol transcoding chip are infinitely forwarded to multiple DMX512 protocol cascade display chips in the DMX512 protocol display circuit connected to the current DMX512 protocol transcoding chip or multiple return-to-zero code protocol cascade display chips in the return-to-zero code protocol display circuit connected to the current DMX512 protocol transcoding chip, until the last DMX512 protocol cascade display chip in the DMX512 protocol display circuit or the last return-to-zero code protocol display chip in the return-to-zero code protocol display circuit receives the control signal.

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