Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a manufacturing method thereof and electronic equipment, relates to the technical field of storage, and aims to improve the accuracy of data reading. The semiconductor structure includes a substrate, and a plurality of memory cells, a first word line, a first bit line, a second word line, and a second bit line disposed on the substrate. The memory cell includes a memory transistor and a write transistor. A memory transistor includes a first gate and a first semiconductor layer. The first grid electrode is electrically connected with the first word line. The first semiconductor layer is electrically connected with the first bit line and the second bit line. A first gate dielectric layer is arranged between the storage gate and the first semiconductor layer. The write transistor includes a second gate and a second semiconductor layer. The second grid electrode is electrically connected with the second word line. The second semiconductor layer is electrically connected with the storage grid electrode and the second bit line.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technologies, and particularly to a semiconductor structure, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technologies, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly, such that any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements for current products. Summary of the Invention

[0004] Based on this, embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and an electronic device, which are beneficial to compensating the threshold voltage of a storage transistor to ensure the accuracy of stored data reading, thereby further improving the performance of the memory.

[0005] According to some embodiments, the present disclosure provides a semiconductor structure on one hand. The semiconductor structure includes a substrate, and a plurality of memory cells, a first word line, a first bit line, a second word line, and a second bit line disposed on the substrate; the memory cell includes: a storage transistor, including: a first gate electrically connected to the first word line; a first semiconductor layer; a storage gate, the storage gate being located on a side of the first semiconductor layer away from the first gate; a write transistor, including: a second gate electrically connected to the second word line; a second semiconductor layer electrically connected to the storage gate and the second bit line respectively; the first semiconductor layer at least partially surrounds the first gate, the first semiconductor layer is electrically connected to the storage gate on one side in a first direction, and the first semiconductor layer is electrically connected to the first bit line and the second bit line respectively on both sides in a second direction; the first direction and the second direction intersect and are parallel to the substrate.

[0006] According to some embodiments, the second semiconductor layer at least partially surrounds the second gate. A first sidewall of the second semiconductor layer close to the storage gate and extending in the first direction is electrically connected to the storage gate. A second sidewall of the second semiconductor layer extending in the first direction and opposite to the first sidewall is electrically connected to the second bit line. The first direction is parallel to the substrate.

[0007] According to some embodiments, the first semiconductor layer covers a surface of the first bit line close to the substrate and a surface away from the substrate, and a surface of the second bit line close to the substrate and a surface away from the substrate.

[0008] According to some embodiments, the second semiconductor layer is electrically connected to the second bit line through the first semiconductor layer.

[0009] According to some embodiments, the second semiconductor layer is in contact with the surface of the first semiconductor layer close to the substrate, the surface away from the substrate, and the sidewall close to the second gate.

[0010] According to some embodiments, the first bit line and the second bit line extend along a first direction respectively and are spaced apart in a second direction; wherein, the storage gate is located between the first bit line and the second bit line and is insulated from both the first bit line and the second bit line.

[0011] According to some embodiments, both the first bit line and the second bit line have protruding portions facing the first gate.

[0012] According to some embodiments, the storage gate includes: a first portion extending along a second direction, and a second portion extending along a first direction and integrally connected to the first portion; wherein, the size of the second portion in the first direction is greater than the size of the second semiconductor layer in the first direction, and there is a gap between the second semiconductor layer and the first portion in the first direction.

[0013] According to some embodiments, the size of the second semiconductor layer in the second direction is greater than or equal to one-half of the size of the first portion in the second direction.

[0014] According to some embodiments, the first word line and the second word line extend along a third direction respectively, and the third direction intersects both the second direction and the first direction; wherein, the first gate and the first word line are an integral structure; the second gate and the second word line are an integral structure.

[0015] According to some embodiments, the data read / write timing of the semiconductor device includes: a pre-charge stage, a data write stage, and a data read stage; the first bit line is configured to: provide a first reference voltage to the storage transistor in the pre-charge stage, write data to the storage transistor in the data write stage, and read data in response to the conduction state of the storage transistor in the data read stage; the sum of the maximum data voltage corresponding to the data and the threshold voltage of the storage transistor is the reference voltage; the first reference voltage is greater than the reference voltage.

[0016] According to some embodiments, the second bit line is configured to: provide the first reference voltage to both the storage transistor and the write transistor in the pre-charge stage, float in the data write stage, and provide a second reference voltage to both the storage transistor and the write transistor in the data read stage; wherein, the first reference voltage is greater than the second reference voltage.

[0017] According to some embodiments, a plurality of memory cells are arranged in columns along a first direction; wherein, a column of memory cells shares a first bit line and a second bit line.

[0018] According to some embodiments, the semiconductor structure further includes: a first isolation structure and a second isolation structure. The first isolation structure is located between adjacent memory cells in the first direction, and between a write transistor and a memory gate in any one of the memory cells. The second isolation structure is located between adjacent columns of memory cells; wherein, the adjacent columns of memory cells are symmetrically arranged with respect to the second isolation structure.

[0019] According to some embodiments, on the other hand, the present disclosure provides a method for manufacturing a semiconductor structure, including the following steps.

[0020] Provide a substrate, and form a stacked structure on the substrate; the stacked structure includes multiple layers of conductive material layers and multiple layers of insulating material layers stacked alternately in a direction perpendicular to the substrate.

[0021] Etch the stacked structure in a direction perpendicular to the substrate to form a plurality of etched trenches and a plurality of first etched holes.

[0022] Based on the etched trenches and the first etched holes, respectively etch the corresponding sidewalls of the conductive material layers, so that the remaining portions of the conductive material layers form memory gates and dummy write transistors, and simultaneously form a first accommodation region, a second accommodation region, and a third accommodation region connecting the first accommodation region and the second accommodation region.

[0023] Form a first gate dielectric layer and a first semiconductor layer in the first accommodation region, the second accommodation region, and the third accommodation region in sequence. Form a first bit line contacting the first semiconductor layer in the first accommodation region, form a second bit line contacting the first semiconductor layer in the second accommodation region, form a second gate dielectric layer at least covering the first semiconductor layer and a first gate covering the second gate dielectric layer in the third accommodation region. The memory transistor includes a first semiconductor layer, a first gate, and a memory gate.

[0024] Form a first word line electrically connected to the first gate in the first etched hole.

[0025] Etch the stacked structure in a direction perpendicular to the substrate to form a second etched hole penetrating through each dummy write transistor.

[0026] Remove each dummy write transistor based on the second etched hole to form a fourth accommodation region.

[0027] Form a write transistor in the fourth accommodation region. The write transistor includes: a second gate and a second semiconductor layer; the second semiconductor layer is electrically connected to the memory gate and the second bit line respectively.

[0028] Form a second word line electrically connected to the second gate in the second etched hole.

[0029] According to some embodiments, before etching the stacked structure along the vertical substrate direction to form a plurality of etching trenches and a plurality of first etching holes, the manufacturing method further includes the following steps.

[0030] Pattern the stacked structure to form a plurality of first isolation trenches. The first isolation trenches are used to define the formation positions of corresponding memory cells and isolate adjacent memory cells in the first direction; the memory cells include memory transistors and write transistors. The first direction is parallel to the substrate.

[0031] Fill the first isolation trenches with an insulating material to form a first isolation structure.

[0032] According to some embodiments, a first gate dielectric layer and a first semiconductor layer are sequentially formed in a first accommodation region, a second accommodation region, and a third accommodation region. A first bit line contacting the first semiconductor layer is formed in the first accommodation region, a second bit line contacting the first semiconductor layer is formed in the second accommodation region, a second gate dielectric layer covering at least the first semiconductor layer and a first gate electrode covering the second gate dielectric layer are formed in the third accommodation region, and a first word line electrically connected to the first gate electrode is formed in the first etching hole, including the following steps.

[0033] In the etching trenches, the first etching holes, and the etching regions of the conductive material layer, a first gate dielectric layer, a first semiconductor material layer, and a first sacrificial layer are sequentially formed.

[0034] Remove the first sacrificial layer and the first semiconductor material layer in the etching trenches and the first etching holes, so that the remaining part of the first semiconductor material layer forms a first semiconductor layer, the remaining part of the first sacrificial layer in the first accommodation region forms a virtual first bit line, the remaining part of the first sacrificial layer in the second accommodation region forms a virtual second bit line, and the remaining part of the first sacrificial layer in the third accommodation region forms a virtual first gate electrode.

[0035] Form a second sacrificial layer covering the first gate dielectric layer in the etching trenches and the first etching holes.

[0036] Remove the second sacrificial layer in the etching trenches, the virtual first bit line, and the virtual second bit line.

[0037] Form a first bit line covering the first semiconductor layer in the first accommodation region.

[0038] Form a second bit line covering the first semiconductor layer in the second accommodation region.

[0039] Fill the etching trenches with an insulating material to form a second isolation structure.

[0040] Remove the second sacrificial layer and the virtual first gate electrode in the first etching hole.

[0041] A second gate dielectric layer, a first gate, and a first word line electrically connected to the first gate are sequentially formed in the first etching hole and the third accommodating region.

[0042] According to some embodiments, a write transistor is formed in the fourth accommodating region, and a second word line electrically connected to the second gate is formed in the second etching hole, including the following steps.

[0043] A second semiconductor material layer and a third sacrificial layer are sequentially formed in the second etching hole and the fourth accommodating region.

[0044] The third sacrificial layer and the second semiconductor material layer in the second etching hole are removed, so that the remaining portion of the second semiconductor material layer forms a second semiconductor layer.

[0045] The remaining third sacrificial layer is removed.

[0046] A third gate dielectric layer, a second gate, and a second word line electrically connected to the second gate are sequentially formed in the second etching hole and the removal region of the remaining third sacrificial layer.

[0047] According to some embodiments, on the other hand, the present disclosure further provides an electronic device, including: the semiconductor structure described in any of the above embodiments.

[0048] The embodiments of the present disclosure may / at least have the following advantages:

[0049] In the embodiments of the present disclosure, by arranging that the first semiconductor layer at least partially surrounds the first gate, one side of the first semiconductor layer in the first direction is electrically connected to the storage gate, and both sides of the first semiconductor layer in the second direction are respectively electrically connected to the first bit line and the second bit line; it is possible to realize that the first semiconductor layer surrounds the first gate to form a gate-all-around structure, thereby improving the gate control ability of the storage transistor, while fully saving space, so that the annular first semiconductor layer can be respectively connected to the storage gate, the first bit line, and the second bit line, improving the density of the storage array.

[0050] By electrically connecting the first gate of the storage transistor to the first word line, electrically connecting the first semiconductor layer of the storage transistor to the first bit line and the second bit line respectively, electrically connecting the second gate of the write transistor to the second word line, and electrically connecting the second semiconductor layer of the write transistor to the storage gate and the second bit line respectively. Based on this, the embodiments of the present disclosure can use the first bit line and the second bit line to provide different electrical signals to the storage transistor at different stages of the data read / write cycle, and combine the control of the control voltages of the storage transistor and the write transistor, so as to retain the threshold voltage of the storage transistor at the storage node while writing data at the storage node during the data writing stage, and further facilitate reading data that is not affected by the threshold voltage of the storage transistor through the first bit line during the data reading stage, so as to ensure the accuracy of the stored data reading and further improve the performance of the memory. In addition, in the embodiments of the present disclosure, the structures of the semiconductor structure and the electronic device are as described above, which is also beneficial to reducing the process complexity to improve the production efficiency and process yield. Description of the Drawings

[0051] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0052] Figure 1 It is an equivalent circuit diagram of a 2T0C architecture memory cell provided in some embodiments of the present disclosure;

[0053] Figure 2 It is an equivalent circuit diagram of a memory cell array in a semiconductor structure provided in some embodiments of the present disclosure;

[0054] Figure 3 It is a structural diagram of a semiconductor structure provided in some embodiments of the present disclosure; wherein, Figure 3 Figure (a) in it is a top view of a semiconductor structure, Figure 3 Figure (b) in it is Figure 3 Figure (a) in Figure 1 a cross-sectional view perpendicular to the substrate along the A-A direction, Figure 3 Figure (c) in it is Figure 3 Figure (a) in Figure 1 a cross-sectional view perpendicular to the substrate along the B-B direction, Figure 3 Figure (d) in it is Figure 3 Figure (a) in Figure 1 a cross-sectional view perpendicular to the substrate along the C-C direction;

[0055] Figure 4Schematic flow chart of a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure;

[0056] Figure 5 Schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure;

[0057] Figure 6 Schematic flow chart of a step S400 provided in some embodiments of the present disclosure;

[0058] Figure 7 Schematic flow chart of a step S700 provided in some embodiments of the present disclosure;

[0059] Figure 8 Schematic diagram of the structure obtained after forming a stacked structure in some embodiments of the present disclosure; wherein, Figure 8 Figure (a) in [reference] is a top view schematic diagram of the structure obtained after forming a stacked structure, Figure 8 Figure (b) in [reference] is Figure 8 Figure (a) in [reference] Figure 1 a schematic cross-sectional view perpendicular to the substrate along the A-A direction;

[0060] Figure 9 Schematic diagram of the structure obtained after forming a first isolation structure in some embodiments of the present disclosure; wherein, Figure 9 Figure (a) in [reference] is a top view schematic diagram of the structure obtained after forming a first isolation structure, Figure 9 Figure (b) in [reference] is Figure 9 Figure (a) in [reference] Figure 1 a schematic cross-sectional view perpendicular to the substrate along the A-A direction;

[0061] Figure 10 Schematic diagram of the structure obtained after forming an etching trench and a first etching hole in some embodiments of the present disclosure; wherein, Figure 10 Figure (a) in [reference] is a top view schematic diagram of the structure obtained after forming an etching trench and a first etching hole, Figure 10 Figure (b) in [reference] is Figure 10 Figure (a) in [reference] Figure 1 a schematic cross-sectional view perpendicular to the substrate along the A-A direction, Figure 10 Figure (c) in [reference] is Figure 10 Figure (a) in [reference] Figure 1 a schematic cross-sectional view perpendicular to the substrate along the B-B direction;

[0062] Figure 11 Schematic diagram of the structure obtained after forming a first accommodation region, a second accommodation region, and a third accommodation region in some embodiments of the present disclosure; wherein, Figure 11Figure (a) in [reference] is a top view schematic diagram of the structure obtained after forming the first accommodation area, the second accommodation area, and the third accommodation area. Figure 11 Figure (b) in [reference] is Figure 11 Figure (a) in [reference] Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the A-A direction. Figure 11 Figure (c) in [reference] is Figure 11 Figure (a) in [reference] Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the B-B direction;

[0063] Figure 12 This is a schematic diagram of the structure obtained after forming the first gate dielectric layer, the first semiconductor material layer, and the first sacrificial layer in some embodiments of the present disclosure; wherein, Figure 12 Figure (a) in [reference] is a top view schematic diagram of the structure obtained after forming the first gate dielectric layer, the first semiconductor material layer, and the first sacrificial layer. Figure 12 Figure (b) in [reference] is Figure 12 Figure (a) in [reference] Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the A-A direction. Figure 12 Figure (c) in [reference] is Figure 12 Figure (a) in [reference] Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the B-B direction;

[0064] Figure 13 This is a schematic diagram of the structure obtained after forming the first semiconductor layer and the second sacrificial layer in some embodiments of the present disclosure; wherein, Figure 13 Figure (a) in [reference] is a top view schematic diagram of the structure obtained after forming the first semiconductor layer and the second sacrificial layer. Figure 13 Figure (b) in [reference] is Figure 13 Figure (a) in [reference] Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the A-A direction. Figure 13 Figure (c) in [reference] is Figure 13 Figure (a) in [reference] Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the B-B direction;

[0065] Figure 14 This is a schematic diagram of the structure obtained after forming the bit line material layer in some embodiments of the present disclosure; wherein, Figure 14 Figure (a) in [reference] is a top view schematic diagram of the structure obtained after forming the bit line material layer. Figure 14 Figure (b) in [reference] is Figure 14 Figure (a) in [reference] Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the A-A direction. Figure 14 Figure (c) in [reference] is Figure 14 Figure (a) in [reference] Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the B-B direction;

[0066] Figure 15 Schematic diagram of a structure obtained after forming a first bit line, a second bit line, and a second isolation structure in some embodiments of the present disclosure; wherein, Figure 15 Figure (a) in is a top view schematic diagram of the structure obtained after forming the first bit line, the second bit line, and the second isolation structure, Figure 15 Figure (b) in is Figure 15 Figure (a) in Figure 1 A schematic cross-sectional view perpendicular to the substrate along the A-A direction, Figure 15 Figure (c) in is Figure 15 Figure (a) in Figure 1 A schematic cross-sectional view perpendicular to the substrate along the B-B direction, Figure 15 Figure (d) in is Figure 15 Figure (a) in Figure 1 A schematic cross-sectional view perpendicular to the substrate along the C-C direction;

[0067] Figure 16 Schematic diagram of a structure obtained after forming a second gate dielectric layer, a first gate, and a first word line in some embodiments of the present disclosure; wherein, Figure 16 Figure (a) in is a top view schematic diagram of the structure obtained after forming the second gate dielectric layer, the first gate, and the first word line, Figure 16 Figure (b) in is Figure 16 Figure (a) in Figure 1 A schematic cross-sectional view perpendicular to the substrate along the A-A direction, Figure 16 Figure (c) in is Figure 16 Figure (a) in Figure 1 A schematic cross-sectional view perpendicular to the substrate along the B-B direction, Figure 16 Figure (d) in is Figure 16 Figure (a) in Figure 1 A schematic cross-sectional view perpendicular to the substrate along the C-C direction;

[0068] Figure 17 Schematic diagram of a structure obtained after forming a second etching hole and a fourth accommodating region in some embodiments of the present disclosure; wherein, Figure 17 Figure (a) in is a top view schematic diagram of the structure obtained after forming the second etching hole and the fourth accommodating region, Figure 17 Figure (b) in is Figure 17 Figure (a) in Figure 1 A schematic cross-sectional view perpendicular to the substrate along the A-A direction, Figure 17 Figure (c) in is Figure 17 Figure (a) in Figure 1 A schematic cross-sectional view perpendicular to the substrate along the B-B direction, Figure 17 Figure (d) in is Figure 17 Figure (a) in Figure 1Schematic cross-sectional view perpendicular to the substrate along the C-C direction;

[0069] Figure 18 Schematic structural diagram of a structure obtained after forming a second semiconductor material layer and a third sacrificial layer in some embodiments of the present disclosure; wherein, Figure 18 Figure (a) in is a top view schematic diagram of the structure obtained after forming the second semiconductor material layer and the third sacrificial layer, Figure 18 Figure (b) in is Figure 18 Figure (a) in Figure 1 Schematic cross-sectional view perpendicular to the substrate along the A-A direction, Figure 18 Figure (c) in is Figure 18 Figure (a) in Figure 1 Schematic cross-sectional view perpendicular to the substrate along the B-B direction, Figure 18 Figure (d) in is Figure 18 Figure (a) in Figure 1 Schematic cross-sectional view perpendicular to the substrate along the C-C direction;

[0070] Figure 19 Schematic structural diagram of a structure obtained after forming a second semiconductor layer in some embodiments of the present disclosure; wherein, Figure 19 Figure (a) in is a top view schematic diagram of the structure obtained after forming the second semiconductor layer, Figure 19 Figure (b) in is Figure 19 Figure (a) in Figure 1 Schematic cross-sectional view perpendicular to the substrate along the A-A direction, Figure 19 Figure (c) in is Figure 19 Figure (a) in Figure 1 Schematic cross-sectional view perpendicular to the substrate along the B-B direction, Figure 19 Figure (d) in is Figure 19 Figure (a) in Figure 1 Schematic cross-sectional view perpendicular to the substrate along the C-C direction;

[0071] Figure 20 Timing diagram of a driving method of a memory provided in some embodiments of the present disclosure;

[0072] Figure 21 Timing diagram of another driving method of a memory provided in some embodiments of the present disclosure;

[0073] Figure 22 Timing diagram of yet another driving method of a memory provided in some embodiments of the present disclosure;

[0074] Figure 23 Curve graph of the current-voltage characteristics of a storage transistor during a data reading stage provided in some embodiments of the present disclosure.

[0075] Reference numerals:

[0076] U - memory cell, 1 - substrate, N - stacked structure, T1 - memory transistor, T2 - write transistor, G0 - memory gate, G01 - first part, G02 - second part, G1 - first gate, G2 - second gate, 21 - first semiconductor layer, 22 - second semiconductor layer, S / D11 - first pole of the memory transistor, S / D12 - second pole of the memory transistor, S / D21 - first pole of the write transistor, S / D22 - second pole of the write transistor, SN - memory node, BL1 - first bit line, BL2 - second bit line, 3 - protrusion, WL1 - first word line, WL2 - second word line; YM - hard mask layer, L1 - conductive material layer, L2 - insulating material layer, H1 - first etching hole, H2 - second etching hole, S - etching trench, R1 - first accommodation area, R2 - second accommodation area, R3 - third accommodation area, R4 - fourth accommodation area, T' - dummy write transistor, BL1' - dummy first bit line, BL2' - dummy second bit line, G1' - dummy first gate, 210 - first semiconductor material layer, 220 - second semiconductor material layer, 11 - first isolation structure, 111 - first sub - isolation part, 112 - second sub - isolation part, 12 - first gate dielectric layer, 13 - first sacrificial layer, 14 - second sacrificial layer, 15 - bit line material layer, 16 - second isolation structure, 17 - second gate dielectric layer, 18 - third sacrificial layer, 19 - third gate dielectric layer. Detailed implementation manners

[0077] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure is thorough and comprehensive.

[0078] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0079] The mention of "embodiments" herein means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present disclosure. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0080] It will be understood that the terms "first", "second", "third", "fourth", etc. used in the present application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.

[0081] It will be understood that in the following embodiments, "connection", if there is a transfer of electrical signals or data between the connected circuits, modules, units, etc., should be understood as "electrical connection", "communication connection", etc.

[0082] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" or "having", etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0083] Some embodiments of the present disclosure provide a semiconductor structure, including a substrate, and a plurality of memory cells, a first word line, a first bit line, a second word line, and a second bit line disposed on the substrate. Please refer to Figures 1 to 3 , the memory cell U includes a memory transistor T1 and a write transistor T2, and the memory transistor T1 and the write transistor T2 can participate in pre-charging simultaneously and participate in writing data simultaneously to achieve threshold voltage compensation of the memory transistor, thereby ensuring the accuracy of data reading. Hereinafter, in at least some embodiments of the present disclosure, the said memory transistor can be understood as a read transistor having at least a data reading function. The read transistor or the memory transistor participates in pre-charging and writing data simultaneously in the data writing stage and is used for reading data in the reading stage.

[0084] Figure 1 The equivalent circuit diagram of a memory cell U in some embodiments of the present disclosure is shown. Please refer to Figure 1, the storage unit U is electrically connected to the first word line WL1, the first bit line BL1, the second word line WL2, and the second bit line BL2 respectively. The storage unit U includes: a storage transistor T1 and a write transistor T2. Among them, the storage transistor T1 includes: a storage gate G0, a first gate G1, a first pole S / D11, and a second pole S / D12. The write transistor T2 includes a second gate G2, a first pole S / D21, and a second pole S / D22. Among them, the first gate G1 is connected to the first word line WL1. The second gate G2 is connected to the second word line WL2. The first pole S / D11 of the storage transistor T1 is connected to the first bit line BL1. The first pole S / D21 of the write transistor T2 is connected to the storage gate G0. The second pole S / D12 of the storage transistor T1 and the second pole S / D22 of the write transistor T2 are respectively connected to the second bit line BL2. Among them, the intersection point where the first pole S / D21 of the write transistor T2 is connected to the storage gate G0 is the storage node SN.

[0085] Here, matching the transmission direction of the current, among the first pole S / D11 and the second pole S / D12 of the storage transistor T1, one can be the source pole and the other can be the drain pole. Among the first pole S / D21 and the second pole S / D22 of the write transistor T2, one can be the source pole and the other can be the drain pole. And, Figure 1 the case where both the storage transistor T1 and the write transistor T2 are N-type transistors is taken as an example for introduction, and the type of the transistor is not limited in practical applications.

[0086] And, it can be understood that the semiconductor structure provided by the embodiments of the present disclosure can be, for example, a memory. A memory usually includes multiple storage units, and each storage unit can be distributed in a two-dimensional single layer or a three-dimensional multi-layer. Exemplarily, the three-dimensional multi-layer distribution of each storage unit and the related wiring can refer to Figure 2 the circuit shown for arrangement, and the embodiments of the present disclosure do not elaborate on this.

[0087] Figure 3 is a schematic structural diagram of a storage unit U in some embodiments of the present disclosure, which is used to implement the circuit of the storage unit U described in the above embodiments.

[0088] Please refer to Figure 3, in some embodiments of the present disclosure, a semiconductor structure is provided, including a substrate 1, and a plurality of memory cells, a first word line WL1, a first bit line BL1, a second word line WL2, and a second bit line BL2 disposed on the substrate 1; the memory cell includes: a memory transistor T1, including: a first gate G1 electrically connected to the first word line; a first semiconductor layer 21; a storage gate G0 located on a side of the first semiconductor layer 21 away from the first gate G1; a write transistor T2, including: a second gate G2 electrically connected to the second word line WL2; a second semiconductor layer 22 electrically connected to the storage gate and the second bit line BL2 respectively; at least a part of the first semiconductor layer 21 surrounds the first gate G1, one side of the first semiconductor layer 21 in a first direction is electrically connected to the storage gate G0, and both sides of the first semiconductor layer 21 in a second direction are electrically connected to the first bit line BL1 and the second bit line BL2 respectively; the first direction and the second direction intersect and are parallel to the substrate.

[0089] By setting that at least a part of the first semiconductor layer surrounds the first gate, one side of the first semiconductor layer in the first direction is electrically connected to the storage gate, and both sides of the first semiconductor layer in the second direction are electrically connected to the first bit line and the second bit line respectively; it is possible to surround the first gate with the first semiconductor layer to form a gate-all-around structure, thereby improving the gate control ability of the memory transistor while fully saving space, so that the annular first semiconductor layer can be respectively connected to the storage gate, the first bit line and the second bit line, improving the density of the memory array.

[0090] The memory transistor T1 includes: a storage gate G0, a first gate G1, and a first semiconductor layer 21. The first gate G1 is electrically connected to the first word line WL1.

[0091] The first semiconductor layer 21 is electrically connected to the first bit line BL1 and the second bit line BL2 respectively. There is a first gate dielectric layer 12 between the storage gate G0 and the first semiconductor layer 21.

[0092] Exemplarily, at least a part of the first semiconductor layer 21 surrounds the first gate G1, and covers the surface of the first bit line BL1 close to the substrate 1 and the surface away from the substrate 1, as well as the surface of the second bit line BL2 close to the substrate 1 and the surface away from the substrate 1. For example, the first semiconductor layer 21 is insulatingly disposed on the sidewall of the first gate G1, and covers the sidewall and the upper and lower surfaces of the first bit line BL1 close to the first gate G1, as well as the sidewall and the upper and lower surfaces of the second bit line BL2 close to the first gate G1.

[0093] Exemplarily, the storage gate G0 extends along a first direction (e.g., the Y direction), and is insulated on the sidewalls of the first semiconductor layer 21 extending along a second direction (e.g., the X direction). The first direction (e.g., the Y direction) and the second direction (e.g., the X direction) are parallel to the substrate 1 and intersect, for example, orthogonally.

[0094] In the storage transistor T1, the portions of the first semiconductor layer 21 corresponding to and connected to the first bit line BL1 and the second bit line BL2 are respectively used to form the first pole S / D11 and the second pole S / D12. Moreover, the first semiconductor layer 21 covers the sidewalls and the upper and lower surfaces of the first bit line BL1 close to the first gate G1, and the sidewalls and the upper and lower surfaces of the second bit line BL2 close to the first gate G1, which can ensure that the storage transistor T1 and the first bit line BL1 and the second bit line BL2 all have a large contact area, so as to facilitate reducing the contact resistance.

[0095] Please continue to refer to Figure 3 , in some embodiments of the present disclosure, the write transistor T2 includes: a second gate G2 and a second semiconductor layer 22. The second gate G2 is electrically connected to the second word line WL2. The second semiconductor layer 22 is electrically connected to the storage gate G0 and the second bit line BL2 respectively.

[0096] Exemplarily, the second gate G2 is located on one side of the storage gate G0 in the second direction (e.g., the X direction).

[0097] Exemplarily, the second semiconductor layer 22 at least partially surrounds the second gate G2. For example, the second semiconductor layer 22 insulatively surrounds the circumference of the second gate G2.

[0098] Exemplarily, the first sidewall of the second semiconductor layer 22 close to the storage gate G0 and extending along the first direction (e.g., the Y direction) is electrically connected to the storage gate G0. The second sidewall of the second semiconductor layer 22 extending along the first direction (e.g., the Y direction) and opposite to the first sidewall is electrically connected to the second bit line BL2.

[0099] It should be added that the data read / write timing sequence of the storage unit U includes: a data writing stage, a data reading stage, and a standby stage (which can be understood as the standby stage) before data writing or reading; wherein, in the embodiments of the present disclosure, a pre-charge stage is further included before the data writing stage, and a data holding stage is further included after the data writing stage. Thus, the above-mentioned first word line WL1, first bit line BL1, second word line WL2, and second bit line BL2 corresponding to and electrically connected to the storage unit U can provide corresponding electrical signals to the storage unit U according to the requirements of different timing stages of the storage unit U.

[0100] Exemplarily, the first bit line BL1 is configured to: provide a first reference voltage to the storage transistor T1 during the standby stage and the pre-charge stage, write data to the storage transistor T1 during the data write stage, and read data in response to the conduction state of the storage transistor T1 during the data read stage. The second bit line BL2 is configured to: provide the first reference voltage to both the storage transistor T1 and the write transistor T2 simultaneously during the standby stage and the pre-charge stage, float during the data write stage, and provide a second reference voltage to both the storage transistor T1 and the write transistor T2 simultaneously during the data read stage; wherein, the sum of the maximum data voltage corresponding to the data and the threshold voltage of the storage transistor T1 is the reference voltage, and the first reference voltage is greater than the reference voltage.

[0101] Exemplarily, both the storage transistor T1 and the write transistor T2 are N-type transistors. The second reference voltage is less than the first reference voltage.

[0102] Exemplarily, the second reference voltage is greater than the minimum data voltage that the storage cell U can store and less than the maximum data voltage that the storage cell U can store.

[0103] Exemplarily, the first word line WL1 is configured to: provide a first write control voltage to the first gate G1 during the pre-charge stage and the data write stage, apply a read control voltage to the first gate G1 during the data read stage, and apply a first turn-off control voltage to the first gate G1 during the standby stage. The second word line WL2 is configured to: provide a second write control voltage to the second gate G2 during the pre-charge stage and the data write stage, and apply a second turn-off control voltage to the second gate G2 during the data read stage and the standby stage. Among them, both the first turn-off control voltage and the second turn-off control voltage are low-level voltages. Both the first write control voltage and the second write control voltage are high-level voltages. The read control voltage is higher than the first write control voltage.

[0104] In the above embodiments of the present disclosure, by insulating the first semiconductor layer 21 of the storage transistor T1 and disposing it on the sidewall of the first gate G1, and covering the sidewall and the upper and lower surfaces of the first bit line BL1 close to the first gate G1, and setting the sidewall and the upper and lower surfaces of the second bit line BL2 close to the first gate G1, the first semiconductor layer 21 of the storage transistor T1 is electrically connected to the first bit line BL1 and the second bit line BL2 respectively and has a large contact area. And, by insulating the storage gate G0 and disposing it on the sidewall of the first semiconductor layer 21 extending in the first direction and making the storage gate G0 extend in the second direction, the second gate G2 of the write transistor T2 can be disposed on one side of the storage gate G0 in the first direction, and the second semiconductor layer 22 of the write transistor T2 is electrically connected to the storage gate G0 and the second bit line BL2 respectively while insulating and surrounding the circumference of the second gate G2.

[0105] In summary, the embodiments of the present disclosure can use the first bit line BL1 and the second bit line BL1 to respectively provide different electrical signals to the storage transistor T1 at different stages of the data read / write cycle, and combine the control of the control voltages of both the storage transistor T1 and the write transistor T2 (i.e., the voltages provided by the first word line WL1 and the second word line WL2), so as to retain the threshold compensation voltage of the storage transistor T1 at the storage node SN while writing data at the storage node during the data writing stage, and further facilitate reading data that is not affected by the threshold voltage Vth of the storage transistor T1 through the first bit line BL1 during the data reading stage, to ensure the accuracy of the stored data reading and further improve the memory performance.

[0106] In addition, in the embodiments of the present disclosure, the structure of the storage unit U is as described above, which is also conducive to reducing the process complexity to improve the production efficiency and process yield.

[0107] In some embodiments, referring to Figure 3 , the storage unit U further includes: a first gate dielectric layer 12 disposed between the storage gate G0 and the first semiconductor layer 21, a second gate dielectric layer 17 disposed between the first semiconductor layer 21 and the first gate G1, and a third gate dielectric layer 19 disposed between the second semiconductor layer 22 and the second gate G2.

[0108] Exemplarily, the materials of the first gate dielectric layer 12, the second gate dielectric layer 17, and the third gate dielectric layer 19 include but are not limited to silicon oxide.

[0109] Exemplarily, the second gate dielectric layer 17 also covers the surface of the first gate dielectric layer 12 that is not covered by the first semiconductor layer 21.

[0110] In some embodiments, the second semiconductor layer 22 is electrically connected to the second bit line BL2 through the first semiconductor layer 21.

[0111] Exemplarily, referring to Figure 3 in the figure (b), the second semiconductor layer 22 is in contact with the surface of the first semiconductor layer 21 close to the substrate 1, the surface away from the substrate 1, and the sidewall close to the second gate G2. In this way, it is beneficial to reduce the contact resistance between the first semiconductor layer 21 and the second semiconductor layer 22.

[0112] Exemplarily, the materials of the first semiconductor layer 21 and the second semiconductor layer 22 include but are not limited to metal oxide semiconductors, for example, it can be indium gallium zinc oxide (Indium Gallium Zinc Oxide, abbreviated as IGZO).

[0113] In some embodiments, referring to Figure 3In FIGS. (a) and (b), the first bit line BL1 and the second bit line BL2 extend along a first direction (e.g., the Y direction) respectively, and are spaced apart in a second direction (e.g., the X direction). Among them, the storage gate G0 is located between the first bit line BL1 and the second bit line BL2, and is insulated from both the first bit line BL1 and the second bit line BL2.

[0114] In the embodiments of the present disclosure, the first bit line BL1 and the second bit line BL2 are arranged in parallel and spaced apart, which is beneficial to achieving a compact arrangement of the memory cells U within the space between the first bit line BL1 and the second bit line BL2, and effectively using the storage gate G0 as the connection node (i.e., the storage node SN) and the position boundary between the storage transistor T1 and the write transistor T2.

[0115] In some embodiments, please refer to Figure 3 FIGS. (a), (b) and (c), the first bit line BL1 and the second bit line BL1 both have an extension portion 3 facing the first gate G1.

[0116] Symmetrically arranged in a direction (e.g., the X direction).

[0117] Exemplarily, the extension portions 3 of the first bit line BL1 and the second bit line BL2 facing the first gate G1 have no or only little overlap with the storage gate G0 in the first direction (e.g., the Y direction). Thus, it is beneficial to ensure that the coupling capacitance between the first bit line BL1 and the storage gate G0 and the coupling capacitance between the second bit line BL2 and the storage gate G0 can have a small ratio.

[0118] In some embodiments, please refer to Figure 3 FIGS. (a), (b) and (d), the storage gate G0 includes: a first portion G01 extending along the second direction (e.g., the X direction), and a second portion G02 extending along the first direction (e.g., the Y direction) and integrally connected to the first portion G01. Among them, the size of the second portion G02 in the first direction (e.g., the Y direction) is larger than the size of the second semiconductor layer 22 in the first direction (e.g., the Y direction), and there is a gap between the second semiconductor layer 22 and the first portion G01 in the first direction (e.g., the Y direction).

[0119] Exemplarily, the size of the second semiconductor layer 22 in the second direction (e.g., the X direction) is greater than or equal to half of the size of the first portion G01 of the storage gate G0 in the second direction (e.g., the X direction).

[0120] Here, it can be understood that the second portion 02 and the first portion 01 of the storage gate G0 extend along different directions, and the second portion 02 and the first portion 01 of the storage gate G0 can be used as the corresponding boundaries of the accommodation area respectively, so as to facilitate the arrangement of the write transistor T1 within the accommodation area.

[0121] In some embodiments, the first word line WL1 and the second word line WL2 extend along a third direction (e.g., the Z direction perpendicular to the substrate 1), and the third direction (e.g., the Z direction) intersects both the second direction (e.g., the X direction) and the first direction (e.g., the Y direction); wherein, the first gate G1 and the first word line WL1 are of an integral structure; the second gate G2 and the second word line WL2 are of an integral structure.

[0122] In some embodiments, please continue to refer to Figure 3 , a plurality of memory cells U are arranged in columns along the first direction (e.g., the Y direction); wherein, a column of memory cells U share a first bit line BL1 and a second bit line BL2.

[0123] In some embodiments, please continue to refer to Figure 3 , the memory further includes: a first isolation structure 11 and a second isolation structure 16. The first isolation structure 11 is located between adjacent memory cells U in the first direction (e.g., the Y direction), and between the write transistor T2 and the storage gate G0 in any one of the memory cells U. The second isolation structure 16 is located between adjacent columns of memory cells U; wherein, the adjacent columns of memory cells U are symmetrically arranged with respect to the second isolation structure 16.

[0124] Some embodiments of the present disclosure also provide a manufacturing method of a semiconductor structure for manufacturing the semiconductor structure in the above - mentioned some embodiments. The semiconductor structure has the technical advantages, and the manufacturing method of the semiconductor structure also has all of them, which will not be elaborated here.

[0125] Please refer to Figure 4 , in some embodiments of the present disclosure, the manufacturing method of the memory includes the following steps.

[0126] S100, provide a substrate, and form a stacked structure on the substrate; the stacked structure includes multiple conductive material layers and multiple insulating material layers that are alternately stacked along the direction perpendicular to the substrate.

[0127] S200, etch the stacked structure along the direction perpendicular to the substrate to form a plurality of etched trenches and a plurality of first etched holes.

[0128] S300, respectively etch the corresponding sidewalls of the conductive material layers based on the etched trenches and the first etched holes, so that the remaining portions of the conductive material layers form storage gates and virtual write transistors, and simultaneously form a first accommodation area, a second accommodation area, and a third accommodation area connecting the first accommodation area and the second accommodation area.

[0129] S400, form a first gate dielectric layer and a first semiconductor layer in a first accommodation area, a second accommodation area, and a third accommodation area in sequence, form a first bit line contacting the first semiconductor layer in the first accommodation area, form a second bit line contacting the first semiconductor layer in the second accommodation area, and form a second gate dielectric layer at least covering the first semiconductor layer and a first gate covering the second gate dielectric layer in the third accommodation area. The storage transistor includes a first semiconductor layer, a first gate, and a storage gate. Form a first word line electrically connected to the first gate in a first etching hole.

[0130] S500, etch the stacked structure along a direction perpendicular to the substrate to form a second etching hole penetrating through each virtual write transistor.

[0131] S600, remove each virtual write transistor based on the second etching hole to form a fourth accommodation area.

[0132] S700, form a write transistor in the fourth accommodation area; the write transistor includes: a second gate and a second semiconductor layer; the second semiconductor layer is electrically connected to the storage gate and the second bit line respectively. Form a second word line electrically connected to the second gate in the second etching hole.

[0133] Please refer to Figure 5 , in some embodiments of the present disclosure, before step S200 etches the stacked structure along a direction perpendicular to the substrate to form a plurality of etching trenches and a plurality of first etching holes, the manufacturing method further includes the following steps.

[0134] S110, pattern the stacked structure to form a plurality of first isolation trenches; the first isolation trenches are used to define the formation positions of corresponding memory cells and isolate adjacent memory cells in a first direction. The memory cell includes a storage transistor and a write transistor. The first direction is parallel to the substrate.

[0135] S120, fill an insulating material in the first isolation trenches to form a first isolation structure.

[0136] Please refer to Figure 6 , in some embodiments of the present disclosure, step S400 forms a first gate dielectric layer and a first semiconductor layer in a first accommodation area, a second accommodation area, and a third accommodation area in sequence, forms a first bit line contacting the first semiconductor layer in the first accommodation area, forms a second bit line contacting the first semiconductor layer in the second accommodation area, forms a second gate dielectric layer at least covering the first semiconductor layer and a first gate covering the second gate dielectric layer in the third accommodation area, and forms a first word line electrically connected to the first gate in the first etching hole, including the following steps.

[0137] S410, form a first gate dielectric layer, a first semiconductor material layer, and a first sacrificial layer in sequence in the etching trenches, the first etching holes, and the etching area of the conductive material layer.

[0138] S420, Remove the first sacrificial layer and the first semiconductor material layer in the etching trenches and the first etching holes, such that the remaining portion of the first semiconductor material layer forms a first semiconductor layer, the remaining portion of the first sacrificial layer in the first accommodating region forms a virtual first bit line, the remaining portion of the first sacrificial layer in the second accommodating region forms a virtual second bit line, and the remaining portion of the first sacrificial layer in the third accommodating region forms a virtual first gate.

[0139] S430, Form a second sacrificial layer covering the first gate dielectric layer in the etching trenches and the first etching holes.

[0140] S440, Remove the second sacrificial layer in the etching trenches, the virtual first bit line, and the virtual second bit line.

[0141] S450, Form a first bit line covering the first semiconductor layer in the first accommodating region; form a second bit line covering the first semiconductor layer in the second accommodating region.

[0142] S460, Fill the etching trenches with an insulating material to form a second isolation structure.

[0143] S470, Remove the second sacrificial layer and the virtual first gate in the first etching hole.

[0144] S480, Sequentially form a second gate dielectric layer, a first gate, and a first word line electrically connected to the first gate in the first etching hole and the third accommodating region.

[0145] Please refer to Figure 7 , In some embodiments of the present disclosure, step S700 forms a write transistor in the fourth accommodating region and forms a second word line electrically connected to the second gate in the second etching hole, including the following steps.

[0146] S710, Sequentially form a second semiconductor material layer and a third sacrificial layer in the second etching hole and the fourth accommodating region.

[0147] S720, Remove the third sacrificial layer and the second semiconductor material layer in the second etching hole, such that the remaining portion of the second semiconductor material layer forms a second semiconductor layer.

[0148] S730, Remove the remaining third sacrificial layer.

[0149] S740, Sequentially form a third gate dielectric layer, a second gate, and a second word line electrically connected to the second gate in the second etching hole and the removal region of the remaining third sacrificial layer.

[0150] In the above embodiments of the present disclosure, unless otherwise clearly stated herein, the execution of each step in the method does not have a strict order limit. These steps may not necessarily be executed in the described order and may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily need to be executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0151] To more clearly illustrate the manufacturing method of the memory in some of the above embodiments, the following embodiments are described in detail by taking the Figure 5 shown method as an example, and please refer to Figures 8 to 19 for understanding.

[0152] In step S100, please refer to Figure 8 , provide a substrate 1, and form a stacked structure N on the substrate 1; the stacked structure N includes multiple conductive material layers L1 and multiple insulating material layers L2 alternately stacked along the direction perpendicular to the substrate 1 (for example, the Z direction).

[0153] Exemplarily, the substrate 1 can be made of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0154] Exemplarily, the number of stacked layers of the conductive material layer L1 and the insulating material layer L2 can be selected and set according to requirements. Moreover, the alternating stacking of the conductive material layer L1 and the insulating material layer L2 can start with the conductive material layer L1 and end with the insulating material layer L2. However, it is not limited thereto. For example, it can start with the insulating material layer L2 and end with the conductive material layer L1; or start with the conductive material layer L1 and end with the conductive material layer L1, etc.; all are allowed. Here, it can be understood that in the example starting with the conductive material layer L1, the conductive material layer L1 should be insulated from the substrate 1.

[0155] In some examples, please continue to refer to Figure 8, taking the conductive material layer L1 as the starting layer and the insulating material layer L2 as the ending layer for the film layers deposited on the substrate 1 as an example. Moreover, the film layers deposited on the substrate 1 may further include a protective layer covering the top insulating material layer L2, such as a hard mask layer YM.

[0156] Exemplarily, the hard mask layer YM includes, but is not limited to, a silicon nitride layer.

[0157] In steps S110 and S120, refer to Figure 9 , pattern the stacked structure N to form a plurality of first isolation trenches; the first isolation trenches are used to define the formation positions of the corresponding storage cells U and isolate the adjacent storage cells U in the first direction (e.g., the Y direction). Fill the insulating material in the first isolation trenches to form the first isolation structure 11.

[0158] Here, the first isolation structure 11 is obtained by filling the first isolation trenches, and the shape of the first isolation trenches is the same as that of the first isolation structure 11.

[0159] Exemplarily, the material of the first isolation structure 11 includes, but is not limited to, a high-k dielectric material. Wherein, k is the dielectric constant, which is used to measure the ability of the material to store charges. Usually, materials can be classified into low-k (low dielectric constant) materials and high-k (high dielectric constant) materials according to the value of k; generally, the k value of low-k materials is less than 3.0, and the k value of high-k materials is greater than 3.9. High-k dielectric materials include, for example: aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum pentoxide (Ta2O5), titanium oxide (TiO2), or strontium titanate (SrTiO3), etc.

[0160] Exemplarily, as shown in the (a) figure of Figure 9 , the first isolation structure 11 in any storage cell U includes an L-shaped first sub-isolation part 111 and a straight-shaped second sub-isolation part 112; wherein, the second sub-isolation part 112 is used to define the interval between the second semiconductor layer 11 in the write transistor T2 and the first part G01 in the storage gate G0; the long side of the first sub-isolation part 111 extends along the second direction (e.g., the X direction), which is used to define the isolation boundary between adjacent storage cells U in the first direction (e.g., the Y direction); the wide side of the first sub-isolation part 111 extends along the first direction (e.g., the Y direction), which is used to define the space on the side of the second part G02 of the storage gate G0 away from the write transistor T1, so as to effectively isolate the first bit line BL1 and the second part G02 of the storage gate G0.

[0161] In step S200, refer to Figure 10 , etch the stacked structure N along the direction perpendicular to the substrate (e.g., the Z direction) to form a plurality of etch trenches S and a plurality of first etch holes H1.

[0162] Exemplarily, a plurality of etching grooves S are arranged at intervals in a second direction (e.g., the X direction), and a plurality of first etching holes H1 are formed between every two adjacent etching grooves S; wherein, the etching grooves S extend in a first direction (e.g., the Y direction), the first etching holes H1 extend in the second direction (e.g., the X direction), and the plurality of first etching holes H1 are arranged at intervals in the first direction (e.g., the Y direction). The first direction (e.g., the Y direction) and the second direction (e.g., the X direction) intersect, for example, orthogonally.

[0163] Here, there is a gap between the first etching hole H1 and the adjacent etching groove S, and the dimension of this gap in the second direction (e.g., the X direction) can be used to define the line width of the subsequent corresponding first bit line BL1 or second bit line BL2.

[0164] In step S300, please refer to Figure 11 , respectively etch the corresponding sidewalls of the conductive material layer L1 based on the etching grooves S and the first etching holes H1, so that the remaining part of the conductive material layer L1 forms a storage gate G0 and a virtual write transistor T', and simultaneously form a first accommodation region R1, a second accommodation region R2, and a third accommodation region R3 connecting the first accommodation region R1 and the second accommodation region R2.

[0165] Here, the virtual write transistor T' means that other materials (e.g., the remaining part of the conductive material layer L1) are used to fill the to-be-formed region of the write transistor, and the to-be-formed region of the write transistor is reserved and occupied in advance, so as to be removed and replaced with a write transistor in the subsequent process.

[0166] In step S400, please refer to Figures 12 to 16 , sequentially form a first gate dielectric layer 12 and a first semiconductor layer 21 in the first accommodation region R1, the second accommodation region R2, and the third accommodation region R3, form a first bit line BL1 contacting the first semiconductor layer 21 in the first accommodation region R1, form a second bit line BL2 contacting the first semiconductor layer 21 in the second accommodation region R2, form a second gate dielectric layer 17 at least covering the first semiconductor layer 21 and a first gate G1 covering the second gate dielectric layer 17 in the third accommodation region R3, and form a first word line WL1 electrically connected to the first gate G1 in the first etching hole H1.

[0167] In some embodiments, step S400 includes but is not limited to steps S410 to S480.

[0168] In step S410, please refer to Figure 12 , sequentially form a first gate dielectric layer 12, a first semiconductor material layer 210, and a first sacrificial layer 13 in the etching region of the etching groove S, the first etching hole H1, and the conductive material layer L1.

[0169] Exemplarily, the first gate dielectric layer 12, the first semiconductor material layer 210, and the first sacrificial layer 13 are all formed by a deposition process. The deposition process includes but is not limited to an atomic layer deposition process.

[0170] Exemplarily, the material of the first gate dielectric layer 12 includes but is not limited to silicon oxide.

[0171] Exemplarily, the material of the first semiconductor material layer 210 includes but is not limited to metal oxide semiconductor, for example, it can be indium gallium zinc oxide (Indium Gallium Zinc Oxide, abbreviated as IGZO).

[0172] In step S420, please refer to Figure 13 , remove the first sacrificial layer 13 and the first semiconductor material layer 210 in the etching trench S and the first etching hole H, so that the remaining part of the first semiconductor material layer 210 forms the first semiconductor layer 21, and the remaining part of the first sacrificial layer 13 in the first accommodation area R1 forms the virtual first bit line BL1', the remaining part of the first sacrificial layer 13 in the second accommodation area R2 forms the virtual second bit line BL2', and the remaining part of the first sacrificial layer 13 in the third accommodation area R3 forms the virtual first gate G1'.

[0173] Here, the virtual first bit line BL1', the virtual second bit line BL2', and the virtual first gate G1' can be understood with reference to the aforementioned virtual write transistor T'; that is, the virtual structure means that other materials (such as the remaining part of the first sacrificial layer 13) are used to fill the area to be formed of the target structure, and the area to be formed of the target structure is reserved and occupied in advance, so as to be removed and replaced with the target structure in the subsequent process.

[0174] Exemplarily, the first sacrificial layer 13 and the first semiconductor material layer 210 in the etching trench S and the first etching hole H can be removed by a dry etching process with self-alignment.

[0175] In step S430, please continue to refer to Figure 13 , form a second sacrificial layer 14 covering the first gate dielectric layer 12 in the etching trench S and the first etching hole H1.

[0176] Here, it can be understood that the second sacrificial layer 14 also covers the sidewalls of the virtual first bit line BL1', the virtual second bit line BL2', and the virtual first gate G1' exposed in the etching trench S and the first etching hole H1.

[0177] Exemplarily, the materials of the second sacrificial layer 14 and the first sacrificial layer 13 are different.

[0178] In step S440, please refer to Figure 14 , remove the second sacrificial layer 14 and the virtual first bit line BL1', the virtual second bit line BL2' in the etching trench S.

[0179] In step S450, refer to Figure 14 and Figure 15 , a first bit line BL1 covering the first semiconductor layer 21 is formed in the first accommodation region R1; a second bit line BL2 covering the first semiconductor layer 21 is formed in the second accommodation region R2.

[0180] Exemplarily, as shown in Figure 14 , a bit line material layer 15 is filled in the removal regions of the virtual first bit line BL1' and the virtual second bit line BL2' and in the etching trench S. As shown in Figure 15 , the bit line material layer 15 in the etching trench S is removed to form a first bit line BL1 replacing the virtual first bit line BL1' in the first accommodation region R1, and a second bit line BL2 replacing the virtual second bit line BL2' in the second accommodation region R2.

[0181] Exemplarily, the bit line material layer 15 can be formed by a deposition process, including but not limited to an atomic layer deposition process.

[0182] Exemplarily, after filling to form the bit line material layer 15, a polishing process can be used to planarize the surface of the obtained structure.

[0183] In step S460, continue to refer to Figure 15 , an insulating material is filled in the etching trench S to form a second isolation structure 16.

[0184] Exemplarily, the second isolation structure 16 is made of the same material as the first isolation structure 11.

[0185] In steps S470 and S480, refer to Figure 16 , the second sacrificial layer 14 and the virtual first gate G1' in the first etching hole H1 are removed, and a second gate dielectric layer 17, a first gate G1, and a first word line WL1 electrically connected to the first gate G1 are sequentially formed in the first etching hole H1 and the third accommodation region R3.

[0186] Exemplarily, the first gate G1 and the first word line WL1 can be obtained by filling a conductive material in the first etching hole H1 and the third accommodation region R3. Thus, the first gate G1 and the first word line WL1 are an integral structure; in other words, the first gate G1 can be regarded as a component part of the first word line WL1 in the corresponding region.

[0187] In step S500, refer to Figure 17 , the stacked structure N is etched along the direction perpendicular to the substrate 1 (for example, the Z direction) to form a second etching hole H2 penetrating through each virtual write transistor T'.

[0188] In step S600, continue to refer to Figure 17, based on the second etching hole H2, each virtual write transistor T' is removed to form a fourth accommodating region R4.

[0189] Exemplarily, on opposite sides of the fourth accommodating region R4 in the first direction (e.g., the Y direction), the corresponding sidewalls of the storage gate G0 and the second bit line BL2 are respectively exposed.

[0190] In step S700, please refer to Figure 18 and Figure 19 , a write transistor T2 is formed in the fourth accommodating region R4; the write transistor T2 includes: a second gate G2 and a second semiconductor layer 22. The second semiconductor layer 22 is electrically connected to the storage gate G0 and the second bit line BL2 respectively. A second word line WL2 electrically connected to the second gate G2 is formed in the second etching hole H2.

[0191] Exemplarily, the second semiconductor layer 22 is insulated and surrounds the second gate G2 circumferentially. The first sidewall of the second semiconductor layer 22 close to the storage gate G0 and extending in the first direction (e.g., the Y direction) is electrically connected to the storage gate G0. The second sidewall of the second semiconductor layer 22 extending in the first direction (e.g., the Y direction) and opposite to its first sidewall is electrically connected to the second bit line BL2.

[0192] In some embodiments, step S700 may include steps S710 to S740.

[0193] In step S710, please refer to Figure 18 , a second semiconductor material layer 220 and a third sacrificial layer 18 are sequentially formed in the second etching hole H2 and the fourth accommodating region R4.

[0194] In step S720, please refer to Figure 19 , the third sacrificial layer 18 and the second semiconductor material layer 220 in the second etching hole H2 are removed, so that the remaining part of the second semiconductor material layer 220 forms the second semiconductor layer 22.

[0195] In step S730, please combine Figure 18 and Figure 19 to understand that the remaining third sacrificial layer 18 is removed.

[0196] Exemplarily, the third sacrificial layer 18 can be removed by a wet etching process.

[0197] In step S740, please refer to Figure 3 , a third gate dielectric layer 19, a second gate G2, and a second word line WL2 electrically connected to the second gate G2 are sequentially formed in the second etching hole H2 and the removal region of the remaining third sacrificial layer 18.

[0198] For example, the second gate G2 and the second word line WL2 can be obtained by filling the conductive material in the second etched hole H2 and the removed area of ​​the remaining third sacrificial layer 18. In this way, the second gate G2 and the second word line WL2 are an integrated structure; in other words, the second gate G2 can be regarded as a component of the second word line WL2 located in the corresponding area.

[0199] It should be added that, in some of the above embodiments, after the first sacrificial layer 13 , the second sacrificial layer 14 and the third sacrificial layer 18 are formed respectively, a grinding process may be used to planarize the surface of the obtained structure.

[0200] In the semiconductor structure provided by some embodiments of the present disclosure, the storage transistor T1 and the writing transistor T2 can participate in precharging and writing data at the same time to achieve threshold voltage compensation of the storage transistor T1 in the writing stage. Figure 20 , Figure 21 and Figure 22 Some possible data reading and writing driving methods when the semiconductor structure provided by the embodiments of the present disclosure is used as a memory are respectively shown.

[0201] In some embodiments, see Figures 20 to 22 , the data read and write cycle t of the storage unit U includes the write cycle t W , read cycle t R and standby phase (e.g., the first standby phase t D1 and the second standby stage t D2 ).

[0202] In some embodiments, Figure 20 As shown in the figure, the write cycle t W Including the pre-charge stage t W1 and data writing phase t W2 .

[0203] In the pre-charge stage t W1 , the first bit line BL1 provides the first reference voltage V1 to the storage transistor T1, and the second bit line BL2 provides the first reference voltage V1 to the storage transistor T1 and the write transistor T2 at the same time; the write transistor T2 is turned on to precharge the storage node SN. Among them, the maximum data voltage corresponding to the data stored in the storage unit U is the threshold voltage V th The sum of the first reference voltage V1 is a reference voltage, and the first reference voltage V1 is greater than the reference voltage. Here, after the precharge of the storage node SN is completed, the voltage of the storage node SN is the first reference voltage V1.

[0204] Exemplarily, the data that the storage unit U can store includes data "0" and data "1", where the data voltage Vdata1 corresponding to data "1" is greater than the data voltage Vdata0 corresponding to data "0". Based on this, the data voltage Vdata1 corresponding to data "1" can be the maximum data voltage of the data that the storage unit U can store. Vice versa. Based on this, when the data voltage Vdata1 corresponding to data "1" is the maximum data voltage of the data that the storage unit U can store, the reference voltage is Vdata1 + Vth, and the first reference voltage is greater than Vdata1 + Vth. Moreover, the difference between the first reference voltage and the reference voltage can be reasonably set according to requirements.

[0205] Here, the reference voltage is defined as the sum of the maximum data voltage and the threshold voltage Vth of the storage transistor T1 for the convenience of description, and it is only used to indicate the value range of the first reference voltage when the reference voltage is used as the reference standard.

[0206] In some embodiments, the storage transistor T1 adopts a double-gate structure, including a first gate G1 and a storage gate G0. The first gate G1 is connected to the first word line WL1 and serves as the control gate of the storage transistor T1 to control the conduction and cutoff of the storage transistor T1. The storage gate G0 is connected to the write transistor T2 and serves as a floating gate to capture charges to store data. Moreover, the threshold voltage V th of the storage transistor T1 refers to the threshold voltage Vth corresponding to the storage gate G0 in the storage transistor T1 when the first word line WL1 provides a preset voltage to the first gate G1.

[0207] Exemplarily, the storage transistor T1 is an N-type transistor, and the preset voltage provided by the first word line WL1 to the first gate G1 is a fixed high-level voltage. However, it is not limited thereto. For example, if the storage transistor T1 adopts a P-type transistor, the voltage signals of the first gate G1 and other components connected to the storage transistor T1 can be adaptively adjusted to realize data reading and writing, which are also allowed. Similarly, it is also allowed for the write transistor T2 to adopt an N-type transistor or a P-type transistor.

[0208] In addition, the second gate G2 of the write transistor T2 is connected to the second word line WL2 and can be turned on or off in response to the control signal provided by the second word line WL2. For the convenience of description, in the following some embodiments, the storage transistor T1 and the write transistor T2 are taken as N-type transistors as examples for description.

[0209] In some embodiments, please continue to refer to Figure 20 that in the pre-charge stage t W1 the first word line WL1 provides a first write control voltage V to the first gate G1 of the storage transistor T1 CW1。The second word line WL2 supplies a second write control voltage V to the second gate G2 of the write transistor T2 CW2 。At this time, the first bit line BL1 supplies a first reference voltage V1 to the first pole of the storage transistor T1, and the second bit line BL2 supplies a first reference voltage V1 to the second pole of the storage transistor T1. The storage transistor T1 is in a non-conducting state. Exemplarily, the first write control voltage V CW1 and the second write control voltage V CW2 are both high-level voltages.

[0210] Exemplarily, the first write control voltage V CW1 is less than the second write control voltage V CW2 , and the first write control voltage V CW1 can be reasonably set according to requirements.

[0211] During the data writing stage t W2 , in response to a write command, the second bit line BL2 floats, and the first bit line BL1 supplies a data voltage Vdata to the storage transistor T1. The storage transistor T1 conducts, and the storage node SN discharges to a stable state to write the data data corresponding to the data voltage Vdata.

[0212] Here, the storage node SN discharging to a stable state means that the voltage change of the storage node SN tends to 0. After the storage node SN discharges to a stable state, the voltage of the storage node SN is Vdata + Vth (including approximately equal to).

[0213] And, as shown in Figure 20 , during the data writing stage t W2 , the first word line WL1 continuously supplies the first write control voltage V CW1 to the first gate G1 of the storage transistor T1. The second word line WL2 continuously supplies the second write control voltage V CW2 to the second gate G2 of the write transistor T2. At this time, the first bit line BL1 supplies the data voltage Vdata to the first pole of the storage transistor T1, the second bit line BL2 floats, and the storage transistor T1 is in a conducting state.

[0214] In addition, the data voltage Vdata supplied by the first bit line BL1 is related to the data to be written. For example, when the data to be written is the data "1", the data voltage supplied by the first bit line BL1 during the data writing stage t W2 is Vdata1. Or, for another example, when the data to be written is the data "0", the data voltage supplied by the first bit line BL1 during the data writing stage t W2 is Vdata0.

[0215] In some embodiments, referring to Figure 21 , the write cycle t WIt further includes: during the data writing stage t W2 and the subsequent data holding stage t W3 .

[0216] During the data holding stage t W3 , the voltage of the first bit line BL1 is pulled up to the first reference voltage V1, and after the voltage of the first bit line BL1 reaches the first reference voltage V1, the write transistor T2 is turned off first, and then the voltage of the second bit line BL2 is pulled up to the first reference voltage V1.

[0217] In addition, by way of example, please refer to Figure 21 , after turning off the write transistor T2, a first turn-off control voltage V is applied to the storage transistor T1 CG1 .

[0218] In the embodiment of the present disclosure, during the data holding stage t after writing the data data to the storage node SN W3 , the voltage of the first bit line BL1 can be pulled up to the first reference voltage V1, and the storage transistor T1 is turned off due to the voltage difference between the first pole S / D11 of the storage transistor T1 and the storage node SN. At this time, the write transistor T2 connecting the storage node SN and the second bit line BL2 is in the conducting state. Based on the coupling effect between the first bit line BL1 and the second bit line BL2, the voltage of the storage node SN can be kept stable (for example, kept at Vdata + Vth). Then, the write transistor T2 is turned off first, and then the first reference voltage V1 is provided to both the storage transistor T1 and the write transistor T2 through the second bit line BL2, so that the data data can be retained at the storage node SN (the voltage of the storage node SN includes Vdata + Vth).

[0219] It can be understood that during the data reading stage t R , the first bit line BL1 reads the data data in response to whether the storage transistor T1 is conducting, which can be manifested as reading the data data through the change of the current or voltage transmitted by the first bit line BL1. Therefore, during the data holding stage t W3 , after turning off the write transistor T2, the first word line WL1 can also be used to apply the first turn-off control voltage V to the storage transistor T1 CG1 . This can not only further ensure the off state of the storage transistor T1 to avoid leakage, but also facilitate applying the read control voltage V to the storage transistor T1 through the first word line WL1 subsequently CR to realize the read scan control of the data data.

[0220] Here, please refer to Figure 21 , during the data holding stage t W3, after turning off the write transistor T2, first pull up the voltage of the second bit line BL2 to the first reference voltage V1, or first apply a first turn-off control voltage V to the storage transistor T1 through the first word line WL1 CG1 , or both at the same time are also allowed.

[0221] Moreover, after turning off the write transistor T2, when the first word line WL1 applies a first turn-off control voltage V to the storage transistor T1 CG1 , the voltage of the storage node SN will change accordingly. For example, when the first turn-off control voltage V CG1 is a low-level voltage, if the data written to the storage node SN is data "1", the voltage of the storage node SN can correspondingly change to: Vdata1 + Vth - △V; if the data written to the storage node SN is data "0", the voltage of the storage node SN can correspondingly change to: Vdata0 + Vth - △V. Correspondingly, in the subsequent data reading stage t R , when the first word line WL1 applies a read control voltage VCR to the storage transistor T1, the voltage of the storage node SN will change accordingly. For example, when the read control voltage VCR is a high-level voltage, if the data written to the storage node SN is data "1", the voltage of the storage node SN can correspondingly change to: Vdata1 + Vth - △V + △V'; if the data written to the storage node SN is data "0", the voltage of the storage node SN can correspondingly change to: Vdata0 + Vth - △V + △V'.

[0222] In the embodiments of the present disclosure, although the voltage of the storage node SN changes after the first word line WL1 applies a first turn-off control voltage V CG1 or a read control voltage VCR to the storage transistor T1, the voltage of the storage node SN always includes the data voltage Vdata corresponding to the written data and the threshold voltage Vth of the storage transistor T1, and corresponding to different data voltages (such as Vdata1 and Vdata0), the voltage change of the storage node SN is the same, which does not affect the accurate reading of data in the data reading stage t R .

[0223] In some other examples, please refer to Figure 22 , in the data holding stage t W3 , first pull up the voltage of the first bit line BL1 to the first reference voltage V1, turn off the storage transistor T1; then turn off the write transistor T2, and pull up the voltage of the second bit line BL2 to the first reference voltage V1.

[0224] Here, it can be understood that the turn-off of the storage transistor T1 can be achieved by applying a first turn-off control voltage V to the first gate G1 through the first word line WL1 CG1Control implementation. Turning off the write transistor T2 can be achieved by applying a second turn-off control voltage V to the second gate G2 through the second word line WL2 CG2 Control implementation.

[0225] Exemplarily, the first turn-off control voltage V CG1 and the second turn-off control voltage V CG2 are the same.

[0226] Exemplarily, both the storage transistor T1 and the write transistor T2 are N-type transistors. Correspondingly, the first turn-off control voltage V CG1 and the second turn-off control voltage V CG2 are both low-level voltages.

[0227] In the embodiments of the present disclosure, after writing data data to the storage node SN, first turn off the storage transistor T1, and then pull up the voltage of the first bit line BL1 to the first reference voltage V1. At this time, the write transistor T2 connecting the storage node SN and the second bit line BL2 remains in the conducting state, and the voltage of the storage node SN remains stable (for example, remains at Vdata + Vth). Then, turn off the write transistor T2, and then provide the first reference voltage to both the storage transistor T1 and the write transistor T2 through the second bit line BL2, which can avoid the generation of leakage current in the write transistor T2, thereby stabilizing the data data at the storage node SN (for example, the voltage of the storage node SN is Vdata + Vth).

[0228] In some embodiments, as Figure 20 , Figure 21 and Figure 22 shown, the read cycle t R includes: a data reading stage t R .

[0229] In the data reading stage t R , in response to a read command, apply a read control voltage V CR to the storage transistor T1, and provide a second reference voltage V2 to both the storage transistor T1 and the write transistor T2 through the second bit line BL2; wherein, the first bit line BL1 is further configured to: read data in response to whether the storage transistor is conducting.

[0230] Exemplarily, the second reference voltage V2 is less than the first reference voltage V1.

[0231] Exemplarily, the second reference voltage V2 is greater than the minimum data voltage that the storage cell U can store data, and less than the maximum data voltage that the storage cell U can store data. For example, Vdata1 > V2 > Vdata0.

[0232] Here, it can be understood that in the actual application of the data read / write circuit, considering the coupling effect between the first bit line BL1 and the second bit line BL2, the second reference voltage V2 can be greater than the sum of the minimum data voltage and the voltage variable (vector) caused by the coupling effect, and less than the sum of the maximum data voltage and the voltage variable (vector) caused by the coupling effect.

[0233] Exemplarily, in the data read phase t R , the first word line WL1 applies a read control voltage V CR to the first gate G1 of the memory transistor T1. CR The read control voltage V W and the first write control voltage V CW1 provided by the first word line WL1 during the write cycle t

[0234] Exemplarily, the read control voltage V CR and the first write control voltage V CW1 are the same.

[0235] Exemplarily, the read control voltage V CR is higher than the first write control voltage V CW1 .

[0236] Here, the read control voltage V CR applied to the memory transistor T1 in response to a read command means that: through the appropriate voltage applied by the first word line WL1, it can ensure that the memory transistor T1 is in different states corresponding to different data stored at the storage node SN.

[0237] Exemplarily, please refer to Figure 20 , Figure 21 , Figure 22 and Figure 23 to understand that the data written to the storage node SN includes "1" or "0". In the data read phase t R , after applying the read control voltage V CR to the memory transistor T1:

[0238] If the data stored at the storage node SN is "1", then the gate-source voltage V GS (i.e., the voltage difference between the storage gate G0 and its second pole S / D12) of the memory transistor T1 is large and greater than the threshold voltage Vth of the memory transistor T1, and the memory transistor T1 is in the on state.

[0239] If the data stored at the storage node SN is "0", then the gate-source voltage V GS (i.e., the voltage difference between the storage gate G0 and its second pole S / D12) of the memory transistor T1 is small and less than the threshold voltage Vth of the memory transistor T1, and the memory transistor T1 is in the off state.

[0240] To more clearly illustrate the data reading process in stage t R of the data reading process, the following uses Figure 20 and Figure 22 to give an example of the data reading process shown, and the data reading process shown in Figure 21 can be understood adaptively.

[0241] In data reading stage t R , if the voltage of storage gate G0 in storage transistor T1 is the voltage after writing data "1" to storage node SN, i.e., = Vdata1 + Vth. The voltage of the second pole S / D12 in storage transistor T1 is the second reference voltage V2 provided by the second bit line BL2. The gate-source voltage V of storage transistor T1 GS = Vdata1 + Vth - V2. Since V2 is less than Vdata1, the gate-source voltage V of storage transistor T1 GS is greater than Vth.

[0242] In data reading stage t R , if the voltage of storage gate G0 in storage transistor T1 is the voltage after writing data "0" to storage node SN, i.e., = Vdata0 + Vth. The voltage of the second pole S / D12 in storage transistor T1 is the second reference voltage V2 provided by the second bit line BL2. The gate-source voltage V of storage transistor T1 GS = Vdata0 + Vth - V2. Since V2 is greater than Vdata0, the gate-source voltage V of storage transistor T1 GS is less than Vth.

[0243] In addition, in the way of the matching data read / write circuit reading data, the way of the first bit line BL1 reading data in response to whether the storage transistor is turned on can be expressed as: current sensing reading or voltage sensing reading.

[0244] It is worth mentioning that in some embodiments, please refer to Figure 20 , Figure 21 and Figure 22 , the data read / write cycle t further includes: a standby stage (i.e., the Standby stage) located before the pre-charge stage t W1 and / or before the data reading stage t R .

[0245] Exemplarily, as shown in Figure 21 , the data read / write cycle t further includes: a data holding stage t W2 after the data writing stage t W3 . The data reading stage t R is located in the data holding stage t W3After that, the standby stage includes: a first standby stage t before the pre-charging stage t W1 and a second standby stage t after the data holding stage t D1 and before the data reading stage t W3 . Correspondingly, during the standby stage (including the first standby stage t R and the second standby stage t D2 ), the storage transistor T1 and the write transistor T2 are in the off state. The first bit line BL1 provides the first reference voltage V1 to the storage transistor T1, and the second bit line BL2 provides the first reference voltage V1 to both the storage transistor T1 and the write transistor T2 simultaneously. D1 D2

[0246] In the embodiments of the present disclosure, during the standby stage, the first reference voltage V1 can be provided to the first pole of the storage transistor T1 by the first bit line BL1, and the first reference voltage V1 can be provided to the second pole of the storage transistor T2 by the second bit line BL2, so as to ensure that there is no large voltage difference between the first pole and the second pole of the storage transistor T1, effectively reducing the risk of leakage current generation. Especially when the first reference voltage V1 is a high-level voltage.

[0247]

[0248] In addition, it can be understood that the first standby stage t D1 and the second standby stage t D2 mentioned in some of the above embodiments are independent of the write cycle t D1 and the second standby stage t w is independent of the read cycle t D2 . In some examples, based on the first standby stage t R and the second standby stage t D1 , the voltage signals provided by the first bit line BL1, the second bit line BL2, the first word line WL1, and the second word line WL2 are the same. The first standby stage t D2 and the second standby stage t D1 can also be regarded as the same standby stage, and different read and write cycles are entered in response to different received commands. For example, when a write command is received, the write cycle is entered correspondingly, or when a read command is received, the read cycle is entered correspondingly. D2

[0248] It can be understood that during the first standby stage t D1 and the second standby stage t D2 , the first word line WL1 applies the first turn-off control voltage V CG1 to the first gate G1 of the storage transistor T1, and the second word line WL2 applies the second turn-off control voltage V CG2 to the second gate G2 of the write transistor T2.

[0249] Exemplarily, the first turn-off control voltage V CG1 and the second turn-off control voltage V CG2 are the same.

[0250] Exemplarily, both the storage transistor T1 and the write transistor T2 are N-type transistors. The first turn-off control voltage V CG1 and the second turn-off control voltage V CG2 are both low-level voltages.

[0251] In an embodiment of the present disclosure, the storage unit U is configured to store data, including the connected storage transistor T1 and write transistor T2. In the embodiment of the present disclosure, by connecting the first bit line BL1 to the storage transistor T1 in the storage unit U, and connecting the second bit line BL2 to the storage transistor T1 and the write transistor T2 in the storage unit U, during the pre-charge stage t W1 , after the first bit line BL1 provides the first reference voltage V1 to the storage transistor T1, the second bit line BL2 provides the first reference voltage V1 to both the storage transistor T1 and the write transistor T2, and the write transistor T2 is turned on, the storage node SN of the storage unit U is pre-charged. Based on the fact that the first reference voltage V1 is greater than the reference voltage (i.e., the sum of the maximum data voltage corresponding to the data that the storage unit U can store and the threshold voltage of the storage transistor T1, for example, Vdata1 + Vth), that is, V1 > (Vdata1 + Vth), after the storage node SN of the storage unit U is pre-charged, the voltage of the storage node SN (= or ≈ V1) can be greater than the reference voltage, for example, greater than (Vdata1 + Vth). Thus, during the data writing stage t W2 , in response to the write command, after the second bit line BL2 is floated and the first bit line BL1 provides the data voltage Vdata to the storage transistor T1, the storage transistor T1 is turned on, and the storage node SN can be naturally discharged to a stable state to write the data data corresponding to the foregoing data voltage Vdata.

[0252] In the embodiment of the present disclosure, since the voltage of the storage node SN after pre-charging is greater than the reference voltage, for example, greater than (Vdata1 + Vth), that is: the voltage of the storage node SN is not only greater than the data voltage Vdata provided by the first bit line BL1, but also the difference between the voltage of the storage node SN and the foregoing data voltage Vdata is greater than the threshold voltage Vth of the storage transistor T1. Therefore, after the storage node SN is discharged to a stable state, the voltage of the storage node SN corresponds to the sum of the foregoing data voltage Vdata and the threshold voltage Vth of the storage transistor T1 (i.e., = or ≈ Vdata + Vth), so that the threshold compensation voltage of the storage transistor T1 (= or ≈ Vth) can be retained at the storage node SN while writing the data data.

[0253] On this basis, after writing data data, some embodiments of the present disclosure can turn off the storage transistor T1 and the write transistor T2 (see the relevant description in the data retention stage t W3 . And, in the second standby stage t D2 , the first reference voltage V1 can be provided to the storage transistor T1 by the first bit line BL1 and the second bit line BL2 respectively, and the first reference voltage V1 can be provided to the write transistor T2 by the second bit line BL2. At this time, both the storage transistor T1 and the write transistor T2 are in the off state, and the voltage of the storage node SN can be kept stable. After that, in the data reading stage t R , in response to a read command, a read control voltage V CR can be applied to the storage transistor T1, and the second reference voltage V2 can be provided to both the storage transistor T1 and the write transistor T2 by the second bit line BL2. When the first reference voltage V1 is provided by the first bit line BL1, the second reference voltage V2 is provided by the second bit line BL1, and the read control voltage V CR is applied to the storage transistor T1, the magnitude of the voltage stored in the storage node SN can affect the conduction or non-conduction between the first and second poles of the storage transistor T1, so that the first bit line BL1 reads data in response to whether the storage transistor T1 is conducting. Since the voltage stored in the storage node SN includes the threshold compensation voltage of the storage transistor T1 (= or ≈ Vth), the data read by the first bit line BL1 in response to whether the storage transistor T1 is conducting can be unaffected by the threshold voltage Vth of the storage transistor T1, ensuring the accuracy of the stored data data reading, thereby further improving the memory performance.

[0254] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a photocopier, a network device, a household appliance, an instrument, a mobile phone, a computer, and other devices with data storage functions. The electronic device may include a housing, a circuit board disposed in the housing, and a semiconductor structure integrated on the circuit board. The semiconductor structure can refer to the relevant description in the above-mentioned some embodiments. Other necessary elements or components may also be included in the electronic device, and the embodiments of the present disclosure do not limit this.

[0255] In some embodiments, the semiconductor structure is a memory, and the memory can be coupled to an external control device such as a processor or an actuator. The processor is coupled to the memory, and the processor can control the read and write operations of the memory.

[0256] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0257] The embodiments described above merely represent several implementation manners of the present disclosure. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several variations and improvements can still be made, and these all fall within the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising a substrate, and a plurality of memory cells, a first word line, a first bit line, a second word line, and a second bit line disposed on the substrate; The memory cell includes: A memory transistor, including: a first gate electrically connected to the first word line; a first semiconductor layer; a storage gate located on a side of the first semiconductor layer away from the first gate; A write transistor, including: a second gate electrically connected to the second word line; a second semiconductor layer electrically connected to the storage gate and the second bit line respectively; At least a part of the first semiconductor layer surrounds the first gate, one side of the first semiconductor layer in a first direction is electrically connected to the storage gate, and both sides of the first semiconductor layer in a second direction are electrically connected to the first bit line and the second bit line respectively; the first direction and the second direction intersect and are parallel to the substrate.

2. The semiconductor structure according to claim 1, wherein At least a part of the second semiconductor layer surrounds the second gate.

3. The semiconductor structure according to claim 2, wherein A first side wall of the second semiconductor layer that is close to the storage gate and extends along the first direction is electrically connected to the storage gate; a second side wall of the second semiconductor layer that extends along the first direction and is opposite to the first side wall is electrically connected to the second bit line.

4. The semiconductor structure according to claim 1, characterized in that, The first semiconductor layer covers a surface of the first bit line close to the substrate and a surface away from the substrate, and a surface of the second bit line close to the substrate and a surface away from the substrate.

5. The semiconductor structure according to claim 4, wherein The second semiconductor layer is electrically connected to the second bit line through the first semiconductor layer.

6. The semiconductor structure according to claim 4, wherein The second semiconductor layer is in contact with a surface of the first semiconductor layer close to the substrate, a surface away from the substrate, and a side wall close to the second gate.

7. The semiconductor structure according to claim 1, wherein The first bit line and the second bit line extend along the first direction respectively, and are spaced apart in the second direction; wherein, the storage gate is located between the first bit line and the second bit line, and is insulated from both the first bit line and the second bit line.

8. The semiconductor structure according to claim 7, wherein Both the first bit line and the second bit line have protruding portions facing the first gate.

9. The semiconductor structure according to claim 7, wherein, The storage gate includes: a first part extending along the second direction, and a second part extending along the first direction and integrally connected to the first part; wherein, A dimension of the second part in the first direction is greater than a dimension of the second semiconductor layer in the first direction, and there is a gap between the second semiconductor layer and the first part in the first direction.

10. The semiconductor structure according to claim 9, characterized in that, A dimension of the second semiconductor layer in the second direction is greater than or equal to one half of a dimension of the first part in the second direction.

11. The semiconductor structure according to claim 1, wherein The first word line and the second word line extend along a third direction respectively, and the third direction intersects both the second direction and the first direction; wherein, The first gate and the first word line are of an integral structure; The second gate and the second word line are of an integral structure.

12. The semiconductor structure according to claim 1, wherein The data read / write timing of the semiconductor device includes: a pre-charge stage, a data write stage, and a data read stage; The first bit line is configured to: provide a first reference voltage to the storage transistor during the pre-charging stage, write data to the storage transistor during the data writing stage, and read data in response to the conduction state of the storage transistor during the data reading stage; the sum of the maximum data voltage corresponding to the data and the threshold voltage of the storage transistor is the reference voltage; the first reference voltage is greater than the reference voltage.

13. The semiconductor structure according to claim 12, wherein The second bit line is configured to: provide the first reference voltage to both the storage transistor and the write transistor during the pre-charging stage, float during the data writing stage, and provide a second reference voltage to both the storage transistor and the write transistor during the data reading stage; wherein, the first reference voltage is greater than the second reference voltage.

14. The semiconductor structure according to claim 13, wherein A plurality of the storage units are arranged in columns along a first direction; wherein, one column of the storage units shares one first bit line and one second bit line.

15. The semiconductor structure according to claim 14, characterized in that, Further comprising: A first isolation structure, located between the storage units adjacent in the first direction, and between the write transistor and the storage gate in any one of the storage units; A second isolation structure, located between adjacent columns of the storage units; wherein, adjacent columns of the storage units are symmetrically arranged with respect to the second isolation structure.

16. A manufacturing method of a semiconductor structure, characterized in that, Comprising: Providing a substrate, and forming a stacked structure on the substrate; the stacked structure includes a plurality of conductive material layers and a plurality of insulating material layers alternately stacked in a direction perpendicular to the substrate; Etching the stacked structure in a direction perpendicular to the substrate to form a plurality of etching trenches and a plurality of first etching holes; Based on the etching trenches and the first etching holes, respectively etching the conductive material layers, so that the remaining portions of the conductive material layers form a storage gate and a dummy write transistor, and synchronously forming a first accommodation region, a second accommodation region, and a third accommodation region; Sequentially forming a first gate dielectric layer and a first semiconductor layer in the first accommodation region, the second accommodation region, and the third accommodation region, forming a first bit line contacting the first semiconductor layer in the first accommodation region, forming a second bit line contacting the first semiconductor layer in the second accommodation region, forming a second gate dielectric layer at least covering the first semiconductor layer and a first gate covering the second gate dielectric layer in the third accommodation region; the storage transistor includes the first semiconductor layer, the first gate, and the storage gate; Forming a first word line electrically connected to the first gate in the first etching hole; Etching the stacked structure in a direction perpendicular to the substrate to form a second etching hole penetrating through each of the dummy write transistors; Removing each of the dummy write transistors based on the second etching hole to form a fourth accommodation region; Forming a write transistor in the fourth accommodation region; the write transistor includes: a second gate and a second semiconductor layer; the second semiconductor layer is electrically connected to the storage gate and the second bit line respectively; Forming a second word line electrically connected to the second gate in the second etching hole.

17. The manufacturing method of the semiconductor structure according to claim 16, wherein, Before etching the stacked structure along the direction perpendicular to the substrate to form a plurality of etching trenches and a plurality of first etching holes, the manufacturing method further includes: Patterning the stacked structure to form a plurality of first isolation trenches; the first isolation trenches are used to define the formation positions of corresponding memory cells and isolate the memory cells adjacent in a first direction; the memory cells include the memory transistor and the write transistor; the first direction is parallel to the substrate; Filling an insulating material in the first isolation trenches to form a first isolation structure.

18. The manufacturing method of the semiconductor structure as described in claim 16, characterized in that, Forming a first gate dielectric layer and a first semiconductor layer in the first accommodation region, the second accommodation region, and the third accommodation region in sequence, forming a first bit line contacting the first semiconductor layer in the first accommodation region, forming a second bit line contacting the first semiconductor layer in the second accommodation region, forming a second gate dielectric layer at least covering the first semiconductor layer and a first gate electrode covering the second gate dielectric layer in the third accommodation region, and forming a first word line electrically connected to the first gate electrode in the first etching hole, includes: Forming a first gate dielectric layer, a first semiconductor material layer, and a first sacrificial layer in sequence in the etching trenches, the first etching holes, and the etching regions of the conductive material layer; Removing the first sacrificial layer and the first semiconductor material layer in the etching trenches and the first etching holes, so that the remaining portion of the first semiconductor material layer forms the first semiconductor layer, the remaining portion of the first sacrificial layer in the first accommodation region forms a virtual first bit line, the remaining portion of the first sacrificial layer in the second accommodation region forms a virtual second bit line, and the remaining portion of the first sacrificial layer in the third accommodation region forms a virtual first gate electrode; Forming a second sacrificial layer covering the first gate dielectric layer in the etching trenches and the first etching holes; Removing the second sacrificial layer in the etching trenches and the virtual first bit line and the virtual second bit line; Forming a first bit line covering the first semiconductor layer in the first accommodation region; Forming a second bit line covering the first semiconductor layer in the second accommodation region; Filling an insulating material in the etching trenches to form a second isolation structure; Removing the second sacrificial layer and the virtual first gate electrode in the first etching hole; Forming the second gate dielectric layer, the first gate electrode, and the first word line electrically connected to the first gate electrode in the first etching hole and the third accommodation region in sequence.

19. The method for manufacturing a semiconductor structure according to claim 16, wherein, Forming a write transistor in the fourth accommodation region and forming a second word line electrically connected to the second gate electrode in the second etching hole, includes: Forming a second semiconductor material layer and a third sacrificial layer in sequence in the second etching hole and the fourth accommodation region; Removing the third sacrificial layer and the second semiconductor material layer in the second etching hole, so that the remaining portion of the second semiconductor material layer forms the second semiconductor layer; Removing the remaining third sacrificial layer; A third gate dielectric layer, the second gate, and the second word line electrically connected to the second gate are sequentially formed in the second etching hole and the removal region where the third sacrificial layer remains.

20. An electronic device, characterized in that, Comprising: The semiconductor structure according to any one of claims 1 to 15.

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