Memory, preparation method thereof and electronic equipment

Abstract

The invention discloses a memory, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. The method comprises the following steps: forming a first groove which penetrates through a laminated structure and extends along a column direction in the laminated structure; the row direction and the column direction intersect and are both parallel to the substrate; word line through holes penetrating through the laminated structure are formed in the laminated structure, and the word line through holes and the first grooves are arranged at intervals in the row direction; laterally etching the sacrificial layer based on the first groove to form a first filling groove; a bit line structure, a storage transistor and the storage capacitor which are sequentially arranged in the row direction are formed in the first filling groove, and a word line structure is formed in the word line through hole; wherein the bit line structure extends along the column direction, the storage transistor is respectively connected with the bit line structure and the storage capacitor, and the first filling groove is communicated with the word line through hole and the first groove. And the performance of the memory is improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and particularly to a memory, a method for manufacturing the same, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly. As a result, any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0004] Embodiments of the present disclosure provide a memory, a method for manufacturing the same, and an electronic device, which can reduce the cost of the memory and optimize the stress and etching morphology of the memory device.

[0005] The present disclosure provides a method for manufacturing a memory. The memory includes a word line structure, a bit line structure, and memory cells stacked longitudinally perpendicular to a substrate. The memory cells include memory transistors and memory capacitors arranged in a row direction. The manufacturing method includes: The memory includes a word line structure, a bit line structure, and memory cells stacked longitudinally perpendicular to a substrate. The memory cells include memory transistors and memory capacitors arranged in a row direction. The manufacturing method includes:

[0006] Providing a substrate, and forming a stacked structure on the substrate, the stacked structure including an insulating layer and a sacrificial layer alternately stacked along the longitudinal direction;

[0007] Forming a first trench in the stacked structure, the first trench penetrating the stacked structure and extending along a column direction; the row direction and the column direction intersect and are both parallel to the substrate;

[0008] Forming a word line through hole penetrating the stacked structure in the stacked structure, the word line through hole being spaced from the first trench in the row direction;

[0009] Laterally etching the sacrificial layer based on the first trench to form a first filling groove; forming the bit line structure, the memory transistors, and the memory capacitors arranged in sequence along the row direction in the first filling groove, and forming the word line structure in the word line through hole;

[0010] Wherein, the bit line structure extends along the column direction, the memory transistors are respectively connected to the bit line structure and the memory capacitors, and the first filling trench communicates with the word line through hole and the first trench.

[0011] In some embodiments, a word line via is formed before laterally etching the sacrificial layer, and then the sacrificial layer is laterally etched based on the first trench and the word line via to form the first filling groove.

[0012] In some embodiments, forming the bit line structure, the memory transistor, and the memory capacitor arranged in sequence along the row direction in the first filling groove includes:

[0013] Forming a first conductive material layer, a dielectric material layer, and a second conductive material layer on the inner walls of the word line via and the first filling groove in sequence;

[0014] Removing the second conductive material layer, the dielectric material layer, and the first conductive material layer in the word line via, and the second conductive material layer in a partial area of the first filling groove close to the word line via, to form a second filling groove surrounding the word line via, and obtaining a bit line structure and a first electrode composed of the remaining second conductive material layer;

[0015] Removing the dielectric material layer and the first conductive material layer on the side wall of the second filling groove, and obtaining a capacitor dielectric layer composed of the dielectric material layer surrounding the first electrode, and a second electrode composed of the first conductive material layer surrounding the capacitor dielectric layer;

[0016] Forming the memory transistor in the second filling groove;

[0017] Wherein, the memory capacitor includes the first electrode, the second electrode, and the capacitor dielectric layer.

[0018] In some embodiments, the first filling groove includes a bit line filling groove extending along the column direction. Forming the first conductive material layer, the dielectric material layer, and the second conductive material layer on the inner walls of the word line via and the first filling groove in sequence further includes:

[0019] Forming the first conductive material layer, the dielectric material layer, and the second conductive material layer on the inner wall of the first trench in sequence, and filling the bit line filling groove with the second conductive material layer;

[0020] The manufacturing method further includes:

[0021] Etching and removing the second conductive material layer, the dielectric material layer, and the first conductive material layer in the first trench;

[0022] Filling and forming a bit line isolation structure in the first trench.

[0023] In some embodiments, forming the bit line structure, the storage transistor, and the storage capacitor arranged in sequence along the row direction in the first filling groove, and forming the word line structure in the word line through hole, includes:

[0024] Forming a first conductive material layer, a dielectric material layer, and a second conductive material layer on the inner walls of the first trench and the first filling groove in sequence;

[0025] Removing the second conductive material layer, the dielectric material layer, and the first conductive material layer in the first trench, and the second conductive material layer in a partial area of the first filling groove close to the first trench, to obtain a first electrode composed of the remaining second conductive material layer; removing the dielectric material layer and the first conductive material layer on the side wall of the first filling groove, to obtain a capacitor dielectric layer composed of the dielectric material layer surrounding the first electrode, and a second electrode composed of the first conductive material layer surrounding the capacitor dielectric layer; forming the channel and the bit line structure of the storage transistor in the first filling groove; wherein, the storage capacitor includes the first electrode, the second electrode, and the capacitor dielectric layer.

[0026] In some embodiments, forming the word line structure in the word line through hole includes:

[0027] Forming a nitride layer and a gate dielectric layer on the side wall of the word line through hole in sequence;

[0028] Wherein, the storage transistor includes the gate dielectric layer.

[0029] In some embodiments, forming the storage transistor in the second filling groove includes:

[0030] Forming a semiconductor layer and a gate layer on the inner wall of the second filling groove in sequence, with the semiconductor layer surrounding the gate layer;

[0031] Wherein, the storage transistor includes the semiconductor layer and the gate layer.

[0032] In some embodiments, forming the semiconductor layer and the gate layer on the inner wall of the second filling groove in sequence includes:

[0033] Forming a semiconductor material layer on the inner wall of the second filling groove, with the semiconductor material layer extending to cover the inner wall of the word line through hole;

[0034] Forming a gate material layer on the semiconductor material layer;

[0035] Etching and removing the gate material layer and the semiconductor material layer in the word line through hole, to obtain the semiconductor layer and the gate layer.

[0036] The present disclosure also provides a memory, which includes:

[0037] a substrate;

[0038] at least one layer of memory cells disposed on the substrate; one layer of memory cells includes a plurality of memory cells; the memory cells include memory transistors and memory capacitors arranged along a row direction parallel to the substrate; the memory capacitors include a first electrode, a capacitive dielectric layer, and a second electrode, the first electrode is connected to the memory transistor, and the second electrode is located on a side of the capacitive dielectric layer away from the first electrode; a reference signal line is further included, the reference signal line is connected to the second electrode, and the reference signal line overlaps with the first electrode in both the row direction and the column direction; the column direction is parallel to the substrate and intersects with the row direction.

[0039] In some embodiments, the reference signal line is grounded.

[0040] In some embodiments, the memory includes multiple layers of memory cells;

[0041] the reference signal line vertically penetrates the multiple layers of memory cells along a longitudinal direction perpendicular to the substrate; the reference signal line extends along the column direction and is connected to two adjacent second electrodes in the row direction.

[0042] In some embodiments, it further includes:

[0043] a word line structure that vertically penetrates multiple memory cells along a longitudinal direction perpendicular to the substrate, and the memory transistors in each memory cell share the word line structure.

[0044] In some embodiments, it further includes:

[0045] a word line via hole that extends along the longitudinal direction, and the word line structure is located in the word line via hole;

[0046] a first filling groove that communicates with the word line via hole, and both the memory transistor and the memory capacitor are located in the first filling groove.

[0047] In some embodiments, the memory transistor includes a gate layer and a semiconductor layer, and the memory further includes: an insulating layer that is alternately stacked with the memory cell in the longitudinal direction; the gate layer is in contact with the word line structure, the gate layer is located in the first filling groove between adjacent insulating layers, and the semiconductor layer covers the top surface and the bottom surface of the gate layer close to the insulating layer and covers the side surface between the top surface and the bottom surface of the gate layer.

[0048] In some embodiments, the memory transistor further includes:

[0049] The gate dielectric layer is located between the semiconductor layer and the word line structure.

[0050] In some embodiments, the gate dielectric layer at least covers a partial surface of the word line structure, and the memory further includes:

[0051] A second dielectric layer is located in the word line through hole and covers the surface of the gate dielectric layer facing away from the word line structure.

[0052] In some embodiments, the first electrode is connected to the semiconductor layer, the capacitive dielectric layer covers the surface of the first electrode parallel to the substrate and covers the surface of the first electrode facing away from the semiconductor layer, and the second electrode covers the surface of the capacitive dielectric layer facing away from the first electrode.

[0053] In some embodiments, it further includes: a bit line structure located in the first filling groove, extending along the column direction and connected to the semiconductor layer.

[0054] In some embodiments, the bottom surface of the bit line structure close to the substrate, the top surface away from the substrate, and the side surface connecting the top surface and the bottom surface are all covered by the semiconductor layer.

[0055] The present disclosure also provides an electronic device including the memory as described above.

[0056] The manufacturing method of the above memory forms a first trench and a word line through hole penetrating the stacked structure in a stacked structure including an insulating layer and a sacrificial layer stacked alternately, laterally etches the sacrificial layer based on the first trench to form a first filling groove, and then forms a bit line structure, a storage transistor, and a storage capacitor in the first filling groove, reducing the stress of the memory, reducing the defects caused by the increase in stress, avoiding the problem of etching topography, and improving the performance of the memory. Moreover, the stacked multi-layer storage units in the memory are prepared by alternately stacking an insulating layer and a sacrificial layer, and the manufacturing process is simple. For the multi-layer storage units stacked longitudinally perpendicular to the substrate, the area of the memory on the substrate is reduced while the storage capacity of the memory remains unchanged, reducing the cost. A semiconductor layer surrounding the word line through hole is formed in the first filling groove, avoiding the formation of parasitic transistors in the storage transistor, improving the read and write speed of data in the memory, and further improving the performance of the memory.

[0057] In the above-mentioned memory, there is at least one layer of memory cells disposed on the substrate; one layer of memory cells includes a plurality of memory cells; the memory cells include memory transistors and memory capacitors arranged along the row direction parallel to the substrate; the memory capacitors include a first electrode, a capacitive dielectric layer, and a second electrode, the first electrode is connected to the memory transistor, and the second electrode is located on the side of the capacitive dielectric layer away from the first electrode; by providing a reference signal line in the memory and connecting the reference signal line to the second electrode, the reference signal line overlaps with the first electrode in both the row direction and the column direction; thus, a reference signal line is connected in parallel outside the capacitor, increasing the capacitance capacity of the memory and improving the data retention ability of the memory. Description of the Drawings

[0058] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the following-described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0059] Figure 1 It is a schematic flowchart of a method for manufacturing a memory in some embodiments;

[0060] Figure 2 It is a top view schematic diagram of a memory after forming a stacked structure in some embodiments;

[0061] Figure 3 For Figure 2 A schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the AA direction;

[0062] Figure 4 It is a top view schematic diagram of a memory after forming a device isolation structure in some embodiments;

[0063] Figure 5 For Figure 4 A schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the AA direction;

[0064] Figure 6 It is a top view schematic diagram of a memory after forming a reference signal line in some embodiments;

[0065] Figure 7 For Figure 6 A schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the AA direction;

[0066] Figure 8 For Figure 6 A schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the BB direction;

[0067] Figure 9 Top view schematic of the memory after forming the first trench and the word line via in some embodiments;

[0068] Figure 10 is Figure 9 Cross-sectional schematic of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0069] Figure 11 is Figure 9 Cross-sectional schematic of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0070] Figure 12 Top view schematic of the memory after forming the first filling groove in some embodiments;

[0071] Figure 13 is Figure 12 Cross-sectional schematic of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0072] Figure 14 is Figure 12 Cross-sectional schematic of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0073] Figure 15 Top view schematic of the memory after forming the second conductive material layer in some embodiments;

[0074] Figure 16 is Figure 15 Cross-sectional schematic of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0075] Figure 17 is Figure 15 Cross-sectional schematic of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0076] Figure 18 Top view schematic of the memory after forming the storage capacitor in some embodiments;

[0077] Figure 19 is Figure 18 Cross-sectional schematic of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0078] Figure 20 is Figure 18 Cross-sectional schematic of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0079] Figure 21 Top view schematic of the memory after forming the storage transistor in some embodiments;

[0080] Figure 22 is Figure 21Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0081] Figure 23 is Figure 21 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0082] Figure 24 is a top view schematic of the memory after forming the word line structure in some embodiments;

[0083] Figure 25 is Figure 24 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0084] Figure 26 is Figure 24 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0085] Figure 27 is a top view schematic of the memory after forming the bit line isolation structure in some embodiments;

[0086] Figure 28 is Figure 27 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0087] Figure 29 is Figure 27 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0088] Figure 30 is Figure 27 3D schematic of;

[0089] Figure 31 is a top view schematic of the memory after forming the third trench in another embodiment;

[0090] Figure 32 is Figure 31 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0091] Figure 33 is Figure 31 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0092] Figure 34 is a top view schematic of the memory after forming the word line structure in some embodiments;

[0093] Figure 35 is Figure 34 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0094] Figure 36 is Figure 34 a schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the BB direction;

[0095] Figure 37 is a top view of the memory after forming the word line structure in some embodiments;

[0096] Figure 38 is Figure 37 a schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the AA direction;

[0097] Figure 39 is Figure 37 a schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the BB direction.

[0098] Description of reference numerals:

[0099] 102, substrate; 104, stacked structure; 106, device isolation structure; 108, reference signal line; 110, bit line structure; 112, first electrode; 114, capacitor dielectric layer; 116, second electrode; 118, storage capacitor; 120, storage transistor; 122, semiconductor layer; 124, gate structure; 126, gate dielectric layer; 128, gate; 130, word line structure; 132, bit line isolation structure; 202, insulating layer; 204, sacrificial layer; 206, first trench; 208, word line via; 210, first filling groove; 212, first conductive material layer; 214, dielectric material layer; 216, second conductive material layer; 218, insulating material; 302, bit line filling groove; 304, second filling groove; 305, third filling groove; 306, capacitor filling groove. Detailed implementation manners

[0100] To facilitate the understanding of the embodiments of the present disclosure, the embodiments of the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the embodiments of the present disclosure are given in the drawings. However, the embodiments of the present disclosure can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the embodiments of the present disclosure more thorough and comprehensive.

[0101] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the embodiments of the present disclosure belong. The terms used in the description of the embodiments of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present disclosure. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0102] In the description of the embodiments of the present disclosure, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings. These are only for the convenience of describing the embodiments of the present disclosure and for simplification, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be construed as a limitation on the embodiments of the present disclosure.

[0103] It can be understood that the terms "first", "second", etc. used in the present disclosure may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first filling groove may be referred to as the second filling groove, and similarly, the second filling groove may be referred to as the first filling groove. Both the first filling groove and the second filling groove are filling grooves, but they are not the same filling groove.

[0104] In addition, the terms "first", "second" are only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second" may explicitly or implicitly include at least one of such features. In the description of the present disclosure, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined. In the description of the present disclosure, "several" means at least one, such as one, two, etc., unless otherwise specifically defined.

[0105] As used herein, the terms "substrate", "base" mean and include the base material or structure of the material of the memory transistor introduced in the present disclosure. The substrate may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0106] In the present disclosure, the upper surface of the substrate is the surface of the substrate forming a laminated structure, the lower surface of the substrate is the surface arranged opposite to the upper surface, and the upper and lower surfaces of other structures or layers are relative to the upper surface of the substrate. For the structure or layer located in the substrate, the two surfaces parallel to the substrate surface that are close to the upper surface of the substrate are the upper surface / top surface / top / top surface, and the surface that is away from the upper surface of the substrate is the lower surface / bottom surface / bottom / bottom surface. For the structure or layer located on the substrate, on the contrary, the two surfaces that are close to the upper surface of the substrate are the lower surface / bottom surface / bottom / bottom surface, and the surface that is away from the upper surface of the substrate is the upper surface / top surface / top / top surface. For the structure, groove, hole or layer formed in the semiconductor structure from the substrate surface to the direction away from the substrate, the surface in the longitudinal direction is the side wall / side surface / side surface of the structure, groove, hole or layer, and the position where the groove or hole stops penetrating is the bottom of the groove or hole. Figure 1 FIG. 1 is a flow chart of a method for preparing a memory in an embodiment. Figure 1 As shown, in this embodiment, a method for preparing a memory is provided, the memory includes a word line structure, a bit line structure, and memory cells stacked in a vertical direction perpendicular to a substrate, the memory cells include memory transistors and storage capacitors arranged in a row direction, and the method for preparing the memory includes:

[0107] S102, providing a substrate having a laminated structure.

[0108] A substrate is provided, and a stacked structure is formed on the substrate. The stacked structure includes insulating layers and sacrificial layers alternately stacked from bottom to top. From bottom to top, the stacked structure is formed from the upper surface of the substrate to the direction away from the substrate, that is, the stacked structure is alternately stacked in the direction away from the substrate. In some embodiments, the constituent material of the substrate includes but is not limited to undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC) or any combination thereof. As an example, in this embodiment, the constituent material of the substrate is selected from single crystal silicon. The substrate has a certain thickness and can serve as a structural support for a device structure (such as a stacked structure) formed thereon. In some embodiments, the substrate can be removed or thinned in some subsequent process steps. S104, a first groove is formed in the stacked structure that penetrates the stacked structure and extends along the column direction.

[0109] A first trench penetrating the stacked structure is formed in the stacked structure, and the first trench extends along a column direction parallel to the substrate.

[0110] S106, forming a word line through hole penetrating the stacked structure in the stacked structure.

[0111] A word line via hole penetrating the stacked structure is formed in the stacked structure. In the row direction within the plane parallel to the substrate, the word line via hole and the first trench are arranged at intervals. It can be understood that the word line via hole can be formed simultaneously with the first trench in the same process step, or can be formed separately from the first trench in different process steps.

[0112] S108, laterally etch the sacrificial layer based on the first trench to form a first filling groove communicating with the first trench.

[0113] Based on the sacrificial layer exposed by laterally etching the sidewalls of the first trench, a first filling groove is formed. The first filling groove is located between adjacent insulating layers or between an adjacent insulating layer and the substrate, and communicates with the first trench. Multiple first filling grooves formed by laterally etching through the same first trench are arranged at intervals in the longitudinal direction perpendicular to the substrate, and there is an insulating layer between adjacent first filling grooves.

[0114] S110, form a bit line structure, a memory transistor, and a memory capacitor in the first filling groove, and form a word line structure in the word line via hole.

[0115] A bit line structure, a memory transistor, and a memory capacitor are formed in the first filling groove and arranged in sequence along the row direction. The bit line structure extends along the column direction. The memory transistor is located between the bit line structure and the memory capacitor. The memory transistor is penetrated by the word line via hole, and the memory transistor is respectively connected to the bit line structure and the memory capacitor. The bit line structure and the memory capacitor do not contact each other. The first filling groove surrounds the word line via hole and the first trench, and the first filling groove, the word line via hole, and the first trench communicate with each other. A word line structure is formed in the word line via hole. In the longitudinal direction, multiple vertically stacked memory cells share the word line structure, that is, the same word line structure is electrically connected to the memory transistors in multiple vertically stacked memory cells.

[0116] In the method for manufacturing the above memory, a first trench and a word line via hole penetrating the stacked structure are formed in a stacked structure including alternately stacked insulating layers and sacrificial layers. The sacrificial layer is laterally etched based on the first trench to form a first filling groove, and then a bit line structure, a memory transistor, and a memory capacitor are formed in the first filling groove, reducing the stress of the memory, reducing the defects caused by increased stress, avoiding the problem of etching topography, and improving the performance of the memory. Moreover, by using insulating layers and sacrificial layers alternately stacked to prepare the stacked multi-layer memory cells in the memory, the manufacturing process is simple. A memory transistor surrounding the word line via hole is formed in the first filling groove, avoiding the formation of parasitic transistors in the memory transistor, improving the data reading and writing speeds in the memory, and further improving the performance of the memory.

[0117] Figure 2 FIG. is a top view schematic diagram of the memory after forming the stacked structure in an embodiment. Figure 3 For Figure 2Schematic cross-sectional view of the corresponding semiconductor structure in the AA direction, where Figure 2 The schematic cross-sectional view of the corresponding semiconductor structure in the BB direction is the same as Figure 3 Exemplarily, the X direction can be Figure 2 The row direction in the plane parallel to the substrate 102 shown, and the Y direction can be Figure 2 The column direction in the plane parallel to the substrate 102 shown, and the Z direction can be Figure 2 The direction from the top surface of the substrate 102 to the bottom surface of the substrate 102 along, as Figure 2 - Figure 3 Shown, a substrate 102 is provided, and a stacked structure 104 is formed on the substrate 102. The stacked structure 104 includes an insulating layer 202 and a sacrificial layer 204 that are alternately stacked in the longitudinal direction perpendicular to the substrate 102. The constituent materials of the insulating layer 202 and the sacrificial layer 204 are different, and the number of layers of the sacrificial layer 204 can be set according to the number of memory cells stacked longitudinally. The number of memory cells is the same as the number of layers of the sacrificial layer 204. Optionally, the top of the stacked structure 104 can be the insulating layer 202 or the sacrificial layer 204; the bottom of the stacked structure 104 can also be the insulating layer 202 or the sacrificial layer 204.

[0118] Optionally, the constituent materials of the insulating layer 202 and the sacrificial layer 204 include but are not limited to one or more of silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), carbide (silicon carbide). Exemplarily, the constituent material of the insulating layer 202 includes silicon dioxide, and the constituent material of the sacrificial layer 204 includes silicon nitride. Compared with using a conductive material to form the sacrificial layer 204, by setting the sacrificial layer 204 made of an insulating material, problems of stress and etching profile during etching the sacrificial layer 204 to prepare each layer of memory cells are avoided. In one embodiment, the bottom of the stacked structure 104 is the sacrificial layer 204, an isolation layer is formed on the surface of the substrate 102, and a first trench is formed in the stacked structure 104 that penetrates the stacked structure 104 and extends along the column direction Y, including: forming a first trench in the stacked structure 104 that penetrates the stacked structure 104 and extends into the isolation layer; forming a word line via hole that penetrates the stacked structure in the stacked structure, including: forming a word line via hole that penetrates the stacked structure and is spaced from the first trench in the row direction X. The stacked structure 104 is located on the surface of the isolation layer, and by setting the isolation layer, the memory cells close to the substrate 102 in the memory device are isolated from the device structure in the substrate 102. Exemplarily, the constituent material of the isolation layer includes but is not limited to one or more of undoped polysilicon, silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), carbide (silicon carbide).

[0119] In one embodiment, the top of the stacked structure 104 is a sacrificial layer 204. Before forming a word line via hole that penetrates the stacked structure 104 and extends along the column direction Y in the stacked structure 104, it further includes:

[0120] A support layer is formed on the top of the stacked structure 104, and the first filling groove at the top is located between the insulating layer 202 and the adjacent support layer. By providing the support layer, the first filling grooves are all located between adjacent two film layers, and the storage units formed in the first filling grooves subsequently have the same repetitive structure. Hereinafter, an example is given with the insulating layers 202 at both the top and the bottom of the stacked structure 104. Exemplarily, the constituent materials of the support layer include, but are not limited to, one or more of undoped polysilicon, silicon oxides (such as silicon dioxide), silicon nitrides (silicon oxynitride), nitrides (such as silicon nitride), and carbides (silicon carbide).

[0121] In one embodiment, the first groove and the word line via hole are formed in the stacked structure 104 by the same process step. Lateral etching of the sacrificial layer 204 based on the first groove to form the first filling groove includes: Lateral etching of the sacrificial layer based on the first groove and the word line via hole to form the first filling groove, which simplifies the process steps and saves the manufacturing cost.

[0122] Figure 4 FIG. is a top view schematic diagram of a memory after forming a device isolation structure in one embodiment. Figure 5 For Figure 4 a cross-sectional schematic diagram of the corresponding semiconductor structure in the AA direction, where Figure 4 the cross-sectional schematic diagram of the corresponding semiconductor structure in the BB direction is the same as Figure 3 that, as Figure 4 - Figure 5 shown, in one embodiment, before forming the first groove and the word line via hole in the stacked structure 102 by the same step, it further includes: a step of forming a device isolation structure 106 in the stacked structure 104. Specifically, the step of forming the device isolation structure 106 in the stacked structure 104 includes: step S202 - step S204.

[0123] S202, forming isolation trenches arranged in an array in the stacked structure 104, and the isolation trenches penetrate the stacked structure 104.

[0124] S204, forming a device isolation structure 106 in the isolation trenches, the first groove is located between the device isolation structures 106 adjacent in the row direction X, and the word line via hole is located between the device isolation structures 106 adjacent in the column direction Y.

[0125] Specifically, through a photolithography process and an etching process, an array arrangement is formed in the stacked structure 104, and isolation trenches penetrating the stacked structure 104 are formed. A device isolation structure 106 is filled in the isolation trenches. The subsequent first trenches are located between adjacent device isolation structures 106 in the row direction X, and the word line vias are located between adjacent device isolation structures 106 in the column direction Y. In a plane parallel to the substrate 10, adjacent memory cells in the column direction Y are separated by the device isolation structure 106. At the same time, the device isolation structure 106 separates adjacent bit line structures and reference signal lines in the row direction X. The device isolation structure is formed before the first trenches and word line vias that penetrate the stacked structure 104 and are arranged at intervals in the row direction X are formed, so that when the subsequent lateral etching forms the first filling groove and the second filling groove, the device isolation structure can be used as an etching stop layer for lateral etching. It can be understood that when the second trench for filling and forming the reference signal line is subsequently laterally etched, the device isolation structure can also be used as an etching stop layer for lateral etching. Exemplarily, the device isolation structure 106 fills the isolation trenches.

[0126] It can be understood that when the first trenches and the word line vias are formed in different steps, the positions of the subsequently formed word line vias are the same as the positions of the word line vias in step S204.

[0127] Exemplarily, the constituent materials of the device isolation structure 106 include, but are not limited to, one or more of undoped polysilicon, silicon oxides (such as silicon dioxide), silicon nitrides (silicon oxynitrides), nitrides (such as silicon nitride), and carbides (silicon carbide). Exemplarily, the constituent material of the device isolation structure 106 is silicon dioxide.

[0128] In some embodiments, the bottom of the isolation trench is flush with the bottom surface of the stacked structure 104. In other embodiments, in the longitudinal direction Z, the isolation trench extends into the substrate 102 (isolation layer), and through this setting, the influence of process deviation on the isolation effect of the device isolation structure in isolating adjacent memory cells, adjacent bit line structures, and reference signal lines is eliminated.

[0129] In some embodiments, adjacent bit line structures and reference signal lines are separated by a sacrificial layer 204.

[0130] In some embodiments, in a plane parallel to the substrate 102, adjacent memory cells in the column direction Y are separated by a sacrificial layer 204.

[0131] Figure 6 It is a top view schematic diagram of the memory after the reference signal line is formed in an embodiment. Figure 7 For Figure 6 The cross-sectional schematic diagram of the corresponding semiconductor structure in the AA direction. Figure 8 For Figure 6Schematic cross-sectional view of the corresponding semiconductor structure in the BB direction, as shown in Figure 6 - Figure 8 In one embodiment, before forming the first trenches and word line vias that penetrate the stacked structure 104 and are spaced along the row direction X in the stacked structure 104, it further includes: a step of forming a reference signal line 108 in the stacked structure 104. Specifically, the step of forming the reference signal line 108 in the stacked structure 104 includes: step S302 - step S304.

[0132] S302, forming a second trench that penetrates the stacked structure 104 in the stacked structure 104, the second trench extends along the column direction Y, is spaced from the subsequently formed word line vias, and is located on the side of the word line vias away from the subsequently formed first trench.

[0133] S304, forming a reference signal line 108 in the second trench, the reference signal line 108 is electrically connected to the adjacent storage capacitors to be formed subsequently.

[0134] Steps S302 - S304 are specifically: using a photolithography process and a dry etching process to form a second trench that penetrates the stacked structure 104 and extends along the column direction Y in the stacked structure 104, the sidewalls of the second trench expose the sidewalls of the adjacent device isolation structures 106, the subsequently formed word line vias are located in the stacked structure 104 on both sides of the second trench, and the word line vias are located between the adjacent device isolation structures 106 in the column direction Y, and the subsequently formed first trench is located in the stacked structure 104 on the side of the word line vias away from the second trench. Then, a chemical deposition process (such as atomic layer deposition process) and a chemical mechanical planarization process are used to fill and form a reference signal line 108 in the second trench. The reference signal line 108 is used to fix the second electrode of the storage capacitor in the subsequently formed memory at a reference potential, and the reference signal line 108 is electrically connected to the adjacent storage capacitors in the row direction X, column direction Y, and longitudinal direction Z. Exemplarily, the reference signal line 108 fills the second trench.

[0135] In some embodiments, in a plane parallel to the substrate 102, the first width L1 of the reference signal line 108 between the adjacent device isolation structures 106 in the row direction X is greater than the second width L2 of the reference signal line 108 between the adjacent word line vias in the row direction X. By this setting, the contact area between the second electrode and the reference signal line 108 can be increased, and the contact resistance between the second electrode and the reference signal line 108 can be reduced.

[0136] Optionally, the material of the reference signal line 108 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); the metal silicide includes tungsten silicide (WSi). Exemplarily, the material of the reference signal line 108 includes a stack of titanium + titanium nitride + tungsten metal, and the stacking direction is from the inner wall of the second trench to the direction away from the inner wall of the second trench.

[0137] Figure 9 For Figure 6 A top view schematic diagram of the memory after forming the first trench and the word line via hole in a corresponding embodiment. Figure 10 For Figure 9 A cross-sectional schematic diagram of the corresponding semiconductor structure in the AA direction. Figure 11 For Figure 9 A cross-sectional schematic diagram of the corresponding semiconductor structure in the BB direction. As Figure 9 - Figure 11 shown, the first trench 206 and the word line via hole 208 are formed in the stacked structure 104 through the same lithography and etching process. For example, the etching process can refer to a wet etching process or a dry etching process, etc. The dimensions and shapes of the first trench 206 and the word line via hole 208 can be obtained by patterning the stacked structure 104. Exemplarily, in the row direction X, the word line via hole 208 is located in the stacked structure 104 on both sides of the first trench 206, and in the column direction Y, the word line via hole 208 is located in the stacked structure 106 between adjacent device isolation structures 106. Exemplarily, the first trench 206 and the word line via hole 208 extend into the substrate 102 in the longitudinal Z direction.

[0138] Figure 12 For Figure 9 A top view schematic diagram of the memory after forming the first filling groove in a corresponding embodiment. Figure 13 For Figure 12 A cross-sectional schematic diagram of the corresponding semiconductor structure in the AA direction. Figure 14 For Figure 12 A cross-sectional schematic diagram of the corresponding semiconductor structure in the BB direction. As Figure 12 - Figure 12 shown, in one embodiment, the sacrificial layer 204 is etched laterally based on the first trench 206 and the word line via hole 208 to form the first filling groove 210, including steps S402 - step S404.

[0139] S402, based on the first trench 206, etch the sacrificial layer 204 laterally in the row direction X to form the bit line filling groove 302.

[0140] S404, laterally etch the sacrificial layer 204 on the sidewalls around the word line via 208 to form a second filling groove 304 and a capacitor filling groove 306 on one side of the second filling groove 304. The second filling groove 304 communicates with the bit line filling groove 302 and the capacitor filling groove 306.

[0141] Specifically, steps S402 and S404 are as follows: Using an etching process (such as a wet etching process), laterally etch the sacrificial layer 204 based on the first trench 206 and the word line via 208 to obtain a first filling groove 210. The first filling groove 210 includes a bit line filling groove 302, a second filling groove 304, and a capacitor filling groove 306. The bit line filling groove 302 is used for subsequent filling to form a bit line structure, the second filling groove 304 is used for subsequent formation of a storage transistor, and the capacitor filling groove 306 is used for subsequent formation of a storage capacitor. Based on the first trench 206, laterally etch the sacrificial layer 204 in the row direction X to obtain the bit line filling groove 302. Based on the sidewalls around the word line via 208, laterally etch the sacrificial layer 204 in the plane to obtain the second filling groove 304 surrounding the word line via 208 and the capacitor filling groove 306 on the side of the second filling groove 304 away from the bit line filling groove 302. The device isolation structure 106 and the reference signal line 108 serve as an etching stop layer for lateral etching (lateral etching in the plane). In the column direction Y, the sidewall of the second filling groove 304 exposes the sidewall of the adjacent device isolation structure 106. In the row direction X, the sidewall of the bit line filling groove 302 exposes the sidewall of the adjacent device isolation structure 106, where the second filling groove 304 communicates with both the bit line filling groove 302 and the capacitor filling groove 306. When there is a reference signal line 108, the sidewall of the capacitor filling groove 306 exposes the sidewall of the reference signal line 108. In some embodiments, in the row direction X, the sacrificial layer 204 between the first trench 206 and the word line via 208 is completely removed; in the column direction Y, the sacrificial layer 204 between the word line via 208 and the adjacent device isolation structure 106 is completely removed; in the row direction X, the sacrificial layer 204 between the word line via 208 and the reference signal line 108 is completely removed, and the sidewall of the capacitor filling groove 306 exposes a part of the sidewalls of the adjacent device isolation structure 106 and the reference signal line 108.

[0142] Figure 15 For Figure 12 A top view schematic diagram of the memory after forming the second conductive material layer in a corresponding embodiment. Figure 16 For Figure 15 A cross-sectional schematic diagram of the corresponding semiconductor structure in the AA direction. Figure 17 For Figure 15 A cross-sectional schematic diagram of the corresponding semiconductor structure in the BB direction. Figure 18 For Figure 15 A top view schematic diagram of the memory after forming the storage capacitor in a corresponding embodiment. Figure 19 ForFigure 18 Schematic cross-sectional view of the corresponding semiconductor structure in the AA direction, Figure 20 is Figure 18 Schematic cross-sectional view of the corresponding semiconductor structure in the BB direction, Figure 21 is Figure 18 Top view of the memory after forming the memory transistor in one embodiment of the corresponding one, Figure 22 is Figure 21 Schematic cross-sectional view of the corresponding semiconductor structure in the AA direction, Figure 23 is Figure 21 Schematic cross-sectional view of the corresponding semiconductor structure in the BB direction, as Figure 15 - Figure 23 shown, in one of the embodiments, a bit line structure 110, a memory transistor 114, and a memory capacitor 112 are formed in the first filling groove 210 and arranged in sequence along the row direction X, including: step S502 - step S508.

[0143] S502, a first conductive material layer 212, a dielectric material layer 214, and a second conductive material layer 216 are sequentially formed on the inner walls of the word line through hole 208 and the first filling groove 210.

[0144] A first conductive material layer 212, a dielectric material layer 214, and a second conductive material layer 216 are sequentially formed on the inner walls of the word line through hole 208 and the first filling groove 210 by a deposition process (such as atomic layer deposition process). In some embodiments, the second conductive material layer 216 at least fills the first filling groove 210.

[0145] Exemplarily, the constituent materials of the first conductive material layer 212 and the second conductive material layer 216 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); the metal silicide includes tungsten silicide (WSi). The constituent materials of the first conductive material layer 212 and the second conductive material layer 216 can be the same or different.

[0146] Exemplarily, the constituent materials of the dielectric material layer 214 include, but are not limited to, silicon oxides (such as silicon dioxide), silicon nitrides (silicon oxynitrides), nitrides (such as silicon nitride), metal oxides (such as Al2O3), metal oxynitrides (such as AlON), metal silicides, high-k dielectric materials (dielectric constant greater than 3.9), ferroelectric materials, antiferroelectric materials, or combinations thereof. Exemplarily, the high-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). Using a high-k dielectric material as the dielectric material layer 214 can increase the storage capacity of the storage capacitor. Exemplarily, the constituent material of the dielectric material layer 214 is hafnium oxide (HfO2).

[0147] S504, Remove the second conductive material layer 216, the dielectric material layer 214, and the first conductive material layer 212 in the word line via 208, and the second conductive material layer 216 in the partial area of the first fill groove 210 close to the word line via 208, to form a second fill groove 304 surrounding the word line via 208, and obtain the bit line structure 110 and the first electrode 112 composed of the remaining second conductive material layer 216.

[0148] Use photolithography and a first etching process (such as a dry etching process) to remove the second conductive material layer 216 in the word line via 208, as well as the dielectric material layer 214 and the first conductive material layer 212 on the inner wall of the word line via 208. Adopt a second etching process (such as a wet etching process) to laterally remove the second conductive material layer 216 in the partial area (partial length in the row direction X) of the first fill groove 210 close to the word line via 208. The part of the first fill groove 210 where the second conductive material layer 216 is removed forms a second fill groove 304 surrounding the word line via 208, and obtain the bit line structure 110 and the first electrode 112 composed of the remaining second conductive material layer 216. The remaining first electrodes 112 are close to the reference signal line 108, and the bit line structure 110 is close to the first trench 206, that is, the bit line structure 110 is located in the bit line fill groove 302, and the first electrode 112 is located in the capacitor fill groove 306.

[0149] S506, Remove the dielectric material layer 214 and the first conductive material layer 212 on the side wall of the second fill groove 304, and obtain the capacitor dielectric layer 114 composed of the dielectric material layer 214 surrounding the first electrode 112, and the second electrode 116 composed of the first conductive material layer 212 surrounding the capacitor dielectric layer 114.

[0150] Etch away the dielectric material layer 214 and the first conductive material layer 212 on the sidewall of the second filling groove 304 to obtain a capacitor dielectric layer 114 composed of the dielectric material layer 214 surrounding the first electrode 112, and a second electrode 116 composed of the first conductive material layer 212 surrounding the capacitor dielectric layer 114. Among them, the storage capacitor 118 includes the first electrode 112, the second electrode 116, and the capacitor dielectric layer 114. At this time, the first conductive material layer 212 and the dielectric material layer 114 cover the top surface and the bottom surface of the bit line structure 110 close to the insulating layer 202, improving the packaging effect of the bit line structure 110 and preventing water vapor from contacting the bit line structure 110 and affecting the performance of the memory. In one embodiment, the dielectric material layer 214 and the first conductive material layer 212 exposed on the sidewall of the second filling groove 304 are completely removed.

[0151] S508, form a storage transistor 120 in the second filling groove 304.

[0152] In one embodiment, forming a storage transistor 120 in the second filling groove 304 includes: sequentially forming a semiconductor layer 122 and a gate layer 124 on the inner wall of the second filling groove 304, and the semiconductor layer 122 surrounds the gate layer 124; among them, the storage transistor 120 includes the semiconductor layer 122 and the gate layer 124.

[0153] In one embodiment, sequentially forming a semiconductor layer 122 and a gate layer 124 on the inner wall of the second filling groove 304 includes steps S602 - S606.

[0154] S602, form a semiconductor material layer on the inner wall of the second filling groove 304, and the semiconductor material layer extends and covers the inner wall of the word line through hole 208.

[0155] S604, form a gate material layer on the semiconductor material layer.

[0156] S606, etch away the gate material layer and the semiconductor material layer in the word line through hole 208 to obtain the semiconductor layer 122 and the gate layer 124.

[0157] Specifically, for steps S602 - S606, a semiconductor material layer is formed at the bottom of the second filling groove 304 by using a first deposition process (such as atomic layer chemical vapor deposition process), and the semiconductor material layer extends along the side wall of the second filling groove 304 to cover the inner wall of the word line through hole 208. A gate material layer (gate dielectric material layer and gate material layer) is conformally formed on the semiconductor material layer by using a second deposition process (such as atomic layer chemical vapor deposition process), and then the gate material layer (gate dielectric material layer and gate material layer) and the semiconductor material layer in the word line through hole 208 (inner wall of the word line through hole 208) are etched away (such as by dry etching process) to obtain a semiconductor layer 122 composed of the remaining semiconductor material layer in the second filling groove 304 and a gate layer 124 composed of the remaining gate material layer in the second filling groove 304 (a gate dielectric layer 126 composed of the remaining gate dielectric material layer and a gate 128 composed of the remaining gate material layer). Among them, the gate layer 124 includes the gate dielectric layer 126 and the gate 128. The gate dielectric layer 126 is the part of the gate layer 124 in contact with the semiconductor layer 122. The semiconductor layer 122 is in contact with the bit line structure 110 and the first electrode 112 at the same time. Among them, the part of the semiconductor layer 122 in contact with the bit line structure 110 is the drain contact area, and the part of the semiconductor layer 122 in contact with the first electrode 112 is the source contact area. The semiconductor layer 122 between the drain contact area and the source contact area is the channel area of the memory transistor 120. Optionally, the gate material layer at least fills the second filling groove 304. At this time, the gate 128 fills the second filling groove 304.

[0158] Exemplarily, the constituent material of the semiconductor layer 122 includes silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), metal oxide (such as Al2O3), metal oxynitride (such as AlON), metal silicide, high-k dielectric material (dielectric constant greater than 3.9), low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (dielectric constant less than 2.5), ferroelectric material, antiferroelectric material, IGZO, indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), or a combination thereof. Exemplarily, the high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). When using IGZO as the semiconductor layer 122, it has the advantages of low leakage current and short refresh time. The material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the leakage current of the transistor can meet the requirements, and it can be adjusted according to the actual situation specifically.

[0159] Exemplarily, the constituent material of the gate dielectric layer 126 includes silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), metal oxide (such as Al2O3), metal oxynitride (such as AlON), metal silicide, high-k dielectric material (dielectric constant greater than 3.9), low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (dielectric constant less than 2.5), ferroelectric material, antiferroelectric material, or a combination thereof. Exemplarily, the high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3).

[0160] Optionally, the constituent material of the gate 128 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicide (WSi).

[0161] Figure 24 For Figure 21 a top view schematic diagram of the memory after forming the word line structure in a corresponding embodiment, Figure 25 For Figure 24 a cross-sectional schematic diagram of the corresponding semiconductor structure in the AA direction, Figure 26 For Figure 24 a cross-sectional schematic diagram of the corresponding semiconductor structure in the BB direction. As Figure 24 - Figure 26 shown, in the process of forming the bit line structure 110, the memory transistor 120, and the storage capacitor 118 arranged in sequence along the row direction X in the first filling groove 210, it further includes the step of forming the word line structure 130 in the word line through hole 208. Specifically, the word line structure 130 is formed in the word line through hole 208 by using chemical vapor deposition process and chemical mechanical polishing process, and the word line structure 130 is in contact with the gate layer 124 of the memory transistor 120 in each memory cell stacked in the longitudinal Z direction.

[0162] Exemplarily, the constituent material of the word line structure 130 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicide (WSi).

[0163] Figure 27 For Figure 24 a top view schematic diagram of the memory after forming the bit line isolation structure in a corresponding embodiment, Figure 28 For Figure 27 a cross-sectional schematic diagram of the corresponding semiconductor structure in the AA direction, Figure 29 For Figure 27 a cross-sectional schematic diagram of the corresponding semiconductor structure in the BB direction. As Figure 21 - Figure 29As shown, in one embodiment, the first filling groove 210 includes a bit line filling groove 302 extending along the column direction Y. A first conductive material layer 212, a dielectric material layer 214, and a second conductive material layer 216 are sequentially formed on the inner walls of the word line through hole 208 and the first filling groove 210. It further includes:

[0164] A first conductive material layer 212, a dielectric material layer 214, and a second conductive material layer 216 are sequentially formed on the inner wall of the first groove 206, and the second conductive material layer 216 fills the bit line filling groove 302;

[0165] The method for manufacturing the memory further includes:

[0166] Etch and remove the second conductive material layer 216, the dielectric material layer 214, and the first conductive material layer 212 in the first groove 206;

[0167] A bit line isolation structure 132 is filled and formed in the first groove 206.

[0168] Exemplarily, the constituent material of the bit line isolation structure 132 includes, but is not limited to, one or more of oxides, nitrides, oxynitrides, and carbides. Exemplarily, the oxide includes silicon dioxide (SiO2); the nitride includes silicon nitride (SiN); the oxynitride includes silicon oxynitride (SiON), and the carbide includes silicon carbide. Optionally, a bit line isolation structure 132 and voids are formed in the first groove 206, or the first groove 206 is filled with the bit line isolation structure 312.

[0169] Figure 31 For Figure 6 The top view schematic diagram of the memory after forming the third groove in the corresponding another embodiment, Figure 32 For Figure 31 The cross-sectional schematic diagram of the corresponding semiconductor structure in the AA direction, Figure 33 For Figure 31 The cross-sectional schematic diagram of the corresponding semiconductor structure in the BB direction, Figure 34 For Figure 31 The top view schematic diagram of the memory after forming the word line structure in the corresponding one embodiment, Figure 35 For Figure 34 The cross-sectional schematic diagram of the corresponding semiconductor structure in the AA direction, Figure 36 For Figure 34 The cross-sectional schematic diagram of the corresponding semiconductor structure in the BB direction, Figure 37 For Figure 34 The top view schematic diagram of the memory after forming the word line structure in the corresponding one embodiment, Figure 38 For Figure 37 The cross-sectional schematic diagram of the corresponding semiconductor structure in the AA direction, Figure 39 For Figure 37Schematic cross-sectional view of the corresponding semiconductor structure in the BB direction, as shown in Figure 31 - Figure 39 In one embodiment, after forming the first filling groove 210 in the stacked structure 104, a word line through hole 208 is formed in the stacked structure 104. The bit line structure 110, the storage transistor 120, and the storage capacitor 118 arranged in sequence along the row direction X are formed in the first filling groove 210, and the word line structure 130 is formed in the word line through hole 208, including steps S702 - S708.

[0170] S702, a first conductive material layer, a dielectric material layer, and a second conductive material layer are sequentially formed on the inner walls of the first groove 206 and the first filling groove 210.

[0171] S704, the second conductive material layer, the dielectric material layer, and the first conductive material layer in the first groove 206 and in the partial area of the first filling groove 210 close to the first groove 206 are removed to form a third filling groove 305 surrounding the first groove 206, obtaining a first electrode 112 composed of the remaining second conductive material layer, a capacitive dielectric layer 114 composed of the dielectric material layer surrounding the first electrode 112, and a second electrode 116 composed of the first conductive material layer surrounding the capacitive dielectric layer 114. Among them, the storage capacitor 118 includes the first electrode 112, the second electrode 116, and the capacitive dielectric layer 114.

[0172] In one embodiment, the third filling groove 305 includes a bit line filling groove 302 extending along the column direction Y. After forming the third filling groove 305 surrounding the first groove 206 (step S704), it includes: depositing an insulating material 218 in the first groove 206 and the third filling groove 305; forming a word line through hole 208 in the stacked structure 104. In the row direction X, the word line through hole 208 is located between the insulating material 218 in the first groove 206 and the storage capacitor 118. Specifically, the word line through hole 208 penetrates the stacked structure 104 between the first groove 206 and the storage capacitor 118. At this time, there is an overlapping space between the word line through hole 208 and the third filling groove 305, and the structure formed by this overlapping space can be regarded as being formed in the third filling groove 305.

[0173] S706, form a word line structure 130 in the word line through hole 208.

[0174] In one embodiment, before forming the word line structure 130 in the word line through hole 208, the following steps are further included: forming a nitride layer (not shown in the figure) and a gate dielectric layer 126 on the side wall (inner wall) of the word line through hole 208 in sequence; wherein, the storage transistor 120 includes the gate dielectric layer 126. At this time, the nitride layer and the gate dielectric layer 126 cover the side surface of the word line structure 130, improving the encapsulation effect of the word line structure 130 and preventing water vapor from contacting the word line structure 130.

[0175] In one embodiment, after forming the word line structure 130 in the word line through hole 208, the following steps are further included: removing the insulating material 218 in the first trench 206 and the third filling groove 305; forming a semiconductor layer 122 and a third conductive material layer on the inner walls of the first trench 206 and the third filling groove 305 in sequence, and the third conductive material layer fills the third filling groove 305. At this time, a semiconductor layer 122 is provided between the third conductive material layer for forming the bit line structure 110 and the insulating layer 202 during subsequent etching, increasing the contact area between the bit line structure 110 and the semiconductor layer 122, reducing the contact resistance, improving the writing rate and reading rate of data in the memory, and reducing the transmission delay of data in the memory.

[0176] In one embodiment, removing the insulating material 218 in the first trench 206 and the third filling groove 305 includes: removing the nitride layer in the third filling groove 305; wherein, the semiconductor layer 122 is in contact with the gate dielectric layer 126. By removing the nitride layer in the third filling groove 305, the semiconductor layer 122 is brought into contact with the gate dielectric layer 126, thereby reducing the distance between the semiconductor layer 122 and the gate layer 124 and increasing the gate control ability in the storage transistor.

[0177] S708, forming a semiconductor layer 122 and a bit line structure 110 in the third filling groove 305 in sequence. Wherein, the storage transistor 120 includes the semiconductor layer 122, and the gate 128 of the storage transistor 120 is located at the position where the third filling groove 305 is penetrated by the word line through hole 208. At this time, the gate 128 is the part of the word line structure 130 opposite to the semiconductor layer 122.

[0178] It should be understood that although Figure 1 the steps in the flowchart are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order restriction, and these steps can be executed in other orders. Moreover, Figure 1At least a part of the steps may include multiple sub-steps or multiple stages, and these sub-steps or stages do not necessarily need to be completed at the same moment, but can be executed at different moments. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turns with at least a part of other steps or sub-steps or stages of other steps. As Figure 2 - Figure 39 shown, the present disclosure also provides a memory. The same or corresponding parts as those in the embodiments of the above memory preparation method will not be elaborated below. The memory includes: a substrate 102; at least one layer of memory cells disposed on the substrate 102; one layer of memory cells includes a plurality of memory cells; the memory cells include a memory transistor 120 and a memory capacitor 118 arranged along a row direction parallel to the substrate; the memory capacitor 118 includes a first electrode 112, a capacitor dielectric layer 114, and a second electrode 116. The first electrode 112 is connected to the memory transistor 120, and the second electrode 116 is located on a side of the capacitor dielectric layer 114 away from the first electrode; it further includes a reference signal line 108, the reference signal line 108 is connected to the second electrode, and the reference signal line 108 overlaps with the first electrode 112 in both the row direction and the column direction; the column direction is parallel to the substrate and intersects with the row direction.

[0179] In the above memory, the memory capacitor includes a first electrode, a capacitor dielectric layer, and a second electrode. The first electrode is connected to the memory transistor, and the second electrode is located on a side of the capacitor dielectric layer away from the first electrode; by providing a reference signal line in the memory and connecting the reference signal line to the second electrode, the reference signal line overlaps with the first electrode in both the row direction and the column direction; thus, a reference signal line is connected in parallel outside the capacitor, increasing the capacitance of the memory and improving the data retention ability of the memory. It further includes a plurality of layers of memory cells stacked in the longitudinal Z direction perpendicular to the substrate 102; a word line structure 130 runs through the stacked plurality of memory cells along the longitudinal Z direction. The memory transistors 120 in each memory cell share the word line structure 130, and a semiconductor layer 122 surrounds the sidewall of the word line structure 130. The semiconductor layers 122 in different layers of memory cells are spaced apart in the longitudinal Z direction;

[0180] A word line through hole 208 extends along the longitudinal Z direction, and the word line structure 130 is located in the word line through hole 208;

[0181] A first filling groove 210 is communicated with the word line through hole 208, and both the memory transistor 120 and the memory capacitor 118 are located in the first filling groove 210.

[0182] In one embodiment, the storage transistor includes a gate layer and a semiconductor layer, and further includes an insulating layer 202, which is alternately stacked with the storage unit in the longitudinal direction; the gate layer 124 is in contact with the word line structure 130, and the gate layer 124 is located in the first filling groove 210 between adjacent insulating layers 202. The semiconductor layer 122 covers the top surface and the bottom surface of the gate layer 124 close to the insulating layer 202, and covers the side surface between the top surface and the bottom surface of the gate layer 124.

[0183] In some embodiments, the storage transistor further includes: a gate dielectric layer 126, which is located between the semiconductor layer 122 and the word line structure 130, and conformally covers the surface of the semiconductor layer 122 close to the gate layer 124.

[0184] In some embodiments, the gate dielectric layer covers at least a part of the surface of the word line structure, and the memory further includes:

[0185] A second dielectric layer, which is located in the word line through hole and covers the surface of the gate dielectric layer facing away from the word line structure. Here, the second dielectric layer is equivalent to the nitride layer in the manufacturing method. The nitride layer and the gate dielectric layer cover the side surface of the word line structure, improving the encapsulation effect of the word line structure and preventing water vapor from contacting the word line structure.

[0186] In some embodiments, there is the gate dielectric layer 126 between the semiconductor layer and the word line structure. The side surface of the semiconductor layer close to the word line structure 130 is in contact with the gate dielectric layer, and the top surface and the bottom surface of the semiconductor layer 122 parallel to the substrate are respectively in contact with the second dielectric layer. Here, the second dielectric layer is equivalent to the nitride layer in the manufacturing method. By setting the semiconductor layer in contact with the gate dielectric layer, the distance between the semiconductor layer 122 and the gate layer 124 can be reduced, increasing the gate control ability of the memory.

[0187] In some embodiments, the first electrode 112 is connected to the semiconductor layer 122. The capacitive dielectric layer 114 covers the surface of the first electrode 112 parallel to the substrate and covers the surface of the first electrode 112 facing away from the semiconductor layer 122. The second electrode 116 covers the surface of the capacitive dielectric layer 114 facing away from the first electrode 112.

[0188] In some embodiments, the memory further includes:

[0189] A bit line structure 110, which is located in the first filling groove 210, extends along the column direction, and is connected to the semiconductor layer 122;

[0190] In some embodiments, the bit line structure 110 is covered by the semiconductor layer 122 on the bottom surface close to the substrate 102, the top surface far from the substrate, and the side surfaces connecting the top surface and the bottom surface. The contact area between the bit line structure and the semiconductor layer is increased, the contact resistance is reduced, the writing rate and the reading rate of data in the memory are provided, and the transmission delay of data in the memory is reduced.

[0191] In some embodiments, the first electrode 112 is a solid structure.

[0192] In some embodiments, each layer of memory cells includes a plurality of memory cells arranged in an array in a plane parallel to the substrate 102, and the memory cells in the same layer and the same column are connected to the same bit line structure 110.

[0193] In some embodiments, the memory further includes: a bit line isolation structure 132, which penetrates through the stacked multiple layers of the memory cells along the longitudinal direction Z, extends along the column direction Y, and is located between adjacent bit line structures 110. Exemplarily, the memory transistors and the memory capacitors in the same layer of memory cells are mirror-symmetrical with respect to the bit line isolation structure 132.

[0194] In some embodiments, the memory further includes: a reference signal line 108, which penetrates through the stacked multiple layers of memory cells along the longitudinal direction Z, extends along the column direction Y, is located between the first electrodes of adjacent memory capacitors 118, and is electrically connected to the second electrodes 116 of the memory capacitors 118.

[0195] Exemplarily, the memory cells (the memory transistors and the memory capacitors) in the same layer are mirror-symmetrical with respect to the reference signal line 108.

[0196] In some embodiments, a memory is fabricated using the fabrication method as described above. The fabrication method of this memory forms a first trench and a word line via penetrating the stacked structure including alternately stacked insulating layers and sacrificial layers, laterally etches the sacrificial layer based on the first trench to form a first filling groove, and then forms a bit line structure, a memory transistor, and a memory capacitor in the first filling groove, reducing the stress of the memory, reducing the defects caused by increased stress, avoiding the problem of etching topography, and improving the performance of the memory. Moreover, the stacked multiple layers of memory cells in the memory are fabricated using alternately stacked insulating layers and sacrificial layers, and the fabrication process is simple. For the multiple layers of memory cells stacked longitudinally perpendicular to the substrate, the area of the memory on the substrate is reduced while the storage capacity of the memory remains unchanged, reducing the cost. A memory transistor surrounding the word line via is formed in the first filling groove, avoiding the formation of parasitic transistors in the memory transistor, improving the reading and writing speeds of data in the memory, and further improving the performance of the memory.

[0197] The present disclosure also provides an electronic device, including the memory as described above. The electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device or a smart mobile terminal. The embodiments of the present application do not impose special restrictions on the specific form of the above-mentioned electronic device.

[0198] The technical features of the above-described embodiments may be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0199] The above-described embodiments merely represent several implementation manners of the embodiments of the present disclosure, and the description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the embodiments of the present disclosure, several modifications and improvements can be made, and these all belong to the protection scope of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a memory, characterized in that, The memory includes a word line structure, a bit line structure, and memory cells stacked in a longitudinal direction perpendicular to the substrate. The memory cells include memory transistors and memory capacitors arranged in a row direction. The manufacturing method includes: Providing a substrate and forming a stacked structure on the substrate. The stacked structure includes insulating layers and sacrificial layers alternately stacked along the longitudinal direction. Forming a first trench that penetrates the stacked structure and extends in a column direction in the stacked structure. The row direction and the column direction intersect and are both parallel to the substrate. Forming a word line via hole that penetrates the stacked structure in the stacked structure. The word line via hole and the first trench are spaced apart from each other in the row direction. Laterally etching the sacrificial layer based on the first trench to form a first filling groove. Forming the bit line structure, the memory transistors, and the memory capacitors arranged in sequence along the row direction in the first filling groove, and forming the word line structure in the word line via hole. Wherein, the bit line structure extends in the column direction. The memory transistors are respectively connected to the bit line structure and the memory capacitors. The first filling trench communicates with the word line via hole and the first trench.

2. The preparation method according to claim 1, characterized in that, The word line via hole is formed before laterally etching the sacrificial layer, and then the sacrificial layer is laterally etched based on the first trench and the word line via hole to form the first filling groove.

3. The preparation method according to claim 2, characterized in that, The forming the bit line structure, the memory transistors, and the memory capacitors arranged in sequence along the row direction in the first filling groove includes: Sequentially forming a first conductive material layer, a dielectric material layer, and a second conductive material layer on the inner walls of the word line via hole and the first filling groove. Removing the second conductive material layer, the dielectric material layer, and the first conductive material layer in the word line via hole, and the second conductive material layer in a partial area of the first filling groove close to the word line via hole, to form a second filling groove surrounding the word line via hole, and obtaining a bit line structure and a first electrode composed of the remaining second conductive material layer. Removing the dielectric material layer and the first conductive material layer on the sidewall of the second filling groove, and obtaining a capacitor dielectric layer composed of the dielectric material layer surrounding the first electrode and a second electrode composed of the first conductive material layer surrounding the capacitor dielectric layer. Forming the memory transistors in the second filling groove. Wherein, the memory capacitor includes the first electrode, the second electrode, and the capacitor dielectric layer.

4. The preparation method according to claim 3, wherein, The first filling groove includes a bit line filling groove extending in the column direction. The sequentially forming the first conductive material layer, the dielectric material layer, and the second conductive material layer on the inner walls of the word line via hole and the first filling groove further includes: Sequentially forming the first conductive material layer, the dielectric material layer, and the second conductive material layer on the inner wall of the first trench. The second conductive material layer fills the bit line filling groove. The manufacturing method further includes: Etching and removing the second conductive material layer, the dielectric material layer, and the first conductive material layer in the first trench. Filling and forming a bit line isolation structure in the first trench.

5. The preparation method according to claim 1, characterized in that, Forming the bit line structure, the memory transistor, and the storage capacitor arranged in sequence along the row direction in the first filling groove, and forming the word line structure in the word line through hole, includes: Sequentially forming a first conductive material layer, a dielectric material layer, and a second conductive material layer on the inner walls of the first trench and the first filling groove; Removing the second conductive material layer, the dielectric material layer, and the first conductive material layer in the first trench, and the second conductive material layer in a partial area of the first filling groove close to the first trench, to obtain a first electrode composed of the remaining second conductive material layer; removing the dielectric material layer and the first conductive material layer on the side wall of the first filling groove, to obtain a capacitor dielectric layer composed of the dielectric material layer surrounding the first electrode, and a second electrode composed of the first conductive material layer surrounding the capacitor dielectric layer; forming a channel and a bit line structure of the memory transistor in the first filling groove; wherein, the storage capacitor includes the first electrode, the second electrode, and the capacitor dielectric layer.

6. The preparation method according to claim 5, characterized in that, Forming the word line structure in the word line through hole includes: Sequentially forming a nitride layer and a gate dielectric layer on the side wall of the word line through hole; Wherein, the memory transistor includes the gate dielectric layer.

7. The preparation method according to claim 3, wherein Forming the memory transistor in the second filling groove includes: Sequentially forming a semiconductor layer and a gate layer on the inner wall of the second filling groove, the semiconductor layer surrounding the gate layer; Wherein, the memory transistor includes the semiconductor layer and the gate layer.

8. The preparation method according to claim 7, wherein Sequentially forming a semiconductor layer and a gate layer on the inner wall of the second filling groove includes: Forming a semiconductor material layer on the inner wall of the second filling groove, the semiconductor material layer extending and covering on the inner wall of the word line through hole; Forming a gate material layer on the semiconductor material layer; Etching and removing the gate material layer and the semiconductor material layer in the word line through hole, to obtain the semiconductor layer and the gate layer.

9. A memory, characterized in that, The memory includes: A substrate; At least one layer of memory cells arranged on the substrate; one layer of memory cells includes a plurality of memory cells; the memory cell includes a memory transistor and a storage capacitor arranged along a row direction parallel to the substrate; the storage capacitor includes a first electrode, a capacitor dielectric layer, and a second electrode, the first electrode is connected to the memory transistor, the second electrode is located on a side of the capacitor dielectric layer away from the first electrode; further includes a reference signal line, the reference signal line is connected to the second electrode, and the reference signal line overlaps with the first electrode both in the row direction and the column direction; the column direction is parallel to the substrate and intersects with the row direction.

10. The memory according to claim 9, characterized in that, The reference signal line is grounded.

11. The memory according to claim 10, wherein Includes: Multiple layers of memory cells; The reference signal line penetrates through the multiple layers of memory cells longitudinally perpendicular to the substrate; The reference signal line extends along the column direction and is connected to two adjacent second electrodes in the row direction.

12. The memory according to claim 9, wherein Further includes: A word line structure, longitudinally penetrating through a plurality of the memory cells perpendicular to the substrate, and the memory transistors in each of the memory cells share the word line structure.

13. The memory according to claim 12, wherein Further includes: A word line through hole extends along the longitudinal direction, and the word line structure is located in the word line through hole; A first filling groove is communicated with the word line through hole, and both the storage transistor and the storage capacitor are located in the first filling groove.

14. The memory according to claim 13, wherein, The storage transistor includes a gate layer and a semiconductor layer, and the memory further includes: An insulating layer is alternately stacked with the storage unit in the longitudinal direction; the gate layer is in contact with the word line structure, the gate layer is located in the first filling groove between adjacent insulating layers, and the semiconductor layer covers the top surface and the bottom surface of the gate layer close to the insulating layer and covers the side surface between the top surface and the bottom surface of the gate layer.

15. The memory according to claim 14, wherein The storage transistor further includes: A gate dielectric layer is located between the semiconductor layer and the word line structure.

16. The memory according to claim 15, wherein The gate dielectric layer at least covers a part of the surface of the word line structure, and the memory further includes: A second dielectric layer is located in the word line through hole and covers the surface of the gate dielectric layer facing away from the word line structure.

17. The memory according to claim 16, wherein The first electrode is connected to the semiconductor layer, the capacitive dielectric layer covers the surface of the first electrode parallel to the substrate and covers the surface of the first electrode facing away from the semiconductor layer, and the second electrode covers the surface of the capacitive dielectric layer facing away from the first electrode.

18. The memory according to claim 17, wherein Further includes: A bit line structure is located in the first filling groove, extends along the column direction, and is connected to the semiconductor layer.

19. The memory according to claim 18, wherein, The bottom surface of the bit line structure close to the substrate, the top surface away from the substrate, and the side surface connecting the top surface and the bottom surface are all covered by the semiconductor layer.

20. An electronic device, characterized in that, Includes the memory according to any one of claims 9-19.

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