Memory structure, manufacturing method thereof and operating method thereof

Abstract

The invention provides a memory structure, a manufacturing method of the memory structure and an operating method of the memory structure. The memory structure includes a plurality of insulating layers, a plurality of gate layers, a first doped layer, a plurality of channel layers, a columnar channel, a plurality of second doped layers, a first dielectric layer, a plurality of second dielectric layers, a third dielectric layer and a plurality of fourth dielectric layers. The first doped layer and the columnar channel penetrate through the insulating layers and the gate layers which are alternately stacked, the channel layer is connected to the first doped layer, the channel layer and the insulating layers are alternately stacked, and the second doped layer surrounds the columnar channel and is connected to the channel layer. The first dielectric layer is located between the first doped layer and the gate layer, the second dielectric layer is located between the second doped layer and the gate layer, the third dielectric layer is located between the columnar channel and the second doped layer, and the fourth dielectric layer is located between the channel layer and the gate layer.

Description

Technical Field

[0001] The present disclosure relates to a memory structure, a method for manufacturing a memory structure, and a method for operating a memory structure. Background Art

[0002] Dynamic random access memory (DRAM) has advantages such as high density, low cost, and low power consumption, and thus has been widely used. However, as memory technology gradually approaches the physical limit, traditional DRAM (such as DRAM with one transistor and one capacitor (1T1C)) is facing many severe challenges in development. For example, the size of DRAM is not easily scaled down, the DRAM process becomes more complex, and the aspect ratio of the capacitor increases significantly as the size shrinks. In view of the above, there is a need to provide a new dynamic random access memory and a method for manufacturing the same to overcome the above problems. Summary of the Invention

[0003] The present disclosure provides a memory structure, which includes multiple insulating layers, multiple gate layers, a first doping layer, multiple channel layers, a columnar channel, multiple second doping layers, a third doping layer, a fourth doping layer, a first dielectric layer, multiple second dielectric layers, a third dielectric layer, and multiple fourth dielectric layers. These insulating layers and these gate layers are alternately stacked; the first doping layer penetrates through these insulating layers and these gate layers, and these channel layers are respectively connected to the first doping layer, wherein these channel layers and these insulating layers are alternately stacked. The columnar channel penetrates through these insulating layers and these gate layers, and these second doping layers respectively surround the columnar channel, wherein these second doping layers are respectively connected to these channel layers. The third doping layer is coupled to the columnar channel, and the fourth doping layer is coupled to the columnar channel. The first dielectric layer is disposed between the first doping layer and these gate layers, these second dielectric layers are respectively disposed between these second doping layers and these gate layers, the third dielectric layer is disposed between the columnar channel and these second doping layers, and these fourth dielectric layers are respectively disposed between these channel layers and these gate layers.

[0004] In some embodiments, the memory structure further includes a write bit line disposed on the first doping layer.

[0005] In some embodiments, the third doping layer is disposed under the columnar channel, and the fourth doping layer is disposed on the columnar channel.

[0006] In some embodiments, the memory structure further includes a read bit line disposed on the fourth doping layer.

[0007] In some embodiments, the first doping layer and these second doping layers have a first conductivity type, the third doping layer and the fourth doping layer have a second conductivity type, and the first conductivity type is different from the second conductivity type.

[0008] In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type.

[0009] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

[0010] In some embodiments, these channel layers have the second conductivity type and the columnar channels have the first conductivity type.

[0011] In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type.

[0012] In some embodiments, these channel layers and columnar channels are undoped.

[0013] The present disclosure provides a method of manufacturing a memory structure, which includes the following operations: forming a first hole through an alternating stack of a plurality of insulating layers and a plurality of first gate layers; forming a first dielectric layer covering the sidewalls of the first hole; forming a first doped layer in the first hole; forming a second hole through these insulating layers and these first gate layers, and partially removing these first gate layers exposed from the second hole to form a plurality of recesses; forming a plurality of second dielectric layers in these recesses; forming a plurality of second doped layers covering these second dielectric layers; forming a third dielectric layer in the second hole, covering these insulating layers and these second doped layers; forming columnar channels in the second hole, removing the first dielectric layer, these first gate layers and these second dielectric layers located between the first doped layer and these second doped layers to form a plurality of channels; forming a plurality of channel layers in these channels to connect to the first doped layer and these second doped layers.

[0014] In some embodiments, after forming the columnar channels in the second hole, these channel layers are formed to connect to the first doped layer and these second doped layers.

[0015] In some embodiments, the method of manufacturing the memory structure further includes: after forming these channel layers in these channels, forming a plurality of fourth dielectric layers beside these channel layers; and forming a plurality of second gate layers beside these fourth dielectric layers.

[0016] In some embodiments, the method of manufacturing the memory structure further includes: before forming the second hole through these insulating layers and these first gate layers, forming a third doped layer in the substrate, and forming these insulating layers and these first gate layers on the substrate, wherein the second hole exposes the third doped layer; and doping the top portion of the columnar channels to form a fourth doped layer.

[0017] In some embodiments, the method of manufacturing the memory structure further includes: forming a write bit line on the first doped layer; and forming a read bit line on the fourth doped layer.

[0018] The present disclosure provides an operation method for a memory structure, which includes the following operations: receiving the memory structure of any of the foregoing embodiments, wherein these gate layers, the first doping layer, these channel layers, and these second doping layers form a plurality of write transistors, and these gate layers, these second doping layers, the third doping layer, the fourth doping layer, and the columnar channels form a plurality of read transistors. Performing a write operation, the write operation includes: applying a first voltage to the select gate of these gate layers of these write transistors, wherein the first voltage is higher than the threshold voltage of the select gate; and applying a second voltage to the first doping layer of these write transistors to charge or not charge one of these second doping layers corresponding to the select gate, wherein the second voltage is a positive voltage or 0V.

[0019] In some embodiments, these write transistors are N-type transistors and these read transistors are P-type transistors.

[0020] In some embodiments, the operation method of the memory structure further includes: performing a read operation. The read operation includes: applying a third voltage to the select gate, wherein the third voltage is 0V or lower than the threshold voltage of the select gate; applying a plurality of fourth voltages to the plurality of unselected gates of these gate layers of these write transistors, wherein these fourth voltages are negative voltages; and applying a fifth voltage to the third doping layer, wherein the fifth voltage is a positive voltage.

[0021] In some embodiments, these write transistors are P-type transistors and these read transistors are N-type transistors.

[0022] In some embodiments, the operation method of the memory structure further includes: performing a read operation. The read operation includes: applying a third voltage to the select gate, wherein the third voltage is 0V or lower than the threshold voltage of the select gate; applying a plurality of fourth voltages to the plurality of unselected gates of these gate layers of these write transistors, wherein these fourth voltages are positive voltages; and applying a fifth voltage to the third doping layer, wherein the fifth voltage is a positive voltage. Description of the Drawings

[0023] By reading the following detailed description of the embodiments and referring to the drawings, the present disclosure can be more comprehensively understood.

[0024] Figure 1 is a three-dimensional schematic diagram of a memory structure according to various embodiments of the present disclosure.

[0025] Figure 2 is a cross-sectional schematic diagram of a memory structure according to various embodiments of the present disclosure.

[0026] Figure 3 is along Figure 2 the cross-sectional line A-A' of the cross-sectional schematic diagram.

[0027] Figure 4 is a schematic cross - sectional view along the Figure 2 section line B - B’.

[0028] Figure 5A and Figure 5B is a flowchart of a method for manufacturing a memory structure according to various embodiments of the present disclosure.

[0029] Figures 6A to 6I is a schematic cross - sectional view of an intermediate stage of manufacturing a memory structure according to various embodiments of the present disclosure.

[0030] Figure 7 is a schematic circuit diagram of a memory array according to various embodiments of the present disclosure.

[0031] Figure 8 is a schematic circuit diagram of a memory cell and its surrounding circuitry according to various embodiments of the present disclosure.

[0032] Figure 9 is an I - V graph of a write transistor according to various embodiments of the present disclosure.

[0033] Figure 10 is an I - V graph of a read transistor according to various embodiments of the present disclosure.

[0034] Description of Reference Numerals

[0035] 100: Memory structure

[0036] 110: Substrate

[0037] 120: Gate layer

[0038] 130: Insulating layer

[0039] 500: Manufacturing method

[0040] 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, 536, 538, 540, 542, 544: Operations

[0041] 1400: Memory structure

[0042] 1500: Circuit

[0043] A - A’, B - B’: Section lines

[0044] CC: Columnar channel

[0045] CL: Channel layer

[0046] DL1: First dielectric layer

[0047] DL2: Second dielectric layer

[0048] DL3: The third dielectric layer

[0049] DL4: The fourth dielectric layer

[0050] FG: Floating gate

[0051] G1: The first gate layer

[0052] G2: The second gate layer

[0053] H1: The first hole

[0054] H2: The second hole

[0055] P1: The first part

[0056] P2: The second part

[0057] RBL, RBL0, RBLn: Read bit line

[0058] RP: Recessed part

[0059] RWL, RWL0, RWLn: Read word line

[0060] RT: Read transistor

[0061] MC: Memory cell

[0062] SD1: The first doped layer

[0063] SD2: The second doped layer

[0064] SD3: The third doped layer

[0065] SD4: The fourth doped layer

[0066] SN: Storage node

[0067] STI: Isolation structure

[0068] SW: Sidewall

[0069] T: Channel

[0070] WBL, WBL0, WBLn: Write bit line

[0071] WT: Write transistor

[0072] WWL, WWL0, WWL1, WWLn: Write word line Detailed implementation manners

[0073] The following multiple embodiments are described and disclosed in detail with reference to the accompanying drawings. For clarity of illustration, many practical details will be set forth in the following description. However, it should be understood that these practical details are not intended to limit the present disclosure. That is to say, in some embodiments of the present disclosure, these practical details are not necessary. In addition, to simplify the drawings, some known structures and elements will be shown schematically in the drawings.

[0074] In this document, the use of terms such as first, second, and third to describe various elements, components, regions, layers, and / or blocks is understandable. However, these elements, components, regions, layers, and / or blocks should not be limited by these terms. These terms are only used to distinguish a single element, component, region, layer, and / or block. Therefore, a first element, component, region, layer, and / or block hereinafter may also be referred to as a second element, component, region, layer, and / or block without departing from the spirit of the present disclosure.

[0075] In addition, it should be understood that when element A is referred to as "connected to" or "coupled to" element B, element A can be directly connected to element B or indirectly connected to element B (for example, an intermediate element C (and / or other elements) can be provided between element A and element B).

[0076] The present disclosure provides a memory structure, which is a three-dimensional (3D) dynamic random access memory (DRAM) structure. The memory structure includes a plurality of memory cells, and each memory cell includes a write transistor and a read transistor to form a 2T0C DRAM structure. The memory structure of the present disclosure has a high density of memory cells, so it is beneficial to the size reduction of the memory structure. Moreover, the manufacturing process of the memory structure is simple, so the manufacturing cost can be reduced, and thus the traditional 1T1C DRAM structure can be replaced.

[0077] Figure 1 is a three-dimensional schematic diagram of a memory structure according to various embodiments of the present disclosure. Figure 2 is a cross-sectional schematic diagram of a memory structure according to various embodiments of the present disclosure. Figure 3 is along Figure 2 a cross-sectional schematic diagram taken along the section line A-A'. Figure 4 is along Figure 2 a cross-sectional schematic diagram taken along the section line B-B'. As Figures 1 to 4 shown, the memory structure 100 includes a substrate 110, an isolation structure STI, a multi-layer gate layer 120, a multi-layer insulating layer 130, a first doped layer SD1, a plurality of second doped layers SD2, a multi-layer channel layer CL, a third doped layer SD3, a fourth doped layer SD4, a columnar channel CC, a first dielectric layer DL1, a plurality of second dielectric layers DL2, a third dielectric layer DL3, and a plurality of fourth dielectric layers DL4.

[0078] In some embodiments, the substrate 110 is a semiconductor substrate. In some embodiments, the substrate 110 comprises any suitable semiconductor material and / or semiconductor materials for forming semiconductor structures. Semiconductor materials include, for example, one or more materials such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, germanium, gallium arsenide, other suitable semiconductor materials, or combinations thereof. In some embodiments, the substrate 110 is a silicon substrate. In some embodiments, the gate layer 120 comprises a metal conductive material, a non-metal conductive material, or a combination thereof, such as tungsten, copper, aluminum, gold, silver, other suitable metals, metal alloys, polysilicon, or combinations thereof. In some embodiments, the insulating layer 130 comprises an oxide, a nitride, or a combination thereof, such as silicon dioxide, silicon nitride, or combinations thereof. In some embodiments, the isolation structure STI is a shallow trench isolation (STI).

[0079] Please refer to Figure 1 and Figure 2 as well. The insulating layer 130 and the gate layer 120 are alternately stacked, and the number of the insulating layer 130 and the gate layer 120 can be adjusted arbitrarily and is not limited thereto. The first doped layer SD1 penetrates through the insulating layer 130 and the gate layer 120. The channel layers CL are each connected to the first doped layer SD1, wherein the channel layers CL and the insulating layer 130 are alternately stacked. The columnar channels CC penetrate through the insulating layer 130 and the gate layer 120. As Figure 2 and Figure 3 shown, the second doped layers SD2 each surround the columnar channels CC, wherein the second doped layers SD2 are each connected to the channel layers CL. Therefore, the gate layer 120, the first doped layer SD1, the channel layers CL, and the second doped layers SD2 form a plurality of write transistors. The gate layer 120 can also be referred to as a control gate. As Figure 2 shown, the first doped layer SD1 includes a first portion P1 and a second portion P2 that are connected to each other, wherein the first portion P1 penetrates through the insulating layer 130 and the gate layer 120, and the second portion P2 is located in the substrate 110. As Figure 3 shown, each gate layer 120 includes a first gate layer G1 and a second gate layer G2. The first gate layer G1 surrounds the first doped layer SD1, the second doped layer SD2, and the columnar channels CC. The second gate layer G2 is located on both sides of the channel layers CL. In some embodiments, the first doped layer SD1 is a source, and the second doped layer SD2 is a drain. In other embodiments, the first doped layer SD1 is a drain, and the second doped layer SD2 is a source.

[0080] Please continue to refer to Figure 2 and Figure 3, the third doped layer SD3 is coupled to the columnar channel CC, and the fourth doped layer SD4 is coupled to the columnar channel CC. In some embodiments, as Figure 2 shown, the third doped layer SD3 is disposed under the columnar channel CC, and the fourth doped layer SD4 is disposed on the columnar channel CC, but the arrangement is not limited thereto. In some embodiments, the third doped layer SD3 is the source electrode, and the fourth doped layer SD4 is the drain electrode. In other embodiments, the third doped layer SD3 is the drain electrode, and the fourth doped layer SD4 is the source electrode. The gate layer 120, the second doped layer SD2, the third doped layer SD3, the fourth doped layer SD4, and the columnar channel CC form a plurality of read transistors. As Figure 2 shown, these read transistors are connected to each other longitudinally. As Figure 3 shown, the columnar channel CC of the read transistor is surrounded by the second doped layer SD2 and the gate layer 120, and the second doped layer SD2 and the gate layer 120 serve as the gate of the read transistor. The second doped layer SD2 is annular. A write operation can be performed by applying a gate voltage to a write transistor and applying a voltage or no voltage to the first doped layer SD1 to make the corresponding second doped layer SD2 surrounding the columnar channel CC have a high potential or a low potential. Therefore, data 1 or data 0 is written into the read transistor. The second doped layer SD2 can store charges and is rechargeable or dischargeable. The potential of the second doped layer SD2 can be regulated by charging or discharging the second doped layer SD2. The second doped layer SD2 can also be referred to as a storage node SN (storage node, SN), a floating gate (floating gate, FG), or a gate node. The operation method of the memory structure will be further described with a circuit diagram later.

[0081] As Figures 2 to 4 shown, the first dielectric layer DL1 is disposed between the first doped layer SD1 and the gate layer 120 and between the first doped layer SD1 and the insulating layer 130, so the gate layer 120 and the first doped layer SD1 are electrically isolated. The second dielectric layer DL2 is disposed between the second doped layer SD2 and the gate layer 120 respectively, so the gate layer 120 and the second doped layer SD2 are electrically isolated. The third dielectric layer DL3 is disposed between the columnar channel CC and the second doped layer SD2 and between the columnar channel CC and the insulating layer 130, so the columnar channel CC and the second doped layer SD2 are electrically isolated. The third dielectric layer DL3 is annular. The fourth dielectric layer DL4 is disposed between the channel layer CL and the gate layer 120 respectively, so the gate layer 120 and the channel layer CL are electrically isolated. Please refer to Figure 1 and Figure 2。In some embodiments, the third dielectric layer DL3 is disposed between the fourth doped layer SD4 and one of the insulating layers 130. In some embodiments, the first dielectric layer DL1, the second dielectric layer DL2, the third dielectric layer DL3, and the fourth dielectric layer DL4 each include a gate oxide. In some embodiments, the first dielectric layer DL1, the second dielectric layer DL2, the third dielectric layer DL3, and the fourth dielectric layer DL4 each include silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, other suitable high-k dielectric materials, or combinations thereof.

[0082] Please refer again to Figure 2 and Figure 3 。In some embodiments, the first doped layer SD1 and the second doped layer SD2 have a first conductivity type, and the third doped layer SD3 and the fourth doped layer SD4 have a second conductivity type, where the first conductivity type is different from the second conductivity type. In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. The write transistor including the first doped layer SD1 and the second doped layer SD2 is an N-type transistor, such as an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET), and the read transistor including the third doped layer SD3 and the fourth doped layer SD4 is a P-type transistor, such as a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET). In some embodiments, the channel layer CL has the second conductivity type, and the columnar channel CC has the first conductivity type. In other embodiments, the channel layer CL and the columnar channel CC are undoped. In some embodiments, the first doped layer SD1 and the second doped layer SD2 are N+ doped regions, the channel layer CL is a P- doped region or an undoped silicon layer, the third doped layer SD3 and the fourth doped layer SD4 are P+ doped regions, and the columnar channel CC is an N- doped region.

[0083] In other embodiments, the first conductivity type is P-type and the second conductivity type is N-type. The write transistor including the first doped layer SD1 and the second doped layer SD2 is a P-type transistor, such as a PMOSFET, and the read transistor including the third doped layer SD3 and the fourth doped layer SD4 is an N-type transistor, such as an NMOSFET. In some embodiments, the channel layer CL has the second conductivity type, and the columnar channel CC has the first conductivity type. In some embodiments, the channel layer CL and the columnar channel CC are undoped.

[0084] In some embodiments, the materials of the channel layer CL and the columnar channels CC each include silicon, germanium, polysilicon, semiconductor oxides (such as indium oxide (In2O3), indium gallium zinc oxide (IGZO), indium tin oxide (ITO)), or other suitable group III-V materials.

[0085] The present disclosure provides a method for manufacturing a memory structure. Please refer to Figure 3 and Figures 5A to 6I . Figure 5A and Figure 5B are flowcharts of a method 500 for manufacturing a memory structure according to various embodiments of the present disclosure. The manufacturing method 500 includes operations 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, 536, 538, 540, 542, and 544. Figures 6A to 6I is a cross-sectional schematic view of an intermediate stage of manufacturing a memory structure according to various embodiments of the present disclosure. Subsequently, Figures 6A to 6I and Figure 3 will be used to illustrate the above operations 512 to 544. Although the following uses a series of operations or steps to illustrate the methods disclosed herein, the order shown by these operations or steps should not be construed as a limitation of the present disclosure. For example, certain operations or steps may be performed in a different order and / or simultaneously with other steps. In addition, not all of the shown operations, steps, and / or features must be performed to implement the embodiments of the present disclosure. In addition, each operation or step described herein may include several sub-steps or actions.

[0086] In operation 512, as Figure 6A shown, a first portion P1 of a first doped layer SD1 and a third doped layer SD3 are formed in a substrate 110. The first portion P1 of the first doped layer SD1 and the third doped layer SD3 are electrically isolated by an isolation structure STI embedded in the substrate 110. In some embodiments, the first portion P1 of the first doped layer SD1 and the third doped layer SD3 are each formed by doping a portion of the substrate 110. In operation 514, as Figure 6A shown, a multi-layer insulating layer 130 and a multi-layer first gate layer G1 are formed alternately stacked on the substrate 110. In operation 516, as Figure 6A shown, a first hole H1 is formed through the insulating layer 130 and the first gate layer G1 to expose the first portion P1 of the first doped layer SD1. In some embodiments, the first hole H1 is formed by an etching process.

[0087] In operation 518, asFigure 6B As shown, a first dielectric layer DL1 is formed to cover the sidewall SW of the first hole H1. In operation 520, as Figure 6B shown, a second portion P2 of the first doped layer SD1 is formed in the first hole H1. In some embodiments, the second portion P2 of the first doped layer SD1 is formed by a deposition process. In some embodiments, the first doped layer SD1 has a first conductivity type, the third doped layer SD3 has a second conductivity type, and the first conductivity type is different from the second conductivity type. In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

[0088] In operation 522, as Figure 6C shown, a second hole H2 is formed to penetrate through the insulating layer 130 and the first gate layer G1. The second hole H2 exposes the third doped layer SD3. In some embodiments, the second hole H2 is formed by an etching process. In operation 524, as Figure 6D shown, a part of the first gate layer G1 exposed from the second hole H2 is removed. After operation 524, the sidewall of the second hole H2 has a plurality of recessed portions RP. In some embodiments, removing a part of the first gate layer G1 is performed by a wet etching process.

[0089] In operation 526, as Figure 6E shown, a plurality of second dielectric layers DL2 are formed in the recessed portions RP to cover the partially removed first gate layer G1. Specifically, the second dielectric layers DL2 are each formed in the recessed portions RP and do not fill the recessed portions RP. In operation 528, as Figure 6F shown, a plurality of second doped layers SD2 are formed to cover the second dielectric layers DL2. Specifically, the second doped layers SD2 are each formed in the recessed portions RP and fill the recessed portions RP. In operation 530, as Figure 6F shown, a third dielectric layer DL3 is formed in the second hole H2 to cover the insulating layer 130 and the second doped layer SD2. The third dielectric layer DL3 does not fill the second hole H2. In operation 532, as Figure 6F shown, a columnar channel CC is formed in the second hole H2. The columnar channel CC fills the second hole H2.

[0090] In operation 534, as Figure 6G shown, the first dielectric layer DL1, the first gate layer G1, and the second dielectric layer DL2 located between the first doped layer SD1 and the second doped layer SD2 are removed to form a plurality of channels T. Specifically, a plurality of portions of the first dielectric layer DL1, a plurality of portions of the first gate layer G1, and a plurality of portions of the second dielectric layer DL2 are removed to form the channels T. In operation 536, as Figure 6HAs shown, a multi-layer channel layer CL is formed in the channel T to connect to the first doped layer SD1 and the second doped layer SD2. Please refer to the cross-section along the section line A-A' Figure 3 . In some embodiments, the channel layer CL is formed by a deposition process. In some embodiments, as Figure 6F shown in the figures to Figure 6H shown in the figures, operations 528, 530, 532, 534, and 536 are sequentially performed. After forming the columnar channel CC in the second hole H2, a channel layer CL is formed to connect to the first doped layer SD1 and the second doped layer SD2. In other embodiments, after forming the channel layer CL to connect to the first doped layer SD1 and the second doped layer SD2, the columnar channel CC is formed in the second hole H2. In operation 538, as Figure 3 shown, a plurality of fourth dielectric layers DL4 are formed beside the channel layer CL. In operation 540, as Figure 3 shown, a plurality of second gate layers G2 are formed beside the fourth dielectric layers DL4. In operation 542, as Figure 6H shown, the top portion of the columnar channel CC is doped to form a fourth doped layer SD4.

[0091] In operation 544, as Figure 6I shown, a write bit line WBL is formed on the first doped layer SD1 and a read bit line RBL is formed on the fourth doped layer SD4. Figure 6I The memory structure 1400 of Figure 2 differs from the memory structure 100 of

[0092] in that the memory structure 1400 further includes a write bit line WBL disposed on the first doped layer SD1 and a read bit line RBL disposed on the fourth doped layer SD4. Figure 6I Please refer to Figure 7 . In the memory structure 1400, the gate layer 120, the first doped layer SD1, the channel layer CL, and the second doped layer SD2 form a plurality of write transistors. In addition, the gate layer 120, the second doped layer SD2, the third doped layer SD3, the fourth doped layer SD4, and the columnar channel CC form a plurality of read transistors. Figure 8 is a circuit schematic diagram of a memory array according to various embodiments of the present disclosure. The circuit 1500 is an equivalent circuit schematic diagram of the memory structure 1400. Figure 7 is a circuit schematic diagram of a memory cell MC and its surrounding circuits according to various embodiments of the present disclosure. The memory cell MC includes a write transistor WT and a read transistor RT. It can be seen that

[0093] Please refer to Figure 7 , the memory array includes a plurality of write word lines (WWL), a plurality of write bit lines (WBL), a plurality of read word lines (RWL) and a plurality of read bit lines (RBL). The write word lines include write word lines WWL0, WWL1...WWLn. The write bit lines include write bit lines WBL0...WBLn. The read word lines include read word lines RWL0...RWLn. The read bit lines include read bit lines RBL0...RBLn. The write word lines and the write bit lines are arranged alternately. Figure 6I As shown, the read transistors are connected to each other in the vertical direction, so in circuit 1500, the read word line RWL0 and the read bit line RBL0 are connected to the first and last of the read transistors.

[0094] Please also refer to Figure 6I and Figure 8 , Figure 8 14 is a schematic diagram of an equivalent circuit of a memory cell in the memory structure 1400. The memory cell MC includes a write transistor WT and a read transistor RT. The write transistor WT is coupled to the write word line WWL, and the first doped layer SD1 is coupled to the write bit line WBL. A second doped layer SD2 serves as a storage node SN of the read transistor RT, and the storage node SN is also a floating gate FG. The read transistor RT is coupled to the read word line RWL and the read bit line RBL.

[0095] Please also refer to Figures 6I to 8 . The write operation includes the following operations. A first voltage is applied to a selection gate of the gate layer 120 of the plurality of write transistors. The first voltage is higher than the threshold voltage of the selection gate. The gate layer 120 includes a selection gate and a plurality of unselected gates, wherein the selection gate is a gate to which the first voltage is applied, and the unselected gate is a gate to which the first voltage is not applied. In other words, the first voltage is applied only to the selected write word line, and the first voltage is not applied to other write word lines. A second voltage is applied to the first doping layer SD1 of these write transistors to charge or not charge one of the corresponding selection gates in the second doping layer SD2, wherein the second voltage is a positive voltage or 0V.

[0096] Please refer to Figure 8 The memory cell MC of the writing transistor WT is a memory cell MC. The logic state of the memory cell MC depends on whether the storage node SN of the reading transistor RT stores charge. In other words, the logic state depends on whether the storage node SN is at a high potential or a low potential. In some embodiments, the writing transistor WT is an N-type transistor and the reading transistor RT is a P-type transistor. Figure 9It is the current-voltage graph of a write transistor according to various embodiments of the present disclosure, where the write transistor is an N-type transistor. When a write operation is performed, the gate voltage is higher than the threshold voltage, and the write transistor WT is in an on state. When a read operation is performed, the gate voltage is 0V or lower than the threshold voltage, and the write transistor WT is in an off state. Figure 10 It is the current-voltage graph of a read transistor according to various embodiments of the present disclosure, where the read transistor is a P-type transistor. The magnitude of the current depends on the voltage level of the storage node SN of the read transistor RT. In Figure 10 the current higher than I sense is I read1 , and I read1 corresponds to data 1. The current lower than I sense is I read0 , and I read0 corresponds to data 0.

[0097] When writing data 0 to a P-type transistor, a first voltage is applied to one of the gate layers 120 of the N-type transistor, and a second voltage (positive voltage) is applied to the first doped layer SD1 of the N-type transistor. Thus, the storage node SN (second doped layer SD2) of the P-type transistor is charged, causing the storage node SN to be at a high potential. When the storage node SN of the P-type transistor is at a high potential, the P-type transistor is in an off state. Therefore, during a read operation, no current flows through the P-type transistor or only a current less than I sense flows through the P-type transistor.

[0098] When writing data 1 to a P-type transistor, a first voltage is applied to one of the gate layers 120 of the N-type transistor, and a second voltage (0V) is applied to the first doped layer SD1 of the N-type transistor. Since the storage node SN (second doped layer SD2) of the P-type transistor is not charged, the storage node SN is at a low potential. When the storage node SN of the P-type transistor is at a low potential, the P-type transistor is in an on state. Therefore, during a read operation, a current of the P-type transistor will be measured, such as a current higher than I sense .

[0099] Please refer to Figures 6I to 8 and Figure 10. In some embodiments, the method of operating the memory structure further includes: performing a read operation. In the memory structure 1400, the write transistor is an N-type transistor and the read transistor is a P-type transistor. The read operation includes: applying a third voltage to the select gate of the N-type transistor, where the third voltage is 0V or lower than the threshold voltage of the select gate. Thus, the select gate is in the off state. Applying a plurality of fourth voltages to the plurality of unselected gates of the gate layer 120 of the N-type transistor, where the fourth voltages are negative voltages to turn the unselected gates off. Applying a fifth voltage to the third doped layer SD3 of the P-type transistor, where the fifth voltage is a positive voltage, thereby measuring the current value of the P-type transistor. If the current value is higher than I sense , it can be known that the P-type transistor stores data 1. If the current value is lower than I sense , it can be known that the P-type transistor stores data 0.

[0100] Next, an example embodiment is used to illustratively describe the method of operating the memory structure. Please also refer to Figure 6I 、 Figure 7 and Table 1 below. In the memory array, the write transistor is an N-type transistor and the read transistor is a P-type transistor. When writing data 0, a voltage of 3V is applied to the selected write word line and write bit line respectively, and no voltage is applied to the unselected write word lines, read word lines, and read bit lines. When writing data 1, a gate voltage of 3V is applied to the selected write word line, and no voltage is applied to the unselected write word lines, write bit lines, read word lines, and read bit lines. When reading, no voltage is applied to the selected write word line to turn off the write transistor coupled to the selected write word line. A negative voltage is applied to the unselected write word lines for the following two purposes. Purpose (1) is to turn off the write transistors coupled to the unselected write word lines. Purpose (2) is as follows. From Figure 6I , it can be seen that these read transistors on the right are adjacent to the gate layer 120, so they will also be controlled by the negative voltage. Since the read transistors are P-type transistors, the channels of these read transistors are in the on state, allowing current to flow through. In addition, when reading, a voltage of 1V is applied to the read word line, and the magnitude of the current depends on the level of the storage node voltage of the read transistor.

[0101] Table 1

[0102] Write data 0 Write data 1 Read Selected write word line 3V 3V 0V Unselected write word line 0V 0V -3V Write bit line 3V 0V 0V Read word line 0V 0V 1V Read bit line 0V 0V 0V

[0103] Please also refer to Figures 6I to 8 and Figure 10. In other embodiments, the write transistor is a P-type transistor and the read transistor is an N-type transistor. The operation principle of this embodiment can be inferred from the principle of the foregoing embodiment (where the write transistor is an N-type transistor and the read transistor is a P-type transistor), and will not be elaborated here. In some embodiments, the operation method of the memory structure further includes: performing a read operation. The read operation includes: applying a third voltage to the select gate of the P-type transistor, where the third voltage is 0V or lower than the threshold voltage of the select gate. Thus, the select gate is in the off state. Applying a plurality of fourth voltages to the plurality of non-select gates of the gate layer 120 of the P-type transistor. The fourth voltage is a positive voltage, so the non-select gates are in the off state. Applying a fifth voltage to the third doped layer SD3 of the N-type transistor, where the fifth voltage is a positive voltage, thereby measuring the current value of the N-type transistor.

[0104] According to the above, the present disclosure provides a memory structure, a manufacturing method thereof, and an operation method thereof. In the memory structure, the read transistors are connected to each other longitudinally, so that the density of memory cells can be increased, which is beneficial to the size reduction of the memory structure. Moreover, the manufacturing method of the present disclosure has a simple process flow, so the manufacturing cost can be reduced.

[0105] Although the present disclosure has been described in considerable detail with reference to certain embodiments, there may be other embodiments. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0106] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the claims.

Claims

1. A memory structure comprising: Multiple insulating layers and multiple gate layers are alternately stacked; a first doped layer, penetrating the insulating layers and the gate layers; A plurality of channel layers, each connected to the first doped layer, wherein the channel layers and the insulating layers are alternately stacked; A columnar channel penetrates the insulating layers and the gate layers; A plurality of second doped layers, each surrounding the columnar channel, wherein each of the second doped layers is connected to the channel layers; a third doped layer coupled to the columnar channel; a fourth doped layer coupled to the columnar channel; a first dielectric layer disposed between the first doped layer and the gate layers; A plurality of second dielectric layers, each disposed between the second doped layers and the gate layers; a third dielectric layer disposed between the columnar channel and the second doped layers; as well as A plurality of fourth dielectric layers are respectively disposed between the channel layers and the gate layers. 2 . The memory structure according to claim 1 , further comprising a write bit line disposed on the first doped layer. 3 . The memory structure according to claim 1 , wherein the third doped layer is disposed under the columnar channel, and the fourth doped layer is disposed on the columnar channel. 4 . The memory structure according to claim 3 , further comprising a read bit line disposed on the fourth doped layer. 5 . The memory structure according to claim 1 , wherein the first doped layer and the second doped layers have a first conductivity type, the third doped layer and the fourth doped layer have a second conductivity type, and the first conductivity type is different from the second conductivity type. The memory structure according to claim 5 , wherein the first conductivity type is N type, and the second conductivity type is P type. 7 . The memory structure according to claim 5 , wherein the first conductivity type is P type, and the second conductivity type is N type. 8 . The memory structure according to claim 5 , wherein the channel layers have the second conductivity type, and the columnar channel has the first conductivity type. 9 . The memory structure according to claim 8 , wherein the first conductivity type is N type, and the second conductivity type is P type.

10. The memory structure of claim 1, wherein the channel layers and the pillar channel are undoped.

11. A method for manufacturing a memory structure, comprising: Forming a first hole penetrating the alternately stacked multiple insulating layers and multiple first gate layers; forming a first dielectric layer to cover a side wall of the first hole; forming a first doped layer in the first hole; Forming a second hole penetrating through the insulating layers and the first gate layers; Partially removing the first gate layers exposed from the second hole to form a plurality of recessed portions; forming a plurality of second dielectric layers in the recessed portions; forming a plurality of second doped layers to cover the second dielectric layers; forming a third dielectric layer in the second hole to cover the insulating layers and the second doped layers; forming a columnar channel in the second hole; removing the first dielectric layer, the first gate layers and the second dielectric layers between the first doped layer and the second doped layers to form a plurality of channels; as well as A plurality of channel layers are formed in the channels to connect to the first doping layer and the second doping layers. 12 . The method for manufacturing a memory structure according to claim 11 , wherein after forming the columnar channel in the second hole, the channel layers are formed to connect to the first doping layer and the second doping layers.

13. The method for manufacturing a memory structure according to claim 11, further comprising: After forming the channel layers in the channels, forming a plurality of fourth dielectric layers beside the channel layers; as well as A plurality of second gate layers are formed beside the fourth dielectric layers.

14. The method for manufacturing a memory structure according to any one of claims 11 to 13, further comprising: Before forming the second hole penetrating the insulating layers and the first gate layers, forming a third doped layer in a substrate, and forming the insulating layers and the first gate layers on the substrate, wherein the second hole exposes the third doped layer; and A top portion of the columnar channel is doped to form a fourth doped layer.

15. The method for manufacturing a memory structure according to claim 14, further comprising: forming a write bit line on the first doped layer; as well as A read bit line is formed on the fourth doped layer.

16. A method for operating a memory structure, comprising: Receive the memory structure according to claim 1, wherein the gate layers, the first doped layers, the channel layers and the second doped layers form a plurality of write transistors, and the gate layers, the second doped layers, the third doped layers, the fourth doped layers and the pillar channel form a plurality of read transistors; as well as Performing a write operation, the write operation comprising: Applying a first voltage to a selection gate of the gate layers of the write transistors, wherein the first voltage is higher than a threshold voltage of the selection gate; as well as A second voltage is applied to the first doping layer of the write transistors to charge or uncharge one of the second doping layers corresponding to the select gate, wherein the second voltage is a positive voltage or 0V. 17 . The operating method of the memory structure according to claim 16 , wherein the write transistors are N-type transistors, and the read transistors are P-type transistors.

18. The method for operating the memory structure according to claim 17, further comprising: Performing a read operation, the read operation comprising: Applying a third voltage to the selection gate, wherein the third voltage is 0V or lower than the threshold voltage of the selection gate; applying a plurality of fourth voltages to a plurality of unselected gates of the gate layers of the write transistors, wherein the fourth voltages are negative voltages; and A fifth voltage is applied to the third doped layer, wherein the fifth voltage is a positive voltage.

19. The operating method of the memory structure according to claim 16, wherein the write transistors are P-type transistors, and the read transistors are N-type transistors.

20. The method for operating the memory structure according to claim 19, further comprising: Performing a read operation, the read operation comprising: Applying a third voltage to the selection gate, wherein the third voltage is 0V or lower than the threshold voltage of the selection gate; applying a plurality of fourth voltages to a plurality of unselected gates of the gate layers of the write transistors, wherein the fourth voltages are positive voltages; and A fifth voltage is applied to the third doped layer, wherein the fifth voltage is a positive voltage.

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