Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a semiconductor substrate, a stacking structure, a bit line and a capacitor structure. The stacked structure is stacked on the semiconductor substrate in the vertical direction. The stacked structure comprises separation layers and composite layers which are alternately stacked in the vertical direction. The composite layer comprises an active layer. The active layer includes a channel region, a source region, and a drain region. The source region and the drain region are located at the two opposite ends of the channel region in the first direction respectively. The bit line is located on one side of the stack structure in the first direction and penetrates through the stack structure in the vertical direction. The bit line contacts an end surface and a portion of the side surface of the source region. The capacitor structure comprises a first polar plate. The first plate contacts a portion of a side of the drain region.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor technology, traditional two-dimensional (2D) memories are facing increasingly severe challenges in terms of integration density and performance. Due to the gradual failure of Moore's Law, it has become increasingly difficult to solely rely on reducing the transistor size to improve the storage density and performance. To break through this bottleneck, three-dimensional (3D) memory technology has emerged and become an important development direction in the field of semiconductor storage.

[0003] By stacking memory cells in the vertical direction, 3D memories significantly increase the storage density while reducing the chip area. Compared with the traditional 2D planar structure, 3D memories can integrate more memory cells per unit area, thereby meeting the requirements for high-capacity and high-performance memories in the big data era. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

[0005] The technical solution of the embodiments of the present disclosure is implemented as follows:

[0006] Embodiments of the present disclosure provide a semiconductor structure, which includes: a semiconductor substrate, a stacked structure, a bit line, and a capacitor structure; the stacked structure is stacked on the semiconductor substrate in the vertical direction; the stacked structure includes: a separation layer and a composite layer alternately stacked in the vertical direction; the composite layer includes: an active layer; the active layer includes: a channel region, a source region, and a drain region; the source region and the drain region are respectively located at opposite ends of the channel region along a first direction; the first direction is parallel to the top surface of the semiconductor substrate; the bit line is located on one side of the stacked structure along the first direction and penetrates the stacked structure in the vertical direction; the bit line contacts the end face and part of the side face of the source region; the capacitor structure includes: a first electrode plate; the first electrode plate is located in the composite layer; the first electrode plate contacts part of the side face of the drain region.

[0007] In some embodiments of the present disclosure, the length of the contact surface between the first electrode plate and the drain region along the first direction is equal to the length of the first electrode plate along the first direction.

[0008] In some embodiments of the present disclosure, the length of the drain region along the first direction is greater than the length of the source region along the first direction.

[0009] In some embodiments of the present disclosure, the composite layer further includes: a word line and a gate dielectric layer; the word line extends in a second direction; the second direction is parallel to the top surface of the semiconductor substrate; the gate dielectric layer covers at least a part of three side surfaces of the word line; wherein, a first part of the gate dielectric layer is between the channel layer and the word line; a second part of the gate dielectric layer is between the bit line and the word line; a third part of the gate dielectric layer is between the first electrode plate and the word line.

[0010] In some embodiments of the present disclosure, the thickness of the second part of the gate dielectric layer in the vertical direction, and the thickness of the third part of the gate dielectric layer in the vertical direction are both greater than or equal to the thickness of the word line in the vertical direction.

[0011] In some embodiments of the present disclosure, the material of the active layer includes: indium gallium zinc oxide (IGZO).

[0012] Embodiments of the present disclosure further provide a method for forming a semiconductor structure, the method for forming the semiconductor structure includes: providing a semiconductor substrate; forming a stacked structure on the semiconductor substrate; the stacked structure is stacked on the semiconductor substrate in a vertical direction; the stacked structure includes: a spacer layer and a composite layer stacked alternately in the vertical direction; the composite layer includes: an active layer; the active layer includes: a channel region, a source region, and a drain region; the source region and the drain region are respectively located at two opposite ends of the channel region along a first direction; the first direction is parallel to the top surface of the semiconductor substrate; forming a bit line; the bit line is located on one side of the stacked structure along the first direction and penetrates the stacked structure in the vertical direction; the bit line contacts the end face and part of the side surface of the source region; forming a capacitor structure; the capacitor structure includes: a first electrode plate; the first electrode plate is located in the composite layer; the first electrode plate contacts part of the side surface of the drain region.

[0013] In some embodiments of the present disclosure, the method for forming the stacked structure includes: forming a stacked material layer on the semiconductor substrate; the stacked material layer includes: a sacrificial layer and the spacer layer stacked alternately in the vertical direction; forming a patterned first isolation structure; the first isolation structure penetrates the stacked material layer in the vertical direction; forming a first etching hole and a second etching hole; the first etching hole and the second etching hole penetrate the stacked material layer in the vertical direction; the remaining stacked material layer represents the pattern of the channel layer; selectively etching the exposed sacrificial layer to remove the sacrificial layer and form a first space; sequentially depositing composite layer materials in the first space; etching the side walls of the first etching hole and the side walls of the second etching hole to cut off the connection parts of the composite layer materials in different layers and form the composite layer.

[0014] In some embodiments of the present disclosure, the method of forming the bit line includes: filling sacrificial materials in the first etching hole and the second etching hole; removing the sacrificial materials in the first etching hole to expose the composite layer; selectively etching a part of the composite layer exposed by the first etching hole to make the side wall of the first etching hole protrude towards the composite layer; filling a conductive material in the first etching hole to form the bit line.

[0015] In some embodiments of the present disclosure, the capacitor structure further includes: a dielectric layer and a second electrode plate; the method of forming the capacitor structure includes: selectively etching a part of the composite layer exposed by the second etching hole to form a second space; the second space exposes a part of the side surface of the drain region; in the second space, the first electrode plate, the dielectric layer, and the second electrode plate are sequentially deposited and formed; in the remaining second space and the second etching hole, a conductive material is filled to form a capacitor connection structure; the capacitor connection structure connects the second electrode plates of different layers.

[0016] It can be seen that in the embodiments of the present disclosure, the bit line forms an electrical contact with the source region, and the end surface and a part of the side surface of the bit line contacting the source region. That is to say, the bit line protrudes towards the active layer, so that the bit line not only forms an electrical contact with the end surface of the source region, but also forms an electrical contact with a part of the side surface of the source region. In this way, on the one hand, the contact area between the bit line and the source region is increased, so that the contact resistance between the bit line and the source region can be effectively reduced, and the power consumption can be reduced; on the other hand, the protruding part of the bit line has a larger cross-sectional area, so that the resistance of the bit line can be reduced, and the power consumption can be reduced. Description of the Drawings

[0017] Figure 1 is a circuit schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure;

[0018] Figure 2 is a structural schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure Figure 1 ;

[0019] Figure 3 is a structural schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure Figure 2 ;

[0020] Figure 4 is a structural schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure Figure 3 ;

[0021] Figure 5 is a structural schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure Figure 4 ;

[0022] Figure 6 Structural schematic of the semiconductor structure provided by the embodiments of the present disclosure Figure 5 ;

[0023] Figure 7 Structural schematic of the method for forming the semiconductor structure provided by the embodiments of the present disclosure Figure 1 ;

[0024] Figure 8 Structural schematic of the method for forming the semiconductor structure provided by the embodiments of the present disclosure Figure 2 ;

[0025] Figure 9 Structural schematic of the method for forming the semiconductor structure provided by the embodiments of the present disclosure Figure 3 ;

[0026] Figure 10 Structural schematic of the method for forming the semiconductor structure provided by the embodiments of the present disclosure Figure 4 ;

[0027] Figure 11 Structural schematic of the method for forming the semiconductor structure provided by the embodiments of the present disclosure Figure 5 ;

[0028] Figure 12 Structural schematic of the method for forming the semiconductor structure provided by the embodiments of the present disclosure Figure 6 ;

[0029] Figure 13 Structural schematic of the method for forming the semiconductor structure provided by the embodiments of the present disclosure Figure 7 ;

[0030] Figure 14 Structural schematic of the method for forming the semiconductor structure provided by the embodiments of the present disclosure Figure 8 ;

[0031] Figure 15 Structural schematic of the method for forming the semiconductor structure provided by the embodiments of the present disclosure Figure 9 ;

[0032] Figure 16 Structural schematic of the method for forming the semiconductor structure provided by the embodiments of the present disclosure Figure 10 ;

[0033] Figure 17 Structural schematic of the method for forming the semiconductor structure provided by the embodiments of the present disclosure Figure 10 One;

[0034] Figure 18 Structural schematic of the method for forming the semiconductor structure provided by the embodiments of the present disclosure Figure 10 Two;

[0035] Figure 19 Structural schematic of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 10 Three;

[0036] Figure 20 Structural schematic of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 10 Four. Detailed implementation manners

[0037] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on the present disclosure. All other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0038] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0039] If similar descriptions such as "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" only distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged in a specific order or sequence when permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0040] In this document, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be intermediate layers / components between them. Additionally, in one orientation, a layer / component is "on" another layer / component, and when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0042] Figure 1 The circuit schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure is shown.

[0043] Reference Figure 1, a three-dimensional semiconductor memory device may include a cell array CA, and the cell array CA includes a plurality of sub-cell arrays SCA. The sub-cell arrays SCA may be arranged along a second direction D2. Among them, each sub-cell array SCA may include: a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cell transistors MCT. One memory cell transistor MCT may be between one word line WL and one bit line BL.

[0044] Continue to refer to Figure 1 , each bit line BL may be a conductive pattern extending in a direction perpendicular to the substrate (third direction D3). The bit lines BL in one sub-cell array SCA may be arranged in a first direction D1. The bit lines BL may be commonly connected to the memory cell transistors MCT stacked along the third direction D3.

[0045] Continue to refer to Figure 1 , the word line WL may be a conductive pattern stacked on the substrate in the third direction D3. Each word line WL may extend in the second direction D2, and each word line WL may be connected to the gates of the memory cell transistors MCT in the sub-cell array SCA.

[0046] Continue to refer to Figure 1 , the gate of the memory cell transistor MCT may be connected to the word line WL, the source of the memory cell transistor MCT may be connected to the bit line BL, and the drain of the memory cell transistor MCT may be connected to the data storage element DS. In some embodiments, the data storage element DS may be a capacitor, and the drain of the memory cell transistor MCT may be connected to the first electrode of the capacitor.

[0047] It should be noted that Figures 2 to 6 is a schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure. Among them, Figure 2 is a three-dimensional schematic diagram of the semiconductor structure, Figure 3 is a schematic cross-sectional structure diagram along the cutting line A-A1 in Figure 2 , Figure 4 is a schematic cross-sectional structure diagram along the cutting line B-B1 in Figure 3 , Figure 5 is a schematic cross-sectional structure diagram along the cutting line C-C1 in Figure 3 , Figure 6 is Figure 2 a three-dimensional schematic diagram of the local structure in

[0048] It should also be noted that in the schematic diagram of the structure provided by the embodiments of the present disclosure, the vertical direction Z is perpendicular to the top surface of the semiconductor substrate 10. The first direction X and the second direction Y are both parallel to the top surface of the semiconductor substrate 10, that is, the first direction X and the second direction Y are both perpendicular to the vertical direction Z. The first direction X and the second direction Y intersect, and the size of the included angle is not limited.

[0049] Embodiments of the present disclosure provide a semiconductor structure, as Figure 2 shown, the semiconductor structure includes: a semiconductor substrate 10, a stacked structure 20, and a bit line 50.

[0050] In embodiments of the present disclosure, referring to Figure 2 , the stacked structure 20 is stacked on the semiconductor substrate 10 in the vertical direction Z. Combining Figure 3 , the stacked structure 20 includes: a separation layer 40 and a composite layer 30 alternately stacked in the vertical direction Z. Among them, devices and circuit structures are formed in the composite layer 30, and the separation layer 40 is used to separate the respective composite layers.

[0051] It can be understood that the alternately stacked separation layer 40 and composite layer 30 can form a three-dimensional semiconductor structure, thereby improving the integration degree, enhancing the performance, and reducing the cost.

[0052] In embodiments of the present disclosure, referring to Figure 3 , the composite layer 30 includes: an active layer 310. Combining Figure 5 and Figure 6 , the active layer 310 includes: a channel region 311, a source region 312, and a drain region 313. Among them, the channel region 311, the source region 312, and the drain region 313 are divided by a dotted line in Figure 5 and Figure 6 .

[0053] In embodiments of the present disclosure, referring to Figure 5 and Figure 6 , the source region 312 and the drain region 313 are respectively located at opposite ends of the channel region 311 along the first direction X. The channel region 311 can form the channel of the transistor structure, the source region 312 can form the source of the transistor structure, and the drain region 313 can form the drain of the transistor structure. Among them, the transistor structure can be Figure 1 the memory cell transistor MCT shown.

[0054] In some embodiments of the present disclosure, the material for forming the active layer 310 may include IGZO (indium gallium zinc oxide). IGZO has advantages such as high electron mobility and low power consumption, thus being able to improve the performance of the transistor structure; at the same time, using IGZO to form the active layer 310 also has the advantages of low process requirements and high yield.

[0055] In embodiments of the present disclosure, referring to Figure 2 and Figure 6, the bit line 50 is located on one side of the stacked structure 20 along the first direction X and penetrates the stacked structure 20 along the vertical direction Z. Among them, the bit line 50 can be composed of one or more layers of conductive materials, and the conductive materials can include one or more of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0056] Reference Figure 6 , the bit line 50 forms an electrical contact with the source region 312, and the bit line 50 contacts the end face and part of the side face of the source region 312. That is to say, the bit line 50 protrudes towards the active layer 310. Thus, the bit line 50 not only forms an electrical contact with the end face of the source region 312, but also forms an electrical contact with part of the side face of the source region 312. In this way, on the one hand, the contact area between the bit line 50 and the source region 312 is increased, so that the contact resistance between the bit line 50 and the source region 312 can be effectively reduced, and the power consumption can be reduced; on the other hand, the protruding bit line 50 has a larger cross-sectional area, so that the resistance of the bit line 50 can be reduced, and the power consumption can be reduced.

[0057] In some embodiments of the present disclosure, reference Figure 6 , the semiconductor structure further includes: a capacitor structure 60. The capacitor structure 60 includes a first electrode plate 601, where the first electrode plate 601 is located in the composite layer 30. The first electrode plate 601 forms an electrical contact with the drain region 313, and the first electrode plate 601 contacts part of the side face of the drain region 313.

[0058] It can be understood that, compared with the first electrode plate 601 contacting the end face of the drain region 313, the first electrode plate 601 contacting part of the side face of the drain region 313 can form a larger contact area, so that the contact resistance between the first electrode plate 601 and the drain region 313 can be effectively reduced, and the power consumption can be reduced.

[0059] In some embodiments of the present disclosure, reference Figure 5 Or Figure 6 , the length of the contact surface between the first electrode plate 601 and the drain region 313 along the first direction X is equal to the length of the first electrode plate 601 along the first direction X. In this way, the contact area between the first electrode plate 601 and the drain region 313 is maximally increased, so that the contact resistance between the first electrode plate 601 and the drain region 313 can be maximally reduced, and the power consumption can be reduced.

[0060] In the embodiments of the present disclosure, in combination with Figure 3 And Figure 6 , the capacitor structure 60 further includes a second electrode plate 602 and a dielectric layer 603, where the dielectric layer 603 is located between the first electrode plate 601 and the second electrode plate 602. The first electrode plate 601, the second electrode plate 602, and the dielectric layer 603 located in the same composite layer 30 can form a capacitor ( Figure 1 The capacitor DS shown).

[0061] In the embodiments of the present disclosure, with reference to Figure 6 , the materials of the first electrode plate 601 and the second electrode plate 602 may include titanium (Ti) and / or titanium nitride (TiN). The material of the dielectric layer 603 may include a high-k material, where the high-k material may include: hafnium-based oxides (such as HfO2, HfSiO, HfSiON, etc.), aluminum-based oxides (such as Al2O3), and zirconium-based oxides (such as ZrO2), either alone or in combination.

[0062] In the embodiments of the present disclosure, in combination with Figure 3 and Figure 6 , the first electrode plate 601 and the second electrode plate 602 can form a sleeve-type capacitor. That is to say, the first electrode plate 601 forms a sleeve extending along the first direction X, and the second electrode plate 602 extends into the sleeve. In this way, the plate area of the capacitor can be increased, and the capacitance can be improved. At the same time, a partial side surface of the first electrode plate 601 forms electrical contact with a partial side surface of the drain region 313, effectively increasing the contact area between the first electrode plate 601 and the drain region 313 and reducing the contact resistance.

[0063] In some embodiments of the present disclosure, in combination with Figure 2 and Figure 6 , the semiconductor structure further includes a capacitor connection structure 61. The capacitor connection structure 61 extends along the vertical direction Z, and the capacitor connection structure 61 connects the second electrode plates 602 of different layers. The capacitor connection structure 61 can be the connection line PLT shown in Figure 1 . The material of the capacitor connection structure 61 may include a doped semiconductor material.

[0064] In some embodiments of the present disclosure, with reference to Figure 5 and Figure 6 , taking the central axis of the channel region 311 along the second direction Y as a reference, the active layer 310 is an asymmetric structure. Among them, the length of the drain region 313 along the first direction X is greater than the length of the source region 312 along the first direction X. That is to say, the length of the drain region 313 along the first direction X is extended.

[0065] It can be understood that the semiconductor structure provided by the embodiments of the present disclosure is not limited to designing the active layer 310 as a symmetric structure. Thus, based on the structural characteristics of the first electrode plate 601 of the capacitor structure, the length of the drain region 313 along the first direction X is extended. In this way, the contact area between the first electrode plate 601 and the drain region 313 is maximally increased, and thus, the power consumption can be effectively reduced.

[0066] In some embodiments of the present disclosure, in combination with Figure 3 and Figure 6, the composite layer 30 further includes: word lines 70 and a gate dielectric layer 320.

[0067] Combined with Figure 4 and Figure 6 , the word lines 70 extend along the second direction Y and are in contact with a plurality of gate dielectric layers 320. The portions of the word lines 70 in contact with the gate dielectric layers 320 can serve as the gates of the transistor structures. Thus, the word lines 70 can be connected to the gates of a plurality of transistor structures, that is, Figure 1 the word line WL shown is connected to the gate of the memory cell transistor MCT. Among them, the material of the word lines 70 may include one or more of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0068] In some embodiments of the present disclosure, referring to Figure 6 , the gate dielectric layer 320 covers at least a part of three sides of the word lines 70. Among them, the first part of the gate dielectric layer 320 is between the channel layer 311 and the word lines 70; the second part of the gate dielectric layer 320 is between the bit lines 50 and the word lines 70; the third part of the gate dielectric layer 320 is between the first electrode plate 601 and the word lines 70. In this way, the gate dielectric layer 320 surrounds three sides of the gate, effectively isolating the gate from the surrounding conductive structures, thus avoiding short circuits and leakage.

[0069] In some embodiments of the present disclosure, continuing to refer to Figure 6 , the thickness of the second part of the gate dielectric layer 320 along the vertical direction Z, and the thickness of the third part of the gate dielectric layer 320 along the vertical direction Z are both greater than or equal to the thickness of the word lines 70 along the vertical direction Z. In this way, the second part of the gate dielectric layer 320 can completely isolate the bit lines 50 from the word lines 70. Similarly, the third part of the gate dielectric layer 320 can completely isolate the first electrode plate 601 from the word lines 70, thus ensuring the isolation effect and avoiding short circuits and leakage.

[0070] In some embodiments of the present disclosure, continuing to refer to Figure 6 , the thickness of the second part and the third part of the gate dielectric layer 320 along the third direction (which may be the vertical direction Z) is greater than or equal to the sum of the thickness of the word lines 70 and the thickness of the first part of the gate dielectric layer 320. In this way, the gate dielectric layer 320 completely wraps the word lines 70 at least from three sides. Thus, the parasitic capacitance between the word lines 70 and the bit lines 50 is reduced, and the parasitic capacitance between the word lines 70 and the first electrode plate 601 is reduced.

[0071] In some embodiments of the present disclosure, the material for forming the gate dielectric layer 320 may include a high-k material. Among them, the high-k material may include one or a combination of hafnium-based oxides (such as HfO2, HfSiO, HfSiON, etc.), aluminum-based oxides (such as Al2O3), and zirconium-based oxides (such as ZrO2). The gate dielectric layer 320 formed of the high-k material has a higher dielectric constant, thereby reducing the parasitic capacitance between the word line 70 and other structures (such as the bit line 50 or the first electrode plate 601).

[0072] In the embodiments of the present disclosure, with reference to Figure 3 and Figure 6 , in each composite layer 30, there is one layer of word line 70, that is, one layer of gate is included; in addition, in each composite layer 30, there is also one layer of gate dielectric layer 320 and one layer of active layer 310. At the same time, the word line 70 (including the gate), the gate dielectric layer 320, and the active layer 310 in two adjacent composite layers 30 are mirror-symmetrical with respect to the plane between the two adjacent composite layers 30. That is to say, the embodiments of the present disclosure provide a mirror-symmetrical single-gate single-channel transistor structure.

[0073] It can be understood that each transistor unit in the single-gate single-channel transistor structure (the transistor structure in one composite layer 30) only includes one layer of active layer 310, one layer of gate dielectric layer 320, and one layer of word line 70 in the vertical direction Z. Therefore, compared with the double-gate double-channel transistor structure, the single-gate single-channel transistor structure provided by the embodiments of the present disclosure can reduce the vertical pitch by more than 30%, thereby improving the storage density.

[0074] At the same time, compared with the non-mirror transistor structure, the mirror-symmetrical single-gate single-channel transistor structure provided by the embodiments of the present disclosure is simpler in the formation process. For example, the mirror-symmetrical word line 70, gate dielectric layer 320, and active layer 310 in two composite layers 30 can be formed at one time, and then cut off through subsequent processes.

[0075] It should be noted that Figures 7 to 20 is a schematic structural diagram of each step in the method for forming the semiconductor structure provided by the embodiments of the present disclosure, and is used to illustrate the steps in the method for forming the semiconductor structure. Among them, Figure 20 is consistent with the semiconductor structure shown in Figure 2 , so Figures 3 to 6 can also be used to show the semiconductor structure in Figure 20 .

[0076] It should also be noted that, in the structural schematic diagram provided by the embodiments of the present disclosure, the vertical direction Z is perpendicular to the top surface of the semiconductor substrate 10. The first direction X and the second direction Y are both parallel to the top surface of the semiconductor substrate 10, that is, the first direction X and the second direction Y are both perpendicular to the vertical direction Z. The first direction X and the second direction Y intersect, and the size of the included angle is not limited.

[0077] The embodiments of the present disclosure also provide a method for forming a semiconductor structure, including steps S101 to S103. Each step will be described in combination.

[0078] S101. Provide a semiconductor substrate 10.

[0079] In the embodiments of the present disclosure, referring to Figure 7 , the substrate 10 may include a semiconductor substrate 11 and an etch stop layer 12. The etch stop layer 12 is located on the top surface of the semiconductor substrate 11. The etch stop layer 12 is used to block during the etching process to protect the semiconductor substrate 11. Among them, the semiconductor substrate 11 may be a silicon substrate, and the material of the etch stop layer 12 may include undoped silicon germanium (SiGe).

[0080] S102. Form a stacked structure 20 on the semiconductor substrate 10.

[0081] In the embodiments of the present disclosure, referring to Figure 20 , the stacked structure 20 is stacked on the semiconductor substrate 10 along the vertical direction Z. The stacked structure 20 includes: a separation layer 40 and a composite layer 30 that are alternately stacked along the vertical direction Z. Among them, devices and circuit structures are formed in the composite layer 30, and the separation layer 40 is used to separate the respective composite layers. The alternately stacked separation layer 40 and composite layer 30 can form a three-dimensional semiconductor structure, thereby improving the integration degree, enhancing the performance, and reducing the cost.

[0082] In the embodiments of the present disclosure, referring to Figure 3 , the composite layer 30 includes: an active layer 310. Combining Figure 5 and Figure 6 , the active layer 310 includes: a channel region 311, a source region 312, and a drain region 313. Among them, the channel region 311, the source region 312, and the drain region 313 are divided by dotted lines in Figure 5 and Figure 6 .

[0083] In the embodiments of the present disclosure, referring to Figure 5 and Figure 6 , the source region 312 and the drain region 313 are respectively located at opposite ends of the channel region 311 along the first direction X. The channel region 311 may constitute the channel of the transistor structure, the source region 312 may constitute the source of the transistor structure, and the drain region 313 may constitute the drain of the transistor structure. Among them, the transistor structure may beFigure 1 The shown memory cell transistor MCT.

[0084] In some embodiments of the present disclosure, the material forming the active layer 310 may include IGZO (indium gallium zinc oxide). IGZO has advantages such as high electron mobility and low power consumption, thereby being able to improve the performance of the transistor structure; at the same time, using IGZO to form the active layer 310 also has the advantages of low process requirements and high yield.

[0085] In some embodiments of the present disclosure, referring to Figure 3 , the composite layer 30 further includes: a word line 70 and a gate dielectric layer 320.

[0086] Combined with Figure 4 and Figure 6 , the word line 70 extends along the second direction Y and contacts a plurality of gate dielectric layers 320. The portion where the word line 70 contacts the gate dielectric layer 320 can serve as the gate of the transistor structure. Thus, the word line 70 can be connected to the gates of a plurality of transistor structures, that is, Figure 1 the shown word line WL is connected to the gate of the memory cell transistor MCT. Wherein, the material of the word line 70 may include one or more of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0087] In some embodiments of the present disclosure, referring to Figure 6 , the gate dielectric layer 320 covers at least a part of three sides of the word line 70. Among them, the first part of the gate dielectric layer 320 is between the channel layer 311 and the word line 70; the second part of the gate dielectric layer 320 is between the bit line 50 and the word line 70; the third part of the gate dielectric layer 320 is between the first electrode plate 601 and the word line 70. In this way, the gate dielectric layer 320 surrounds three sides of the gate, effectively isolating the gate from the surrounding conductive structures, thereby avoiding short circuits and leakage.

[0088] In some embodiments of the present disclosure, continuing to refer to Figure 6 , the thickness of the second part of the gate dielectric layer 320 along the vertical direction Z, and the thickness of the third part of the gate dielectric layer 320 along the vertical direction Z are both greater than or equal to the thickness of the word line 70 along the vertical direction Z. In this way, the second part of the gate dielectric layer 320 can completely isolate the bit line 50 and the word line 70. Similarly, the third part of the gate dielectric layer 320 can completely isolate the first electrode plate 601 and the word line 70, thereby ensuring the isolation effect and avoiding short circuits and leakage.

[0089] In some embodiments of the present disclosure, the material forming the gate dielectric layer 320 may include a high-k material. Among them, the high-k material may include: hafnium-based oxides (such as HfO2, HfSiO, HfSiON, etc.), aluminum-based oxides (such as Al2O3), and zirconium-based oxides (such as ZrO2), either alone or in combination. The gate dielectric layer 320 formed of the high-k material has a higher dielectric constant, thereby reducing the parasitic capacitance between the word line 70 and other structures (such as the bit line 50 or the first electrode plate 601).

[0090] In the embodiments of the present disclosure, referring to Figure 3 and Figure 6 , each composite layer 30 includes a layer of word line 70, that is, includes a single-layer gate; in addition, each composite layer 30 further includes a layer of gate dielectric layer 320 and a layer of active layer 310. At the same time, the word line 70 (including the gate), the gate dielectric layer 320, and the active layer 310 in two adjacent composite layers 30 are mirror-symmetrical with respect to the plane between the two adjacent composite layers 30. That is to say, the embodiments of the present disclosure form a mirror-symmetrical single-gate single-channel transistor structure.

[0091] It can be understood that, compared with the double-gate double-channel transistor structure, the single-gate single-channel transistor structure formed in the embodiments of the present disclosure can reduce the vertical pitch by more than 30%, thereby improving the storage density. At the same time, compared with the non-mirror transistor structure, the mirror-symmetrical single-gate single-channel transistor structure formed in the embodiments of the present disclosure is simpler in the forming process.

[0092] S103. Form the bit line 50.

[0093] In the embodiments of the present disclosure, referring to Figure 20 , the bit line 50 is located on one side of the stacked structure 20 along the first direction X and penetrates the stacked structure 20 along the vertical direction Z. Among them, the bit line 50 may be composed of one or more layers of conductive materials, and the conductive materials may include one or more of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0094] In the embodiments of the present disclosure, in combination with Figure 20 and Figure 6, the bit line 50 forms an electrical contact with the source region 312, and the bit line 50 contacts the end face and a part of the side face of the source region 312. That is to say, the bit line 50 protrudes towards the active layer 310. Thus, the bit line 50 not only forms an electrical contact with the end face of the source region 312, but also forms an electrical contact with a part of the side face of the source region 312. In this way, on the one hand, the contact area between the bit line 50 and the source region 312 is increased, so that the contact resistance between the bit line 50 and the source region 312 can be effectively reduced, and the power consumption is reduced; on the other hand, the protruding part of the bit line 50 has a larger cross-sectional area, so that the resistance of the bit line 50 can be reduced, and the power consumption is reduced.

[0095] In some embodiments of the present disclosure, the method for forming the semiconductor structure further includes step S104. Each step will be described in combination.

[0096] S104. Form a capacitor structure 60.

[0097] In the embodiments of the present disclosure, in combination with Figure 20 and Figure 6 , the capacitor structure 60 includes a first electrode plate 601, wherein the first electrode plate 601 is located in the composite layer 30. The first electrode plate 601 forms an electrical contact with the drain region 313, and the first electrode plate 601 contacts a part of the side face of the drain region 313. Compared with the first electrode plate 601 contacting the end face of the drain region 313, the first electrode plate 601 contacting a part of the side face of the drain region 313 can form a larger contact area, so that the contact resistance between the first electrode plate 601 and the drain region 313 can be effectively reduced, and the power consumption is reduced.

[0098] In some embodiments of the present disclosure, referring to Figure 5 or Figure 6 , the length of the contact surface between the first electrode plate 601 and the drain region 313 along the first direction X is equal to the length of the first electrode plate 601 along the first direction X. In this way, the contact area between the first electrode plate 601 and the drain region 313 is maximally increased, so that the contact resistance between the first electrode plate 601 and the drain region 313 can be maximally reduced, and the power consumption is reduced.

[0099] In the embodiments of the present disclosure, in combination with Figure 3 and Figure 6 , the capacitor structure 60 further includes a second electrode plate 602 and a dielectric layer 603, wherein the dielectric layer 603 is located between the first electrode plate 601 and the second electrode plate 602. The first electrode plate 601, the second electrode plate 602 and the dielectric layer 603 located in the same composite layer 30 can form a capacitor ( Figure 1 the capacitor DS shown).

[0100] In the embodiments of the present disclosure, referring to Figure 6, the materials of the first electrode plate 601 and the second electrode plate 602 may include titanium (Ti) and / or titanium nitride (TiN). The material of the dielectric layer 603 may include a high-k material, where the high-k material may include: hafnium-based oxides (such as HfO2, HfSiO, HfSiON, etc.), aluminum-based oxides (such as Al2O3), and zirconium-based oxides (such as ZrO2) alone or in combination.

[0101] In the embodiments of the present disclosure, in combination with Figure 3 and Figure 6 , the first electrode plate 601 and the second electrode plate 602 can form a sleeve-type capacitor. That is to say, the first electrode plate 601 forms a sleeve extending along the first direction X, and the second electrode plate 602 extends into the sleeve. In this way, the plate area of the capacitor can be increased, and the capacitance can be improved. At the same time, a partial side surface of the first electrode plate 601 forms electrical contact with a partial side surface of the drain region 313, effectively increasing the contact area between the first electrode plate 601 and the drain region 313 and reducing the contact resistance.

[0102] In some embodiments of the present disclosure, in combination with Figure 2 and Figure 6 , the semiconductor structure further includes a capacitor connection structure 61. The capacitor connection structure 61 extends along the vertical direction Z, and the capacitor connection structure 61 connects the second electrode plates 602 of different layers. The capacitor connection structure 61 may be the connection line PLT shown in Figure 1 . The material of the capacitor connection structure 61 may include a doped semiconductor material.

[0103] In some embodiments of the present disclosure, with reference to Figure 5 and Figure 6 , taking the central axis of the channel region 311 along the second direction Y as a reference, the active layer 310 is an asymmetric structure. Among them, the length of the drain region 313 along the first direction X is greater than the length of the source region 312 along the first direction X. That is to say, the length of the drain region 313 along the first direction X is extended.

[0104] It can be understood that the semiconductor structure formed in the embodiments of the present disclosure is not limited to designing the active layer 310 as a symmetric structure. Therefore, based on the structural characteristics of the first electrode plate 601 of the capacitor structure, the length of the drain region 313 along the first direction X is extended. In this way, the contact area between the first electrode plate 601 and the drain region 313 is maximally increased, and thus, the power consumption can be effectively reduced.

[0105] In some embodiments of the present disclosure, the method for forming the stacked structure includes steps S201 to S206. Each step will be described in combination.

[0106] S201. Form a stacked material layer on the semiconductor substrate 10.

[0107] In the embodiments of the present disclosure, referring to Figure 7 , the stacked material layer includes: a sacrificial layer 41 and a spacer layer 40 alternately stacked in the vertical direction Z. Among them, the material of the sacrificial layer 41 may include silicon nitride (SiN), and the material of the spacer layer 40 may include silicon oxide (SiO).

[0108] S202. Form a patterned first isolation structure 42.

[0109] In the embodiments of the present disclosure, referring to Figure 8 , the first isolation structure 42 penetrates the stacked material layer in the vertical direction Z. In the Figure 12 illustrated step, the first isolation structure 42 is removed; furthermore, in the Figure 13 illustrated step, the first isolation structure 42 is refilled. Figures 8 to 10 The material of the first isolation structure 42 illustrated in Figures 13 to 20 may include polysilicon, and the material of the first isolation structure 42 illustrated in

[0110] S203. Form a first etching hole 51 and a second etching hole 52.

[0111] In the embodiments of the present disclosure, referring to Figure 9 , the first etching hole 51 and the second etching hole 52 penetrate the stacked material layer in the vertical direction Z. The first isolation structure 42, the first etching hole 51, and the second etching hole 52 divide the stacked material layer, and the remaining stacked material layer characterizes the pattern of the channel layer.

[0112] S204. Perform selective etching on the exposed sacrificial layer 41 to remove the sacrificial layer 41 and form a first space.

[0113] In the embodiments of the present disclosure, in combination with Figure 9 and Figure 10 , the sidewalls of the first etching hole 51 and the second etching hole 52 expose the sacrificial layer 41 and the spacer layer 40. Furthermore, perform selective etching on the exposed sacrificial layer 41 to remove the sacrificial layer 41 while retaining other structures, and the area where the removed sacrificial layer 41 is located can form a first space.

[0114] S205. Sequentially deposit a composite layer material in the first space.

[0115] In the embodiments of the present disclosure, in combination with Figure 10 and Figure 11 , a composite layer material can be sequentially deposited in the first space to form Figure 6 the channel layer 310, the gate dielectric layer 320, and the word line 70 illustrated in

[0116] In the embodiments of the present disclosure, the composite layer material may include: a semiconductor oxide, a high-k material, a conductive material, and a spacer material. Among them, the semiconductor oxide is used to form the channel layer 310, the high-k material is used to form the gate dielectric layer 320, and the conductive material is used to form the word line 70. That is to say, in the first space, the semiconductor oxide is deposited first to form the channel layer 310, then the high-k material is deposited to form the gate dielectric layer 320, then the conductive material is deposited to form the word line 70, and finally the spacer material is deposited for filling and isolation.

[0117] In the embodiments of the present disclosure, since the formed structure is a mirror-symmetric single-gate single-channel transistor structure, therefore, by sequentially depositing the composite layer material, the mirror-symmetric word line 70, gate dielectric layer 320, and active layer 310 in the two-layer composite layer 30 can be formed at one time, and the process is simpler.

[0118] S206. Etch the sidewalls of the first etching hole 51 and the second etching hole 52 to cut off the connection parts of the composite layer material in different layers, thereby forming the composite layer 30.

[0119] In the embodiments of the present disclosure, referring to Figure 11 , after sequentially depositing the composite layer material in the first space, the sidewalls of the first etching hole 51 and the second etching hole 52 can be etched to cut off the connection parts of the composite layer material in different layers, thereby forming the composite layer 30.

[0120] In some embodiments of the present disclosure, the method for forming the bit line includes steps S301 to S304, which will be described in combination with each step.

[0121] S301. Fill the sacrificial material 43 in the first etching hole 51 and the second etching hole 52.

[0122] In the embodiments of the present disclosure, in combination with Figure 11 and Figure 12 , the sacrificial material 43 can be filled in the first etching hole 51 and the second etching hole 52. The sacrificial material 43 can be polysilicon.

[0123] S302. Remove the sacrificial material 43 in the first etching hole 51 to expose the composite layer 30.

[0124] In the embodiments of the present disclosure, in combination with Figure 12 and Figure 13 , the sacrificial material 43 in the first etching hole 51 can be removed, and the sidewall of the first etching hole 51 exposes the composite layer 30.

[0125] S303. Selectively etch the part of the composite layer 30 exposed by the first etching hole 51 to make the sidewall of the first etching hole 51 protrude towards the composite layer 30.

[0126] In the embodiments of the present disclosure, in combination with Figure 13 and Figure 14 , the exposed portion of the composite layer 30 in the first etching hole 51 can be selectively etched, so that the portion of the composite layer 30 is recessed, and thus, the sidewall of the first etching hole 51 protrudes towards the composite layer 30.

[0127] S304. Fill the first etching hole 51 with a conductive material to form a bit line 50.

[0128] In the embodiments of the present disclosure, in combination with Figure 14 and Figure 15 , after the selective etching of the portion of the composite layer 30 is completed, a conductive material can be filled in the first etching hole 51 to form a bit line 50.

[0129] It can be understood that the exposed portion of the composite layer 30 in the first etching hole 51 is selectively etched, so that the sidewall of the first etching hole 51 protrudes towards the composite layer 30, and then, a bit line 50 is formed in the first etching hole 51. In this way, on the one hand, the contact area between the bit line 50 and the source region in the composite layer 30 is increased, and thus, the contact resistance between the bit line 50 and the source region can be effectively reduced, reducing power consumption; on the other hand, the protruding portion of the bit line 50 has a larger cross-sectional area, and thus, the resistance of the bit line 50 can be reduced, reducing power consumption.

[0130] In some embodiments of the present disclosure, the method for forming a capacitor structure includes steps S401 to S403. Each step will be described in combination.

[0131] S401. Selectively etch the exposed portion of the composite layer in the second etching hole to form a second space.

[0132] In the embodiments of the present disclosure, in combination with Figure 16 and Figure 17 , the conductive material and the high-k material in the composite layer 30 exposed by the second etching hole can be selectively etched, and the remaining conductive material forms a word line 70, and then, a high-k material is filled again so that the high-k material wraps the side surface of the word line 70.

[0133] Furthermore, in combination with Figure 17 and Figure 18 , the filled high-k material is etched again to expose a partial side surface of the drain region in the active layer, forming a second space. The remaining high-k material serves as the third part of the gate dielectric layer 320, completely isolating the first electrode plate and the word line 70.

[0134] S402. In the second space, deposit and form a first electrode plate, a dielectric layer, and a second electrode plate in sequence;

[0135] In the embodiments of the present disclosure, in combination with Figure 18 and Figure 19, in the second space, the first electrode plate 601, the dielectric layer, and the second electrode plate can be sequentially deposited and formed, thereby forming Figure 20 the capacitor structure 60 shown in Figure 20 . Among them, since a partial side surface of the drain region is exposed in the second space, the first electrode plate 601 forms electrical contact with the partial side surface of the drain region, thereby increasing the contact area between the first electrode plate 601 and the drain region and reducing the contact resistance.

[0136] S403. In the remaining second space and the second etching hole 52, a conductive material is filled to form a capacitor connection structure 61. The capacitor connection structure connects the second electrode plates of different layers.

[0137] In the embodiments of the present disclosure, in combination with Figure 19 and Figure 20 , in the remaining second space and the second etching hole, a conductive material can be filled to form a capacitor connection structure 61. The conductive material for forming the capacitor connection structure 61 may include a doped semiconductor material.

[0138] It should be noted that the semiconductor structure and its forming method provided by the embodiments of the present disclosure can be applied to a dynamic random access memory DRAM, providing a new solution for three-dimensional memory products.

[0139] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0140] The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0141] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all should be covered by the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: a semiconductor substrate, a stacked structure, a bit line and a capacitor structure; The stacked structure is stacked on the semiconductor substrate in a vertical direction; the stacked structure comprises: a separation layer and a composite layer alternately stacked in a vertical direction; The composite layer comprises: an active layer; the active layer comprises: a channel region, a source region and a drain region; the source region and the drain region are respectively located at two opposite ends of the channel region along a first direction; the first direction is parallel to the top surface of the semiconductor substrate; The bit line is located at one side of the stack structure along the first direction and penetrates the stack structure along the vertical direction; the bit line contacts the end surface and part of the side surface of the source region; The capacitor structure includes: a first electrode plate; the first electrode plate is located in the composite layer; the first electrode plate contacts a part of the side surface of the drain region.

2. The semiconductor structure according to claim 1, characterized in that: The length of the contact surface between the first electrode plate and the drain region along the first direction is equal to the length of the first electrode plate along the first direction.

3. The semiconductor structure according to claim 1, characterized in that: A length of the drain region along the first direction is greater than a length of the source region along the first direction.

4. The semiconductor structure according to claim 1, characterized in that The composite layer also includes: a word line and a gate dielectric layer; The word line extends along a second direction; the second direction is parallel to the top surface of the semiconductor substrate; The gate dielectric layer covers at least part of the three sides of the word line; wherein the first part of the gate dielectric layer is between the channel layer and the word line; the second part of the gate dielectric layer is between the bit line and the word line; and the third part of the gate dielectric layer is between the first electrode plate and the word line.

5. The semiconductor structure according to claim 4, characterized in that: The thickness of the second portion of the gate dielectric layer along the vertical direction and the thickness of the third portion of the gate dielectric layer along the vertical direction are both greater than or equal to the thickness of the word line along the vertical direction.

6. The semiconductor structure according to claim 1, characterized in that The material of the active layer includes: indium gallium zinc oxide IGZO.

7. A method for forming a semiconductor structure, characterized in that: The method for forming the semiconductor structure comprises: providing a semiconductor substrate; A stacking structure is formed on the semiconductor substrate; the stacking structure is stacked on the semiconductor substrate in a vertical direction; the stacking structure comprises: a separation layer and a composite layer alternately stacked in a vertical direction; the composite layer comprises: an active layer; the active layer comprises: a channel region, a source region and a drain region; the source region and the drain region are respectively located at two opposite ends of the channel region along a first direction; the first direction is parallel to the top surface of the semiconductor substrate; forming a bit line; the bit line is located on one side of the stack structure along the first direction and penetrates the stack structure along the vertical direction; the bit line contacts the end surface and part of the side surface of the source region; A capacitor structure is formed; the capacitor structure comprises: a first electrode plate; the first electrode plate is located in the composite layer; the first electrode plate contacts a part of the side surface of the drain region.

8. The method for forming a semiconductor structure according to claim 7, characterized in that: The method of forming the stacked structure includes: On the semiconductor substrate, a stacked material layer is formed; the stacked material layer comprises: sacrificial layers and the separation layers alternately stacked along the vertical direction; forming a patterned first isolation structure; the first isolation structure penetrates the stacked material layer along the vertical direction; forming a first etching hole and a second etching hole; the first etching hole and the second etching hole penetrate the stacked material layer along the vertical direction; the remaining stacked material layer represents the pattern of the channel layer; Selectively etching the exposed sacrificial layer to remove the sacrificial layer and form a first space; In the first space, composite layer materials are deposited sequentially; The sidewalls of the first etching hole and the sidewalls of the second etching hole are etched to cut off the connection parts of the composite layer materials in different layers to form the composite layer.

9. The method for forming a semiconductor structure according to claim 8, characterized in that: The method of forming the bit line includes: Filling the first etched hole and the second etched hole with a sacrificial material; removing the sacrificial material in the first etched hole to expose the composite layer; Selectively etching the portion of the composite layer exposed by the first etching hole so that the sidewall of the first etching hole protrudes toward the composite layer; A conductive material is filled in the first etched hole to form the bit line.

10. The method for forming a semiconductor structure according to claim 8, wherein: The capacitor structure further includes: a dielectric layer and a second electrode plate; The method of forming the capacitor structure includes: Selectively etching the portion of the composite layer exposed by the second etching hole to form a second space; the second space exposes a portion of the side surface of the drain region; In the second space, the first electrode plate, the dielectric layer and the second electrode plate are sequentially deposited and formed; The remaining second space and the second etched hole are filled with conductive material to form a capacitor connection structure; the capacitor connection structure connects the second electrodes of different layers.

Images