Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method. The semiconductor device comprises a substrate; the array of stacked gate structures is located on the surface of the substrate and distributed in parallel in the first direction; the side walls are located on the side walls of the stacked gate structure in the second direction, gaps are formed between the adjacent side walls, and the first direction is perpendicular to the second direction; the doped regions are positioned in the substrate between the adjacent side walls; the shielding grids are located in the gaps between the adjacent side walls, and the bottoms of the shielding grids are electrically connected with the doped regions; the problem of programming interference between adjacent stacked gate structures is effectively avoided, and the overall reliability of the NAND flash memory is improved, so that the long-term stability of data storage of a device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor device and a method for forming the same. Background Art

[0002] NAND flash is a non-volatile flash memory, whose main function is to store data. It has a relatively high storage cell density, fast erasing speed. At the same time, the storage cell size of NAND flash is almost half of that of NOR flash, and it can provide higher capacity within a given die size. Currently, it is mainly used in digital camera flash memory cards and MP3 players.

[0003] The storage cells of existing NAND flash are usually of planar structure, and polysilicon is usually used as the floating gate. As the size of semiconductor devices decreases, using polysilicon as the floating gate faces problems such as insufficient electrons that can tunnel to the floating gate, and the need to use multiple photolithography and etching processes during the formation of the polysilicon floating gate. More seriously, existing NAND flash also has the problem of program disturb.

[0004] However, the performance of existing NAND flash still needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, which effectively avoid the program disturb problem between adjacent stacked gate structures, improve the overall reliability of NAND flash, and thus improve the long-term stability of data storage of the device.

[0006] To solve the above problems, the present invention provides a semiconductor device, including: a substrate; an array of stacked gate structures parallelly distributed along a first direction on the surface of the substrate; sidewalls located on the sidewalls of the stacked gate structures along a second direction, with a gap between adjacent sidewalls, the first direction being perpendicular to the second direction; doping regions in the substrate between adjacent sidewalls; a shielding gate in the gap between adjacent sidewalls, the bottom of the shielding gate being electrically connected to the doping regions.

[0007] Optionally, the doping regions have first doping ions, the shielding gate has second doping ions, and the types of the first doping ions are the same as those of the second doping ions.

[0008] Optionally, the stacked gate structure includes a tunneling dielectric layer on the surface of the substrate; a floating gate layer on the surface of the tunneling dielectric layer; an inter-gate dielectric layer on the surface of the floating gate layer; a control gate layer on the surface of the inter-gate dielectric layer; and a mask layer formed on the surface of the control gate layer.

[0009] Optionally, the top surface of the shielding gate is not lower than the bottom surface of the mask layer, and the material of the shielding gate is polysilicon.

[0010] Optionally, the upper end of the shielding gate is in a floating state.

[0011] Correspondingly, the present invention further provides a method for forming a semiconductor device, including: providing a substrate; forming an array of stacked gate structures distributed in parallel along a first direction on the surface of the substrate; forming sidewalls along a second direction on the sidewalls of the stacked gate structures, with a gap between adjacent sidewalls, the first direction being perpendicular to the second direction; performing ion doping on the substrate between adjacent stacked gate structures to form a doped region; forming a shielding gate on the surface of the substrate between adjacent sidewalls, the shielding gate filling the gap, and the bottom of the shielding gate forming an electrical connection with the doped region.

[0012] Optionally, the doped region has a first doping ion, and the shielding gate has a second doping ion, and the type of the first doping ion is the same as the type of the second doping ion.

[0013] Optionally, the stacked gate structure includes a tunneling dielectric layer formed on the surface of the substrate; a floating gate layer formed on the surface of the tunneling dielectric layer; a gate dielectric layer formed on the surface of the floating gate layer; a control gate layer formed on the surface of the gate dielectric layer; and a mask layer formed on the surface of the control gate layer.

[0014] Optionally, the top surface of the shielding gate is not lower than the bottom surface of the mask layer.

[0015] Optionally, the method for forming the stacked gate structure includes: forming an initial tunneling dielectric layer on the surface of the substrate; forming an initial floating gate layer on the surface of the initial tunneling dielectric layer; forming the initial gate dielectric layer on the surface of the initial floating gate layer; forming an initial control gate layer on the surface of the initial gate dielectric layer; forming an initial mask layer on the surface of the initial control gate layer; providing a mask plate, using the mask plate as a mask, and etching the initial mask layer, the initial control gate layer, the initial gate dielectric layer, the initial floating gate layer, and the initial tunneling dielectric layer at one time to form the stacked gate structure on the substrate.

[0016] Optionally, the method for forming the shielding gate includes: depositing polysilicon on the surface of the substrate between the sidewalls, the polysilicon layer filling the gap; and performing in-situ doping during the deposition of the polysilicon.

[0017] Optionally, after forming the shielding gate, the method further includes: forming a dielectric layer on the substrate, where the dielectric layer is formed on the top surface of the mask layer, the top surface of the shielding gate, and the sidewalls of the sidewalls; performing source-drain doping on the substrate on both sides of the dielectric layer to form source-drain doping regions.

[0018] Optionally, the sidewall includes an oxide layer formed on the sidewall of the stacked gate structure and a silicon nitride layer formed on the sidewall of the oxide layer.

[0019] Optionally, the method for forming the sidewall includes: depositing an initial oxide layer on the top surface and the sidewall surface of the stacked gate structure; depositing an initial silicon nitride layer on the surface of the initial oxide layer; forming a sacrificial oxide layer on the surface of the initial silicon nitride layer; using an etching process to form an oxide layer on the sidewall surface of the stacked gate structure, a silicon nitride layer is formed on the sidewall surface of the oxide layer, and a sacrificial oxide layer is formed on the sidewall surface of the silicon nitride layer; removing the sacrificial oxide layer to form the sidewall.

[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021] In the semiconductor device of the present invention, the stacked gate structures are parallelly distributed along a first direction on the surface of the substrate, the sidewalls are located on the sidewalls of the stacked gate structures along a second direction, there are gaps between the sidewalls, wherein the first direction is perpendicular to the second direction, the doping regions are located in the substrate between adjacent sidewalls, the shielding gate is located in the gap between adjacent sidewalls, and the bottom of the shielding gate is electrically connected to the doping region; due to the presence of the shielding gate, during the programming process of the NAND flash memory, a high voltage is applied to the stacked gate structure, the source-drain ends are grounded, and at this time the potential of the shielding gate is 0V, then the voltage coupling effect between adjacent stacked gate structures is shielded by the shielding gate, reducing the interference between adjacent stacked gate structures, thereby improving the overall performance of the NAND flash memory, reducing the probability of misoperation, and improving the stability of long-term use. Description of the Drawings

[0022] Figures 1 to 2 Schematic structural diagram of a semiconductor device in an embodiment;

[0023] Figures 3 to 12 It is a schematic structural diagram of a semiconductor device in an embodiment of the present invention. Detailed Embodiments

[0024] The electrical performance of NAND flash memory devices in the prior art still needs to be improved. For specific details, please refer to Figures 1 to 2 for specific analysis.

[0025] Figure 1 is Figure 2 a top view of Figure 2 isFigure 1 Cross-sectional view taken along A-A

[0026] Please refer to Figures 1 to 2 , a semiconductor device, comprising a substrate 100; an array of stacked gate structures 101 parallelly distributed along a first direction (Y) on the surface of the substrate 100; sidewalls 102 on the sidewalls of the stacked gate structures 101 along a second direction (X); a dielectric layer 103 located on the substrate 100 and covering the stacked gate structures 101; source / drain doping regions 104 located within the substrate 101, with the stacked gate structures 101 and the dielectric layer 103 located between the source / drain doping regions 104; a first contact hole 105 located on the source / drain doping regions 104 and a second contact hole 106 located on the stacked gate structures 101.

[0027] For ease of explanation Figure 1 only the relationship diagram between the substrate, the array of stacked gate structures and the source / drain doping regions is shown.

[0028] The inventors' research found that during the programming process of the array of adjacent stacked gate structures 101 along the first direction Y, there is a problem of programming interference between adjacent stacked gate structures 101, increasing the probability of misoperation, and to a certain extent affecting the use of NAND flash memory.

[0029] The inventors' research found that the stacked gate structures are parallelly distributed on the surface of the substrate along the first direction, the sidewalls are located on the sidewalls of the stacked gate structures along the second direction, there are gaps between the sidewalls, where the first direction is perpendicular to the second direction, the doping regions are located within the substrate between adjacent sidewalls, the shielding gates are located within the gaps between adjacent sidewalls, and the bottom of the shielding gates forms an electrical connection with the doping regions; due to the presence of the shielding gates, during the programming of the NAND flash memory, a high voltage is applied to the stacked gate structures, the source / drain ends are grounded, and at this time the potential of the shielding gates is 0V, then the voltage coupling effect between adjacent stacked gate structures is shielded by the shielding gates, reducing the interference between adjacent stacked gate structures, thereby improving the overall performance of the NAND flash memory, reducing the probability of misoperation, and enhancing the stability of long-term use.

[0030] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention in detail with reference to the accompanying drawings.

[0031] First, please refer to Figure 3 , and provide a substrate 200.

[0032] In this embodiment, the substrate 200 is a P-type substrate 200.

[0033] In some embodiments, the substrate 200 may also be an N-type substrate 200.

[0034] In this embodiment, after providing the P-type substrate 200, a photoresist layer is coated on the surface of the P-type substrate 200, and the region of the deep N-type well (DNW) is defined by a photolithography process. A photoresist is coated on the surface of the substrate 200 where the deep N-type well (DNW) has been formed, and the region of the high-voltage P-type well (HVPW) is defined by a photolithography process. Specifically, high-energy N-type doping ions (such as phosphorus ions P⁺ or arsenic ions As⁺) are used for ion implantation. High-energy implantation can ensure that the doping ions penetrate deep into the substrate 200 to form a deep N-type well; P-type doping ions (such as boron ions B⁺) are used for ion implantation. The implantation energy and dose are adjusted according to the design requirements to ensure the depth and doping concentration of the HVPW.

[0035] Please refer to Figure 4 and Figure 5 , and an array of stacked gate structures 201 is formed in parallel distribution along a first direction on the surface of the substrate 200.

[0036] Wherein Figure 5 is Figure 4 a top view, Figure 4 and Figure 5 is a cross-sectional view taken along A-A.

[0037] In this embodiment, the stacked gate structure 201 includes a tunneling dielectric layer 201a formed on the surface of the substrate 200; a floating gate layer 201b formed on the surface of the tunneling dielectric layer 201a; a gate dielectric layer 201c formed on the surface of the floating gate layer 201b; a control gate layer 201d formed on the surface of the gate dielectric layer 201c; and a mask layer 201e formed on the surface of the control gate layer 201d, enabling the device to effectively store and control charges and realize operations such as data writing, reading, and erasing. At the same time, this layered structure also provides a clear direction for subsequent process optimization and device performance improvement, facilitating improvements and adjustments according to the characteristics of different layers to meet different application requirements.

[0038] In this embodiment, the specific formation method of the stacked gate structure 201 includes: forming an initial tunneling dielectric layer (not shown in the figure) on the surface of the substrate 200; forming an initial floating gate layer (not shown in the figure) on the surface of the initial tunneling dielectric layer (not shown in the figure); forming the initial inter-gate dielectric layer (not shown in the figure) on the surface of the initial floating gate layer (not shown in the figure); forming an initial control gate layer (not shown in the figure) on the surface of the initial inter-gate dielectric layer (not shown in the figure); forming an initial mask layer (not shown in the figure) on the surface of the initial control gate layer (not shown in the figure); providing a mask plate, using the mask plate as a mask, etching the initial mask layer (not shown in the figure), the initial control gate layer (not shown in the figure), the initial inter-gate dielectric layer (not shown in the figure), the initial floating gate layer (not shown in the figure), and the initial tunneling dielectric layer (not shown in the figure) at one time, and forming the stacked gate structure 201 on the substrate 200.

[0039] In this embodiment, the material of the tunneling dielectric layer 201a is silicon oxide.

[0040] In this embodiment, the material of the floating gate layer 201b is polysilicon.

[0041] In this embodiment, the inter-gate dielectric layer 201c adopts a stacked material, specifically an ONO stacked structure of oxide-nitride-oxide.

[0042] In this embodiment, the function of the mask layer 201e can, on the one hand, protect the stacked gate structure 201; on the other hand, it can play an isolation role, mainly increasing the isolation between the subsequently formed shielding gate and the control gate layer 201d.

[0043] In this embodiment, the first direction is the Y direction.

[0044] Please refer to Figure 6 and Figure 7 , and sidewalls 202 are formed along the second direction on the sidewalls of the stacked gate structure 201. There is a gap 203 between adjacent sidewalls 202, and the first direction is perpendicular to the second direction.

[0045] Among them, Figure 7 is Figure 6 a top view of Figure 6 is Figure 7 a cross-sectional view taken along A-A.

[0046] In this embodiment, the first direction is the Y direction, and the second direction is the X direction.

[0047] In this embodiment, the sidewall 202 includes an oxide layer 202a formed on the sidewall of the stacked gate structure 201 and a silicon nitride layer 202b formed on the sidewall of the oxide layer 202a.

[0048] Specifically, the method for forming the sidewall 202 includes: depositing an initial oxide layer (not shown in the figure) on the top surface and sidewall surface of the stacked gate structure 201; depositing an initial silicon nitride layer (not shown in the figure) on the surface of the initial oxide layer; forming a sacrificial oxide layer (not shown in the figure) on the surface of the initial silicon nitride layer; using an etching process to form an oxide layer 202a on the sidewall surface of the stacked gate structure 201, forming a silicon nitride layer 202b on the sidewall surface of the oxide layer 202a, and forming a sacrificial oxide layer (not shown in the figure) on the sidewall surface of the silicon nitride layer 202b. The oxide layer 202a, the silicon nitride layer 202b, and the sacrificial oxide layer fill the gap between adjacent stacked gate structures 201; removing the sacrificial oxide layer (not shown in the figure) to form the sidewall 202, and there is a gap 203 between adjacent sidewalls 202.

[0049] Please refer to Figure 8 , and perform ion doping on the substrate 200 between adjacent stacked gate structures 201 to form a doped region 204.

[0050] Figure 8 The view direction of Figure 6 is the same as that of

[0051] In this embodiment, the doped region 204 has a first doping ion, and the type of the first doping ion is N-type.

[0052] In some embodiments, the type of the first doping ion can also be P-type.

[0053] In this embodiment, the doped region 204 extends to the bottom of the sidewall 202 and does not extend to the bottom of the stacked gate structure 201, aiming to help avoid hot carrier effects and leakage, and can improve the shielding effect of the subsequent shielding gate as much as possible.

[0054] Please refer to Figure 9 and Figure 10 , and form a shielding gate 205 on the surface of the substrate 200 between adjacent sidewalls 202. The shielding gate 205 fills the gap 203, and the bottom of the shielding gate 205 is electrically connected to the doped region 204.

[0055] Among them, Figure 10 is the top view of Figure 9 , Figure 9 is Figure 10 the cross-sectional view along A-A.

[0056] In this embodiment, the method for forming the shielding gate 205 includes: depositing polysilicon on the surface of the substrate 200 between the sidewalls 202, and the polysilicon layer fills the gap 203; in-situ doping is performed simultaneously during the deposition of the polysilicon.

[0057] In this embodiment, the shielding gate 205 has second doping ions, and the type of the second doping ions is the same as that of the first doping ions. Specifically, the second doping ions are N-type ions.

[0058] In other embodiments, the second doping ions can also be P-type ions.

[0059] In this embodiment, when the types of the first doping ions in the doping region 204 are the same as those of the second doping ions in the shielding gate 205, good matching of the electrical characteristics between the two can be ensured. This helps to enhance the electrical connection stability between the shielding gate 205 and the doping region 204, further improve the performance of the device, ensure that the electric potentials between the two are the same, so as to better realize the interference suppression effect of the shielding gate 205 on the adjacent stacked gate structure 201, and improve the overall performance and reliability of the device.

[0060] In this embodiment, the shielding gate 205 is a conductive polysilicon structure, and the charge distribution inside it can be dynamically adjusted with the change of the external electric field. When a voltage is applied to the control gate layer 201d (CG), the charges in the shielding gate 205 will redistribute to form a stable electric field distribution, thereby reducing the influence of the electric field on the adjacent stacked gate structure 201; moreover, the polysilicon material has good electrical conductivity and stability, which can ensure that the shielding gate 205 maintains stable electrical performance during long-term operation, further improving the reliability and service life of the device.

[0061] In this embodiment, the top surface of the shielding gate 205 is not lower than the bottom surface of the mask layer 201e, and the shielding gate 205 is isolated from the control gate layer 201d (CG) through the mask layer 201e. This structural design physically isolates the shielding gate 205 from the control gate layer 201d (CG), and at the same time forms a good electrical connection with the bottom doping region 204, effectively preventing the electric field from directly propagating from the control gate layer 201d (CG) to the adjacent stacked gate structure 201, but being shielded and dispersed through the shielding gate 205, thereby reducing the interference between the adjacent stacked gate structures 201.

[0062] In this embodiment, the upper end of the shielding gate 205 is floating, which means it is not directly connected to an external circuit. This floating characteristic enables the potential of the shielding gate 205 to be dynamically adjusted according to the change of the surrounding electric field, further enhancing its shielding effect.

[0063] In this embodiment, due to the presence of the shielding gate 205, during the programming process of the NAND flash memory, a high voltage is applied to the stacked gate structure 201, and the source-drain (source-drain doping region 207) terminal is grounded. At this time, the potential of the shielding gate is 0V, so the voltage coupling effect between adjacent stacked gate structures 201 is shielded by the shielding gate 205, reducing the interference between adjacent stacked gate structures 201, thereby improving the overall performance of the NAND flash memory, reducing the probability of misoperation, and enhancing the stability of long-term use.

[0064] Please refer to Figures 11 to 12 , further comprising: forming a dielectric layer 206 on the substrate 200, the dielectric layer 206 being formed on the top surface of the mask layer 201e, the top surface of the shielding gate 205, and the sidewalls of the sidewalls 202; performing source-drain doping on the substrate 200 on both sides of the dielectric layer 206 to form source-drain doping regions 207.

[0065] Wherein, Figure 11 the view direction of Figure 9 is the same as that of

[0066] Please refer to Figure 12 , forming a first contact hole on the top surface of the source-drain doping region 207, forming a second contact hole in the stacked gate structure 201, and forming a third contact hole on the top surface of the shielding gate 205. The first contact hole, the second contact hole, and the third contact hole are respectively filled with a metal layer to form a first contact metal layer 208, a second contact metal layer 209, and a third contact metal layer 210, which are used to electrically connect the source-drain doping region 207, the control gate layer 201d, and the shielding gate 205 to the outside respectively.

[0067] Figure 12 the view direction of Figure 10 is the same as that of

[0068] Wherein, for the convenience of observation, Figure 12 only the relationship between the stacked gate structure 201, the shielding gate 205, and the source-drain doping region 207 on the substrate is shown.

[0069] In this embodiment, during the programming process, a high voltage is applied to the control gate layer 201d, the source-drain doped region 207 is grounded, and electrons in the depletion region pass through the thin oxide layer barrier with a certain probability under the action of a strong electric field and are captured by the floating gate layer 201b. Since the bottom of the shielding gate 205 is electrically connected to the doped region 204, a low-impedance path is formed. When a programming voltage (high) is applied to the control gate layer 201d (CG), the electric field is mainly concentrated between the shielding gate 205 and the doped region 204, rather than directly acting on the adjacent stacked gate structure 201. This low-impedance path can effectively disperse the electric field, reduce the interference of the electric field on the adjacent stacked gate structure 201, and shield the floating gate layer 201b (FG) of the adjacent stacked gate structure 201, preventing the adjacent stacked gate structure 201 from being partially programmed (program disturb) due to electric field coupling. This shielding effect significantly improves the isolation between adjacent stacked gate structures 201 and reduces the probability of misoperation.

[0070] Correspondingly, the present invention further provides a semiconductor device. Please refer to Figure 11 and Figure 12 , including a substrate 200; an array of stacked gate structures 201 parallelly distributed along a first direction on the surface of the substrate 200; sidewalls 202 located on the sidewalls of the stacked gate structures 201 along a second direction, with a gap 203 between adjacent sidewalls 202, the first direction being perpendicular to the second direction; a doped region 204 in the substrate 200 between adjacent sidewalls 202; a shielding gate 205 in the gap 203 between adjacent sidewalls 202, the bottom of the shielding gate 205 being electrically connected to the doped region 204.

[0071] In this embodiment, due to the presence of the shielding gate 205, during the programming of the NAND flash memory, a high voltage is applied to the stacked gate structure 201, the source-drain (source-drain doped region 207) terminal is grounded, and at this time, the potential of the shielding gate is 0V. Then, the voltage coupling effect between adjacent stacked gate structures 201 is shielded by the shielding gate 205, reducing the interference between adjacent stacked gate structures 201, thereby improving the overall performance of the NAND flash memory, reducing the probability of misoperation, and enhancing the stability during long-term use.

[0072] In this embodiment, the doped region 204 contains a first doping ion, the shielding gate 205 contains a second doping ion, and the type of the first doping ion is the same as that of the second doping ion.

[0073] In this embodiment, the stacked gate structure 201 includes a tunneling dielectric layer 201a on the surface of the substrate 200; a floating gate layer 201b on the surface of the tunneling dielectric layer 201a; an inter-gate dielectric layer 201c on the surface of the floating gate layer 201b; a control gate layer 201d on the surface of the inter-gate dielectric layer 201c; and a mask layer 201e formed on the surface of the control gate layer 201d.

[0074] In this embodiment, the top surface of the shielding gate 205 is not lower than the bottom surface of the mask layer 201e, and the material of the shielding gate 205 is polysilicon.

[0075] In this embodiment, the upper end of the shielding gate 205 is in a floating state.

[0076] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; An array of stacked gate structures distributed in parallel along a first direction on the surface of the substrate; Sidewalls located on the sidewalls of the stacked gate structure along a second direction, with gaps between adjacent sidewalls, and the first direction is perpendicular to the second direction; a doped region in the substrate between adjacent sidewalls; A shielding gate is located in the gap between adjacent sidewalls, and a bottom of the shielding gate is electrically connected to the doped region.

2. The semiconductor device according to claim 1, wherein The doping region has first doping ions, the shielding gate has second doping ions, and the type of the first doping ions is the same as the type of the second doping ions.

3. The semiconductor device according to claim 1, wherein The stacked gate structure includes a tunneling dielectric layer located on the surface of the substrate; A floating gate layer located on the surface of the tunnel dielectric layer; an inter-gate dielectric layer located on the surface of the floating gate layer; and a control gate layer located on the surface of the inter-gate dielectric layer; A mask layer is formed on the surface of the control gate layer.

4. The semiconductor device according to claim 3, characterized in that The top surface of the shielding gate is not lower than the bottom surface of the mask layer, and the material of the shielding gate is polysilicon.

5. The semiconductor device according to claim 1, wherein: The upper end of the shielding gate is in a floating state.

6. A method for forming a semiconductor device, characterized in that: include: providing a substrate; Forming an array of stacked gate structures distributed in parallel along a first direction on the surface of the substrate; Forming sidewalls on the sidewalls of the stacked gate structure along a second direction, with gaps between adjacent sidewalls, and the first direction is perpendicular to the second direction; Performing ion doping on the substrate between adjacent stacked gate structures to form a doped region; A shielding gate is formed on the surface of the substrate between adjacent sidewalls, the shielding gate completely fills the gap, and the bottom of the shielding gate is electrically connected to the doping region.

7. The method for forming a semiconductor device according to claim 6, wherein: The doping region has first doping ions, the shielding gate has second doping ions, and the type of the first doping ions is the same as the type of the second doping ions.

8. The method for forming a semiconductor device according to claim 6, wherein: The stacked gate structure includes a tunneling dielectric layer formed on the surface of the substrate; a floating gate layer formed on the surface of the tunneling dielectric layer; an intergate dielectric layer formed on the surface of the floating gate layer; a control gate layer formed on the surface of the intergate dielectric layer; and a mask layer formed on the surface of the control gate layer.

9. The method for forming a semiconductor device according to claim 8, wherein: The top surface of the shielding grid is not lower than the bottom surface of the mask layer.

10. The method for forming a semiconductor device according to claim 8, wherein: The method for forming the stacked gate structure comprises: forming an initial tunneling dielectric layer on the surface of the substrate; forming an initial floating gate layer on the surface of the initial tunneling dielectric layer; forming the initial inter-gate dielectric layer on the surface of the initial floating gate layer; forming an initial control gate layer on the surface of the initial inter-gate dielectric layer; forming an initial mask layer on a surface of the initial control gate layer; A mask plate is provided, and the initial mask layer, the initial control gate layer, the initial inter-gate dielectric layer, the initial floating gate layer and the initial tunnel dielectric layer are etched at one time using the mask plate as a mask to form the stacked gate structure on the substrate.

11. The method for forming a semiconductor device according to claim 6, wherein: The method of forming the shielding grid comprises: Depositing polysilicon on the surface of the substrate between the sidewalls, wherein the polysilicon layer fills the gap; In-situ doping is performed simultaneously during the process of depositing the polysilicon.

12. The method for forming a semiconductor device according to claim 8, wherein: After forming the shielding gate, it also includes: forming a dielectric layer on the substrate, the dielectric layer is formed on the top surface of the mask layer, the top surface of the shielding gate and the side wall of the side wall; performing source and drain doping on the substrate on both sides of the dielectric layer to form source and drain doping areas.

13. The method for forming a semiconductor device according to claim 6, wherein: The sidewall spacer includes an oxide layer formed on a sidewall of the stacked gate structure and a silicon nitride layer formed on a sidewall of the oxide layer.

14. The method for forming a semiconductor device according to claim 13, wherein: The method for forming the sidewall comprises: depositing an initial oxide layer on the top surface and sidewall surface of the stacked gate structure; depositing an initial silicon nitride layer on the surface of the initial oxide layer; forming a sacrificial oxide layer on the surface of the initial silicon nitride layer; using an etching process to form an oxide layer on the sidewall surface of the stacked gate structure, forming a silicon nitride layer on the sidewall surface of the oxide layer, and forming a sacrificial oxide layer on the sidewall surface of the silicon nitride layer; and removing the sacrificial oxide layer to form the sidewall.

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