Ferroelectric memory device

Abstract

In one aspect, a ferroelectric memory device is provided, comprising: a memory array arranged in a next process interconnect structure of the memory device, comprising: a vertical stack of horizontally extending plate lines; and a pillar structure vertically extending through the plate line stack and including a metal core and a memory layer stack, the memory layer stack including an oxide semiconductor layer circumferentially surrounding the metal core and a ferroelectric layer circumferentially surrounding the oxide semiconductor layer, in which a vertical stack of ferroelectric storage capacitors is defined along the pillar structure, the memory device further includes a bit line select transistor including a first current terminal coupled to a bit line of the memory array, a second current terminal coupled to a metal core of the pillar structure, and a gate terminal coupled to a bit select line; a plate line selection transistor coupled to a respective one of the plate lines; and a sensing circuit coupled to the metal core of the pillar structure.

Description

Technical Field

[0001] The present invention generally relates to ferroelectric memory devices. Background Art

[0002] Ferroelectric random access memory (FeRAM) is a non-volatile memory technology that uses ferroelectric capacitors to store information in the form of polarization states in a ferroelectric layer between capacitor electrodes. By applying an electric field of sufficient strength in a direction opposite to the current polarization state, the ferroelectric layer can be switched between two opposite polarization states.

[0003] According to a conventional read operation, the polarization state of a ferroelectric capacitor can be sensed by applying a voltage across the capacitor electrodes, which results in the amount of bit line charging depending on the polarization state of the ferroelectric capacitor. Thus, the read operation is destructive, meaning that after reading, the sensed polarization state needs to be rewritten to the ferroelectric capacitor.

[0004] Another read approach that has been studied involves sensing the capacitance of a ferroelectric capacitor. This approach is based on the fact that the capacitance of the ferroelectric layer varies with the polarization state of the ferroelectric layer. However, the capacitance change exhibited in conventional metal-ferroelectric-metal (MFM) capacitors (e.g., ferroelectric layers including Hf 0.5 Zr 0.5 O2) is typically limited to about 10 - 20% (Luo et al., "Non-volatile, small-signal capacitance in ferroelectric capacitors", Appl. Phys. Lett., 117, 073501, 2020). Using metal-ferroelectric-semiconductor (MFS) or metal-ferroelectric-semiconductor-insulator (MFIS) stacks, the polarization state of the ferroelectric layer can be pushed into depletion or accumulation, allowing capacitance changes of more than 100% (Tripathi et al., "Investigation of BiFeO3 / HfO2 gate stack for ferroelectric field effect transistors in IOT applications", Journal of Materials Science: Materials in Electronics, 32:22517 - 22526, 2021). Summary of the Invention

[0005] While the above technologies are promising, they are limited to proof-of-concept in small-scale laboratory environments. Therefore, there is a need to provide a ferroelectric memory device whose design allows non-destructive readout based on capacitance sensing and can also be scaled up to achieve high memory density. The object of the present invention is to provide a ferroelectric memory device suitable for FeRAM to achieve one or more of these objectives.

[0006] Accordingly, in one aspect of the present invention, there is provided a ferroelectric memory device comprising:

[0007] a memory array disposed in a back-end-of-line interconnect structure of the memory device, the memory array comprising:

[0008] a vertical stack of horizontally extending plate lines; and

[0009] a column structure that vertically extends through the plate line stack and includes a metal core and a storage layer stack, the storage layer stack including an oxide semiconductor layer that circumferentially surrounds the metal core and a ferroelectric layer that circumferentially surrounds the oxide semiconductor layer,

[0010] wherein a vertical stack of ferroelectric storage capacitors is defined along the column structure, each ferroelectric storage capacitor including a first capacitor electrode formed by a plate line in the plate line stack, a second capacitor electrode formed by the metal core of the column structure, and a storage region formed by a portion of the storage layer stack sandwiched between the corresponding first capacitor electrode and the metal core;

[0011] the memory device further comprising:

[0012] a bit line selection transistor including a first current terminal coupled to a bit line of the memory array, a second current terminal coupled to the metal core of the column structure, and a gate terminal coupled to a bit select line;

[0013] a plate line selection transistor coupled to a corresponding one of the plate lines; and

[0014] a sensing circuit coupled to the metal core of the column structure.

[0015] Thus, this aspect is based on the concept that a vertical stack of ferroelectric (FE) storage capacitors based on metal-ferroelectric-semiconductor-metal (MFSM) can be realized in an effective area along a common vertical column structure that includes an internal metal core (M) forming a common capacitor electrode for the ferroelectric storage capacitor stack, an oxide semiconductor layer (S) formed on the sidewall of the internal metal core to circumferentially surround the internal metal core, a ferroelectric layer (F) formed on the oxide semiconductor layer and circumferentially surrounding it, and a stack of metal plate lines (M) defining the respective body capacitor electrodes of the individual ferroelectric storage capacitors of the stack.

[0016] As described in the background art section, a ferroelectric layer and a semiconductor layer are combined and used as a storage stack in a ferroelectric storage capacitor, such that the polarization state of the ferroelectric layer can push the semiconductor layer into depletion or accumulation, thereby allowing a large capacitance change between the polarization states. For an oxide semiconductor, such as in the ferroelectric storage capacitor of the memory device in this aspect, this effect can also be achieved. This enables the memory device to employ a capacitance-based sensing scheme for a sensing circuit coupled to a metal core of a column structure. In other words, the sensing circuit can be configured to sense the polarization state of the ferroelectric layer by sensing the capacitance of any one (e.g., selected by appropriately switching a bit selection transistor and a plate line selection transistor) of the vertically stacked ferroelectric storage capacitors. The capacitive sensing technique will be elaborated in detail below.

[0017] In addition, compared with a silicon-based MFSM FE capacitor, specifically setting the semiconductor layer as an oxide semiconductor has many advantages:

[0018] The oxide semiconductor has a larger bandgap (>3 eV) than Si and is not easily inverted due to the lack of minority carriers. At the same time, the ferroelectric layer can be programmed to push the oxide semiconductor layer into accumulation (corresponding to a higher capacitance state) or depletion (corresponding to a lower capacitance state).

[0019] In addition, traditional silicon-based MFS devices may include a SiOx interface layer, which may cause electrons to be trapped, thereby reducing the endurance performance. Traditional silicon-based MFS devices are typically limited to 10 4 -10 6 cycles. However, the interface layer can be omitted in the oxide semiconductor-based MFSM capacitor in this aspect. This results in a lower trapping rate and thus higher endurance (e.g., estimated >10 8 cycles).

[0020] In addition, due to the absence of an interface oxide layer, the depolarization field in the oxide semiconductor-based MFSM capacitor can be lower than that in the silicon-based MFSM. This can improve the retention ability.

[0021] Since the internal metal core serves as a common capacitor electrode for the stack of FE capacitors, both the bit line selection transistor and the sensing circuit can be shared by all the ferroelectric storage capacitors of the stack. At the same time, providing a corresponding plate line selection transistor for each ferroelectric storage capacitor of the stack helps to individually address any FE capacitor of the stack.

[0022] In some embodiments, the bit line select transistor is disposed on top of the column structure and includes a channel layer of an oxide semiconductor material. Thus, the bit line select transistor can be stacked on top of the vertical stack of ferroelectric storage capacitors, further contributing to area efficiency. The stacking is achieved by the oxide semiconductor material of the channel layer, which is compatible with back-end-of-line processing.

[0023] The oxide semiconductor layer and / or the channel layer of the column structure can be formed of the same or different oxide semiconductor materials. Using the same material can enable more reasonable manufacturing. Employing an oxide semiconductor material with a high channel mobility for the channel layer of the bit line select transistor can further enable efficient driving of the bit line.

[0024] In some embodiments, the metal core of the column structure is coupled to a reference voltage node via a reference capacitor disposed below the vertical stack of ferroelectric storage capacitors, and wherein the sense circuit is coupled to a sense node between the metal core and the reference capacitor. Thus, the reference capacitor can be configured with the metal core to define a capacitive voltage divider. By being coupled to the sense node between the metal core and the reference capacitor (i.e., the sense node of the capacitive voltage divider), the sense circuit can thus be configured to sense the capacitance at the sense node and thereby sense the polarization state implied by the capacitance. The reference capacitor allows adjustment of the effective capacitance at the sense node to facilitate capacitive sensing.

[0025] With the ferroelectric layer, each ferroelectric storage capacitor in the stack of ferroelectric storage capacitors can be switched between a first polarization state and a second polarization state, the first polarization state resulting in a first capacitance of the ferroelectric storage capacitor and the second polarization state resulting in a second capacitance of the ferroelectric storage capacitor, the second capacitance being less than the first capacitance.

[0026] In some embodiments, the ratio of the capacitance at the sense node to the second capacitance (second capacitance ratio CR2) exceeds the ratio of the capacitance at the sense node to the first capacitance (first capacitance ratio CR1) by a factor of 1.3 or greater. A larger ratio means a greater capacitance difference between the two polarization states of the ferroelectric storage capacitor. This in turn means that a lower read voltage is required to easily distinguish between the first and second polarization states. The MFSM structure of the ferroelectric storage capacitor achieves a second capacitance ratio to first capacitance ratio (i.e., CR2 / CR1≥1.3) of 1.3 or greater. In fact, the oxide semiconductor layer can achieve higher ratios, such as CR2 / CR1≥2, or even CR2 / CR1≥3.

[0027] Depending on the conduction type (n or p) of the oxide semiconductor layer, the first polarization state (higher capacitance) can correspond to the erased state of the ferroelectric capacitor, and the second polarization state can correspond to the programmed state of the ferroelectric capacitor (for n-type), or vice versa (for p-type).

[0028] In some embodiments, the memory device further includes a memory controller configured to perform a read operation to determine the polarization state of a selected ferroelectric storage capacitor in a stack of ferroelectric storage capacitors by the following steps:

[0029] Disable each bit line selection transistor;

[0030] Enable the plate line selection transistor coupled to the plate line associated with the selected ferroelectric storage capacitor;

[0031] Apply a read voltage to the plate line associated with the selected ferroelectric storage capacitor via the enabled plate line selection transistor, wherein the read voltage is distributed across the selected ferroelectric storage capacitor and a reference capacitor; and

[0032] Determine the polarization state of the selected ferroelectric storage capacitor by using a sense circuit to sense the voltage at the sense node in response to the read voltage.

[0033] According to the read operation, the memory controller can thus select a ferroelectric storage capacitor in the stack of storage capacitors whose polarization state is to be read and determine the polarization state based on the voltage at the sense node caused by the read voltage.

[0034] The amplitude of the read voltage can ensure that the read operation does not cause a state transition of the FE storage capacitor. In other words, the read voltage causes the portion of the read voltage distributed across the selected ferroelectric storage capacitor to be less than the voltage required to switch the polarization state of the selected ferroelectric memory capacitor.

[0035] In some embodiments, the sense circuit includes a differential amplifier configured to compare the voltage at the sense node with a reference sense voltage. Thus, the polarization state of the selected ferroelectric storage capacitor can be determined by comparing the sense node voltage generated by the read voltage with the reference sense voltage. Therefore, the differential amplifier can detect and amplify the difference between the sense node voltage and the reference sense voltage, where the difference indicates the polarization state.

[0036] In some embodiments, the sense circuit may instead include a sense transistor having a gate coupled to the sense node, a first current terminal coupled to a reference voltage node, and a second current terminal coupled to an amplifier of the memory device. Thus, the sense node voltage can be used to bias the gate of the sense transistor, thereby affecting the drain-source current and drain voltage of the sense transistor, which in turn can be amplified or sensed by the sense amplifier. The amplifier can be a sense amplifier configured to sense the voltage at the sense node by sensing the current passing through the sense transistor in response to the read voltage.

[0037] In some embodiments, the effective capacitance at the sense node is such that, in response to a read voltage, the sense transistor is enabled when the selected ferroelectric storage capacitor is in a first polarization state and disabled when the selected ferroelectric storage capacitor is in a second polarization state. Thus, the sense node voltage can be used to turn off or on the sense transistor, thereby creating a large difference in sense current between the polarization states.

[0038] The memory device of the first aspect can be extended to include a plurality of vertical stacks of memory cells. Thus, in some embodiments, the stack of plate lines extends in the row direction of the memory array, and the memory array further includes a set of bit lines, where the bit lines extend above and across the stack of plate lines in the column direction of the memory array to define a row of intersections between the set of bit lines and the stack of plate lines. The memory array includes:

[0039] A column structure at each intersection, each column structure extending vertically through the stack of plate lines and including a metal core and a stack of storage layers, the stack of storage layers including a ferroelectric layer and an oxide semiconductor layer circumferentially surrounding the metal core.

[0040] Wherein a vertical stack of ferroelectric storage capacitors is defined along the respective column structure at each intersection, each ferroelectric storage capacitor in each ferroelectric storage capacitor stack includes a first capacitor electrode formed by a plate line in the stack of plate lines, a second capacitor electrode formed by the metal core of the respective column structure, and a storage region formed by a portion of the stack of storage layers of the respective column structure sandwiched between the respective first capacitor electrode and the respective metal core.

[0041] Wherein the memory device includes a respective bit line selection transistor associated with each respective intersection, each bit line selection transistor including a first current terminal coupled to the bit line at the respective intersection, a second current terminal coupled to the metal core of the column structure at the respective intersection, and a gate terminal coupled to a word selection line.

[0042] Wherein the sense circuit is connected to the metal core of each column structure.

[0043] Thus, a plurality of column structures corresponding to the number of bit lines can be arranged to extend through the stack of plate lines and accordingly define a vertical stack of a row of FE storage capacitors. Thus, the stack of plate lines can be shared by the vertical stack of this row of ferroelectric storage capacitors. The details and advantages discussed above with reference to a single vertical stack of ferroelectric storage capacitors apply accordingly to each vertical stack of this row.

[0044] In some embodiments, the bit - line selection transistors are disposed on top of the column structures at the associated intersections and include a channel layer of oxide semiconductor material. Similar to the above discussion, thus, a bit - line selection transistor compatible with back - end - of - line integration can be provided for each stack of ferroelectric storage capacitors with substantially no area penalty.

[0045] In some embodiments, the gate terminals of each bit - line selection transistor are coupled to a respective bit - select line. Thus, any stack of ferroelectric storage capacitors can be individually addressed, for example, during a read or write, by selectively biasing its associated bit - select line.

[0046] In some embodiments, the gate terminals of the bit - line selection transistors along a row are instead coupled to the same bit - select line. Since the metal columns forming the common second capacitor electrodes of the individual vertical stacks of ferroelectric storage capacitors are coupled to respective sense circuits, any ferroelectric storage capacitor along a row can be selectively read despite the shared bit - select line. Thus, the shared bit - select line can facilitate routing and biasing schemes during a read. Additionally, since no space for an insulating region between the gate terminals of the bit - line selection transistors is required, the vertical stacks can be more closely spaced. In addition to providing higher density, since fewer processing masks are required, the manufacturing cost and complexity can be reduced. However, selective writing may require additional considerations, which will be discussed further below.

[0047] In embodiments where the gate terminals of each bit - line selection transistor are coupled to respective bit - select lines, the memory device may further include write circuitry implementing a first write scheme, where the write circuitry may be configured to:

[0048] Selectively enable one of the plate - line selection transistors, the enabled plate - line selection transistor being coupled to a plate line (hereinafter referred to as the "selected plate line") associated with a first group of ferroelectric storage capacitors to be erased and a second group of ferroelectric storage capacitors to be programmed,

[0049] And when the selected plate - line selection transistor is enabled:

[0050] Perform an erase step, including: selectively enabling the bit - line selection transistors coupled to the first group of ferroelectric storage capacitors and simultaneously applying an erase voltage to the selected plate line (i.e., applying when the bit - line selection transistors are enabled) and a reference voltage to the bit lines coupled to the enabled bit - line selection transistors; and

[0051] Perform a programming step, including: selectively enabling the bit - line selection transistors coupled to the second group of ferroelectric storage capacitors and simultaneously applying a programming voltage to the bit lines coupled to the enabled bit - line selection transistors (i.e., applying when the bit - line selection transistors are enabled) and a reference voltage to the selected plate line.

[0052] Accordingly, the erase step and the program step can be sequentially applied to the ferroelectric storage capacitor along the selected plate line. The erase step can be performed before or after the program step.

[0053] The first and second sets of ferroelectric storage capacitors can each include one or more ferroelectric storage capacitors.

[0054] The erase voltage and the program voltage can each be a positive voltage (i.e., relative to a reference voltage). The reference voltage can generally be a ground reference voltage, such as approximately 0V. This is a convenient choice because a negative bias generator is not required to generate the reference voltage. In any case, it will be understood that the polarity and magnitude of the bias voltage across each storage capacitor in the first set of ferroelectric storage capacitors caused by the reference voltage and the erase voltage should be sufficient to bring the ferroelectric storage capacitor to the erase state (corresponding to the first capacitance value if the oxide semiconductor layer is n-type, and corresponding to the second capacitance value if the oxide semiconductor layer is p-type). This correspondingly applies to the reference voltage and the program voltage.

[0055] Since the erase and program steps are applied through individually addressable bit lines, the erase and program voltages can be selectively applied. Thus, the first write scheme is associated with a low risk of disturbing ferroelectric storage capacitors that are not selected for erasure or writing along the selected plate line.

[0056] However, in non-ideal situations, there may be leakage through unenabled select transistors and / or capacitive coupling through unintentional voltage dividers, such that the erase and program voltages applied to the selected plate line and bit lines may still disturb unselected ferroelectric storage capacitors.

[0057] Therefore, to further reduce the risk of interference during the erase process, the erase step can further include: simultaneously applying an erase voltage to the selected plate line and a reference voltage to the bit lines coupled to the enabled bit line select transistors, and applying a partial program voltage to the bit lines coupled to the second set of ferroelectric storage capacitors. Specifically, the partial program voltage can be applied to all unselected bit lines (i.e., the bit lines coupled to unenabled bit line select transistors).

[0058] Accordingly, to further reduce the risk of interference during the program process, the program step can further include: simultaneously applying a program voltage to the bit lines coupled to the enabled bit line select transistors and a reference voltage to the selected plate line, and applying a partial program voltage to the bit lines coupled to the first set of ferroelectric storage capacitors. Specifically, the partial program voltage can be applied to all unselected bit lines (i.e., the bit lines coupled to unenabled bit line select transistors).

[0059] This causes the voltage across non-selected ferroelectric memory capacitors to remain small (ideally close to 0V) during the erase and program processes.

[0060] The partial program voltage can be approximately half of the program voltage. More generally, the partial program voltage can be any (positive) voltage corresponding to a fraction of the program voltage, such that the bias voltage across non-selected ferroelectric memory capacitors can be limited during erase and program.

[0061] For corresponding reasons, to further reduce the risk of disturbing ferroelectric memory capacitors along non-selected plate lines, the write circuitry can also be configured to apply a partial erase voltage to the non-selected plate lines during the erase step and the program step. The partial erase voltage can be approximately half of the erase voltage. More generally, the partial erase voltage can be any (positive) voltage corresponding to a fraction of the erase voltage, such that the bias voltage across non-selected ferroelectric memory capacitors along non-selected plate lines can be limited during erase and program.

[0062] In embodiments where the gate terminals of the bit line select transistors are coupled to the same bit select line, the memory device can further include write circuitry implementing a second write scheme, where the write circuitry can be configured to:

[0063] Selectively enable one of the plate line select transistors and each bit line select transistor, where the enabled plate line select transistor is coupled to a plate line associated with a first set of ferroelectric memory capacitors to be erased and a second set of ferroelectric memory capacitors to be programmed (hereinafter referred to as the "selected plate line"),

[0064] And when the selected plate line select transistor and each bit line select transistor are enabled:

[0065] Perform an erase step, including: simultaneously applying an erase voltage to the selected plate line and a reference voltage to each bit line; and

[0066] Perform a program step, including: simultaneously applying a program voltage to the bit lines coupled to the second set of ferroelectric memory capacitors, a partial program voltage to the bit lines coupled to the first set of ferroelectric memory capacitors, and a reference voltage to the selected plate line.

[0067] Thereby, the erase step and the program step can be sequentially applied to the ferroelectric memory capacitors along the selected plate line. The erase step can typically be performed before or after the program step. Thus, first, all ferroelectric memory capacitors along the selected plate line can be erased, and then a program voltage can be selectively applied to the second set of FE memory capacitors to be programmed, such that the first set of FE memory capacitors remains in the erased state.

[0068] As with the first write scheme, the erase voltage and the program voltage can each be a positive voltage (i.e., relative to a reference voltage). The reference voltage can typically be a ground reference voltage, such as approximately 0V. This is a convenient choice because no negative bias generator is required to generate the reference voltage. In any case, it will be understood that the polarity and magnitude of the bias across each of the ferroelectric storage capacitors in the first and second sets caused by the reference voltage and the erase voltage should be sufficient to bring the ferroelectric storage capacitors to the erased state (corresponding to the first capacitance value if the oxide semiconductor layer is n-type and corresponding to the second capacitance value if the oxide semiconductor layer is p-type). Correspondingly, the polarity and magnitude of the bias across each of the ferroelectric storage capacitors in the second set caused by the reference voltage and the program voltage should be sufficient to set the ferroelectric storage capacitors of the second set to the programmed state (corresponding to the second capacitance value if the oxide semiconductor layer is n-type and corresponding to the first capacitance value if the oxide semiconductor layer is p-type). At the same time, the polarity and magnitude of the bias across each of the ferroelectric storage capacitors in the first set generated by the reference voltage and the partial program voltage should keep the ferroelectric storage capacitors of the first set in the erased state.

[0069] Since the erase and program steps are applied through generally addressable bit lines, the second write scheme is associated with an increased risk of disturbing the ferroelectric storage capacitors along the non-selected plate lines.

[0070] Accordingly, the write circuitry can also be configured to further apply a partial erase voltage to the non-selected plate lines during the program step. The partial erase voltage can be approximately two-thirds (~2 / 3) of the erase voltage. More generally, the partial erase voltage can be any (positive) voltage corresponding to a portion of the erase voltage, so as to limit the bias across the non-selected ferroelectric storage capacitors along the non-selected plate lines during erase and program. The write circuitry can also be configured to further apply the reference voltage to the non-selected plate lines during the erase step.

[0071] In some embodiments, a single or plural plate line selection transistors and sense circuitry are included in the peripheral complementary metal oxide semiconductor (CMOS) circuitry of the memory device.

[0072] The memory device of the first aspect can be further extended to include a plurality (e.g., two or more) vertical stacks of plate lines, where a vertical stack of ferroelectric storage capacitors is formed along each plate line stack. Thus, in some embodiments, the memory array includes:

[0073] A set of vertical stacks of plate lines that extend parallel in the row direction of the memory array and are spaced apart in the column direction of the memory array, where the set of bit lines extends above and across each plate line stack to define a plurality of rows and columns of intersections between the set of bit lines and the plate line stacks.

[0074] Column structures at each intersection, each column structure extending vertically through the stack of plate lines at the intersection and including a metal core and a storage layer stack, the storage layer stack including a ferroelectric layer and an oxide semiconductor layer circumferentially surrounding the metal core.

[0075] Wherein a vertical stack of ferroelectric storage capacitors is defined along each corresponding column structure at each intersection, each ferroelectric storage capacitor in each ferroelectric storage capacitor stack including a first capacitor electrode formed by a plate line in the stack of plate lines at the intersection, a second capacitor electrode formed by the metal core of the corresponding column structure, and a storage region formed by a portion of the storage layer stack of the corresponding column structure sandwiched between the corresponding first capacitor electrode and the corresponding metal core.

[0076] Wherein the memory device includes a corresponding bit line selection transistor associated with each corresponding intersection, each bit line selection transistor including a first current terminal coupled to the bit line at the corresponding intersection, a second current terminal coupled to the metal core of the column structure at the corresponding intersection, and a gate terminal coupled to a word selection line.

[0077] Wherein the sensing circuit of the CMOS periphery is connected to the metal core of each column structure.

[0078] The details and advantages discussed above with reference to a single stack of plate lines and a single row of vertical stacks of FE storage capacitors apply correspondingly to each of the stacks of plate lines and each of the rows of vertical stacks. Therefore, they will not be repeated here, but reference may be made to the above content.

[0079] In some embodiments, the bit line selection transistors arranged along the same column of intersections are coupled to a common bit line.

[0080] In some embodiments, the gate terminals of the bit line selection transistors arranged along the same row are coupled to the same word selection line or corresponding word selection lines.

[0081] In some embodiments, the gate terminals of the bit line selection transistors are formed in a gate metal layer covering each of the groups of plate line stacks.

[0082] In some embodiments, each stack of plate lines defines a stepped structure located in the peripheral region of the memory array, and wherein each plate line is coupled to a corresponding plate line selection transistor through a horizontal plate interconnect, first and second vertical plate interconnects, and the current terminals of the corresponding plate line selection transistor, the horizontal plate interconnect being arranged in an interconnect layer above the stepped structure, and the first and second vertical plate interconnects extending from the horizontal plate interconnect and landing on the plate lines at the stepped structure respectively. Description of the Drawings

[0083] The present invention will now be described in more detail with reference to the accompanying drawings showing embodiments of the invention.

[0084] Figure 1 A first cross-sectional view of a memory device according to an embodiment is schematically shown.

[0085] Figure 2 Shown Figure 1 is a second cross-sectional view of the memory device.

[0086] Figure 3 Schematically shown Figure 1 is a third cross-sectional view of the memory device.

[0087] Figure 4 Schematically shown Figure 1 is a top view of the memory device.

[0088] Figure 5 Shown Figure 1 is a circuit diagram of a portion of the memory device shown in the first cross-sectional view.

[0089] Figure 6a -c shows different implementations of the sense circuit.

[0090] Figure 7 Shown is a first write scheme applicable to Figure 1 the memory device.

[0091] Figure 8 A cross-sectional view of a memory device according to yet another embodiment is schematically shown.

[0092] Figure 9 Schematically shown Figure 8 is a top view of the memory device.

[0093] Figure 10 Shown is a second write scheme applicable to Figure 9 the memory device. DETAILED DESCRIPTION

[0094] Embodiments of a memory device based on a vertically stacked ferroelectric storage capacitor will now be described with reference to the accompanying drawings. The drawings are only schematic, and the relative dimensions of some structures and layers may be exaggerated and not drawn to scale. Instead, the dimensions may be adjusted to make the drawings clear and facilitate understanding of the following description. When present in the figures, the indicated axes X, Y, and Z respectively consistently refer to the first horizontal or lateral, second horizontal or lateral, and vertical directions. As used herein, the terms "horizontal" and "lateral" refer to directions parallel to the support substrate of the memory device. The term "vertical" refers to a direction parallel to the normal direction of the substrate, i.e., transverse to the substrate. The X and Y directions may be referred to as the row direction and column direction of the memory array of the memory device, respectively.

[0095] Figures 1-3 Schematically shown are first, second, and third cross-sectional views of a ferroelectric memory device 1 (hereinafter interchangeably referred to as "memory device"), taken along lines A-A, B-B, and C-C shown in the top view of Figure 4 respectively. Figure 5 Further shown is Figure 1 a circuit diagram of a portion of the memory device 1 shown in the first cross-sectional view of

[0096] The memory device 1 includes a substrate 2 and a memory array 10 disposed in a back-end-of-line (BEOL) interconnect structure of the memory device 1, the BEOL interconnect structure being disposed on the substrate 2. The memory array 10 includes a vertical stack of plate lines 100 horizontally extending in the row direction X of the memory array 10.

[0097] The memory array 10 further includes pillar structures 11. As used herein, consistent with Figure 1 the term "pillar structure" refers to a columnar structure (usually cylindrical) extending in the vertical direction Z with respect to the substrate 2.

[0098] The pillar structures 11 extend vertically through the stack of plate lines 100. The pillar structures 11 include vertically extending metal cores 111 (e.g., usually cylindrical). The metal cores 111 are circumferentially surrounded by a storage layer stack. The storage layer stack includes an oxide semiconductor layer 112 disposed on the circumferential sidewalls of the metal cores 111 and circumferentially surrounding the metal cores 111. The storage layer stack further includes a ferroelectric layer 113 disposed on the oxide semiconductor layer 112 and circumferentially surrounding the oxide semiconductor layer 112. The storage layer stack can accordingly define an annular hollow cylindrical layer stack surrounding the metal cores 111.

[0099] By the vertical extension of the pillar structures 11 through the stack of plate lines 100, a vertical stack of ferroelectric storage capacitors 114 (hereinafter interchangeably referred to as "storage capacitor stack") is defined along the pillar structures 11. The storage capacitor stack 114 includes ferroelectric storage capacitors (hereinafter interchangeably referred to as "storage capacitors") the number of which corresponds to the number of plate lines in the stack of plate lines 100. In the example shown, the stack of plate lines 100 includes four plate lines PL1 - PL4, and thus the storage capacitor stack 114 includes four storage capacitors 1141, 1142, 1143, 1144. As shown, each storage capacitor 1141, 1142, 1143, 1144 includes a first capacitor electrode formed by a corresponding plate line in the stack of plate lines 100, a second capacitor electrode formed by the metal core 111 of the pillar structure 11, and a storage region formed by that portion of the storage layer stack (i.e., the oxide semiconductor layer 112 and the ferroelectric layer 113) laterally sandwiched between the corresponding first capacitor electrode and the metal core.

[0100] The metal core 111 can be formed of any suitable CMOS-compatible metal, such as having a sufficiently low resistance and filling characteristics. Non-limiting examples of metals for the metal core 111 include W, TiN, Ti, Ru, Cu, Ta, TaN, or Al, or combinations thereof.

[0101] The oxide semiconductor layer 112 can be formed of one or more suitable oxide semiconductors, such as having a sufficiently large bandgap. A single layer, bilayer, or multi-layer combination of the oxide semiconductor layer 112 is possible. Non-limiting examples of suitable oxide semiconductor materials include indium gallium zinc oxide (IGZO), ZnO, WO, InWO, InSnO, GaZnO, MgZnO, MgAlZnO, and MoO.

[0102] The ferroelectric layer 113 can be formed of any suitable ferroelectric material, such as having a sufficiently large electric coercive force. A single layer, bilayer, or multi-layer combination of the ferroelectric layer 113 is possible. In addition, one or more ferroelectric material layers can be combined with one or more dielectric layers to form a composite ferroelectric layer 113. Non-limiting examples of ferroelectric materials include doped or undoped HZO or HfO2. Possible dopants for HZO include La, Al, Sc, Gd, Y. Possible dopants for HfO2 include the above dopants and additionally include Si. Other non-limiting examples of suitable ferroelectric materials include HfAlO, PZT, BaTiO3, PbTiO3, PbZrO3, and BiFeO3.

[0103] The plate line 100 can be formed of any suitable conventional metal used to form metal wire interconnects in BEOL, such as W, Al, Cu.

[0104] Each of the storage capacitors 1141, 1142, 1143, 1144 can switch between a first polarization state that results in a first capacitance C high and a second polarization state that results in a second capacitance C low < C high The ferroelectric layer 113 allows each storage capacitor to maintain the polarization state written to the storage capacitor and can thus be used as a non-volatile storage element.

[0105] The memory device 1 further includes a bit line selection transistor BST1 disposed on top of the column structure 11. The bit line selection transistor BST1 includes a first current terminal (e.g., drain) coupled to the bit line BL1 of the memory array 1, a second current terminal (e.g., source) coupled to the metal core 111 of the column structure 11, and a gate terminal coupled to the bit selection line WBS1. The second current terminal of the bit line selection transistor BST1 can be directly disposed on the metal core 111, i.e., in physical contact with the metal core 111, thus avoiding the need for additional vertical interconnections between the bit line selection transistor BST1 and the metal core 111.

[0106] As Figure 4 shown, the gate terminal of the bit line selection transistor BST1 can be formed by a gate metal layer GL1 that covers the stack of plate lines 100 and surrounds the channel layer of the bit line selection crystal BST1. The gate metal layer GL1 can be coupled to the bit selection line WBS1 through a vertical connection (e.g., a metal via). The connection between the gate terminal / gate metal layer GL1 and the bit selection line WBS1 is visible in the Figure 2 and Figure 4 as well as Figure 5 circuit diagrams. The bit selection line WBS1 can in turn be coupled to a bit line driver included in the peripheral CMOS circuitry (interchangeably referred to as "CMOS periphery"), as shown by reference numeral 3 in Figures 1-3 . For BEOL compatibility, the bit line selection transistor BST1 can include a channel layer of an oxide semiconductor material, such as a high mobility oxide semiconductor material, such as any of the oxide semiconductor materials mentioned in connection with the oxide semiconductor layer 112. The bit line selection transistor BST1 is configured to enable selective access to the associated storage capacitor stack 114.

[0107] In Figure 4 , each rectangular box with a dashed fill pattern (one example is denoted by reference numeral DV) represents the location (in the horizontal plane XY) of a via that vertically extends and interconnects the lines (e.g., bit lines BL1 - BL4, bit selection lines WBS1 - WBS4, global plate lines GPL1 - GPL4) overlapping the respective rectangular box and the corresponding interconnections in the CMOS periphery 3 below the array 10. Accordingly, the rectangular boxes labeled PL1 - PL12 and BL1 - BL4 each indicate the location of the respective vias that vertically extend and interconnect the lines (e.g., bit lines BL1 - BL2, global plate lines GPL1 - GPL4) overlapping the respective box and the corresponding interconnections (e.g., the drains of the bit line selection transistors BST1 - BST4 or the plate lines PL1 - PL4). The corresponding convention applies to the top view of Figure 9 discussed later.

[0108] As shown, a memory array 10 including a stack of plate lines 100, a stack of storage capacitors, and bit line selection transistors BST1 can also be embedded in an insulating layer 4, such as including an oxide, such as silicon oxide.

[0109] The memory device 1 also includes plate line selection transistors PST1 - PST4, each coupled to a respective one of the plate lines PL1 - PL4. The plate line selection transistors are not separately shown in the Figures 1-3 structural diagram of the memory device in, but can be included in the CMOS periphery 3. However, the plate line selection transistors are shown in the Figure 4 circuit diagram of. Each plate line selection transistor PST1 - PST4 includes a first current terminal (e.g., drain) coupled to a respective plate line driver (e.g., included in the CMOS periphery 3) via a respective global plate line GPL1 - GPL4, a second current terminal (e.g., source) coupled to the respective plate line PL1 - PL4, and a gate coupled to the respective plate select line WL1 - WL4. The plate line selection transistors PST1 - PST4 are configured to enable selective access to the associated plate lines PL1 - PL4 in the stack of plate lines 100.

[0110] The memory device 1 also includes a sense circuit coupled to a metal core 111 of the column structure 11. As Figures 1-4 schematically shown, the sense circuit can include a sense transistor ST1. As shown, the sense transistor ST1 can be included in the CMOS periphery 3 and is disposed below the column structure 11. As shown, the sense transistor ST1 can be at least partially located within the footprint of the storage capacitor stack 114. For example, the metal core 111 can be directly formed on top of a gate contact coupled to the gate of the sense transistor ST1. A more detailed discussion of the sense circuit implementation will be discussed below.

[0111] Referring to Figure 1 , the stack of plate lines 100 can define a stepped structure 100S in the peripheral region of the memory array 10. Thus, as shown, each plate line PL1 - PL4 can be coupled to its associated plate line selection transistor PST1 - PST4 through horizontal plate interconnects in an interconnect level disposed above the stepped structure, first and second vertical plate interconnects extending from the horizontal plate interconnect and landing on the respective plate lines at the stepped structure, and the current terminals of the respective plate line selection transistors. The first vertical plate interconnect of each plate line PL1 - PL4 is visible in Figure 1 . The first and second vertical plate interconnects associated with the plate line PL1 are visible in Figure 3 . The second vertical plate interconnects associated with the other plate lines PL2 - PL4 are outside the cross-section in Figures 1-3 .

[0112] As shown, a bit line BL1 coupled to a bit line selection transistor BST1 can be arranged to extend above and across a stack of plate lines 100 in a column direction Y to define an intersection between the stack of plate lines 100 and the bit line BL1. A pillar structure 11 and thus a storage capacitor stack 114 can be further arranged at the intersection. As in, for example Figure 1 and Figure 4 shown, a memory device 1 can include a set of bit lines BL1, BL2, BL3, BL4 that extend parallel to each other in the column direction Y and across a stack of plate lines 100 to define a row of intersections distributed along a row direction X. As shown, corresponding pillar structures 11, 12, 13, 14 can be arranged to extend through the stack of plate lines 100 at each intersection, defining corresponding storage capacitor stacks 114, 124, 134, 144 at each intersection. Although the stack of plate lines 100 is shared (i.e., common) by a row of storage capacitor stacks 114, 124, 134, 144, each intersection of the row and each storage capacitor stack 114, 124, 134, 144 can be associated with a corresponding bit line selection transistor BST1, BST2, BST3, BST4. Corresponding first current terminals (e.g., drains) of the bit line selection transistors BST1, BST2, BST3, BST4 can be coupled to the bit lines BL1, BL2, BL3, BL4 associated with the corresponding intersections. Corresponding second current terminals (e.g., sources) of the bit line selection transistors BST1, BST2, BST3, BST4 can be coupled to metal pillars of the associated pillar structures 11, 12, 13, 14. Corresponding gate terminals of the bit line selection transistors BST1, BST2, BST3, BST4 can be formed by corresponding individual gate metal layers GL1, GL2, GL3, GL4, each gate metal layer being coupled to a corresponding bit selection line WBS1, WBS2, WBS3, WBS4. Thus, the bit line selection transistors BST1, BST2, BST3, BST4 are configured to enable selective access to the associated storage capacitor stacks 114, 124, 134, 144.

[0113] A sense circuit can be coupled to the metal pillars of each of the pillar structures 11, 12, 13, 14. For example, the sense circuit can include corresponding sense transistors ST1, ST2, ST3, ST4 coupled to each respective metal pillar.

[0114] The description of the pillar structure 11 and the storage capacitor stack 114 correspondingly applies to each of the pillar structures 12, 13, 14 and the associated storage capacitor stacks 124, 134, 144.

[0115] As Figures 3-4Further shown, the memory device 1 and the memory array 10 may include a plurality of stacks of respective plate lines 100, 200, 300 that extend parallel to each other in the row direction X and are spaced apart in the column direction Y. The set of bit lines BL1 to BL4 may extend over and across each stack of the plate lines 100, 200, 300 to define multiple rows of storage capacitor stacks along each stack of the plate lines, each being defined at a respective intersection defined by the set of bit lines BL1 to BL4 and the stack of the plate lines 100, 200, 300. The stacks of the plate lines 100, 200, 300 may be separated by isolation regions that extend in the row direction X and are filled with an insulating material 4. As Figure 4 shown, the storage capacitor stacks arranged in the same column may share the bit lines and the gate metal layers GL1, GL2, GL3, GL4. The respective stacks of the plate lines 100, 200, 300 and the associated rows of storage capacitor stacks may be accessed independently of each other in other ways. Accordingly, the description of a row of storage capacitor stacks 114, 124, 134, 144 along the stack of the plate line 100 applies correspondingly to each of the other rows of storage capacitor stacks defined along the respective stacks of the plate lines 200, 300.

[0116] It should be noted that Figures 1-4 the number of plate lines in each stack of the plate lines 100, 200, 300 shown in Figures 1-4 is only an example, and each stack of the plate lines 100, 200, 300 may generally include a considerably larger number of plate lines. The storage capacitor stacks may include a corresponding number of storage capacitors. It should also be noted that Figures 1-4 the number of bit lines and storage capacitor stacks along each row of the memory array 10 shown in

[0117] is only an example, and the memory array 10 may generally include a considerably larger number of bit lines and storage capacitor stacks along each row. Accordingly, the memory array 10 may include fewer or more stacks of plate lines than Figures 1-4 shown in

[0117] and thus include fewer or more rows of storage capacitor stacks.

[0117] A row of storage capacitor stacks defined along the stack of the plate line 100 will be mainly referred to hereinafter. However, the description applies correspondingly to the storage capacitor stacks of any other row of the memory array 10.

[0118] Figure 6a A first implementation of a part of a sense circuit coupled to one of the storage capacitor stacks (e.g., 114, 124, 134, or 144) is shown. For simplicity, FIG. 6 only shows one of the storage capacitors in the stack, denoted as C FE .

[0119] The storage capacitor C FEThe first electrode (defined by the plate line PL) is coupled to the second current terminal of the plate line selection transistor PST. The storage capacitor C FE The second electrode (defined by the associated metal pillar) is coupled to the reference capacitor C of the sensing circuit ref to a reference voltage node, which in the example shown corresponds to the ground node GND. The reference capacitor C ref can be formed directly below the associated storage capacitor stack, for example using a metal pillar as one capacitor electrode and a separate metal layer below the plate line stack as the other capacitor electrode coupled to the reference voltage node. The reference capacitor C ref can also be formed separately from the metal pillar and be included in the CMOS periphery 3.

[0120] In any case, the metal pillar and the reference capacitor C ref can be coupled (i.e., by an ohmic connection) to the common circuit node SN that defines the sensing node of the sensing circuit. The reference capacitor C ref together with the storage capacitor C FE defines a capacitive voltage divider, where if the storage capacitor is set to the first polarization state, the capacitance of the storage capacitor can be C high and if the storage capacitor is set to the second polarization state, the capacitance of the storage capacitor can be C low . Thus, in response to applying a read voltage to the plate line PL coupled to the storage capacitor C ref , the read voltage will be divided between the storage capacitor C FE and the reference capacitor C ref . Therefore, the voltage V CMOS of the sensing node SN in response to the read voltage will depend on the polarization state of the storage capacitor C FE .

[0121] Further referring Figure 6a , the sensing circuit includes a sensing transistor ST, which has a gate coupled to the sensing node SN, a first current terminal coupled to the reference voltage node GND, and a second current terminal coupled to the amplifier 5 of the memory device 1. The sense amplifier 5 can be included in the CMOS periphery 3. The sense amplifier 5 is configured to sense the voltage at the sensing node SN by sensing the current Id that passes through the sensing transistor ST in response to the read voltage. A small change in the voltage at the sensing node SN causes a corresponding change in the gate voltage of the sensing transistor ST, which in turn can be translated into a change in the drain current Id.

[0122] By the first and second capacitance values C FE and C high of the storage capacitor C lowand the threshold voltage of the sense transistor ST is appropriately tuned to reference capacitor C ref of the capacitor, the voltage at the sense node SN can depend on the polarization state of storage capacitor C EF and vary between above and below the threshold voltage. If storage capacitor C FE is in the first polarization state, the drain current Id can thus correspond to a subthreshold or cutoff state current. Conversely, if storage capacitor C FE is in the second polarization state, the drain current Id can correspond to an on-state current, which can generally be much larger than the subthreshold or cutoff state current. Thus, a small change in the capacitance of storage capacitor C FE can be converted into a large change in the drain current Id, which can be sensed by sense amplifier 5 and used to determine the polarization state of storage capacitor C EF .

[0123] Figure 6b shows a second implementation of the sense circuit. The second implementation corresponds to the first implementation but includes amplifier circuit 6 instead of amplifier 5, which is configured to digitize the output of sense transistor ST into a logic low level (GND) and a logic high level (VDD). Amplifier circuit 6 includes a pull-up transistor, whose drain is coupled to the supply voltage node (VDD) and whose source is coupled to the gate terminal of the pull-up transistor and the drain of sense transistor ST via an internal node IN of amplifier circuit 6. The internal node IN is coupled to the input terminals of a CMOS inverter pair, which generates the digitized output of sense circuit 6. When the capacitance of storage capacitor C FE is C low , the sense node voltage V CMOS of the sense node SN will be below the threshold voltage of sense transistor ST, where sense transistor ST is turned off. Then, the voltage V1 at the internal node IN will be pulled high (VDD) by the pull-up transistor, which will be converted into a low logic level at the inverter output. Conversely, when the capacitance of storage capacitor C FE is C high , the sense node voltage V CMOS of the sense node SN will exceed the threshold voltage of sense transistor ST, where sense transistor ST is turned on. Then, the pull-up transistor will be turned off, and the voltage V1 at the internal node IN will be converted into a low logic level at the inverter output.

[0124] Figure 6c shows a third implementation of the sense circuit. The second implementation corresponds to the first implementation, but differs in that sense transistor ST is replaced by a direct connection between sense node SN and differential amplifier 7. Differential amplifier 7 is configured to compare the voltage V CMOS at sense node SN with a reference sense voltage Vsr Compare them and provide an output signal that amplifies the difference.

[0125] Reference sense voltage V sr For example, it can be set to a level between the first sense node voltage V CMOS,1 and the second sense node voltage V CMOS,2 , where the first sense node voltage V CMOS,1 is the voltage at the sense node SN in response to the read voltage when the storage capacitor C FE has a first polarization state, and where the second sense node voltage V CMOS,2 is the voltage at the sense node SN in response to the read voltage when the storage capacitor C FE has a second polarization state, i.e., V sr ≈(V CMOS,1 +V CMOS,2 ) / 2. Thus, in response to the sense node voltage V CMOS exceeding the reference sense voltage V sr , different polarization states can be converted to a high logic level (VDD), while when the sense node voltage V CMOS is lower than the reference sense voltage V sr , it is converted to a low logic level (VSS or GND).

[0126] The design parameter of the sense circuit as shown above is the capacitance ratio CR, which can be defined as:

[0127]

[0128] where C MOS is the gate capacitance of the sense transistor ST, and C p is the parasitic capacitance. This allows the sense node voltage V CMOS to be calculated as:

[0129]

[0130] where V read is the applied read voltage.

[0131] As a non-limiting illustrative example, given a read voltage V read of 1.5 V, for the C FE and C high states of the storage capacitor C low , in order to obtain a 200 mV difference at the sense node, the storage capacitor should be designed such that C high / C low ≈4.

[0132] Thus, using any of the above implementations of the sensing circuit, the memory device 1 can implement a non-destructive read operation to determine the polarization state of the storage capacitor stack, such as any one of the stacks 114, 124, 134, 144 stacked along the plate line 100. The read operation can be performed by a memory controller implemented in the CMOS periphery 3 of the memory device 1. The read operation can include:

[0133] Disable each bit line selection transistor BST1 to BST4;

[0134] Enable the plate line selection transistor (e.g., PST1 coupled to PL1 associated with the storage capacitor 1141) coupled to the plate line associated with the selected storage capacitor;

[0135] Apply a read voltage V to the plate line (e.g., PL1) associated with the selected storage capacitor (e.g., 1141) through the enabled plate line selection transistor (e.g., PST1), read where the read voltage V read is distributed across the selected storage capacitor (e.g., 1141) and the sensing circuit ( Figure 6a or the reference capacitor C of 6b); and ref and

[0136] Determine the polarization state of the selected storage capacitor (e.g., 1141) by sensing the voltage V at the sensing node SN in response to the read voltage V using the sensing circuit ( Figure 6a or 6b). read of the CMOS sensing node SN.

[0137] Figure 7 FIG. shows a first write scheme applicable to the memory device 1. The first write scheme can be performed by a write circuitry implemented in the CMOS periphery 3. As Figure 7 shown, the first write scheme includes two consecutive steps, an erase step and a program step. Although in Figure 7 the erase step is performed before the program step, the reverse order is also possible. For ease of understanding, will further refer to Figure 5 as an example.

[0138] In the erase step, the write circuitry erases only the selected storage capacitors along the selected plate line. As shown, the erase step includes:

[0139] Selectively enable only one plate line selection transistor (e.g., enable PST1 by applying a conduction voltage to WL1).

[0140] Selectively enable only the selected bit line transistor coupled to the storage capacitor to be erased (e.g., enable BST1 by applying a conduction voltage to WBS1).

[0141] Apply an erase voltage V to the selected plate line erase (e.g., apply V to PL1 through the enabled PST1 and the global plate line GPL1) erase ).

[0142] Optionally, apply V erase / 2 to the non - selected plate lines to reduce the risk of write interference in non - selected storage capacitors (e.g., apply V erase / 2 to the global plate lines GPL2, GPL3, and GPL4 coupled to the non - enabled plate - line selection transistors PST2, PST3, PST4).

[0143] Apply a reference voltage (e.g., ~0V) to the bit line (such as BL1) associated with the storage capacitor to be erased.

[0144] Optionally, apply a partial programming voltage (e.g., V prog / 2) to the bit line associated with the storage capacitor to be programmed to reduce the risk of interfering with the storage capacitors to be programmed or not erased along the selected plate line (e.g., BL2, BL3, BL4).

[0145] In the programming step, the write circuitry programs only the selected storage capacitors along the selected plate line. The programming step includes:

[0146] Selectively enable only one plate - line selection transistor (as shown, typically the same plate - line selection transistor as in the erase step, such as PST1).

[0147] Selectively enable only the selected bit - line transistors coupled to the storage capacitors to be programmed (e.g., enable BST2 by applying a conduction voltage to WBS2).

[0148] Apply a reference voltage (e.g., ~0V) to the selected plate line PL (e.g., apply the reference voltage to PL1 through the enabled PST1 and the global plate line GPL1).

[0149] Optionally, apply a partial erase voltage (e.g., V erase / 2) to the non - selected plate lines to reduce the risk of write interference in non - selected storage capacitors (e.g., apply V erase / 2 to the global plate lines GPL2, GPL3, and GPL4 coupled to the non - enabled plate - line selection transistors PST2, PST3, PST4).

[0150] Optionally, apply a partial programming voltage (e.g., V prog / 2) to the bit line associated with the storage capacitor that should remain erased (i.e., the storage capacitor erased in the erase step) (e.g., BL1).

[0151] Figure 8 And Figure 9 schematically show a cross-sectional view and a top view of a memory device 1' according to another embodiment, respectively. The memory device 1 corresponds to the above-described memory device 1, except that the gate terminals of the bit-line selection transistors BST1 to BST5 provided for each row and each stack of the plate lines 100 of the array 10' are coupled to the same bit selection line WBS. In the case where there is more than one stack of plate lines, the same bit selection line WBS can even be shared by all the bit selection transistors in the memory array 10', as Figure 9 shown. Accordingly, the gate terminals of the bit-line selection transistors BST1 to BST5 can be formed in the same gate metal layer GL covering each stack of the plate lines 100, 200, 300. This reduces the footprint of the memory array 1' because the isolation regions between the gate terminals can be eliminated.

[0152] Figure 10 shows a second write scheme applicable to the memory device 1' having a shared bit selection line WLS. The first write scheme can be performed by a write circuitry implemented in the CMOS periphery 3. As Figure 7 shown, the first write scheme includes two steps, an erase step and a subsequent program step. The erase step erases all the storage capacitors along the plate lines. Then, the program step selectively programs the selected storage capacitors along the plate lines. For the sake of understanding, further reference will be made to Figure 5 as an example.

[0153] As shown, the erase step includes:

[0154] Enabling only one plate line and all the bit-line selection transistors (e.g., enabling PST1 by applying a conduction voltage to WL1, and enabling BST1 to BST4 by applying a conduction voltage to the common WBS).

[0155] Applying an erase voltage V erase (e.g., applying V erase ) to the selected plate line through the enabled PST1 and the global plate line GPL1.

[0156] Optionally, applying a reference voltage (e.g., ~0V) to all the unselected plate lines (e.g., applying a reference voltage to the global plate lines GPL2, GPL3, and GPL4 coupled to the unenabled plate-line selection transistors PST2, PST3, and PST4).

[0157] Applying a reference voltage (e.g., ~0V) to all the bit lines (e.g., BL1 to BL4).

[0158] As shown, the program step includes:

[0159] Enable only one plate line and all bit line selection transistors (as shown, typically the same plate line selection transistors as in the erase step, such as PST1).

[0160] Apply a reference voltage (e.g., ~0V) to the selected plate line (e.g., apply the reference voltage to PL1 through the enabled PST1 and the global plate line GPL1).

[0161] Apply a partial erase voltage (e.g., 2*V erase / 3) to the unselected plate lines (e.g., apply the partial erase voltage to the global plate lines GPL2, GPL3, and GPL4 coupled to the unenabled plate line selection transistors PST2, PST3, and PST4).

[0162] Apply a partial programming voltage (e.g., V prog / 3) to the bit lines associated with the storage capacitors that should remain erased (e.g., apply the partial programming voltage to BL1 and BL2).

[0163] Apply the programming voltage V prog to the bit lines of the storage capacitors to be programmed (e.g., apply V prog to BL3 and BL4).

[0164] Those skilled in the art will recognize that the present invention is in no way limited to the above-described embodiments. On the contrary, many modifications and variations are possible within the scope of the appended claims. For example, although in the above examples, the bit line selection transistors are provided in a back-end process and are arranged on top of each column structure, the bit line selection transistors can also be implemented in a CMOS periphery and each bit line selection transistor can be connected to its corresponding column structure's metal core through a combination of vertical and horizontal interconnections in an interconnect structure.

Claims

1. A ferroelectric memory device (1), comprising: A memory array (10) arranged in a back-end interconnect structure of the memory device, the memory array comprising: a vertical stack of horizontally extending board lines (100); and A pillar structure extending vertically through the stack of plate lines (100) and comprising a metal core (111) and a storage layer stack, wherein the storage layer stack comprises an oxide semiconductor layer (112) surrounding the metal core (111) in a circumferential direction and a ferroelectric layer (113) surrounding the oxide semiconductor layer (112) in a circumferential direction, wherein a vertical stack of ferroelectric storage capacitors (114) is defined along the pillar structure (11), each ferroelectric storage capacitor (1141-1144) comprising a first capacitor electrode formed by a plate line (PL1-PL4) in the stack of plate lines (100), a second capacitor electrode formed by a metal core (111) of the pillar structure (11), and a storage region formed by a portion of a storage layer stack sandwiched between the corresponding first capacitor electrode (PL1-PL4) and the metal core (111); The memory device (1) further comprises: a bit line selection transistor (BST1) comprising a first current terminal coupled to a bit line (BL1) of the memory array (10), a second current terminal coupled to a metal core (111) of the pillar structure (11), and a gate terminal coupled to a bit selection line (WBS1); a plate line selection transistor (PST1-PST4) coupled to a respective one of the plate lines (PL1-PL4); and A sensing circuit (5, 6, 7) is coupled to the metal core (111) of the pillar structure (11).

2. The memory device according to claim 1, wherein: The bit line selection transistor (BST1) is arranged on top of the pillar structure (11) and includes a channel layer of an oxide semiconductor material.

3. The memory device according to any one of the preceding claims, characterized in that The metal core (111) of the pillar structure (11) is connected to the reference capacitor (C) disposed below the vertical stack of the ferroelectric storage capacitors (114). ref ) is coupled to a reference voltage node (GND), and wherein the sensing circuit (5, 6, 7) is coupled to the metal core (111) and the reference capacitor (C ref ) between the sensing nodes (SN).

4. The memory device according to claim 3, wherein: Each ferroelectric storage capacitor (1141-1144) is switchable between a first polarization state and a second polarization state, wherein the first polarization state results in a first capacitance of the ferroelectric storage capacitor and the second polarization state results in a second capacitance of the ferroelectric storage capacitor, the second capacitance being less than the first capacitance, and Wherein a ratio of the capacitance at the sensing node (SN) to the second capacitance exceeds a ratio of the capacitance at the sensing node (SN) to the first capacitance by a factor of 1.3 times or more.

5. The memory device according to any one of claims 3 to 4, characterized in that: The memory device further comprises a memory controller (3) configured to perform a read operation to determine a selected ferroelectric storage capacitor (1141, C FE )’s polarization state: Disable each bit line select transistor (BST1); enabling a plate line select transistor (PST1) coupled to a plate line (PL1) associated with a selected ferroelectric storage capacitor; A read voltage is applied to a plate line (PL1) associated with a selected ferroelectric storage capacitor via an enabled plate line select transistor (PST1), wherein the read voltage is across the selected ferroelectric storage capacitor (1141, C FE ) and the reference capacitor (C ref ) to distribute; and determining the selected ferroelectric storage capacitor (1141, C by using the sensing circuit (5, 6, 7) to sense the voltage at the sensing node (SN) in response to the read voltage FE )'s polarization state.

6. The memory device according to claim 3-5, characterized in that: The sensing circuit comprises a differential amplifier (7) configured to compare the voltage at the sensing node (SN) with a reference sensing voltage.

7. The memory device according to any one of claims 3 to 5, characterized in that: The sensing circuit includes a sensing transistor (ST) having a gate coupled to the sensing node (SN), a first current terminal coupled to the reference voltage node (GND), and a second current terminal coupled to an amplifier (5, 6) of the memory device.

8. The memory device according to claim 7, wherein: The effective capacitance at the sensing node (SN) is such that, in response to the read voltage, when the selected ferroelectric storage capacitor (1141, C FE ) is in the first polarization state, the sensing transistor (ST) is enabled, and when the selected ferroelectric storage capacitor (1141, C FE ) is in the second polarization state, the sensing transistor (ST) is disabled.

9. The memory device according to any one of the preceding claims, characterized in that The stack of plate lines (100) extends in a row direction (X) of the memory array (10), and the memory array further comprises a group of bit lines (BL1-BL4), wherein the bit lines extend above and across the stack of plate lines (100) in a column direction (Y) of the memory array to define a row of intersections between the group of bit lines (BL1-BL4) and the stack of plate lines (100), the memory array comprising: a pillar structure (11, 12, 13, 14) at each intersection, each pillar structure extending vertically through the stack of plate lines (100) and comprising a metal core and a storage layer stack, the storage layer stack comprising a ferroelectric layer and an oxide semiconductor layer circumferentially surrounding the metal core, wherein a vertical stack of ferroelectric storage capacitors (114, 124, 134, 144) is defined along a corresponding pillar structure (11, 12, 13, 14) at each intersection, each ferroelectric storage capacitor in each ferroelectric storage capacitor stack comprises a first capacitor electrode formed by a plate line (PL1-PL4) in a stack of plate lines (100), a second capacitor electrode formed by a metal core of the corresponding pillar structure (11, 12, 13, 14), and a storage region formed by a portion of a storage layer stack of the corresponding pillar structure (11, 12, 13, 14) sandwiched between the corresponding first capacitor electrode and the corresponding metal core; wherein the memory device includes a respective bit line select transistor (BST1-BST4) associated with each respective intersection, each bit line select transistor including a first current terminal coupled to the bit line at the respective intersection, a second current terminal coupled to a metal core of a pillar structure (11, 12, 13, 14) at the respective intersection, and a gate terminal coupled to a bit select line (WBS1-WBW4, WBS); The sensing circuit (5, 6, 7) is connected to the metal core of each pillar structure (11, 12, 13, 14).

10. The memory device according to claim 9, characterized in that Each bit line selection transistor (BST1-BST4) is arranged on top of a pillar structure (11, 12, 13, 14) at an associated intersection, and includes a channel layer of an oxide semiconductor material.

11. The memory device (1, 1') according to any one of claims 9 to 10, characterized in that: A gate terminal of each bit line selection transistor (BST1-BST4) is coupled to a corresponding bit selection line (WBS1-WBS4), or wherein the gate terminals of the bit line selection transistors (BST1-BSS4) are coupled to the same bit selection line (WBS).

12. The memory device (1) according to claim 11, characterized in that A gate terminal of each bit line selection transistor (BST1-BST4) is coupled to a corresponding bit selection line (WBS1-WBS4), and the memory device (2) further includes a write circuit system (3) configured to: selectively enabling one of the plate line select transistors (PST1), the enabled plate line select transistor being coupled to a plate line (PL1) associated with a first set of ferroelectric storage capacitors to be erased and a second set of ferroelectric storage capacitors to be programmed, And when the selected plate line select transistor (PST1) is enabled: performing an erase step, including: selectively enabling a bit line selection transistor (BST1) coupled to the first group of ferroelectric storage capacitors, and simultaneously applying an erase voltage to the plate line (PL1) and a reference voltage to a bit line (BL1) coupled to the enabled bit line selection transistor (BST1); and A programming step is performed, including: selectively enabling a bit line selection transistor (BST2) coupled to the second group of ferroelectric storage capacitors, and simultaneously applying a programming voltage to a bit line (BL2) coupled to the enabled bit line selection transistor (BST2) and applying the reference voltage to the plate line (PL1).

13. The memory device (1') according to claim 11, characterized in that The gate terminals of the bit line selection transistors (BST1-BST4) are coupled to the same bit selection line (WBS), and the memory device (1') further comprises a write circuit system (3) configured to: selectively enabling one of the plate line select transistors (PST1) and each bit line select transistor (BST1-BST4), the enabled plate line select transistor being coupled to a plate line (PL1) associated with a first set of ferroelectric storage capacitors to be erased and a second set of ferroelectric storage capacitors to be programmed, And when the selected plate line select transistor and each bit line select transistor are enabled: Performing an erasing step includes: applying an erasing voltage to the plate line (PL1) and applying a reference voltage to each bit line (BL1-BL4) at the same time; and Executing a programming step includes: simultaneously applying a programming voltage to the bit lines (BL3, BL4) coupled to the second group of ferroelectric storage capacitors, applying a portion of the programming voltage to the bit lines (BL1, BL2) coupled to the first group of ferroelectric storage capacitors, and applying the reference voltage to the plate line (PL1).

14. The memory device according to any one of the preceding claims, characterized in that The single or plural plate line selection transistors and the sensing circuit are included in a peripheral complementary metal oxide semiconductor (CMOS) circuit (3) of the memory device.

15. The memory device according to any one of the preceding claims, characterized in that The oxide semiconductor layer (112) of the pillar structure (11) and / or the channel layer of each bit line selection transistor (BST1) is a high-mobility oxide semiconductor material, such as indium gallium zinc oxide, ZnO, WO, InWO, InSnO, GaZnO, MgZnO, MgAlZnO or MoO.

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