Storage device

Abstract

The invention discloses a storage device which comprises a basic circuit board, a master controller, first storage particles and second storage particles, the master controller is arranged on the basic circuit board and connected with the basic circuit board, the first storage particles are arranged on the first surface of the basic circuit board in an attached mode and connected with the basic circuit board, and the second storage particles are arranged on the second surface of the basic circuit board in an attached mode. The second storage particles are attached to the second surface of the basic circuit board and connected with the basic circuit board, the first storage particles and the second storage particles are overlapped relative to the basic circuit board, and the second surface is an opposite surface of the first surface; wherein the positions of at least part of the pins of the first storage particles and the second storage particles are correspondingly overlapped, and the types of the pins with the correspondingly overlapped positions are correspondingly the same. Through the structure, the length of a data transmission path of the storage device can be greatly shortened, so that the transmission speed is improved by shortening the signal transmission distance, and the signal integrity is guaranteed.

Description

Technical Field

[0001] This application is applied to the technical field of storage devices. Background Art

[0002] A storage device is a hard disk made of a solid-state electronic storage chip array, which has the characteristics of fast read and write, light weight, low energy consumption, and small size.

[0003] Currently, with the rapid development of high-tech in all walks of life, the capacity of storage devices is getting larger and larger. However, at the same time, the number of Dies connected to each channel is also increasing, which will lead to a decrease in the data read or storage rate of storage devices. Summary of the Invention

[0004] This application provides a storage device to solve the problem of the reduced rate of storage devices.

[0005] To solve the above technical problems, this application provides a storage device, including: a base circuit board, a main control, a first storage particle, and a second storage particle. The main control is disposed on the base circuit board and is connected to the base circuit board. The first storage particle is adhesively disposed on the first surface of the base circuit board and is connected to the base circuit board. The second storage particle is adhesively disposed on the second surface of the base circuit board and is connected to the base circuit board, and the first storage particle and the second storage particle are disposed overlappingly with respect to the base circuit board. The second surface is the opposite surface of the first surface; wherein, at least part of the positions of the pins of the first storage particle and the second storage particle correspond and overlap, and the types of the pins corresponding and overlapping in position are correspondingly the same.

[0006] Wherein, the first storage particle and the second storage particle are disposed back to back, and by adjusting the connection relationship between each pin on the main control and each pin on the first storage particle and the connection relationship between each pin on the main control and each pin on the second storage particle, the types of the pins corresponding and overlapping in position on the first storage particle and the second storage particle are correspondingly the same.

[0007] Wherein, a plurality of metallized vias are provided on the base circuit board, and opposite ends of each metallized via are respectively connected to the corresponding and overlapping pins on the first storage particle and the second storage particle.

[0008] Wherein, a plurality of connecting lines are further provided on the base circuit board. One end of the connecting line is connected to the main control, and the other end of the connecting line is connected to the metallized via, so that the main control is connected to the corresponding and overlapping pins on the first storage particle and the second storage particle.

[0009] Among them, the first storage particle includes a first storage unit and a second storage unit, and the second storage particle includes a third storage unit and a fourth storage unit; the first storage unit and the third storage unit are arranged in coincidence, and the second storage unit and the fourth storage unit are arranged in coincidence; the metallized vias include a first metallized via and a second metallized via, and the opposite ends of the first metallized via are respectively connected to the corresponding coincident pins on the first storage unit and the third storage unit; the opposite ends of the second metallized via are respectively connected to the corresponding coincident pins on the second storage unit and the fourth storage unit; the connection lines are respectively connected to the first metallized via and the second metallized via, so that the main control connects the corresponding coincident pins on the first storage particle and the second storage particle.

[0010] Among them, the connection lines include a first connection line and a second connection line; one end of the first connection line is connected to the main control, and the other end of the first connection line is connected to the corresponding second connection line; the second connection line is also respectively connected to the corresponding first metallized via and the second metallized via to connect the first storage particle and the second storage particle.

[0011] Among them, the impedance control of the first connection line is less than that of the second connection line.

[0012] Among them, the impedance control of the first connection line is 15 - 25 ohms less than that of the second connection line, and the length range of the second connection line is 5 - 15 cm.

[0013] Among the first storage unit, the second storage unit, the third storage unit, and the fourth storage unit, at least one storage unit turns on the ODT termination.

[0014] Among them, the storage device further includes an interface, a power supply, and a memory; the interface, the power supply, and the memory are attached to the base circuit board and connected to the base circuit board.

[0015] The beneficial effect of this application is that; different from the prior art, in this application, the main control is arranged on the base circuit board and connected to the base circuit board, the first storage particle and the second storage particle are respectively attached to the opposite sides of the base circuit board, and at least some of the pins of the first storage particle and the second storage particle are arranged in corresponding coincidence, and the types of the pins arranged in corresponding coincidence are correspondingly the same, so that the transmission distance between the first storage particle and the second storage particle is shortened as much as possible by using the coincident pins, making this distance the same as or close to the thickness of the base circuit board, thereby greatly shortening the transmission distance between the first storage particle and the second storage particle and the transmission distances between the main control and the first storage particle and the second storage particle respectively, and further greatly shortening the data transmission path length of the storage device, and further improving the transmission speed and ensuring signal integrity by shortening the signal transmission distance. Description of the Drawings

[0016] Figure 1 It is a schematic structural diagram of an embodiment of the storage device provided by the present application;

[0017] Figure 2 It is a partial structural schematic diagram of an embodiment of the base circuit board;

[0018] Figure 3 It is a schematic structural diagram of an embodiment of the connection between the main control and the storage particles;

[0019] Figure 4 It is a schematic connection structure diagram of the connection line and the metallized via in an embodiment;

[0020] Figure 5 It is a schematic diagram of a signal connection between each pin of the first storage particle and the main control in an embodiment;

[0021] Figure 6 It is a schematic diagram of a signal connection between each pin of the second storage particle and the main control in an embodiment;

[0022] Figure 7 It is an eye diagram schematic diagram of the first embodiment of impedance control;

[0023] Figure 8 It is an eye diagram schematic diagram of the second embodiment of impedance control;

[0024] Figure 9 It is an eye diagram schematic diagram of the first embodiment of impedance control;

[0025] Figure 10 It is a schematic topological structure diagram of a connection between the main control and the storage unit in an embodiment of the present application;

[0026] Figure 11 It is an eye diagram schematic diagram of the first embodiment of the storage unit termination;

[0027] Figure 12 It is an eye diagram schematic diagram of the second embodiment of the storage unit termination;

[0028] Figure 13 It is an eye diagram schematic diagram of the third embodiment of the storage unit termination;

[0029] Figure 14 It is an eye diagram schematic diagram of the fourth embodiment of the storage unit termination. Detailed implementation manners

[0030] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0031] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present application, then the directional indications are only used to explain the relative position relationship, movement conditions, etc. between components in a certain specific posture (as shown in the accompanying drawings). If this specific posture changes, then the directional indications will also change accordingly.

[0032] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, then the descriptions of "first", "second", etc. are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present application.

[0033] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of an embodiment of a storage device provided by the present application.

[0034] The storage device 100 in this embodiment includes a base circuit board 10, a main control 13, a first storage particle 11, and a second storage particle 12. The storage device 100 in this embodiment may include, but is not limited to, a hard disk, a solid-state drive, a mobile hard disk, a USB flash drive, a memory card, a non-volatile memory (NAND FLASH), an optical disc, and cloud storage, etc.

[0035] Among them, the base circuit board 10 is a PCB (Process Control Block) printed circuit board, which can be a multi-layer circuit board or a single-layer circuit board, and can be specifically set based on actual requirements. The main control 13 is a control chip for controlling the storage of the storage device 100. The first storage particle 11 and the second storage particle 12 are two NAND FLASH chips (a type of flash memory) of the same type.

[0036] The main control 13 is disposed on the base circuit board 10 and is connected to the base circuit board 10.

[0037] The first memory particle 11 is adhesively disposed on the first surface 101 of the base circuit board 10 and is connected to the base circuit board 10; the second memory particle 12 is adhesively disposed on the second surface 102 of the base circuit board 10 and is connected to the base circuit board 10, and the first memory particle 11 and the second memory particle 12 are disposed overlappingly with respect to the base circuit board 10, and the second surface 102 is the opposite surface of the first surface 101. For the convenience of adhesion and fixation between the base circuit board 10 and the two memory particles, the first memory particle 11 and the second memory particle 12 may be disposed back to back.

[0038] The main controller 13 is connected to the first memory particle 11 and the second memory particle 12 through the base circuit board 10. Then the signal transmission distance of the storage device 100 is determined by the distance between the main controller 13 and the first memory particle 11, the distance between the main controller 13 and the second memory particle 12, and the distance between the first memory particle 11 and the second memory particle 12.

[0039] Among them, at least some of the positions of the pins of the first memory particle 11 and the second memory particle 12 coincide, and the types of the pins with corresponding coincident positions are correspondingly the same. The first memory particle 11 and the second memory particle 12 may have some or all of the positions of the pins corresponding and coinciding, and the types of the pins with corresponding coincident positions are correspondingly the same, which is specifically set based on actual requirements. Among them, when the pins of the memory particle are completely symmetrical left and right, all the positions of the pins of the first memory particle 11 and the second memory particle 12 may coincide; when the pins of the memory particle are not completely symmetrical left and right, some of the positions of the pins of the first memory particle 11 and the second memory particle 12 may coincide.

[0040] When the storage device 100 performs data storage or data reading, data transmission needs to be carried out between the main control 13 and the first storage particle 11 and / or the second storage particle 12. The longer the transmission distance, the lower the transmission speed and the worse the signal integrity. In this embodiment, by arranging the first storage particle 11 and the second storage particle 12 to overlap with respect to the base circuit board 10, and making the positions and types of the pins of the first storage particle 11 correspond to and overlap with the positions and types of the pins of the second storage particle 12, that is, connecting the same positions on the opposite sides of the base circuit board 10 to the pins of the same type on the two storage particles, so that the main control 13 can realize the connection of the first storage particle 11 and the second storage particle 12 through the base circuit board 10 itself without additional wiring on the surface of the base circuit board 10, which not only reduces the wiring steps and the manufacturing complexity of the storage device 100, but also shortens the transmission distance between the first storage particle 11 and the second storage particle 12 as much as possible, making this distance the same as or close to the thickness of the base circuit board 10, thereby greatly shortening the transmission distance between the first storage particle 11 and the second storage particle 12 and the transmission distances between the main control 13 and the first storage particle 11 and the second storage particle 12 respectively, and then greatly shortening the data transmission path length of the storage device 100, and further improving the transmission speed and ensuring signal integrity by shortening the signal transmission distance.

[0041] With the above structure, in this embodiment of the storage device, the main control is arranged on the base circuit board and connected to the base circuit board. The first storage particle and the second storage particle are respectively attached to the opposite sides of the base circuit board, and at least part of the positions of the pins of the first storage particle and the second storage particle correspond and overlap, and the types of the pins corresponding and overlapping in position are the same. Thus, the transmission distance between the first storage particle and the second storage particle is shortened as much as possible by using the overlapping pins, making this distance the same as or close to the thickness of the base circuit board, thereby greatly shortening the transmission distance between the first storage particle and the second storage particle and the transmission distances between the main control and the first storage particle and the second storage particle respectively, and then greatly shortening the data transmission path length of the storage device, and further improving the transmission speed and ensuring signal integrity by shortening the signal transmission distance.

[0042] Please refer to Figure 2 , Figure 2 which is a partial structural schematic diagram of an embodiment of the base circuit board.

[0043] In some embodiments, a plurality of metallized vias 20 are provided on the base circuit board 10, and the opposite ends of each metallized via 20 are respectively connected to the corresponding and overlapping pins on the first storage particle 11 and the second storage particle 12.

[0044] The connection of corresponding and same-type pins on the first storage particle 11 and the second storage particle 12 can be achieved through the metallized vias 20. Furthermore, the main controller 13 can connect to the first storage particle 11 and the second storage particle 12 by connecting to the metallized vias 20 through the base circuit board 10. And the metallized vias 20 can further shorten the transmission distance between the base circuit board 10 and the first storage particle 11 and the second storage particle 12. The main controller 13 can directly connect to the metallized vias 20 through the base circuit board 10 to achieve the connection with the same-type pins on the two storage particles, thereby further improving the transmission speed and ensuring signal integrity.

[0045] Please refer to Figures 3 - 4 , Figure 3 which is a schematic structural diagram of an implementation manner of the connection between the main controller and the storage particles. Figure 4 which is a schematic connection structure diagram of the connection line and the metallized via. Among them, Figure 3 the base circuit board is hidden for easy viewing, Figure 4 and the base circuit board and the storage particles are hidden for easy viewing.

[0046] In some embodiments, a plurality of connection lines 19 are further provided on the base circuit board 10. One end of the connection line 19 is connected to the main controller 13, and the other end of the connection line 19 is connected to the metallized via 20, so that the main controller 13 connects to the corresponding and overlapping pins on the first storage particle 11 and the second storage particle 12. Different connection lines 19 can connect to different types of pins.

[0047] The connection line 19 can be arranged on the surface or inner layer of the base circuit board 10, and can be specifically set based on the actual situation.

[0048] In some embodiments, the first storage particle 11 includes a first storage unit 111 and a second storage unit 112, and the second storage particle 12 includes a third storage unit 121 and a fourth storage unit 122; the first storage unit 111 and the third storage unit 121 are arranged in an overlapping manner, and the second storage unit 112 and the fourth storage unit 122 are arranged in an overlapping manner.

[0049] The first storage particle 11 and the second storage particle 12 have the same model, and the storage unit is a storage subunit within the storage particle, that is, the pin positions and pin types of different storage subunits are the same, that is, the pin positions and pin types of the first storage unit 111, the second storage unit 112, the third storage unit 121, and the fourth storage unit 122 are the same.

[0050] The metallized vias 20 include a first metallized via 201 and a second metallized via 203. The opposite ends of the first metallized via 201 are respectively connected to the corresponding overlapping pins on the first storage unit 111 and the third storage unit 121; the opposite ends of the second metallized via 203 are respectively connected to the corresponding overlapping pins on the second storage unit 112 and the fourth storage unit 122.

[0051] The connection line 19 is respectively connected to the first metallized via 201 and the second metallized via 203, so that the main control 13 is connected to the corresponding overlapping pins on the first storage chip 11 and the second storage chip 12.

[0052] In a specific application scenario, the same connection line 19 connects the first storage unit 111, the second storage unit 112, the third storage unit 121, and the fourth storage unit 122 by connecting the first metallized via 201 and the second metallized via 203, so as to connect the pins of the same type on these units.

[0053] Among them, there may be multiple types of pins on each storage unit that need to be connected to the main control 13, and the connection line 19 and the metallized via 20 correspondingly have multiple ones. In a specific application scenario, if there are 8 pins on each storage unit that need to be connected to the main control 13, the number of connection lines 19 is 8. The number of the first metallized vias 201 and the second metallized vias 203 is both 8. And so on.

[0054] In some embodiments, the connection line 19 includes a first connection line 191 and a second connection line 192; one end of the first connection line 191 is connected to the main control 13, and the other end of the first connection line 191 is connected to the corresponding second connection line 192; the second connection line 192 is also respectively connected to the corresponding first metallized via 201 and the second metallized via 203 to connect the first storage chip 11 and the second storage chip 12.

[0055] The first connection line 191 represents the transmission distance between the storage chip and the main control 13, and the second connection line 192 represents the transmission distance between the pins of the same type in each storage unit of the storage chip. Since in this embodiment, the positions and types of the pins of the first storage chip 11 correspond and overlap with the positions and types of the pins of the second storage chip 12, the metallized via 20 can be used to connect the corresponding overlapping pins on the overlapping storage units at the same time. Thus, the metallized via 20 can be used to shorten the corresponding overlapping pins on the overlapping storage units, and the overlap of the pins can be used to minimize the length of the second connection line 192 to avoid additional leads or surface leads. Further, by shortening the length of the second connection line 192, the length of the entire connection line 19 is reduced, and then the transmission speed is increased and the signal integrity is ensured by shortening the signal transmission distance, and even the signal transmission speed can reach the full speed.

[0056] In some embodiments, the first storage particle 11 and the second storage particle 12 are arranged back to back. By adjusting the connection relationship between each pin on the main control 13 and each pin on the first storage particle 11 and the connection relationship between each pin on the main control 13 and each pin on the second storage particle 12, the types of the pins at the corresponding overlapping positions of the first storage particle 11 and the second storage particle 12 are made to correspond identically.

[0057] In a specific application scenario, in order to achieve the arrangement of the first storage particle 11 and the second storage particle 12 back to back, and at the same time, the positions and types of the pins of the first storage particle 11 correspond and overlap with the positions and types of the pins of the second storage particle 12, this embodiment is implemented by adjusting the type of the connection signal between the main control 13 and the storage unit.

[0058] Please refer further to Figures 5 - 6 , Figure 5 which is a schematic diagram of an embodiment of the signal connection between each pin of the first storage particle and the main control. Figure 6 which is a schematic diagram of an embodiment of the signal connection between each pin of the second storage particle and the main control.

[0059] Each pin of the first storage unit 111 is connected to the corresponding pin of the main control 13, and each pin of the second storage unit 112 is also connected to the corresponding pin of the main control 13. Each pin of the third storage unit 121 is connected to the corresponding pin of the main control 13, and each pin of the fourth storage unit 122 is connected to the corresponding pin of the main control 13. For details, please refer to Figures 5 - 6 。

[0060] Among them, the ALE pin is the address latch signal, the CE pin is the chip select signal, the CLE pin is the command latch signal, the DQ0 - 7 pins are the data signal lines, the DQSP pin and the DQSN pin are the data latch signals, and the REP pin and the REN pin are the read / write direction signals.

[0061] The DQ0 pin of the first storage unit 111 is connected to the DQ0 pin of the main control 13, that is, in sequence. The DQ0 pin of the second storage unit 112 is connected to the DQ7 pin of the main control 13, that is, in reverse sequence. The DQ0 pin of the third storage unit 121 is connected to the DQ7 pin of the main control 13, that is, in reverse sequence. The DQ0 pin of the fourth storage unit 122 is connected to the DQ0 pin of the main control 13, that is, in sequence.

[0062] The first storage particle 11 and the second storage particle 12 are arranged back to back. Therefore, in this embodiment, by adjusting the pin connection types between the main control 13 and each storage unit, the positions and types of the pins on the two overlapping storage units can correspond, so as to realize the connection of the two ends of the metallization hole 20 to the pins of the same type, thereby shortening the transmission distance between the pins and shortening the transmission distance of the second connection line 192.

[0063] In some embodiments, the impedance control of the first connection line 191 is less than the impedance control of the second connection line 192.

[0064] Impedance control principle: The characteristic impedance Z of the transmission line is (L / C)^(0.5) according to the principle of mutual compensation of inductance and capacitance, where L represents the unit inductance and C represents the unit capacitance. Then, the higher the characteristic impedance of the transmission line, the higher the corresponding inductance.

[0065] In order to reduce signal loss, the applicant of this application found through a large number of experiments that when the impedance control of the first connection line 191 is less than the impedance control of the second connection line 192, the transmission quality of the signal is higher.

[0066] In some embodiments, the impedance control of the first connection line 191 is less than the impedance control of the second connection line 192 by 15 - 25 ohms, specifically, it can be 15 ohms, 18 ohms, 20 ohms, 22 ohms or 25 ohms, etc., and the length range of the second connection line 192 is 5 - 15 cm, specifically, it can be 5 cm, 6 cm, 9 cm, 10 cm, 11 cm, 12 cm or 15 cm, etc.

[0067] Among them, the length range of the second connection line 192 is determined by the size of the storage particle itself. The applicant of this application conducted a large number of experiments on impedance control within the above length range of the second connection line 192 and determined that when the impedance control of the first connection line 191 is less than the impedance control of the second connection line 192 by 15 - 25 ohms, the signal is optimal. Among them, the impedance control of the first connection line 191 has little influence on the signal.

[0068] Please refer to Figures 7 - 9 , Figure 7 is the eye diagram schematic diagram of the first implementation manner of impedance control. Figure 8 is the eye diagram schematic diagram of the second implementation manner of impedance control, Figure 9 is the eye diagram schematic diagram of the first implementation manner of impedance control.

[0069] Among them, the first implementation manner of impedance control is that the impedance control of the first connection line 191 is equal to the impedance control of the second connection line 192. The second implementation manner is that the impedance control of the first connection line 191 is less than the impedance control of the second connection line 192 by 10 ohms; the third implementation manner is that the impedance control of the first connection line 191 is less than the impedance control of the second connection line 192 by 20 ohms.

[0070] Through the simulation comparison of the above eye diagrams, it is found that when the impedance control of the first connection line 191 is less than the impedance control of the second connection line 192 by 20 ohms, the signal quality is the best at this time. In this embodiment, the impedance control of the first connection line 191 is less than the impedance control of the second connection line 192 by 15 - 25 ohms, and the length range of the second connection line 192 is 5 - 15 cm, further improving the stability and integrity of signal transmission.

[0071] In some embodiments, at least one of the first storage unit 111, the second storage unit 112, the third storage unit 121, and the fourth storage unit 122 enables ODT (On - Die Termination) termination. Specifically, one, two, or more storage units can enable ODT termination. In a specific application scenario, when there are 4 storage units, 1 - 2 storage units can be enabled for termination to further improve the signal transmission quality through ODT termination.

[0072] Please refer to Figure 10 , Figure 10 which is a schematic diagram of the topological structure of an implementation manner of the connection between the main control and the storage unit in this application.

[0073] The main control 13 in this implementation manner is connected to the first connection line 191, and the first connection line 191 is also respectively connected to 4 branched second connection lines 192. The 4 branched second connection lines 192 are respectively connected to the first storage unit 111, the second storage unit 112, the third storage unit 121, and the fourth storage unit 122 correspondingly.

[0074] This topological structure is designed as a structure where a main road drags multiple branches. The main road is the first connection line 191, and the branches are the 4 second connection lines 192. If the main road and the branch structure are the same, due to the existence of branch stubs after branching, the time - domain impedance of the signal will decrease after passing through the branches. To solve this problem, this application designs the impedance of the branches and the main road to be inconsistent, which can compensate for the capacitive impedance drop of the branch stubs to a certain extent, optimize the matching setting, and improve the signal quality to a certain extent. In addition, if the branches are not terminated with ODT, the signal will reflect back when it reaches the terminal, causing the reflection to superimpose on the subsequent signal, that is, inter - symbol interference, affecting the signal quality. Therefore, the branch terminals need to be terminated to absorb the signal energy.

[0075] Please refer to Figures 11 - 14 , Figure 11 which is a schematic diagram of the eye diagram of the first implementation manner of the storage unit termination, Figure 12 which is a schematic diagram of the eye diagram of the second implementation manner of the storage unit termination, Figure 13 which is a schematic diagram of the eye diagram of the third implementation manner of the storage unit termination,Figure 14 It is an eye diagram schematic of the fourth implementation of the storage cell termination.

[0076] The first embodiment is the eye diagram when the characteristic impedance of the first connection line 191 is equal to that of the second connection line 192. The second embodiment is the eye diagram when the characteristic impedance of the first connection line 191 is less than that of the second connection line 192. The third embodiment is the eye diagram when the characteristic impedance of the first connection line 191 is less than that of the second connection line 192 and there are two storage cell ODT terminations. The fourth embodiment is the eye diagram when the characteristic impedance of the first connection line 191 is less than that of the second connection line 192 and there is one storage cell ODT termination.

[0077] From the comparison results, it can be seen that different characteristic impedances of the branch and the main road can improve the eye diagram quality. More granular terminations can absorb more energy, greatly improve reflection, and enhance the eye diagram quality.

[0078] In some embodiments, the storage device further includes an interface 15, a power supply 18, and a memory 17; the interface 15, the power supply 18, and the memory 17 are attached to the base circuit board 10 and connected to the base circuit board 10 to connect to the main controller 13.

[0079] The interface 15 is an external connection port of the storage device 100, the power supply 18 powers the storage device 100, and the memory 17 can also store data.

[0080] With the above structure, in this embodiment of the storage device, the main controller is disposed on the base circuit board and connected to the base circuit board. The first storage particle and the second storage particle are respectively attached to opposite sides of the base circuit board, and the positions and types of the pins of the first storage particle correspond and coincide with those of the pins of the second storage particle. Moreover, the connection between the main controller and each storage unit is realized in sequence by using the first connection line, the second connection line, and the metallized via, so that the transmission distance between the first storage particle and the second storage particle is shortened as much as possible, and this distance is the same as or close to the thickness of the base circuit board. Thus, the transmission distance between the first storage particle and the second storage particle and the transmission distances between the main controller and the first storage particle and the second storage particle are greatly shortened. Furthermore, the data transmission path length of the storage device is significantly shortened, and then the transmission speed is increased and the signal integrity is ensured by shortening the signal transmission distance. And in this embodiment, the impedance of the connection line is also controlled, and at least one storage unit is determined to turn on the ODT to further improve the signal transmission, thereby ensuring the signal integrity and reliability.

[0081] The above are only the embodiments of the present application, and do not thus limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall similarly be included within the patent protection scope of the present application.

Claims

1. A storage device, characterized in that, The storage device includes: A base circuit board; A main controller, which is disposed on the base circuit board and connected to the base circuit board; A first memory die, which is attached to the first surface of the base circuit board and connected to the base circuit board; A second memory die, which is attached to the second surface of the base circuit board and connected to the base circuit board, and the first memory die and the second memory die are arranged to overlap with respect to the base circuit board, and the second surface is the opposite surface of the first surface; Wherein, at least some of the pins of the first memory die and the second memory die are arranged to overlap in position, and the types of the pins that overlap in position correspond to each other.

2. The storage device according to claim 1, wherein The first memory die and the second memory die are arranged back to back, and by adjusting the connection relationship between each pin on the main controller and each pin on the first memory die and the connection relationship between each pin on the main controller and each pin on the second memory die, the types of the pins that overlap in position on the first memory die and the second memory die correspond to each other.

3. The storage device according to claim 1 or 2, characterized in that, A plurality of metallized vias are provided on the base circuit board, and opposite ends of each metallized via are respectively connected to the corresponding overlapping pins on the first memory die and the second memory die.

4. The storage device according to claim 3, wherein A plurality of connecting lines are further provided on the base circuit board, one end of each connecting line is connected to the main controller, and the other end of each connecting line is connected to the metallized via, so that the main controller is connected to the corresponding overlapping pins on the first memory die and the second memory die.

5. The storage device according to claim 4, wherein The first memory die includes a first memory cell and a second memory cell, and the second memory die includes a third memory cell and a fourth memory cell; the first memory cell and the third memory cell overlap; the second memory cell and the fourth memory cell overlap; The metallized vias include a first metallized via and a second metallized via, and opposite ends of the first metallized via are respectively connected to the corresponding overlapping pins on the first memory cell and the third memory cell; opposite ends of the second metallized via are respectively connected to the corresponding overlapping pins on the second memory cell and the fourth memory cell; The connecting lines are respectively connected to the first metallized via and the second metallized via, so that the main controller is connected to the corresponding overlapping pins on the first memory die and the second memory die.

6. The storage device according to claim 5, wherein The connecting lines include a first connecting line and a second connecting line; One end of the first connecting line is connected to the main controller, and the other end of the first connecting line is connected to the corresponding second connecting line; The second connecting line is further respectively connected to the corresponding first metallized via and second metallized via to connect the first memory die and the second memory die.

7. The storage device according to claim 6, wherein The impedance control of the first connecting line is less than the impedance control of the second connecting line.

8. The storage device according to claim 6 or 7, characterized in that, The impedance control of the first connection line is less than that of the second connection line by 15 - 25 ohms, and the length range of the second connection line is 5 - 15 cm.

9. The storage device according to claim 5, wherein At least one of the first storage unit, the second storage unit, the third storage unit, and the fourth storage unit enables ODT (on-die termination) termination.

10. The storage device according to claim 1, characterized in that, The storage device further includes an interface, a power supply, and a memory. The interface, the power supply, and the memory are disposed in a fitting manner on the base circuit board and are connected to the base circuit board.

Images