Semiconductor structure

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a semiconductor structure, which comprises a first chip and a second chip which are bonded with each other, the first chip comprises a plurality of storage arrays arranged in an array, and each storage array comprises a plurality of bit lines arranged at intervals; the second chip comprises sensing amplification sections in one-to-one correspondence with the storage arrays; wherein the two adjacent storage arrays in the extending direction of the bit lines form a pair of storage arrays, the two sensing amplification sections corresponding to the pair of storage arrays form a pair of sensing amplification sections, in the pair of storage arrays, part of the bit lines of one storage array and part of the bit lines of the other storage array are coupled to one of the pair of sensing amplification sections, and in the pair of storage arrays, part of the bit lines of the other storage array are coupled to the other sensing amplification sections. The remaining bit lines of one and the remaining bit lines of the other are coupled to the other of the pair of sense amplification sections. The embodiment of the invention is at least beneficial to reducing the layout area of a single chip in the horizontal direction and improving the utilization rate of bit lines in a storage array.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure. Background Art

[0002] To save chip area, a memory chip including a memory cell array and a logic chip having a logic circuit including sense amplifiers and word line drivers are respectively fabricated on two different wafers, and the two different wafers are hybridly bonded using a hybrid bonding process. According to this method, the memory cell array and the logic circuit can be fabricated by separate processes.

[0003] In addition, various operating modes in the memory chip may cause access to the memory cells on the memory cell array. During such operations, the sense amplifier may sense the voltage of the memory cell and output a logic 1 or 0 corresponding to the sensed voltage. When accessing, the memory cell may be coupled to a digital line (e.g., a bit line), and the digital line may in turn be coupled to the sense amplifier. Together with the digital line coupled to the memory cell, a complementary digital line may also be coupled to the sense amplifier. The use of the complementary digital line can be used to provide a reference voltage level to better distinguish the value read / written to the memory cell from the memory cell.

[0004] However, currently, some bit lines in one memory array and some bit lines in an adjacent memory array are mutually referenced, and some bit lines in this memory array and some bit lines in another adjacent memory array are mutually referenced. Based on this, for a memory array located at the edge, since there is only one adjacent memory array for this edge memory array, at least half of the bit lines in this edge memory array do not have corresponding bit lines to be mutually referenced, that is, they cannot be sensed by the sense amplifier (there is no reference bit line).

[0005] Therefore, the electrical connection relationship between each device in the logic chip and the memory cell array in the memory chip needs to be optimized, and the utilization rate of the bit lines in the memory array also needs to be improved. Summary of the Invention

[0006] Embodiments of the present disclosure provide a semiconductor structure, which is at least beneficial to reducing the layout area of a single chip in the horizontal direction and improving the utilization rate of the bit lines in the memory array.

[0007] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a first chip and a second chip bonded to each other; the first chip includes a plurality of memory arrays arranged in an array, and each memory array includes a plurality of bit lines arranged at intervals; the second chip includes sense amplifier blocks corresponding to the memory arrays one by one; wherein, two adjacent memory arrays along the extension direction of the bit line form a pair of memory arrays, and two sense amplifier blocks corresponding to the pair of memory arrays form a pair of sense amplifier blocks. In the pair of memory arrays, some of the bit lines of one and some of the bit lines of the other are coupled to one of the pair of sense amplifier blocks, and the remaining bit lines of one and the remaining bit lines of the other are coupled to the other of the pair of sense amplifier blocks.

[0008] In some embodiments, the bit line is coupled to the corresponding sense amplifier block through a corresponding bit line extension portion, and the bit line extension portion is a first extension portion or a second extension portion, and the extension direction of the bit line extension portion is the same as that of the bit line; wherein, the first extension portion and the corresponding bit line are in the same memory array, the second extension portion and the corresponding bit line are in different memory arrays in the pair of memory arrays, and the first extension portion and the second extension portion extend in different metal layers.

[0009] In some embodiments, the first chip further includes bit line connection blocks corresponding to the memory arrays one by one, one end of the bit line extension portion is located in the bit line connection block, and the other end is electrically connected to the corresponding bit line; wherein, the two bit line connection blocks corresponding to the pair of memory arrays are a first bit line connection block and a second bit line connection block respectively. The plurality of bit line extension portions with one end located in the first bit line connection block include a plurality of first extension portions and a plurality of second extension portions, and the other end of the first extension portion is electrically connected to the bit line in the memory array corresponding to the first bit line connection block, and the other end of the second extension portion is electrically connected to the bit line in the memory array corresponding to the second bit line connection block.

[0010] In some embodiments, the mutually bonded first chip and second chip have a bonding interface, and the positive projections of the bit line connection section and the sense amplification section on the bonding interface coincide; the first chip further includes: a plurality of first bonding pads arranged at intervals along the bit line extension direction and the word line extension direction, among the first bonding pads located in the bit line connection section, at least some of the first bonding pads are electrically connected to one end of the bit line extension; the second chip further includes: a plurality of second bonding pads arranged at intervals along the bit line extension direction and the word line extension direction, the first bonding pads located in the bit line connection section are in contact connection with the second bonding pads located in the sense amplification section, and the word line extension direction intersects the bit line extension direction.

[0011] In some embodiments, the two bit line connection sections corresponding to the pair of memory arrays are adjacent to each other along the bit line extension direction; or, along the bit line extension direction, the first bit line connection section and the second bit line connection section are located on opposite sides of the pair of memory arrays; or, the first bit line connection section and the second bit line connection section are on the same side of the corresponding memory array.

[0012] In some embodiments, the bit line is electrically connected to the corresponding bit line extension through a conductive portion and coupled to the sense amplification section; along the bit line extension direction, the memory array has opposite third and fourth sides, and the conductive portion in contact connection with the bit line in the memory array is located in the area of the third side away from the fourth side, or in the area of the fourth side away from the third side.

[0013] In some embodiments, the bit line is electrically connected to the corresponding bit line extension through a conductive portion and coupled to the sense amplification section; along the bit line extension direction, the two bit line connection sections corresponding to the pair of memory arrays are adjacent to each other along the bit line extension direction, and there is a lead-out section between the adjacent bit line connection sections, and the conductive portions in contact connection with the bit lines in the pair of memory arrays are all located in the lead-out section.

[0014] In some embodiments, the semiconductor structure further includes: a first electrical connection portion in contact connection with the first extension portion, and a second electrical connection portion in contact connection with the second extension portion; in a direction perpendicular to the bonding interface, the first electrical connection portion includes a first sub-portion and a second sub-portion stacked.

[0015] In some embodiments, the mutually bonded first chip and second chip have a bonding interface, and the positive projections of the first extension portion and the second extension portion on the bonding interface at least partially overlap.

[0016] In some embodiments, two adjacent bit lines along the word line extension direction form a pair of bit lines. One of the pair of bit lines is electrically connected to the first extension portion, and the other of the pair of bit lines is electrically connected to the second extension portion. The word line extension direction intersects the bit line extension direction.

[0017] In some embodiments, the second chip further includes a plurality of logic blocks corresponding to the memory array. Each logic block includes a sense amplifier block, a word line driver block, and a peripheral circuit block. In the word line extension direction, the size of the sense amplifier block is equal to the size of the logic block. The word line extension direction intersects the bit line extension direction. Among them, the word line driver block is located between the sense amplifier block and the peripheral circuit block, or the peripheral circuit block is located between the sense amplifier block and the word line driver block.

[0018] In some embodiments, the word line driver block includes a first sub-driver block and a second sub-driver block arranged at intervals along the word line extension direction. Part of the peripheral circuit block is also located between the first sub-driver block and the second sub-driver block.

[0019] In some embodiments, the peripheral circuit blocks corresponding to two adjacent memory arrays along the word line extension direction are adjacent and coupled, and / or the peripheral circuit blocks corresponding to a pair of memory arrays are adjacent and coupled along the bit line extension direction.

[0020] In some embodiments, the first chip further includes: a plurality of word lines arranged at intervals along the bit line extension direction, a first wiring electrically connected to the word lines one by one, and a word line connection block whose orthographic projection on the bonding interface coincides with the orthographic projection of the word line driver block on the bonding interface; in the direction perpendicular to the bonding interface, the word lines whose orthographic projections at least partially coincide with the orthographic projection of the word line connection block are first word lines, and the remaining word lines are second word lines. The first wiring corresponding to the first word line is a first sub-wiring, and the first wiring corresponding to the second word line is a second sub-wiring; among them, the first sub-wiring extends along the word line extension direction; the second sub-wiring includes a first connection portion and a second connection portion connected in contact. The first connection portion extends along the word line extension direction, and the second connection portion extends along the bit line extension direction; one end of any first wiring is electrically connected to the word line, and the other end is located in the word line connection block.

[0021] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0022] Design two adjacent memory arrays along the extension direction of the bit line as a pair of memory arrays, and the two sense amplifier blocks corresponding to the pair of memory arrays are a pair of sense amplifier blocks. On this basis, the coupling relationship between the bit lines in a pair of memory arrays and the corresponding pair of sense amplifier blocks is designed as follows: In a pair of memory arrays, a part of the bit lines of one and a part of the bit lines of the other are coupled to one of the pair of sense amplifier blocks, and the remaining bit lines of one and the remaining bit lines of the other are coupled to the other of the pair of sense amplifier blocks. In this way, all the bit lines in a pair of memory arrays can be referenced to each other. For the memory arrays located at the edge, having a neighboring memory array along the extension direction of the bit line enables all the bit lines in the memory array at the edge to have corresponding reference bit lines, which is beneficial to improving the utilization rate of the bit lines in the memory array.

[0023] In addition, the first chip and the second chip are bonded to each other, that is, the first chip and the second chip are stacked in the vertical direction, which is beneficial to reducing the layout area of a single chip in the horizontal direction. Here, the vertical direction is the direction from the first chip to the second chip, and the horizontal direction is perpendicular to the vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are illustrated by way of example in the accompanying drawings, and these exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, the drawings in the figures do not constitute a proportional limitation; In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 It is a schematic diagram of the coupling between the bit line and the sense amplifier in a memory array;

[0026] Figure 2 It is a three-dimensional structure schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figure 3 It is a top view structure schematic diagram of the first chip and the second chip in the semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figure 4 It is a top view structure schematic diagram of the bit line, the conductive part, and the bit line extension part in the semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figure 5A top view structure diagram of the first chip in the semiconductor structure provided by the embodiments of the present disclosure;

[0030] Figure 6 A cross-sectional structure diagram of the first chip and the second chip provided by the embodiments of the present disclosure;

[0031] Figure 7 Another top view structure diagram of the first chip in the semiconductor structure provided by the embodiments of the present disclosure;

[0032] Figure 8 Yet another top view structure diagram of the first chip in the semiconductor structure provided by the embodiments of the present disclosure;

[0033] Figure 9 Another top view structure diagram of the first chip in the semiconductor structure provided by the embodiments of the present disclosure;

[0034] Figure 10 Another top view structure diagram of the first chip in the semiconductor structure provided by the embodiments of the present disclosure;

[0035] Figure 11 A cross-sectional structure diagram between the bit line extension portion, the first electrical connection portion, and the second electrical connection portion in the semiconductor structure provided by the embodiments of the present disclosure;

[0036] Figures 12 to 14 Three top view structure diagrams of the second chip in the semiconductor structure provided by the embodiments of the present disclosure;

[0037] Figure 15 For two Figure 14 A top view structure diagram of the adjacent logical blocks shown;

[0038] Figure 16 For two Figure 14 Another top view structure diagram of the adjacent logical blocks shown;

[0039] Figure 17 A top view structure diagram of multiple word lines in the memory array provided by the embodiments of the present disclosure;

[0040] Figure 18 A top view structure diagram of the first wiring layer in the first chip provided by the embodiments of the present disclosure;

[0041] Figure 19 A top view structure diagram of some of the second sub-wirings and the first bonding pads in the embodiments of the present disclosure;

[0042] Figure 20 A top view structure diagram of some of the first sub-wirings and the first bonding pads in the embodiments of the present disclosure. Detailed implementation manners

[0043] As is known from the background art, the electrical connection relationship between each device in the logic chip and the memory cell array in the memory chip needs to be optimized, and the utilization rate of the bit lines in the memory array also needs to be improved.

[0044] Upon analysis, it is found that with reference to Figure 1 , Figure 1 is a schematic diagram of the coupling between the bit lines and the sense amplifiers in a memory array. Along the extension direction Y of the bit lines, a plurality of memory arrays 10 can be arranged. Among these plurality of memory arrays 10, there are edge memory arrays 11 located at the upper and lower edges, and several intermediate memory arrays 12 located between the edge memory arrays 11. The memory cell array and the corresponding sense amplifier and word line driver are on the same wafer. For example, Figure 1 in, the sense amplifier 14 is located between adjacent memory arrays 10. Since the space between adjacent memory arrays 10 is limited, the number of sense amplifiers 14 that can be arranged is limited. Therefore, different bit lines in a certain memory array 10 are cross-referenced with two different adjacent memory arrays 10. Moreover, Figure 1 the layout of the structure including the memory cell array and the structure including the logic circuit in makes the horizontal layout area of the semiconductor structure relatively large.

[0045] Continuing to refer to Figure 1 it can be seen that for any edge memory array 11, at least half of the bit lines 13 in the edge memory array 11 do not have corresponding reference bit lines. However, the sense amplifier 14 has two input terminals and needs to be coupled to two different bit lines 13 respectively in order to accurately read the potential on one of the two bit lines 13 by using one of the two bit lines 13 as the reference bit line. Therefore, at least half of the bit lines 13 in the edge memory array 11 cannot be used normally because there is no corresponding reference bit line to be coupled to the same sense amplifier 14.

[0046] It can be seen that the coupling relationship between the bit lines 13 and the sense amplifiers 14 in the current memory array 10 needs to be improved, and the utilization rate of the bit lines 13 in the memory array 10 needs to be increased.

[0047] The present disclosure provides a semiconductor structure. Two adjacent memory arrays along the bit line extension direction are designed as a pair of memory arrays, and two sense amplifier blocks corresponding to the pair of memory arrays are a pair of sense amplifier blocks. The memory arrays and the sense amplifier modules are on different wafers (chips). On this basis, in a pair of memory arrays, a part of the bit lines of one and a part of the bit lines of the other are coupled to one of the pair of sense amplifier blocks, and the remaining bit lines of one and the remaining bit lines of the other are coupled to the other of the pair of sense amplifier blocks. In this way, all the bit lines in a pair of memory arrays can be used as references for each other. For a memory array located at the edge, having an adjacent memory array along the bit line extension direction enables all the bit lines in the memory array at the edge to have corresponding reference bit lines, which is beneficial to improving the utilization rate of the bit lines in the memory array. In addition, the first chip and the second chip are bonded to each other, that is, the first chip and the second chip are stacked in the vertical direction, which is beneficial to reducing the layout area of a single chip in the horizontal direction. Here, the vertical direction is the direction from the first chip to the second chip, and the horizontal direction is perpendicular to the vertical direction.

[0048] The following will elaborate on each embodiment of the present disclosure with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are proposed to help readers better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can still be implemented.

[0049] An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0050] Among them, Figure 2 is a schematic three-dimensional structure diagram of the semiconductor structure provided by the embodiment of the present disclosure; Figure 3 is a schematic top view structure diagram of the first chip and the second chip respectively in the semiconductor structure provided by the embodiment of the present disclosure.

[0051] Refer to Figure 2 and Figure 3, the semiconductor structure includes: a first chip 101 and a second chip 102 bonded to each other; the first chip 101 includes a plurality of memory arrays 100 arranged in an array, and each memory array 100 includes a plurality of bit lines 107 arranged at intervals; the second chip 102 includes sense amplifier sections 106 corresponding to the memory arrays 100 one by one; wherein, two adjacent memory arrays 100 along the bit line extension direction Y are a pair of memory arrays AA, and the two sense amplifier sections 106 corresponding to a pair of memory arrays AA are a pair of sense amplifier sections BB. In a pair of memory arrays AA, a part of the bit lines 107 of one F1 and a part of the bit lines 107 of the other G1 are coupled to one G2 of a pair of sense amplifier sections BB, and the remaining bit lines 107 of one F1 and the remaining bit lines 107 of the other G1 are coupled to the other F2 of a pair of sense amplifier sections BB.

[0052] In this way, all the bit lines 107 in a pair of memory arrays AA can be used as references for each other. For the memory arrays 100 located at the edge, having one adjacent memory array 100 along the bit line extension direction Y can enable all the bit lines 107 in the memory array 100 at the edge to have corresponding reference bit lines, which is beneficial to improving the utilization rate of the bit lines 107 in the memory arrays 100.

[0053] It should be noted that Figure 3 to facilitate the distinction between the two memory arrays 100 in a pair of memory arrays AA, F1 and G1 are used to label the two memory arrays 100 respectively; to facilitate the distinction between the two sense amplifier sections 106 in a pair of sense amplifier sections BB, F2 and G2 are used to label the two sense amplifier sections 106 respectively. In addition, to facilitate the illustration of the corresponding relationship between the memory arrays 100 in the first chip 101 and the sense amplifier sections 106 in the second chip 102, Figure 3 the partial top view structure schematic diagram of the first chip 101 and the partial top view structure schematic diagram of the second chip 102 facing it are shown side by side left and right. In actual application, Figure 3 the partial top view structure schematic diagram of the first chip 101 and the partial top view structure schematic diagram of the second chip 102 are as Figure 2 shown, facing each other along the vertical direction Z.

[0054] In addition, referring to Figure 2 and Figure 3 , the first chip 101 and the second chip 102 are bonded to each other, that is, the first chip 101 and the second chip 102 are stacked along the vertical direction Z, which is beneficial to reducing the layout area of a single chip in the horizontal direction H. Wherein, the vertical direction Z is the direction from the first chip 101 to the second chip 102, and the horizontal direction H is perpendicular to the vertical direction Z.

[0055] It should be noted that, referring toFigure 3 , the storage array 100 includes a plurality of bit lines 107 arranged at intervals, and the bit line extension direction Y is the extension direction of the bit line 107, and the bit line extension direction Y and the horizontal direction H are in the same horizontal plane.

[0056] In some cases, the storage array 100 further includes a plurality of word lines arranged at intervals, the word line extension direction X is the extension direction of the word line, and the bit line extension direction Y, the word line extension direction X, and the horizontal direction H are all in the same horizontal plane. In one example, the bit line extension direction Y is perpendicular to the word line extension direction X, and the horizontal direction H may refer to one of the bit line extension direction Y or the word line extension direction X.

[0057] It should be noted that Figure 2 only one storage array 100 in the first chip 101 is schematically shown, Figure 3 only two storage arrays 100 arranged along the bit line extension direction Y in the first chip 101 are schematically shown. In practical applications, the number of storage arrays 100 in the first chip 101 is not limited, and multiple storage arrays 100 may be arranged only along the bit line extension direction Y, or multiple storage arrays 100 may be arranged in an array along the bit line extension direction Y and the word line extension direction X. The array arrangement here includes but is not limited to square arrangement, rectangular arrangement, or hexagonal arrangement.

[0058] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0059] In some embodiments, referring to Figure 3 and Figure 4 , Figure 4 is a top view structural schematic diagram between a bit line, a conductive part, and a bit line extension part in the semiconductor structure provided by the embodiments of the present disclosure. The bit line 107 is coupled to the corresponding sense amplifier block 106 through the corresponding bit line extension part 117. The bit line extension part 117 is the first extension part 127 or the second extension part 137, and the extension direction of the bit line extension part 117 is the same as that of the bit line 107; wherein, the first extension part 127 and the corresponding bit line 107 are in the same storage array 100, the second extension part 137 and the corresponding bit line 107 are in different storage arrays 100 in a pair of storage arrays AA, and the first extension part 127 and the second extension part 137 extend in different metal layers.

[0060] It can be understood that the bit lines 107 and the bit line extensions 117 correspond one by one. In other words, one bit line 107 is electrically connected to one bit line extension 117. For example, one bit line 107 is electrically connected to one bit line extension 117 through the conductive part 147. In this way, the bit line 107 can transmit an electrical signal to a preset area on the first chip 101 through the bit line extension 117, for example, to the bit line connection section, and then realize the electrical connection between the bit line connection section and the sense amplification section 106 in the second chip 102, so as to realize the coupling between the bit line 107 and the corresponding sense amplification section 106 in the first chip 101.

[0061] It should be noted that the first extension 127 and the corresponding bit line 107 being in the same memory array 100 means that the first extension 127 and the bit line 107 electrically connected thereto are both in the same memory array 100. For example, Figure 3 in the shown memory array F1, the first, third, fifth, and seventh BL#s counted from left to right in total, and the corresponding first extensions 127 thereto are all in the same memory array F1, and Figure 3 in the shown memory array G1, the second, fourth, sixth, and eighth BLs counted from left to right in total, and the corresponding first extensions 127 thereto are all in the same memory array G1.

[0062] In addition, the second extension 137 and the corresponding bit line 107 being in different memory arrays 100 in a pair of memory arrays AA means that the second extension 137 and the bit line 107 electrically connected thereto are in different memory arrays 100 in a pair of memory arrays AA. For example, Figure 3 in the shown memory array F1, the second, fourth, sixth, and eighth BL#s counted from left to right in total are in the memory array F1 in a pair of memory arrays AA, but the corresponding second extensions 137 to these four BL#s are in the memory array G1 in a pair of memory arrays AA, Figure 3 in the shown memory array FG1, the first, third, fifth, and seventh BLs counted from left to right in total are in the memory array G1 in a pair of memory arrays AA, but the corresponding second extensions 137 to these four BLs are in the memory array F1 in a pair of memory arrays AA.

[0063] It can be understood that no matter which memory array 100 in a pair of memory arrays AA, in this memory array 100, some of the bit lines 107 are electrically connected to the first extension 127, and the remaining bit lines 107 are electrically connected to the second extension 137.

[0064] It should be noted that, firstly, for the convenience of distinguishing the bit lines 107 in the two memory arrays 100 in a pair of memory arrays AA, Figure 3Label the bit line 107 located in the memory array F1 as BL#, and label the bit line 107 located in the memory array G1 as BL.

[0065] Second, to facilitate the distinction between whether the bit line extension 117 is the first extension 127 or the second extension 137, along the word line extension direction X, Figure 3 draw the width of the first extension 127 smaller than the width of the second extension 137. In practical applications, there is no limitation on the size relationship between the width of the first extension 127 and the width of the second extension 137.

[0066] Third, Figure 3 is only a simple drawing method of the conductive part 147, aiming to show that the electrical connection between the bit line 107 and the bit line extension 117 is realized through the conductive part 147. Figure 3 There is no limitation on the number of film layers in the first chip 101 that the conductive part 147 crosses to achieve the electrical connection between the bit line 107 and the bit line extension 117, and this number can be adjusted according to the actual situation. The conductive part 147 will be described in detail later.

[0067] In addition, to clearly show the positional relationship among the conductive part 147, the first extension 127, and the second extension 137, Figure 3 a perspective drawing method is adopted for both the first extension 127 and the second extension 137. In some embodiments, refer to Figure 2 and Figure 3 , along the vertical direction Z, the second extension 137 is located on the side of the first extension 127 away from the conductive part 147, that is, the second extension 137 is located above the first extension 127. The vertical direction Z

[0068] In some embodiments, refer to Figure 3 , taking the plane formed by the bit line extension direction Y and the word line extension direction X as the projection plane, the orthographic projection of the conductive part 147 on this projection plane is located within the orthographic projection of the bit line extension 117 on this projection plane.

[0069] In some embodiments, refer to Figure 3 , the bit line 107 is electrically connected to the corresponding bit line extension 117 through the conductive part 147 and coupled to the sense amplifier block 106. One end of the conductive part 147 is in contact connection with the bit line extension 117, and the other end is in contact connection with the bit line 107.

[0070] In Figure 3 Based on the fact that the orthographic projection of the first extension 127 on the projection plane and the orthographic projection of the second extension 137 on the projection plane overlap as shown, combined with Figure 4 the conductive part 147 will be described in detail.

[0071] In some cases, refer toFigure 4 , since the orthographic projections of the first extension portion 127 and the second extension portion 137 on the projection plane overlap, it is necessary to design the first extension portion 127 and the second extension portion 137 to extend in different metal layers, that is, to design the first extension portion 127 and the second extension portion 137 not to be in the same layer. Therefore, it is necessary to design a conductive portion 147 that electrically connects the first extension portion 127 and the bit line 107, and the number of metal layers spanned by the conductive portion 147 that electrically connects the second extension portion 137 and the bit line 107 is different.

[0072] Based on this, the conductive portion 147 between the second extension portion 137 and the bit line 107 is labeled as P, and the conductive portion 147 between the first extension portion 127 and the bit line 107 is labeled as Q. The conductive portion P and the conductive portion Q will be described in detail below.

[0073] Refer to Figure 4 , the conductive portion P includes: a first conductive column CT0 with both ends respectively contacting and connecting the bit line 107 and the first metal layer M0, and a part of the first metal layer M0 in contact connection with the first conductive column CT0. The bit line 107 transmits an electrical signal to the first metal layer M0 through the first conductive column CT0; a second conductive column CT1 with both ends respectively contacting and connecting the first metal layer M0 and the second metal layer M1, and a part of the second metal layer M1 in contact connection with the second conductive column CT1. The electrical signal received by the first metal layer M0 from the bit line 107 is transmitted to the second metal layer M1 through the second conductive column CT1; a third conductive column CT2 with both ends respectively contacting and connecting the second metal layer M1 and the third metal layer M2, and a part of the third metal layer M2 in contact connection with the third conductive column CT2. The electrical signal received by the second metal layer M1 from the bit line 107 is transmitted to the third metal layer M2 through the third conductive column CT2; a fourth conductive column CT3 with both ends respectively contacting and connecting the third metal layer M2 and the fourth metal layer, and a part of the fourth metal layer M3 in contact connection with the fourth conductive column CT3. The electrical signal received by the third metal layer M2 from the bit line 107 is transmitted to the fourth metal layer M3 through the fourth conductive column CT3. It should be noted that a part of the fourth metal layer M3 in contact connection with the conductive column CT3 serves as the second extension portion 137 (refer to Figure 3 ).

[0074] The conductive part Q includes: a first conductive column CT0 with two ends respectively contacting and connecting to the bit line 107 and the first metal layer M0, and a part of the first metal layer M0 in contact connection with the first conductive column CT0. The bit line 107 transmits an electrical signal to the first metal layer M0 through the first conductive column CT0; a second conductive column CT1 with two ends respectively contacting and connecting to the first metal layer M0 and the second metal layer M1, and a part of the second metal layer M1 in contact connection with the second conductive column CT1. The electrical signal received by the first metal layer M0 from the bit line 107 is transmitted to the second metal layer M1 through the second conductive column CT1; a third conductive column CT2 with two ends respectively contacting and connecting to the second metal layer M1 and the third metal layer M2, and a part of the third metal layer M2 in contact connection with the third conductive column CT2. The electrical signal received by the second metal layer M1 from the bit line 107 is transmitted to the third metal layer M2 through the third conductive column CT2. It should be noted that a part of the third metal layer M2 in contact connection with the third conductive column CT2 serves as the first extension part 127 (refer to Figure 3 ).

[0075] It should be noted that Figure 4 the total structure composed of multiple complete structures framed by a dotted-line square in Figure 4 is marked with the conductive part P and the conductive part Q. Moreover Figure 4 the conductive part P and the conductive part Q in

[0076] are only one example. In actual applications, the number of metal layers that the conductive part 147 needs to cross can be adjusted according to the actual wiring situation, and the number of conductive columns that need to be designed based on this can also be adjusted.

[0076] In addition Figure 4 the metal layers M0, M1, M2, and M3 are used to mark the metal layers that the electrical signal on the bit line 107 crosses. In actual applications, not only the wiring for transmitting the electrical signal on the bit line 107 exists in the metal layers M0, M1, M2, and M3, but also other wiring structures are available for transmitting other electrical signals. For example Figure 3 the first extension part 127 shown in Figure 4 is located in the metal layer M2 shown in Figure 3 , that is, the extension length of the first extension part 127 on the metal layer M2 is relatively long. Figure 3 The second extension part 137 shown in Figure 4 is located in the metal layer M3 shown in Figure 3 and Figure 4 , that is, the extension length of the second extension part 137 on the metal layer M3 is relatively long. Combining with the reference Figure 3 and Figure 4 , the layout space of the conductive part 147 corresponding to the first extension part 127 and the second extension part 137 in the metal layer M1 is relatively small. Then, most of the remaining layout space in the metal layer M1 can be used for laying out the wiring layer corresponding to the word line later.

[0077] To clearly show the specific structure of the conductive part 147, Figure 4 a perspective drawing method is adopted for the metal layers M0, M1, M2, and M3 in

[0078] In some embodiments, referring to Figure 5 , the first chip 101 further includes bit line connection sections 157 corresponding one-to-one to the memory arrays 100. One end of the bit line extension 117 is located in the bit line connection section 157, and the other end is electrically connected to the corresponding bit line 107. Among them, the two bit line connection sections 157 corresponding to a pair of memory arrays AA are the first bit line connection section 167 and the second bit line connection section 177 respectively. The multiple bit line extensions 117 with one end located in the first bit line connection section 167 include multiple first extensions 127 and multiple second extensions 137. Moreover, the other end of the first extension 127 is electrically connected to the bit line 107 in the memory array 100 corresponding to the first bit line connection section 167, and the other end of the second extension 137 is electrically connected to the bit line 107 in the memory array 100 corresponding to the second bit line connection section 177.

[0079] Among them, Figure 5 is a top view structural schematic diagram of the first chip in the semiconductor structure provided by the embodiments of the present disclosure.

[0080] It should be noted that for the multiple first extensions 127 and multiple second extensions 137 with one end located in the first bit line connection section 167, the other end of the first extension 127 among them is electrically connected to the bit line 107 in the memory array 100 corresponding to the first bit line connection section 167, and the other end of the second extension 137 among them is electrically connected to the bit line 107 in the memory array 100 corresponding to the second bit line connection section 177. Similarly, for the multiple first extensions 127 and multiple second extensions 137 with one end located in the second bit line connection section 177, the other end of the first extension 127 among them is electrically connected to the bit line 107 in the memory array 100 corresponding to the second bit line connection section 177, and the other end of the second extension 137 among them is electrically connected to the bit line 107 in the memory array 100 corresponding to the first bit line connection section 167.

[0081] It should be noted that the bit line connection section 157 is a preset area in the first chip 101. The ends of the bit line extensions 117 all need to extend into this preset area, but the bit line extensions 117 are not part of this area. Based on this, when the first chip 101 and the second chip 102 are bonded to each other, the bit line extensions 117 with ends extending into the bit line connection section 157 are electrically connected to the sense amplifier section 106.

[0082] In one example, along the vertical direction Z, the bit line connecting section 157 and the sense amplifier section 106 are directly opposite to each other, that is, their orthographic projections on the projection plane formed by the word line extension direction X and the bit line extension direction Y coincide, which is beneficial to reducing the length of the transmission path for the electrical signal to be transmitted from the bit line 107 to the sense amplifier section 106, so as to reduce the loss during the transmission of the electrical signal.

[0083] It should be noted that whether it is the first bit line connecting section 167 or the second bit line connecting section 177, a partial number of the first extension parts 127 and a partial number of the second extension parts 137 both extend into the bit line connecting section 157, and the first extension parts 127 and the second extension parts 137 located in the same bit line connecting section 157 correspond to each other one by one.

[0084] Based on the description of the foregoing embodiments, the first extension part 127 and the corresponding bit line 107 are in the same memory array 100, and the second extension part 137 and the corresponding bit line 107 are in different memory arrays 100 in a pair of memory arrays AA. Therefore, among the first extension parts 127 and the second extension parts 137 located in the same bit line connecting section 157, the bit line 107 electrically connected to the first extension part 127 and the bit line 107 electrically connected to the second extension part 137 come from different memory arrays 100 in a pair of memory arrays AA, so that all the bit lines 107 in the two memory arrays 100 in a pair of memory arrays AA can be paired in pairs through the first extension parts 127 and the second extension parts 137. The paired two bit lines 107 can respectively transmit electrical signals to the corresponding bit line connecting section 157 through the first extension parts 127 and the second extension parts 137, so that the paired two bit lines 107 are electrically connected to the same sense amplifier section 106, thereby enabling the paired two bit lines 107 to be used as reference bit lines for each other, which is beneficial to enabling all the bit lines 107 in the two memory arrays 100 in a pair of memory arrays AA to be used normally, and thus beneficial to improving the utilization rate of the bit lines 107 in the memory array 100.

[0085] In one example, as Figure 5 shown, the first extension part 127 and the second extension part 137 whose orthographic projections on the projection plane formed by the word line extension direction X and the bit line extension direction Y coincide can be a pair of bit line extension parts DD, and the two bit lines 107 electrically connected to the pair of bit line extension parts DD can be used as reference bit lines for each other.

[0086] It should be noted that Figure 5Taking the example that the distance between the two ends of the first extension 127 and the second extension 137 of a pair of bit line extensions DD extending to the two ends of the bit line connection section 157 is relatively small. In actual applications, the distance between the two ends of the first extension 127 and the second extension 137 of the same pair of bit line extensions DD extending to the two ends of the bit line connection section 157 needs to meet the following conditions: This distance needs to reserve at least the size of one conductive pillar to ensure that the first extension 127 and the second extension 137 of the same pair of bit line extensions DD are respectively connected to different conductive pads on the bonding interface through different conductive pillars.

[0087] It should be noted that for the convenience of showing the corresponding relationship between the bit line extension 117 and the bit line connection section 157 in the first chip 101, Figure 5 the partial top view structural schematic diagrams of the bit line 107 and the bit line extension 117 in the first chip 101 and the partial top view structural schematic diagram of the corresponding bit line connection section 157 are shown side by side left and right. In actual applications, Figure 5 the partial top view structural schematic diagrams of the bit line 107 and the bit line extension 117 and the partial top view structural schematic diagram of the corresponding bit line connection section 157 are Figure 2 as shown, facing each other in the vertical direction Z. Moreover, the bit line connection section 157 is located on the side of the bit line extension 117 away from the bit line 107.

[0088] In some embodiments, with reference to Figure 3 , Figure 5 and Figure 6 , the mutually bonded first chip 101 and second chip 102 have a bonding interface w, and the orthographic projections of the bit line connection section 157 and the sense amplifier section 106 on the bonding interface w coincide; the first chip 101 may further include: a plurality of first bonding pads 119 arranged at intervals along the bit line extension direction Y and the word line extension direction X. Among the plurality of first bonding pads 119 located in the bit line connection section 157, at least some of the first bonding pads 119 are electrically connected to one end of the bit line extension 117.

[0089] Among them, Figure 6 is a schematic cross-sectional structure diagram of the first chip and the second chip provided by the embodiments of the present disclosure.

[0090] It can be understood that one end of the bit line extension 117 electrically connected to the first bonding pad 119 is located in the bit line connection section 157, and the other end of the bit line extension 117 is electrically connected to the bit line 107. Since the orthographic projections of the bit line connection section 157 and the sense amplifier section 106 on the bonding interface w coincide, it is beneficial to reduce the length of the transmission path for the electrical signal to be transmitted from the bit line 107 to the sense amplifier section 106, so as to reduce the loss during the electrical signal transmission process.

[0091] Continue to refer toFigure 6 In addition, the second chip 102 may further include: a plurality of second bonding pads 129 arranged at intervals along the bit line extending direction Y and the word line extending direction X. The first bonding pad 119 located in the bit line connection section 157 is in contact connection with the second bonding pad 129 located in the sense amplifier section 106, and the word line extending direction X intersects with the bit line extending direction Y. In this way, the coupling between the bit line 107 and the sense amplifier section 106 can be realized through the contact connection between the first bonding pad 119 and the second bonding pad 129.

[0092] It can be understood that the plurality of second bonding pads 129 are in the same film layer, and this film layer is located on the side of the sense amplifier section 106 close to the first chip 101 (refer to Figure 2 ). In addition, the film layer where the plurality of second bonding pads 129 are located has a plurality of second bonding pads 129 in both the area facing the sense amplifier section 106 and the area facing other sections in the second chip 102.

[0093] The corresponding relationship between the memory array and the bit line connection section will be described in detail below.

[0094] In some embodiments, refer to Figure 5 , two bit line connection sections 157 corresponding to a pair of memory arrays AA are adjacent along the bit line extending direction Y. On this basis, it is designed that there is a gap between the two memory arrays 100 in a pair of memory arrays AA, so that the bit lines 107 in a pair of memory arrays AA are all electrically connected to the bit line extension part 117 from this gap, which is beneficial to reducing the length of the bit line extension part 117 in the bit line extending direction Y.

[0095] It should be noted that, in other embodiments, there may also be no gap between the two memory arrays in a pair of memory arrays, then the end points of the bit lines in the memory array do not exceed the area where the memory array is located. In practical applications, a conductive part can be led out from the middle area of the bit line as needed to realize the electrical connection between the bit line and the bit line extension part.

[0096] In some other embodiments, refer to Figure 7 , the first bit line connection section 267 and the second bit line connection section 277 are on the same side of the corresponding memory array 200. In other words, along the bit line extending direction Y, the memory array 200 has opposite third side S3 and fourth side S4, and the bit line connection sections 257 corresponding to the memory array 200 are all adjacent to the third side S3, and the third side S3 of one of the pair of memory arrays AA and the fourth side S4 of the other are adjacent.

[0097] Among them, Figure 7 is another top view structural schematic diagram of the first chip in the semiconductor structure provided by the embodiments of the present disclosure.

[0098] In still some other embodiments, refer toFigure 8 Along the bit line extension direction Y, the first bit line connection section 367 and the second bit line connection section 377 are located on opposite sides of a pair of memory arrays AA. In other words, along the bit line extension direction Y, a pair of memory arrays AA has opposite first side S1 and second side S2. The bit line connection section 257 corresponding to one of the pair of memory arrays AA is adjacent to the first side S1, and the bit line connection section 357 corresponding to the other of the pair of memory arrays AA is adjacent to the second side S2.

[0099] Among them, Figure 8 is another top view structure diagram of the first chip in the semiconductor structure provided by the embodiment of the present disclosure. It should be noted that Figure 7 and Figure 8 In, the first side S1 of the pair of memory arrays AA is the third side S3 of the memory array F1, and the second side S2 of the pair of memory arrays AA is the fourth side S4 of the memory array G1.

[0100] It should be noted that for the convenience of showing the corresponding relationship between the bit line extension section 317 and the bit line connection section 357 in the first chip 101 (refer to Figure 2 ), Figure 8 In, the partial top view structure diagram of the bit line 307 and the bit line extension section 317 in the first chip 101 and the partial top view structure diagram of the corresponding bit line connection section 357 are shown side by side on the left and right. In actual application, Figure 8 The partial top view structure diagram of the bit line 307 and the bit line extension section 317 and the partial top view structure diagram of the corresponding bit line connection section 357 are Figure 2 As shown, they are directly opposite in the vertical direction Z. Moreover, the bit line connection section 357 is located on the side of the bit line extension section 317 away from the bit line 307.

[0101] In addition, Figure 7 and Figure 8 In the embodiments shown, the same or corresponding parts as those in Figure 5 shown are not described herein again.

[0102] In some embodiments, referring to Figure 3 or Figure 8 , taking the annotation in Figure 3 as an example, the bit line 107 coupled to the sense amplifier section 106 is electrically connected to the corresponding bit line extension section 117 through the conductive portion 147. It should be noted that Figure 8 The same or corresponding parts of the conductive portion 347 in

[0103] In some cases, Figure 8 the specific structure of the conductive portion 347 in Figure 4The specific structure of the conductive part 147 shown is the same; in other cases, due to the positional relationship between the conductive part 347 and the storage array 300 being different from that in the Figure 3 example shown, the orthographic projections of the first extension part 327 and the second extension part 337 on the bonding interface w may not overlap, such that the first extension part 327 and the second extension part 337 can be on the same layer, for example, both on the metal layer M2 or both on the metal layer M3.

[0104] It can be understood that, in some examples, both the first extension part 327 and the second extension part 337 are on the metal layer M2. Whether it is the conductive part 347 in contact with the first extension part 327 or the conductive part 347 in contact with the second extension part 337, the specific structure can be like the Figure 4 specific structure of the conductive part Q shown; in other examples, both the first extension part 327 and the second extension part 337 are on the metal layer M3. Whether it is the conductive part 347 in contact with the first extension part 327 or the conductive part 347 in contact with the second extension part 337, the specific structure can be like the Figure 4 specific structure of the conductive part P shown.

[0105] The positional relationship between the conductive part and the storage array will be described in detail below.

[0106] In some embodiments, referring to Figure 8 , along the bit line extension direction Y, the storage array 300 has opposite third side S3 and fourth side S4; a part of the conductive part 347 in contact connection with the bit line 307 in the storage array 300 is located in the area of the third side S3 far from the fourth side S4, and other conductive parts 347 in contact connection with the bit line 307 in the storage array 300 are located in the area of the fourth side S4 far from the third side S3. It should be noted that in the above description, the third side S3 and the fourth side S4 are based on the same storage array 300. Among the multiple conductive parts 347 corresponding to the same storage array 300, the conductive part 347 with a closer distance in the second direction Y from the bit line connection section 357 corresponding to the storage array 300 is connected to the first extension part 327, and the conductive part 347 with a farther distance in the second direction Y from the bit line connection section 357 corresponding to the storage array 300 is connected to the second extension part 337. In this way, on the one hand, it is beneficial to shorten the lengths of the first extension part 327 and the second extension part 337 in the second direction Y and reduce the wiring space occupied by the first extension part 327. On the other hand, it can make the first extension part 327 and the second extension part 337 in any storage array 300 be on the same layer.

[0107] In other embodiments, referring to Figure 9, along the bit line extension direction Y, the memory array 400 has opposite third side S3 and fourth side S4; the partial conductive part 447 in contact connection with the bit line 407 in the memory array 400 is located in the area where the fourth side S4 is far from the third side S3, and the other conductive part 447 in contact connection with the bit line 407 in the memory array 400 is located in the area where the third side S3 is far from the fourth side S4. It should be noted that in the above description, the third side S3 and the fourth side S4 are based on the same memory array 400. Among the multiple conductive parts 447 corresponding to the same memory array 300, the conductive part 447 closer to the bit line connection section 457 corresponding to the memory array 400 in the second direction Y is connected to the second extension part 437, and the conductive part 447 farther from the bit line connection section 457 corresponding to the memory array 400 in the second direction Y is connected to the first extension part 427. In this way, it is beneficial to reduce the length difference between the first extension part 427 and the second extension part 437 in the second direction Y, so that the parasitic capacitances on the first extension part 427 and the second extension part 437 are similar. It should be noted that the third side S3 and the fourth side S4 here refer to the sides of the memory array, rather than the areas outside the memory array.

[0108] In still some other embodiments, referring to Figure 10 , along the bit line extension direction Y, the memory array 500 has opposite third side S3 and fourth side S4; the conductive part 547 in contact connection with the bit line 507 of the memory array F1 in a pair of memory arrays AA is located in the area where the third side S3 is far from the fourth side S4, and the conductive part 547 in contact connection with the bit line 507 of the memory array G1 in the pair of memory arrays AA is located in the area where the fourth side S4 is far from the third side S3. In this way, it is beneficial to ensure that the orthographic projections of the first extension part 527 and the second extension part 537 in any memory array 500 on the bonding interface do not overlap, that is, the first extension part 327 and the second extension part 337 can be on the same layer.

[0109] It should be noted that Figure 9 the positional relationship between the first bit line connection section 467 and the second bit line connection section 477 in the bit line connection section 457 corresponding to the memory array 400 in Figure 8 is the same as Figure 10 the positional relationship between the first bit line connection section 567 and the second bit line connection section 577 in the bit line connection section 557 corresponding to the memory array 500 in Figure 8 is also the same as

[0110] In still some other embodiments, referring to Figure 5, along the bit line extension direction Y, the storage array 100 has opposite third side S3 and fourth side S4; the conductive part 147 in contact connection with the bit line 107 in the storage array F1 in the pair of storage arrays AA is located in the area where the fourth side S4 is far from the third side S3, and the conductive part 147 in contact connection with the bit line 107 of the storage array G1 in the pair of storage arrays AA is located in the area where the third side S3 is far from the fourth side S4. It should be noted that in the above description, the third side S3 and the fourth side S4 are based on the same storage array 100, and the conductive part 147 is located in the area where the third side S3 of the same storage array 100 is far from the fourth side S4. In this way, it is beneficial to make the first extension part 127 and the second extension part 137 extend in the same direction, thereby facilitating reducing the difference in the lengths of the first extension part 127 and the second extension part 137 in the second direction Y, and making the parasitic capacitances on the first extension part 127 and the second extension part 137 similar.

[0111] In addition, referring to Figure 5 , Figure 7 and Figure 8 , it can be known that the corresponding relationship between the storage array and the bit line connection section can be variable, and the corresponding relationship between the storage array and the conductive part can be variable. Therefore, the position of the metal layer where the bit line extension part, which is electrically connected to the conductive part at one end and located in the bit line connection section at the other end, is located and the length of the bit line extension part in the bit line extension direction are variable. Therefore, the layout among the storage array, the conductive part, the bit line extension part, and the bit line connection section in the embodiments of the present disclosure can be adjusted according to the actual situation, and finally, it can be achieved that "in a pair of storage arrays AA, a part of the bit lines 107 of one, F1, and a part of the bit lines 107 of the other, G1, are coupled to one, G2, of a pair of sense amplifier sections BB, and the remaining bit lines 107 of one, F1, and the remaining bit lines 107 of the other, G1, are coupled to the other, F2, of the pair of sense amplifier sections BB".

[0112] For example, by simultaneously extending Figure 5 the lengths of the first extension part and the second extension part in the two storage arrays, the first bit line connection section and the second bit line connection section can be located on opposite sides of the pair of storage arrays AA. Similarly, by only extending the first extension part and the second extension part in the same storage array, the first bit line connection section and the second bit line connection section can be on the same side of the corresponding storage array; further, by adjusting Figures 8 to 10 the lengths of the first extension part and the second extension part in Figure 5The types. That is to say, there is no absolute corresponding relationship between the layout of the first bit line connection section and the second bit line connection section introduced in this article, and the extension methods and extension lengths of the first extension section and the second extension section. They can be combined according to needs, and only some embodiments are illustrated in this article. In addition, the "first extension section and the second extension section in the storage array" mentioned in this paragraph refer to the extension sections where most of the projection areas coincide with the storage array. One of them is connected to the bit line in this storage array, and the other is connected to the bit line of the other in a pair of storage arrays.

[0113] The following takes Figure 3 the example shown to illustrate the embodiments of the present disclosure in detail.

[0114] In some embodiments, referring to Figure 3 , the bit line 107 coupled to the sense amplifier section 106 is electrically connected to the corresponding bit line extension section 117 through the conductive part 147; along the bit line extension direction Y, two bit line connection sections 157 corresponding to a pair of storage arrays AA are adjacent along the bit line extension direction Y, and there is an extraction section 110 between the adjacent bit line connection sections 157. The conductive parts 147 in contact with the bit lines 107 in the pair of storage arrays AA are all located in the extraction section 110.

[0115] In this way, the bit lines 107 in the pair of storage arrays AA are all electrically connected to the bit line extension section 117 through the conductive parts 147 in the extraction section 110, and the distance between the bit line connection section 157 and the extraction section 110 in the bit line extension direction Y is relatively close, that is, the distance between the bit line connection section 157 and the conductive part 147 in the bit line extension direction Y is relatively close. Therefore, it is beneficial to reduce the length of the bit line extension section 117 in the bit line extension direction Y, so as to reduce the length of the transmission path for the electrical signal to be transmitted from the bit line 107 to the bit line connection section 157, and reduce the loss during the transmission of the electrical signal.

[0116] In some embodiments, referring to Figure 11 , the semiconductor structure may further include: a first electrical connection part 111 in contact connection with the first extension section 127, and a second electrical connection part 121 in contact connection with the second extension section 137; in the direction perpendicular to the bonding interface, the first electrical connection part 111 includes a first sub-part 131 and a second sub-part 141 stacked.

[0117] It should be noted that the first sub - part 131 includes a part of the fourth metal layer M3 and a fourth conductive pillar. The fourth conductive pillar is used to electrically connect the first extension part 127 and this part of the fourth metal layer M3. Among them, the part of the fourth metal layer M3 included in the first sub - part 131 and the second extension part 137 are located in the same layer; the second sub - part 141 includes a part of the fifth metal layer M4 and a fifth conductive pillar. The fifth conductive pillar is used to electrically connect the first sub - part 131 and this part of the fifth metal layer M4. The second electrical connection part 121 includes another part of the fifth metal layer M4 and another fifth conductive pillar. The another fifth conductive pillar is used to electrically connect the second extension part 137 and this another part of the fifth metal layer M4. Among them, the part of the fifth metal layer M4 included in the second sub - part 141 and the another part of the fifth metal layer M4 included in the second electrical connection part 121 are located in the same layer.

[0118] Among them, Figure 11 is a schematic cross - sectional structure diagram among the bit - line extension part, the first electrical connection part and the second electrical connection part of the semiconductor structure provided by the embodiment of the present disclosure.

[0119] In this way, the electrical signal on the bit - line 107 is sequentially transmitted to the metal layer of the first chip 101 closer to the second chip 102 via the first extension part 127 and the first electrical connection part 111, or the electrical signal on the bit - line 107 is sequentially transmitted to the metal layer of the first chip 101 closer to the second chip 102 via the second extension part 137 and the second electrical connection part 121. In one example, the metal layer of the first chip 101 closer to the second chip 102 is Figure 6 the metal layer where the first bonding pad 119 shown in is located. The part of the fifth metal layer M4 included in the second sub - part 141 and the part of the fifth metal layer M4 included in the second electrical connection part 121 are different first bonding pads 119.

[0120] In some embodiments, with reference to Figure 4 and Figure 11, taking the plane formed by the bit line extension direction Y and the word line extension direction X as the projection plane, in a pair of bit line extension portions DD, the orthographic projection of the first extension portion 127 on this projection plane overlaps with the orthographic projection of the second extension portion 137 on this projection plane. Therefore, it is necessary to design that the first extension portion 127 and the second extension portion 137 are located in different layers. On this basis, it is designed that the first electrical connection portion 111 includes a first sub-portion 131 and a second sub-portion 141 stacked. The first sub-portion 131 and the second extension portion 137 are in the same layer, the second sub-portion 141 and the second electrical connection portion 121 are in the same layer, and there is a gap between the first sub-portion 131 and the second extension portion 137 along the bit line extension direction Y, and there is a gap between the second sub-portion 141 and the second electrical connection portion 121 along the bit line extension direction Y. In this way, the first sub-portion 131 and the second extension portion 137 in the same layer will not be short-circuited, and the second sub-portion 141 and the second electrical connection portion 121 in the same layer will not be short-circuited, and the electrical signal on the bit line 107 can be transmitted layer by layer to the first bonding pad 119.

[0121] In some cases, in combination with reference Figure 4 and Figure 11 , there is a gap between adjacent two metal layers, and a dielectric layer can be filled in this gap. For example, Figure 11 there is a gap between the metal layer M2 and the metal layer M3, and there is also a gap between the metal layer M3 and the metal layer M4. Based on this, the first sub-portion 131 includes a conductive pillar (not marked in the figure) located between the metal layer M2 and the metal layer M3 and a wiring layer (not marked in the figure) located in the metal layer M3. The conductive pillar is used to transmit the electrical signal on the first extension portion 127 to the wiring layer located in the metal layer M3; the second sub-portion 141 includes a conductive pillar (not marked in the figure) located between the metal layer M3 and the metal layer M4 and a wiring layer (not marked in the figure) located in the metal layer M4. The conductive pillar is used to transmit the electrical signal on the wiring layer located in the metal layer M3 to the wiring layer located in the metal layer M4; the second electrical connection portion 121 includes a conductive pillar (not marked in the figure) located between the metal layer M3 and the metal layer M4 and a wiring layer (not marked in the figure) located in the metal layer M4. The conductive pillar is used to transmit the electrical signal on the second extension portion 137 to the wiring layer located in the metal layer M4.

[0122] It should be noted that, taking the bonding interface as the projection plane, the orthographic projection of one of the wiring layers in the first sub - part 131 and the wiring layer in the second sub - part 141 may be located within the orthographic projection of the other, or the orthographic projections of both the wiring layer in the first sub - part 131 and the wiring layer in the second sub - part 141 overlap, so as to ensure the contact connection between the first sub - part 131 and the second sub - part 141; in addition, the orthographic projection of the wiring layer in the first sub - part 131 may be located within the orthographic projection of the first extension part 127, or the orthographic projections of both the wiring layer in the first sub - part 131 and the first extension part 127 overlap, so as to ensure the contact connection between the first sub - part 131 and the first extension part 127; in addition, the orthographic projection of the wiring layer in the second electrical connection part 121 may be located within the orthographic projection of the second extension part 137, or the orthographic projections of both the wiring layer in the second electrical connection part 121 and the second extension part 137 overlap, so as to ensure the contact connection between the second electrical connection part 121 and the second extension part 137.

[0123] In some embodiments, with reference to Figure 6 and Figure 11 , the first chip 101 and the second chip 102 that are bonded to each other have a bonding interface w; with reference to Figure 4 , the orthographic projection of the first extension part 127 on the bonding interface w and the orthographic projection of the second extension part 137 on the bonding interface w at least partially overlap.

[0124] The corresponding relationship between multiple bit lines 107 and the first extension part 127 or the second extension part 137 in the same memory array 100 will be described in detail below.

[0125] In some embodiments, with reference to Figure 3 , two adjacent bit lines 107 along the word - line extension direction X are a pair of bit lines CC. One of the pair of bit lines CC is electrically connected to the first extension part 127, and the other of the pair of bit lines CC is electrically connected to the second extension part 137. The word - line extension direction X intersects with the bit - line extension direction Y. Thus, for any memory array 100, the bit lines 107 are alternately electrically connected to the first extension part 127 and the second extension part 137.

[0126] In some embodiments, with reference to Figures 12 to 14 of any one of them, the second chip 102 further includes a plurality of logic blocks 103 corresponding to the memory array 100. Each logic block 103 includes a sense - amplifier block 106, a word - line drive block 104, and a peripheral - circuit block 105. In the word - line extension direction X, the size of the sense - amplifier block 106 is equal to the size of the logic block 103. The word - line extension direction X intersects with the bit - line extension direction Y.

[0127] Wherein, Figures 12 to 14Three top - view structural schematic diagrams of the second chip in the semiconductor structure provided by the embodiments of the present disclosure.

[0128] In some cases, the second chip 102 includes a plurality of logic blocks 103 corresponding to the storage array 100, which means that: the storage array 100 and the logic blocks 103 are in one - to - one correspondence, that is, the orthographic projection of the storage array 100 on the bonding interface coincides with the orthographic projection of the logic blocks 103 on the bonding interface.

[0129] The following details the situations of the word - line driving block 104 and the peripheral - circuit block 105 in each logic block 103.

[0130] In some embodiments, referring to Figure 12 , the word - line driving block 104 is located between the sense - amplifier block 106 and the peripheral - circuit block 105, and the word - line driving block 104 is a complete piece.

[0131] In other embodiments, referring to Figure 13 , the peripheral - circuit block 105 is located between the sense - amplifier block 106 and the word - line driving block 104, and the word - line driving block 104 is a complete piece.

[0132] In still other embodiments, referring to Figure 14 , the word - line driving block 104 includes a first sub - driving block 114 and a second sub - driving block 124 arranged at intervals along the word - line extension direction X. The word - line driving block 104 is not only located between the sense - amplifier block 106 and the peripheral - circuit block 105, but also part of the peripheral - circuit block 105 is located between the first sub - driving block 114 and the second sub - driving block 124.

[0133] In practical applications, the word - line driving block may include a first sub - driving block and a second sub - driving block arranged at intervals along the word - line extension direction. The peripheral - circuit block is not only located between the sense - amplifier block and the word - line driving block, but also part of the peripheral - circuit block is located between the first sub - driving block and the second sub - driving block.

[0134] The following details the arrangement manner of the logic blocks 103 in the second chip 102 facing two adjacent storage arrays 100.

[0135] In some examples, referring to Figure 15 , Figure 15 is a top - view structural schematic diagram of an adjacent situation of two Figure 14 shown logic blocks. The peripheral - circuit blocks 105 corresponding to two adjacent storage arrays along the word - line extension direction X are adjacent and coupled. It should be noted that Figure 15 uses the logic block 103 shown in Figure 14 as an example. In practical applications, Figure 12 andFigure 13 The peripheral circuit blocks 105 corresponding to two adjacent memory arrays along the word line extension direction X as shown can also be adjacent and coupled.

[0136] In some other embodiments, referring to Figure 16 , Figure 16 For another top view structural schematic diagram in which two Figure 14 shown logic blocks are adjacent, two peripheral circuit blocks 105 corresponding to a pair of memory arrays are adjacent and coupled along the bit line extension direction Y. It should be noted that Figure 16 uses the Figure 14 shown logic block 103 as an example. In actual applications, Figure 11 the two peripheral circuit blocks 105 corresponding to a pair of memory arrays as shown can also be adjacent and coupled along the bit line extension direction Y.

[0137] The sense amplifier block 106 will be described in detail below.

[0138] In some embodiments, referring to any one of Figures 12 to 16 , each sense amplifier block 106 may include: a first sense amplifier block 116 and a second sense amplifier block 126 arranged in sequence along the bit line extension direction Y.

[0139] In some cases, the orthographic projection shapes of the first sense amplifier block 116 and the second sense amplifier block 126 on the bonding interface are the same.

[0140] In some embodiments, with reference to Figure 4 , Figure 7 and Figure 16 , in the sense amplifier block 106 corresponding to the memory array F1 in a pair of memory arrays AA, the first extension portions 127 in the memory array F1 are all coupled to one of the first sense amplifier block 116 and the second sense amplifier block 126, and the second extension portions 137 in the memory array F1 are all coupled to the other of the first sense amplifier block 116 and the second sense amplifier block 126. In other words, along the vertical direction Z, the first bit line connection block 267 may include a first block facing the first sense amplifier block 116 and a second block facing the second sense amplifier block 126. The ends of the first extension portions 127 in the memory array F1 all extend to one of the first block and the second block, and the ends of the second extension portions 137 in the memory array F1 all extend to the other of the first block and the second block.

[0141] Similarly, along the vertical direction Z, the second bit line connection section 277 may also include a first section facing the first sense amplification section 116 and a second section facing the second sense amplification section 126. The ends of the first extension section 127 in the storage array G1 all extend into one of the first section and the second section, and the ends of the second extension section 137 in the storage array G1 all extend into the other of the first section and the second section. In this way, all the first extension sections 127 in the storage array G1 are coupled to one of the first sense amplification section 116 and the second sense amplification section 126, and all the second extension sections 137 in the storage array G1 are coupled to the other of the first sense amplification section 116 and the second sense amplification section 126.

[0142] It can be understood that the first sense amplification section 116 and the second sense amplification section 126 in the same logic section 103 are coupled to the bit lines 107 in different storage arrays 100 of a pair of storage arrays AA. Based on this, the bit lines 107 coupled to the same sense amplification section 106 come from different storage arrays 100 of a pair of storage arrays AA, so that all the bit lines 107 in a pair of storage arrays AA can be referenced to each other in the two sense amplification sections 106 corresponding to the pair of storage arrays AA.

[0143] It should be noted that Figure 12 and Figure 13 show the word line driving section 104 in the SWD layout; Figures 14 to 16 show the first sub-driving section 114 in the SWD1 layout and the second sub-driving section 124 in the SWD2 layout; Figures 12 to 16 show the peripheral circuit section 105 in the Peri layout, the first sense amplification section 116 in the SA1 layout, and the second sense amplification section 126 in the SA2 layout.

[0144] In some embodiments, with reference to Figure 12 and Figure 17 , the first chip 101 may further include: a word line connection section 118 facing the word line driving section 104. Figure 17 The word line connection section 118 in Figure 12 is designed based on the word line driving section 104 in Figure 13 . In practical applications, the word line connection section 118 may also face the word line driving section 104 as shown in Figure 14 .

[0145] Among them, Figure 17 is a top view structural schematic diagram of multiple word lines in the storage array provided by the embodiments of the present disclosure.

[0146] In combination with reference Figure 8 and Figure 12 , the sense amplification section 106 and the bit line connection section 157 are bonded to each other; in combination with reference Figure 12 and Figure 17 , the word line driving section 104 and the word line connection section 118 are bonded to each other.

[0147] It can be understood that the sense amplification section 106 and the bit line connection section 157 are bonded to each other, so that the bit lines 107 in the storage array 100 are electrically connected to the sense amplification section 106 at the bit line connection section 157; the word line driving section 104 and the word line connection section 118 are bonded to each other, so that the word lines 108 in the storage array 100 are electrically connected to the word line driving section 104 at the word line connection section 118.

[0148] The word lines 108 and the word line connection section 118 in the first chip 101 are described in detail below.

[0149] In some embodiments, in combination with reference Figures 17 to 20 , the first chip 101 may include: a plurality of word lines 108 arranged at intervals along the bit line extending direction Y, a first wiring 148 electrically connected to the word lines 108 one by one, and a word line connection section 118 whose orthographic projection on the bonding interface w (refer to Figure 6 ) coincides with the orthographic projection of the word line driving section 104 on the bonding interface w; in the direction perpendicular to the bonding interface w, the word lines 108 whose orthographic projections at least partially coincide with the orthographic projection of the word line connection section 118 are the first word lines 128, and the remaining word lines 108 are the second word lines 138, the first wiring 148 corresponding to the first word lines 128 is the first sub-wiring 168, and the first wiring 148 corresponding to the second word lines 138 is the second sub-wiring 178; wherein, the first sub-wiring 168 extends along the word line extending direction X; the second sub-wiring 178 includes a first connection portion 188 and a second connection portion 198 connected in contact, the first connection portion 188 extends along the word line extending direction X, and the second connection portion 198 extends along the bit line extending direction Y; one end of any first wiring 148 is electrically connected to the word line 108, and the other end is located in the word line 108 connection section.

[0150] Wherein, Figure 18 is a top view structural schematic diagram of a first wiring layer in the first chip provided by the embodiment of the present disclosure; Figure 19 is a top view structural schematic diagram of a part of the second sub-wiring and the first bonding pad in the embodiment of the present disclosure; Figure 20 is a top view structural schematic diagram of a part of the first sub-wiring and the first bonding pad in the embodiment of the present disclosure. It should be noted that, Figure 17 different forms of lines are used in

[0151] Among them, with reference to Figures 19 to 20 , the first sub-wiring 168 extends along the word line extending direction X; the second sub-wiring 178 includes a first connection portion 188 and a second connection portion 198 that are in contact connection. The first connection portion 188 extends along the word line extending direction X, and the second connection portion 198 extends along the bit line extending direction Y; one end of any first wiring 148 is electrically connected to the word line 108, and the positive projection of the other end on the reference plane is located in the positive projection of the word line connection section 118 on the reference plane.

[0152] It can be understood that in the vertical direction Z, the first wiring layer 158 can be located between the bit line extension portion 117 and the bit line 107.

[0153] In some embodiments, with reference to Figure 20 , the lengths of adjacent first sub-wirings 168 in the word line extending direction X are different along the bit line extending direction Y, with reference to Figure 19 , the lengths of adjacent first connection portions 188 in the word line extending direction X are different, and the lengths of adjacent second connection portions 198 in the word line extending direction X are different in the bit line extending direction Y.

[0154] In some embodiments, continuing to refer to Figures 19 to 20 , the first chip 101 may further include: a plurality of first bonding pads 119 arranged in an array along the bit line extending direction Y and the word line extending direction X. At least some of the first bonding pads 119 located in the word line connection section 118 are electrically connected to one end of the first wiring 148, and the other end of the first wiring 148 is electrically connected to the word line 108.

[0155] It can be understood that the plurality of first bonding pads 119 are in the same film layer, and this film layer is not only located on the side of the bit line extension portion 117 close to the second chip, but also on the side of the first wiring layer 158 close to the second chip. In addition, the film layer where the plurality of first bonding pads 119 are located has a plurality of first bonding pads 119 in both the area facing the bit line connection section 157 and the area facing the word line connection section 118, that is, some of the first bonding pads 119 are electrically connected to the bit line extension portion 117 to transmit the electrical signal on the bit line 107 in the first chip 101 to the sense amplifier section 106 in the second chip 102, and some of the first bonding pads 119 are electrically connected to the first wiring 148 to transmit the electrical signal on the word line 108 in the first chip 101 to the word line driver section 104 in the second chip 102.

[0156] In some embodiments, in combination with reference to Figure 17 and Figure 18 , the one associated with a memory array 100 (with reference to Figure 3) The corresponding first wiring layer 158 is divided into multiple regions. Among them, along the word line extension direction X, first, the first wiring layer 158 facing the sense amplifier block 106 (refer to Figure 12 ) is successively divided into a D1 part and a D2 part; second, the first wiring layer 158 facing the word line driver block 104 (refer to Figure 12 ) is successively divided into an A1 part, a B1 part, a C1 part, a B2 part, a C2 part, and an A2 part, and the B1 part and the C1 part face each other along the bit line extension direction Y, and the B2 part and the C2 part face each other along the bit line extension direction Y; third, the first wiring layer 158 facing the peripheral circuit block 105 (refer to Figure 12 ) is successively divided into an E1 part and an E2 part.

[0157] It can be understood that Figure 18 the division of the first wiring layer 158 in Figure 12 is based on the sense amplifier block 106, the word line driver block 104, and the peripheral circuit block 105 in the logic block 103 shown in Figure 13 or Figure 14 shown in the logic block 103. In actual applications, the division of the first wiring layer 158 can also be based on Figure 14 the layout of the sense amplifier block 106, the word line driver block 104, and the peripheral circuit block 105 among the three in the logic block 103 shown in

[0158] Refer to Figure 19 , the lengths of the adjacent first connection parts 188 along the bit line extension direction Y are different in the word line extension direction X, and the lengths of the adjacent second connection parts 198 along the word line extension direction X are different in the bit line extension direction Y.

[0159] It should be noted that Figure 19 only shows in Figure 18 the second sub-wiring 178 and the first bonding pad 119 in the local regions of the D1 part and the B1 part, and the second sub-wiring 178 and the first bonding pad 119 in the local regions of the E1 part and the C1 part, and Figure 19The length layout of two parts among multiple second sub-wirings 178 in the word line extension direction X or the bit line extension direction Y is only an example. In actual applications, there can be various different situations for the length layout of two parts among multiple second sub-wirings 178 in the D1 part in the word line extension direction X or the bit line extension direction Y, and there can also be various different situations for the length layout of two parts among multiple second sub-wirings 178 in the E1 part in the word line extension direction X or the bit line extension direction Y. It only needs to satisfy that "the lengths of adjacent first connection parts 188 in the word line extension direction X along the bit line extension direction Y are different, and the lengths of adjacent second connection parts 198 in the bit line extension direction Y along the word line extension direction X are different, so that different second sub-wirings 178 are electrically connected to different first bonding pads 119", and they will not be enumerated one by one here. Moreover, to reflect the positional relationship between the second sub-wiring 178 and the first bonding pad 119, Figure 19 A perspective drawing method is adopted for the rectangle indicating the approximate position where the first bonding pad 119 is located.

[0160] In addition, taking the plane formed by the bit line extension direction Y and the word line extension direction X as the projection plane, Figure 19 The orthographic projection of some second sub-wirings 178 on this projection plane will penetrate the orthographic projections of multiple first bonding pads 119 on this projection plane. However, the second sub-wiring 178 will only be electrically connected to the first bonding pad 119 whose orthographic projection at the end overlaps with it, and one first bonding pad 119 will only be electrically connected to one second sub-wiring 178. Based on this, the purpose that the lengths of two parts among adjacent second sub-wirings 178 are different in both the word line extension direction X and the bit line extension direction Y includes: enabling adjacent second sub-wirings 178 to be electrically connected to different first bonding pads 119.

[0161] In some cases, the arrangement of multiple second sub-wirings 178 located in the D1 part and the D2 part can be axisymmetric along the bit line extension direction Y. In this way, it is beneficial to improve the regularity of the wirings in the word line connection section 118 to reduce the wiring difficulty.

[0162] In some cases, the arrangement of multiple second sub-wirings 178 located in the E1 part and the E2 part can be axisymmetric along the bit line extension direction Y. In this way, it is beneficial to improve the regularity of the wirings in the word line connection section 118 to reduce the wiring difficulty.

[0163] Reference Figure 20 shows that the lengths of adjacent first sub-wirings 168 in the word line extension direction X along the bit line extension direction Y are different.

[0164] It should be noted that Figure 20 only shows Figure 18The first sub-wiring 168 and the first bonding pad 119 in the local area located in the A1 part, and Figure 20 The length layout of the multiple first sub-wirings 168 in the word line extension direction X in the A1 part is only one example. In actual applications, there can be various different situations for the length layout of the multiple first sub-wirings 168 in the A1 part in the word line extension direction X. It only needs to satisfy that "the lengths of adjacent first sub-wirings 168 in the word line extension direction X are different so that different first sub-wirings 168 are electrically connected to different first bonding pads 119", and they will not be enumerated one by one here. Moreover, to reflect the positional relationship between the first sub-wiring 168 and the first bonding pad 119, Figure 20 A perspective drawing method is adopted for the rectangle indicating the approximate position where the first bonding pad 119 is located.

[0165] In addition, taking the plane formed by the bit line extension direction Y and the word line extension direction X as the projection plane, Figure 20 The orthographic projection of some of the first sub-wirings 168 on this projection plane will pass through the orthographic projections of multiple first bonding pads 119 on this projection plane. However, the first sub-wiring 168 will only be electrically connected to the first bonding pad 119 whose end orthographic projection overlaps with it. One first bonding pad 119 will only be electrically connected to one first sub-wiring 168. Based on this, the purpose of the different lengths of adjacent first sub-wirings 168 in the word line extension direction X is to enable adjacent first sub-wirings 168 to be electrically connected to different first bonding pads 119.

[0166] In some cases, the arrangement of the multiple first sub-wirings 168 located in the A1 part and the A2 part can be axisymmetric along the bit line extension direction Y. In this way, it is beneficial to improve the regularity of the wiring in the word line connection section 118 to reduce the wiring difficulty.

[0167] It can be understood that the first wiring 148 and the word line 108 are in one-to-one correspondence, that is, each word line 108 is equipped with a corresponding first wiring 148, and this word line 108 realizes electrical connection with the first bonding pad 119 through the corresponding first wiring 148.

[0168] In some cases, with reference to Figures 17 to 20 , there is a connection post (not shown in the figure) between the first wiring 148 and the word line 108 to realize the electrical connection between the first wiring 148 and the word line 108. In addition, the end of the first wiring 148 that is not electrically connected to the word line 108 can be in contact connection with the first bonding pad 119.

[0169] It should be noted that in the foregoing other embodiments, the word line, the first wiring layer having multiple first wirings, and the first bonding pad may also have the above characteristics, which will not be elaborated here.

[0170] In summary, all bit lines in a pair of memory arrays AA can be referenced to each other. For a memory array located at the edge, having an adjacent memory array along the bit line extension direction Y enables all bit lines in the memory array at the edge to have corresponding reference bit lines, which is conducive to improving the utilization rate of bit lines in the memory array.

[0171] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present disclosure. In actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A first chip and a second chip bonded to each other; The first chip includes a plurality of memory arrays arranged in an array, and each of the memory arrays includes a plurality of bit lines arranged at intervals; The second chip includes sense amplifier blocks corresponding to the memory arrays one by one; Wherein, two adjacent memory arrays in the bit line extending direction are a pair of memory arrays, and two sense amplifier blocks corresponding to the pair of memory arrays are a pair of sense amplifier blocks. In the pair of memory arrays, a part of the bit lines of one and a part of the bit lines of the other are coupled to one of the pair of sense amplifier blocks, and the remaining bit lines of one and the remaining bit lines of the other are coupled to the other of the pair of sense amplifier blocks.

2. The semiconductor structure according to claim 1, wherein The bit lines are coupled to the corresponding sense amplifier blocks through corresponding bit line extension portions, the bit line extension portions are first extension portions or second extension portions, and the extension directions of the bit line extension portions and the bit lines are the same; Wherein, the first extension portion and the corresponding bit line are in the same memory array, the second extension portion and the corresponding bit line are in different memory arrays in the pair of memory arrays, and the first extension portion and the second extension portion extend in different metal layers.

3. The semiconductor structure according to claim 2, wherein The first chip further includes bit line connection blocks corresponding to the memory arrays one by one, one end of the bit line extension portion is located in the bit line connection block, and the other end is electrically connected to the corresponding bit line; Wherein, the two bit line connection blocks corresponding to the pair of memory arrays are a first bit line connection block and a second bit line connection block respectively. A plurality of bit line extension portions with one end located in the first bit line connection block include a plurality of first extension portions and a plurality of second extension portions, and the other end of the first extension portion is electrically connected to the bit line in the memory array corresponding to the first bit line connection block, and the other end of the second extension portion is electrically connected to the bit line in the memory array corresponding to the second bit line connection block.

4. The semiconductor structure according to claim 3, wherein, The bonded first chip and the second chip have a bonding interface, and the orthographic projections of the bit line connection block and the sense amplifier block on the bonding interface coincide; The first chip further includes: a plurality of first bonding pads arranged at intervals in the bit line extending direction and the word line extending direction. Among the first bonding pads located in the bit line connection block, at least some of the first bonding pads are electrically connected to one end of the bit line extension portion; The second chip further includes: a plurality of second bonding pads arranged at intervals in the bit line extending direction and the word line extending direction. The first bonding pads located in the bit line connection block and the second bonding pads located in the sense amplifier block are in contact connection, and the word line extending direction intersects with the bit line extending direction.

5. The semiconductor structure according to claim 3, wherein The two bit line connection blocks corresponding to the pair of memory arrays are adjacent in the bit line extending direction; Alternatively, in the bit line extending direction, the first bit line connection block and the second bit line connection block are located on opposite sides of the pair of memory arrays; Alternatively, the first bit line connection section and the second bit line connection section are on the same side of the corresponding memory array.

6. The semiconductor structure according to claim 2 or 5, wherein The bit line is electrically connected to the corresponding bit line extension portion through a conductive portion and coupled to the sense amplifier section; In the direction of the bit line extension, the memory array has opposite third and fourth sides, and the conductive portion in contact connection with the bit line in the memory array is located in a region of the third side away from the fourth side, or in a region of the fourth side away from the third side.

7. The semiconductor structure according to claim 2, wherein The bit line is electrically connected to the corresponding bit line extension portion through a conductive portion and coupled to the sense amplifier section; In the direction of the bit line extension, the two bit line connection sections corresponding to the pair of memory arrays are adjacent in the direction of the bit line extension, and there is an extraction section between the adjacent bit line connection sections, and the conductive portions in contact connection with the bit lines in the pair of memory arrays are both located in the extraction section.

8. The semiconductor structure according to claim 7, wherein, Further comprising: a first electrical connection portion in contact connection with the first extension portion, and a second electrical connection portion in contact connection with the second extension portion; In a direction perpendicular to the bonding interface, the first electrical connection portion includes a first sub-portion and a second sub-portion stacked.

9. The semiconductor structure according to claim 2 or 7, wherein The first chip and the second chip bonded to each other have a bonding interface, and the orthographic projection of the first extension portion on the bonding interface and the orthographic projection of the second extension portion on the bonding interface at least partially overlap.

10. The semiconductor structure according to claim 2, wherein Two adjacent bit lines in the word line extension direction are a pair of bit lines, one of the pair of bit lines is electrically connected to the first extension portion, the other of the pair of bit lines is electrically connected to the second extension portion, and the word line extension direction intersects the bit line extension direction.

11. The semiconductor structure according to claim 1, wherein The second chip further includes a plurality of logic sections corresponding to the memory array, each logic section includes a sense amplifier section, a word line drive section, and a peripheral circuit section. In the word line extension direction, the size of the sense amplifier section is equal to the size of the logic section, and the word line extension direction intersects the bit line extension direction; Wherein, the word line drive section is located between the sense amplifier section and the peripheral circuit section, or the peripheral circuit section is located between the sense amplifier section and the word line drive section.

12. The semiconductor structure according to claim 11, wherein, The word line drive section includes a first sub-drive section and a second sub-drive section arranged at intervals in the word line extension direction, and a part of the peripheral circuit section is also located between the first sub-drive section and the second sub-drive section.

13. The semiconductor structure according to claim 11 or 12, characterized in that, The peripheral circuit sections corresponding to two adjacent memory arrays in the word line extension direction are adjacent and coupled, and / or the peripheral circuit sections corresponding to the pair of memory arrays are adjacent and coupled in the bit line extension direction.

14. The semiconductor structure according to claim 11, wherein The first chip further includes: a plurality of word lines arranged at intervals in the bit line extension direction, a first wiring electrically connected to the word lines one by one, and a word line connection section whose orthographic projection on the bonding interface coincides with the orthographic projection of the word line drive section on the bonding interface; In a direction perpendicular to the bonding interface, the word line whose orthographic projection at least partially coincides with the orthographic projection of the word line connection section is the first word line, and the remaining word lines are the second word lines. The first wiring corresponding to the first word line is the first sub-wiring, and the first wiring corresponding to the second word line is the second sub-wiring; wherein, the first sub-wiring extends along the extending direction of the word line; the second sub-wiring includes a first connecting portion and a second connecting portion which are in contact connection. The first connecting portion extends along the extending direction of the word line, and the second connecting portion extends along the extending direction of the bit line; one end of any one of the first wirings is electrically connected to the word line, and the other end is located in the word line connection section.

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