Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate and an epitaxial structure located on one side of the substrate. The source electrode structure and the drain electrode structure are located on the side, away from the substrate, of the epitaxial structure; the back electrode is positioned on one side, away from the epitaxial structure, of the substrate; the back electrode is electrically connected with the source electrode structure through via holes in the substrate and the epitaxial structure; a first hollow part penetrating through the back electrode is arranged in the back electrode, and the first hollow part is overlapped with the drain electrode structure along the thickness direction of the semiconductor device. By adopting the technical means, the first hollow part and the drain electrode structure are overlapped along the thickness direction of the semiconductor device, so that the opposite area between the back electrode and the drain electrode structure can be reduced, the parasitic capacitance between the back electrode and the drain electrode structure is further reduced, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Due to characteristics such as a large bandgap width, a high electron saturation drift velocity, a high breakdown field strength, and good thermal conductivity, gallium nitride semiconductor materials have become a current research hotspot.

[0003] For semiconductor devices, in traditional designs, the back metal electrode is usually connected to the source electrode, and the back metal electrode exists on the entire back of the device, forming a parasitic capacitance between the drain ohmic electrode and the drain pad, which affects the performance of the device.

[0004] Therefore, how to improve the performance of semiconductor devices is an urgent problem to be solved currently. Summary of the Invention

[0005] The present invention provides a semiconductor device and a method for manufacturing the same, which can reduce the parasitic capacitance between the back electrode and the drain electrode structure and improve the performance of the semiconductor device.

[0006] In a first aspect, an embodiment of the present invention provides a semiconductor device, including:

[0007] A substrate and an epitaxial structure located on one side of the substrate;

[0008] A source electrode structure and a drain electrode structure, located on the side of the epitaxial structure away from the substrate;

[0009] A back electrode, located on the side of the substrate away from the epitaxial structure; the back electrode is electrically connected to the source electrode structure through a via hole in the substrate and the epitaxial structure; a first hollow portion penetrating the back electrode is provided in the back electrode, and along the thickness direction of the semiconductor device, the first hollow portion overlaps with the drain electrode structure.

[0010] Optionally, along the thickness direction of the semiconductor device, the first hollow portion covers the drain electrode structure.

[0011] Optionally, the drain electrode structure includes a connected drain ohmic electrode and a drain power supply electrode;

[0012] The first hollow portion includes a connected ohmic electrode hollow portion and a power supply electrode hollow portion. Along the thickness direction of the semiconductor device, the ohmic electrode hollow portion overlaps with the drain ohmic electrode, and the power supply electrode hollow portion overlaps with the drain power supply electrode.

[0013] Optionally, the ohmic electrode hollow portion extends to the edge of the semiconductor device, and / or, the power supply electrode hollow portion extends to the edge of the semiconductor device.

[0014] Optionally, along the thickness direction of the semiconductor device, the first hollow portion does not overlap with the via hole.

[0015] Optionally, the back electrode includes a plurality of electrode portions;

[0016] The plurality of electrode portions are connected to each other.

[0017] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, including:

[0018] Providing a substrate and preparing an epitaxial structure on one side of the substrate;

[0019] Preparing a source electrode structure and a drain electrode structure on the side of the epitaxial structure away from the substrate;

[0020] Preparing a via hole in the substrate and the epitaxial structure, the via hole penetrating through the substrate and the epitaxial structure, and the via hole corresponding to the source electrode structure;

[0021] Preparing a back electrode on the side of the substrate away from the epitaxial structure, the back electrode being electrically connected to the source electrode structure through the via hole;

[0022] Patterning the back electrode to form a first hollow portion penetrating through the back electrode in the back electrode, and along the thickness direction of the semiconductor device, the first hollow portion overlaps with the drain electrode structure.

[0023] Optionally, providing a substrate and preparing an epitaxial structure on one side of the substrate includes:

[0024] Providing a master substrate and preparing a master epitaxial structure on one side of the master substrate; the master substrate includes a plurality of the substrates, and the master epitaxial structure includes a plurality of the epitaxial structures;

[0025] Preparing a source electrode structure and a drain electrode structure on the side of the epitaxial structure away from the substrate includes:

[0026] Preparing multiple groups of source electrode structures and multiple groups of drain electrode structures on the side of the master epitaxial structure away from the master substrate, the source electrode structures and the drain electrode structures both corresponding to the epitaxial structure;

[0027] Preparing a via hole in the substrate and the epitaxial structure, the via hole penetrating through the substrate and the epitaxial structure, includes:

[0028] Form vias in the master substrate and the master epitaxial structure, the vias penetrating through the master substrate and the master epitaxial structure;

[0029] Fabricate a back electrode on the side of the substrate away from the epitaxial structure, including:

[0030] Fabricate a master back electrode on the side of the master substrate away from the master epitaxial structure, the master back electrode including a plurality of back electrodes;

[0031] Pattern the back electrode to form a hollow portion penetrating through the back electrode therein, including:

[0032] Provide a mask structure, the mask structure including a first mask pattern and a second mask pattern, the first mask pattern corresponding to the first hollow portion, and the second mask pattern corresponding to the scribe region between two adjacent semiconductor devices;

[0033] Pattern the master back electrode through the mask structure to form the first hollow portion in the region of the master back electrode corresponding to the back electrode, and form a second hollow portion in the region of the master back electrode corresponding to the scribe region;

[0034] After patterning the back electrode to form a hollow portion penetrating through the back electrode therein, further include:

[0035] Cut the master substrate and the master epitaxial structure through the second hollow portion to obtain a plurality of the semiconductor devices.

[0036] Optionally, the drain electrode structure includes a connected drain ohmic electrode and a drain power supply electrode;

[0037] The first hollow portion includes a connected ohmic electrode hollow portion and a power supply electrode hollow portion;

[0038] The power supply electrode hollow portion is integrally provided with a part of the second hollow portion, and / or, the ohmic electrode hollow portion is integrally provided with a part of the second hollow portion.

[0039] Optionally, patterning the back electrode to form a first hollow portion penetrating through the back electrode therein includes:

[0040] Pattern the back electrode to form a first hollow portion penetrating through the back electrode therein and a plurality of electrode portions covering the substrate, the plurality of electrode portions being interconnected.

[0041] In the technical solution of the embodiment of the present invention, a first hollowed-out portion penetrating the back electrode is provided in the back electrode. That is to say, the back electrode is not a continuous metal electrode layer, but there is a first hollowed-out portion. Along the thickness direction of the semiconductor device, the first hollowed-out portion overlaps with the drain electrode structure. That is, along the thickness direction of the semiconductor device, the facing area between the back electrode and the drain electrode structure is small. In this way, the parasitic capacitance between the back electrode and the drain electrode structure can be reduced, and the performance of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a top view schematic diagram of a semiconductor device provided according to an embodiment of the present invention;

[0043] Figure 2 is Figure 1 a schematic cross-sectional structure diagram of a semiconductor device provided along the section line A-A';

[0044] Figure 3 is Figure 1 a schematic cross-sectional structure diagram of a semiconductor device provided along the section line B-B';

[0045] Figure 4 is a top view schematic diagram of another semiconductor device provided according to an embodiment of the present invention;

[0046] Figure 5 is a top view schematic diagram of yet another semiconductor device provided according to an embodiment of the present invention;

[0047] Figure 6 is a flowchart of a method for manufacturing a semiconductor device provided according to an embodiment of the present invention;

[0048] Figure 7 is Figure 6 a process flowchart of a method for manufacturing a corresponding semiconductor device;

[0049] Figure 8 is a flowchart of another method for manufacturing a semiconductor device provided according to an embodiment of the present invention;

[0050] Figure 9 is a top view schematic diagram of a mask structure provided according to an embodiment of the present invention;

[0051] Figure 10 is a flowchart of yet another method for manufacturing a semiconductor device provided according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0053] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the term "comprising" and any of its variants are intended to cover non-exclusive inclusion.

[0054] Figure 1 A top view schematic diagram of a semiconductor device provided by an embodiment of the present invention, Figure 2 is Figure 1 a schematic cross-sectional structure diagram of a semiconductor device along the section line A-A', as Figure 1 and Figure 2 shown. The semiconductor device includes: a substrate 10 and an epitaxial structure 20 located on one side of the substrate 10; a source electrode structure 30 and a drain electrode structure 40, located on the side of the epitaxial structure 20 away from the substrate 10; a back electrode 50, located on the side of the substrate 10 away from the epitaxial structure 20; the back electrode 50 is electrically connected to the source electrode structure 30 through a via 201 located in the substrate 10 and the epitaxial structure 20; a first hollow portion 501 penetrating through the back electrode 50 is provided in the back electrode 50, and along the thickness direction of the semiconductor device (such as Figure 2 the Z direction shown in

[0055] Specifically, continuing to refer to Figure 1 , the semiconductor device may include an active region aa and a passive region bb. The active region aa can be understood as a region where a two-dimensional electron gas, electrons or holes exist below it. Its working state and characteristics are affected by an external circuit, and it is the active working region of the semiconductor device. The passive region bb participates in the operation of the semiconductor device, but its working state is not affected by the external circuit. For example, a lead-out structure of the electrode in the active region aa can be provided in the passive region bb, and the passive region bb can be arranged around the active region aa. Specifically, the active electrode structure 30 can be at least located in the active region aa, and the drain electrode structure 40 can include a structure located in the active region aa and a structure located in the passive region bb.

[0056] Exemplarily, the substrate 10 can be formed of one of the materials such as silicon, sapphire, silicon carbide, and gallium arsenide. The epitaxial structure 20 located on one side of the substrate 10 can be formed of one or more of the group III-V nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride.

[0057] Exemplarily, continuing to refer to Figure 2 , the epitaxial structure 20 can include a nucleation layer 202, a buffer layer 203, a channel layer 204, and a barrier layer 205; the channel layer 204 and the barrier layer 205 can form a heterojunction structure.

[0058] Exemplarily, continuing to refer to Figure 2 , the material of the nucleation layer 202 can be aluminum nitride, which is located between the substrate 10 and the buffer layer 203 and serves to bond the semiconductor material layers to be grown next.

[0059] Exemplarily, continuing to refer to Figure 2 , the buffer layer 203 is located on one side of the substrate 10. The material of the buffer layer 203 can be gallium nitride, and the buffer layer 203 can include iron atoms, which is beneficial to achieving the high-resistance performance of the buffer layer 203, ensuring that vertical leakage can be blocked and the pinch-off performance of the semiconductor device can be improved.

[0060] Exemplarily, continuing to refer to Figure 2 , the channel layer 204 can be a group III nitride, such as Al x Ga 1－x N, where 0 ≤ x < 1, that is, at the interface between the channel layer 204 and the barrier layer 205, namely, the energy of the conduction band edge of the channel layer 204 is less than the energy of the conduction band edge of the barrier layer 205. Exemplarily, x = 0 indicates that the channel layer 204 is GaN. The channel layer 204 can also be other group III nitrides, such as InGaN or AlInGaN. The channel layer 204 can be undoped or unintentionally doped. The channel layer 204 can also be a multi-layer structure, such as a combination of superlattice, GaN, or AlGaN.

[0061] Exemplarily, continuing to refer to Figure 2 , the barrier layer 205 can be AlN, AlInN, AlGaN, or AlInGaN. The barrier layer 205 has a sufficient thickness and a sufficiently high Al component to form a significant carrier concentration at the interface between the channel layer 204 and the barrier layer 205.

[0062] Exemplarily, continuing to refer to Figure 2, the channel layer 204 may include GaN, while the barrier layer 205 may include AlGaN, that is, the material of the barrier layer 205 has a higher bandgap than the material of the channel layer 204, and the channel layer 204 may also have a greater electron affinity than the barrier layer 205. Due to the bandgap difference between the barrier layer 205 and the channel layer 204 and the piezoelectric effect at the interface between the barrier layer 205 and the channel layer 204, a two-dimensional electron gas (2DEG) is formed in the channel layer 204 and the barrier layer 205.

[0063] It can be understood that the epitaxial structure 20 may further include a cap layer, and the cap layer is located on the surface of the barrier layer 205 away from the substrate 10. The cap layer can reduce surface states, reduce surface leakage of subsequent semiconductor devices, and suppress current collapse, thereby improving the performance and reliability of the epitaxial structure 20 and the semiconductor device.

[0064] Specifically, both the source electrode structure 30 and the drain electrode structure 40 can form an ohmic contact with the epitaxial structure 20. Exemplarily, the source electrode structure 30 can be used as the input end of the semiconductor device, and the drain electrode structure 40 can be used as the output end of the semiconductor device. It should be noted that the semiconductor device may further include a gate electrode structure 60, and the gate electrode structure 60 can be used as the control end of the semiconductor device. The current flow between the source electrode structure 30 and the drain electrode structure 40 can be achieved by controlling the voltage of the gate electrode structure 60. That is, when a certain voltage is applied to the gate electrode structure 60, a current will be generated between the source electrode structure 30 and the drain electrode structure 40, and the current between the source electrode structure 30 and the drain electrode structure 40 can be controlled by changing the voltage of the gate electrode structure 60. It can be understood that Figure 1 it is described by taking the semiconductor device including multiple gate electrode structures 60 as an example, that is, the semiconductor device is a multi-cell structure. It can be understood that the semiconductor device may also include only one gate electrode structure 60, that is, the cell structure is a single-cell structure of the source electrode structure 30, the gate electrode structure 60, and the drain electrode structure 40.

[0065] Specifically, the source electrode structure 30 can be connected to the back electrode 50 of the semiconductor device through the via 201. Exemplarily, the via 201 can penetrate through the substrate 10 and the epitaxial structure 20, that is, it is connected to the source electrode structure 30 through the back electrode 50 located on the side of the substrate 10 away from the epitaxial structure 20. That is to say, the back electrode 50 is electrically connected to the source electrode structure 30 through the via 201.

[0066] Exemplarily, the back electrode 50 can adopt a metal conductive material such as gold, and the embodiment of the present invention does not specifically limit the material of the back electrode 50.

[0067] Specifically, continue to refer to Figure 2 , a first hollow portion 501 penetrating the back electrode 50 is provided in the back electrode 50. That is to say, the back electrode 50 is not a continuous whole layer of metal electrode, but there is a first hollow portion 501. And along the thickness direction Z of the semiconductor device, the first hollow portion 501 overlaps with the drain electrode structure 40. That is, along the thickness direction Z of the semiconductor device, at least part of the position corresponding to the drain electrode structure 40 may not have the back electrode 50, but the first hollow portion 501 after patterning the back electrode 50. In this way, the facing area between the back electrode 50 and the drain electrode structure 40 can be reduced, and thus the parasitic capacitance between the back electrode 50 and the drain electrode structure 40 can be reduced, improving the performance of the semiconductor device.

[0068] For a gallium nitride radio frequency power amplifier, by reducing the parasitic capacitance between the back electrode 50 and the drain electrode structure 40, the device efficiency and gain can be improved. For a gallium nitride power electronic device, by reducing the parasitic capacitance between the back electrode 50 and the drain electrode structure 40, the device switching speed can be improved.

[0069] In the semiconductor device of the embodiment of the present invention, a first hollow portion penetrating the back electrode is provided in the back electrode. That is to say, the back electrode is not a continuous whole layer of metal electrode, but there is a first hollow portion. Along the thickness direction of the semiconductor device, the first hollow portion overlaps with the drain electrode structure. That is, along the thickness direction of the semiconductor device, the facing area between the back electrode and the drain electrode structure is small. In this way, the parasitic capacitance between the back electrode and the drain electrode structure can be reduced, improving the performance of the semiconductor device.

[0070] Optionally, continue to refer to Figure 2 , along the thickness direction Z of the semiconductor device, the first hollow portion 501 covers the drain electrode structure 40. In other words, along the thickness direction Z of the semiconductor device, the position of the first hollow portion 501 can completely correspond to the drain electrode structure 40. In this way, it can be ensured that the position directly below the side of the substrate 10 away from the epitaxial structure 20 and corresponding to the drain electrode structure 40 is completely the first hollow portion 501. In other words, along the direction parallel to the plane where the substrate 10 is located, the size of the first hollow portion 501 can be greater than or equal to the size of the drain electrode structure 40. In this way, the first hollow portion 501 can completely cover the drain electrode structure 40, and thus the parasitic capacitance between the back electrode 50 and the drain electrode structure 40 can be further reduced, further improving the performance of the semiconductor device.

[0071] Optionally, Figure 3 is Figure 1 a schematic cross-sectional structure diagram of a semiconductor device along the section line B-B', continue to refer to Figure 1 and Figure 3, the drain electrode structure 40 includes a connected drain ohmic electrode 401 and a drain power supply electrode 402; the first hollow portion 501 includes a connected ohmic electrode hollow portion 5011 and a power supply electrode hollow portion 5012. Along the thickness direction Z of the semiconductor device, the ohmic electrode hollow portion 5011 overlaps with the drain ohmic electrode 401, and the power supply electrode hollow portion 5012 overlaps with the drain power supply electrode 402.

[0072] Specifically, the drain power supply electrode 402 can be understood as a drain pad. The drain ohmic electrode 401 in the active region aa can be connected to the drain power supply electrode 402 located in the passive region bb. The drain ohmic electrode 401 can receive a voltage signal through the drain power supply electrode 402 to ensure the normal operation of the semiconductor device.

[0073] The first hollow portion 501 includes a connected ohmic electrode hollow portion 5011 and a power supply electrode hollow portion 5012. Along the thickness direction Z of the semiconductor device, the ohmic electrode hollow portion 5011 overlaps with the drain ohmic electrode 401, and the power supply electrode hollow portion 5012 overlaps with the drain power supply electrode 402. That is, along the thickness direction Z of the semiconductor device, corresponding to the drain ohmic electrode 401 and located on the side of the substrate 10 away from the epitaxial structure 20 is the ohmic electrode hollow portion 5011. In addition, corresponding to the drain power supply electrode 402 and located on the side of the substrate 10 away from the epitaxial structure 20 is the power supply electrode hollow portion 5012. In this way, the facing area between the drain ohmic electrode 401 and the drain power supply electrode 402 and the back electrode 50 can be reduced, and thus the parasitic capacitance between the back electrode 50 and the drain electrode structure 40 can be reduced, improving the performance of the semiconductor device.

[0074] Furthermore, along the thickness direction Z of the semiconductor device, the ohmic electrode hollow portion 5011 covers the drain ohmic electrode 401, and the power supply electrode hollow portion 5012 covers the drain power supply electrode 402. In this way, the parasitic capacitance can be further reduced, improving the performance of the semiconductor device.

[0075] Exemplarily, the semiconductor device may further include a gate power supply electrode 601, that is, a gate pad. The gate electrode structure 60 in the active region aa can be connected to the gate power supply electrode 601 in the passive region bb. The gate electrode structure 60 can receive a gate voltage signal through the gate power supply electrode 601 to ensure the normal operation of the semiconductor device.

[0076] Optionally, Figure 4 is a top view schematic diagram of another semiconductor device provided by an embodiment of the present invention. Figure 5 is a top view schematic diagram of yet another semiconductor device provided by an embodiment of the present invention. Continue to refer to Figure 1 、 Figure 4 and Figure 5, the ohmic electrode cutout 5011 extends to the edge of the semiconductor device, and / or, the power supply electrode cutout 5012 extends to the edge of the semiconductor device.

[0077] It should be noted that the four peripheral edge positions of the semiconductor device are scribe regions, and the entire device can be cut in the scribe regions to be divided into multiple independent semiconductor devices.

[0078] As a feasible implementation manner, continue to refer to Figure 4 , Figure 4 Only the technical solution of the single cell structure of the semiconductor device with the cell structure being the source electrode structure 30, the gate electrode structure 60, and the drain electrode structure 40 is shown. The ohmic electrode cutout 5011 extends to the edge of the semiconductor device. That is to say, the ohmic electrode cutout 5011 can extend from the position on the side close to the edge of the gate electrode structure 60 all the way to the edge of the semiconductor device. In this way, the ohmic electrode cutout 5011 can extend to the scribe region. Since the scribe region is also set as a cutout, therefore, the cutout corresponding to the ohmic electrode cutout 5011 in the scribe region is connected to form a larger cutout structure, thereby reducing the alignment difficulty in the patterning process of the back electrode 50.

[0079] It can be understood that, continue to refer to Figure 1 , when the semiconductor device is a multi-cell structure, there is at least one drain ohmic electrode 401 located at the edge position of the semiconductor device. At this time, the ohmic electrode cutout 5011 can extend from the position on the side close to the edge of the gate electrode structure 60 all the way to the edge of the semiconductor device. In this way, the ohmic electrode cutout 5011 can extend to the scribe region on at least one side of the semiconductor device and is connected to the scribe region, thereby reducing the alignment difficulty in the patterning process of the back electrode 50.

[0080] As another feasible implementation manner, continue to refer to Figure 5 , the power supply electrode cutout 5012 extends to the edge of the semiconductor device. The power supply electrode cutout 5012 can extend from the position on the side close to the edge of the gate electrode structure 60 all the way to the edge of the semiconductor device. In this way, the power supply electrode cutout 5012 can extend to the scribe region. Since the scribe region is also set as a cutout, therefore, the cutout corresponding to the power supply electrode cutout 5012 in the scribe region is connected to form a larger cutout structure, thereby reducing the alignment difficulty in the patterning process of the back electrode 50.

[0081] It can be understood that, Figure 5 Only the single cell structure is taken as an example for illustration. It can be understood that whether the semiconductor device is a multi-cell structure or a single cell structure, the power supply electrode cutout 5012 can be extended to the edge of the semiconductor device to communicate with the cutout in the scribe region.

[0082] As another feasible implementation manner, continue to refer to Figure 1 , the ohmic electrode via hole portion 5011 extends to the edge of the semiconductor device and the power supply electrode via hole portion 5012 extends to the edge of the semiconductor device. Whether the semiconductor device is a multi-cell structure or a single-cell structure, the ohmic electrode via hole portion 5011 can extend from a position on the side close to the edge of the gate electrode structure 60 to the edge of the semiconductor device, and the power supply electrode via hole portion 5012 can extend from a position on the side close to the edge of the gate electrode structure 60 to the edge of the semiconductor device. In this way, both the ohmic electrode via hole portion 5011 and the power supply electrode via hole portion 5012 can extend to the scribe regions on both sides of the semiconductor device, thereby further reducing the alignment difficulty during the patterning process of the back electrode 50.

[0083] Optionally, continue to refer to Figure 1 and Figure 2 , along the thickness direction Z of the semiconductor device, the first via hole portion 501 does not overlap with the via 201.

[0084] Specifically, along the thickness direction Z of the semiconductor device, the first via hole portion 501 does not overlap with the via 201, so as to ensure the stability of the connection between the back electrode 50 and the source electrode structure 30, and further ensure the stability and reliability of the semiconductor device. The back electrode 50 is electrically connected to the source electrode structure 30 through the via 201 in the epitaxial structure 20 via the substrate 10, and the metal material in the via 201 can be the same as the metal material used for the back electrode 50.

[0085] Optionally, continue to refer to Figure 1 , the back electrode 50 includes a plurality of electrode portions 502; the plurality of electrode portions 502 are connected to each other.

[0086] Specifically, the electrode portion 502 can be understood as the position where the back electrode 50 is not etched, that is, the metal region in the back electrode 50. When the semiconductor device is a multi-cell structure, the plurality of electrode portions 502 are connected to each other, rather than resulting in a plurality of isolated island-like structures for the plurality of electrode portions 502 due to the existence of the first via hole portion 501 in the back electrode 50, thereby causing signal transmission to fail. The connection of the plurality of electrode portions 502 is beneficial to ensuring the stability of signal transmission between the back electrode 50 and the source electrode structure 30.

[0087] It should be understood that from the perspective of semiconductor device design in the embodiments of the present invention, by overlapping the first hollow portion with the drain electrode structure along the thickness direction of the semiconductor device, the parasitic capacitance between the back metal and the drain electrode structure can be reduced, thereby improving the performance of the semiconductor device. The semiconductor devices include but are not limited to: high-power high electron mobility transistors (HEMTs) operating in high-voltage and high-current environments, transistors with a silicon-on-insulator (SOI) structure, gallium arsenide (GaAs)-based transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), metal-insulator-semiconductor heterojunction field-effect transistors (MISHFETs), or other field-effect transistors. The first hollow portion penetrating the back electrode provided in the semiconductor device in the embodiments of the present invention can be widely used in the manufacturing fields of semiconductor devices such as radio frequency microwave and power electronics. In particular, it has more obvious advantages for gallium nitride electronic devices with a wide bandgap, high electron mobility, high breakdown field strength, and good thermal conductivity, and can better meet the high-performance requirements of rapidly developing fields such as electronic communication.

[0088] Based on the same inventive concept, an embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 6 FIG. is a schematic flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 7 is Figure 6 A corresponding process flowchart of a method for manufacturing a semiconductor device, as Figure 6 and Figure 7 shown, the method for manufacturing the semiconductor device includes:

[0089] S101. Provide a substrate and fabricate an epitaxial structure on one side of the substrate.

[0090] Specifically, referring back to Figure 7 step a therein, the substrate 10 can be formed of one of the materials such as silicon, sapphire, silicon carbide, and gallium arsenide. The epitaxial structure located on one side of the substrate 10 can be formed of one or more of the group III-V nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride.

[0091] S102. Fabricate a source electrode structure and a drain electrode structure on the side of the epitaxial structure away from the substrate.

[0092] Specifically, referring back to Figure 7 step b therein, both the source electrode structure 30 and the drain electrode structure 40 can form an ohmic contact with the epitaxial structure 20. Exemplarily, the source electrode structure 30 can serve as the input end of the semiconductor device, and the drain electrode structure 40 can serve as the output end of the semiconductor device. It should be noted that the semiconductor device may further include a gate electrode structure 60, and the gate electrode structure 60 can serve as the control end of the semiconductor device. The current flow between the source electrode structure 30 and the drain electrode structure 40 can be achieved by controlling the voltage of the gate electrode structure 60. That is, when a certain voltage is applied to the gate electrode structure 60, a current will be generated between the source electrode structure 30 and the drain electrode structure 40, and the current between the source electrode structure 30 and the drain electrode structure 40 can be controlled by changing the voltage of the gate electrode structure 60.

[0093] S103. Fabricate a via hole in the substrate and the epitaxial structure. The via hole penetrates through the substrate and the epitaxial structure and corresponds to the source electrode structure.

[0094] Specifically, referring back to Figure 7 step c therein, a via hole 201 is fabricated in the substrate 10 and the epitaxial structure 20. The via hole 201 can penetrate through the substrate 10 and the epitaxial structure 20 and corresponds to the source electrode structure 30, so that the back electrode 50 is electrically connected to the source electrode structure 30 through the via hole 201.

[0095] S104. Fabricate a back electrode on the side of the substrate away from the epitaxial structure. The back electrode is electrically connected to the source electrode structure through the via hole.

[0096] Specifically, referring back to Figure 7 step d therein, a back electrode 50 is fabricated on the side of the substrate 10 away from the epitaxial structure 20. That is to say, the back electrode 50 is located on the lower surface of the substrate 10, and the back electrode 50 is electrically connected to the source electrode structure 30 through the via hole 201. The metal material in the via hole 201 can be the same as the metal material used for the back electrode 50.

[0097] S105. Pattern the back electrode to form a first hollow portion penetrating the back electrode, and along the thickness direction of the semiconductor device, the first hollow portion overlaps with the drain electrode structure.

[0098] Specifically, referring back to Figure 7 Step e in, an etching process can be used to pattern the back electrode 50 to form a first hollow portion 501 penetrating the back electrode 50. That is to say, the back electrode 50 is not a continuous whole layer of metal electrode, but there is a first hollow portion 501, and along the thickness direction of the semiconductor device, the first hollow portion 501 overlaps with the drain electrode structure 40. That is, along the thickness direction of the semiconductor device, at the position corresponding to the drain electrode structure 40, there may be no back electrode 50, but the first hollow portion 501 after patterning the back electrode 50. In this way, the facing area between the back electrode 50 and the drain electrode structure 40 can be reduced, and thus the parasitic capacitance between the back electrode 50 and the drain electrode structure 40 can be reduced, improving the performance of the semiconductor device.

[0099] In the manufacturing method of the semiconductor device provided in this embodiment of the present invention, by patterning the back electrode to form a first hollow portion penetrating the back electrode, along the thickness direction of the semiconductor device, the first hollow portion overlaps with the drain electrode structure, that is, along the thickness direction of the semiconductor device, the facing area between the back electrode and the drain electrode structure is small, so that the parasitic capacitance between the back electrode and the drain electrode structure can be reduced, improving the performance of the semiconductor device.

[0100] Optionally, Figure 8 is a schematic flow chart of another manufacturing method of the semiconductor device provided in the embodiment of the present invention. Figure 8 On the basis of the above embodiment, the operation of providing a substrate and preparing an epitaxial structure on one side of the substrate is elaborated in detail, as Figure 8 shown, the manufacturing method of the semiconductor device includes:

[0101] S201. Provide a master substrate and prepare a master epitaxial structure on one side of the master substrate; the master substrate includes a plurality of substrates, and the master epitaxial structure includes a plurality of epitaxial structures.

[0102] Specifically, the master substrate can be understood as the whole substrate before dicing, and the master epitaxial structure can be understood as the whole epitaxial structure before dicing. The master substrate can be obtained by dicing to get a plurality of substrates, and the master epitaxial structure can be obtained by dicing to get epitaxial structures.

[0103] S202. Prepare a plurality of groups of source electrode structures and a plurality of groups of drain electrode structures on the side of the master epitaxial structure away from the master substrate, and both the source electrode structures and the drain electrode structures correspond to the epitaxial structure.

[0104] Specifically, since the master epitaxial structure includes multiple epitaxial structures, a plurality of source electrode structures and drain electrode structures are fabricated on the side of the master epitaxial structure away from the master substrate. Each epitaxial structure can correspond to one source electrode structure and one drain electrode structure, thus forming a semiconductor device with a single-cell structure, or each epitaxial structure can correspond to multiple source electrode structures and multiple drain electrode structures, thus forming a semiconductor device with a multi-cell structure.

[0105] S203. Fabricate vias in the master substrate and the master epitaxial structure. The vias penetrate through the master substrate and the master epitaxial structure and correspond to the source electrode structures.

[0106] Specifically, vias are fabricated in the master substrate and the master epitaxial structure. The vias can penetrate through the master substrate and the master epitaxial structure and correspond to the source electrode structures, so that the back electrode is electrically connected to the source electrode structures through the vias.

[0107] S204. Fabricate a master back electrode on the side of the master substrate away from the master epitaxial structure. The master back electrode includes multiple back electrodes, and the back electrodes are electrically connected to the source electrode structures through the vias.

[0108] Specifically, a master back electrode is fabricated on the side of the master substrate away from the master epitaxial structure. That is to say, the master back electrode is located on the lower surface of the substrate, and the master back electrode is electrically connected to the source electrode structures through the vias. In the process of fabricating the master back electrode, the master back electrode material fills the vias, that is, the metal material in the vias can be the same as the metal material used for the master back electrode.

[0109] S205. Provide a mask structure. The mask structure includes a first mask pattern and a second mask pattern. The first mask pattern corresponds to the first hollow portion, and the second mask pattern corresponds to the scribe region between two adjacent semiconductor devices.

[0110] Figure 9 The top view schematic diagram of a mask structure provided by an embodiment of the present invention is shown in Figure 9 As shown, specifically, the mask structure can be understood as a mask plate. The mask structure includes a first mask pattern 100 corresponding to the first hollow portion and a second mask pattern 200 corresponding to the scribe region between two adjacent semiconductor devices, so as to realize the patterning of the master back electrode.

[0111] It can be understood that Figure 9Only an exemplary technical solution in which the first mask pattern 100 is discontinuous with the second mask pattern 200 is shown. The first hollow portion formed by the first mask pattern 100 forms an approximate interdigital structure. When the power supply electrode hollow portion and a part of the second hollow portion are integrally provided, and / or when the ohmic electrode hollow portion and a part of the second hollow portion are integrally provided, the first mask pattern 100 can also be integrally provided with the second mask pattern 200.

[0112] S206. Pattern the back electrode of the master by the mask structure to form a first hollow portion in the region corresponding to the back electrode in the back electrode of the master, and form a second hollow portion in the region corresponding to the scribe region of the master. Along the thickness direction of the semiconductor device, the first hollow portion overlaps with the drain electrode structure.

[0113] Specifically, the first mask pattern in the mask structure is used to pattern the back electrode of the master to form the first hollow portion, so as to reduce the facing area between the back electrode and the drain electrode structure, thereby reducing the parasitic capacitance between the two and improving the performance of the semiconductor device. The second mask pattern in the mask structure is used to pattern the scribe region between two adjacent semiconductor devices to form the second hollow portion, so as to cut the master substrate and the master epitaxial structure in the scribe region.

[0114] Further, continue to refer to Figure 1 、 Figure 4 and Figure 5 , the drain electrode structure 40 includes a connected drain ohmic electrode 401 and a drain power supply electrode 402; the first hollow portion 501 includes a connected ohmic electrode hollow portion 5011 and a power supply electrode hollow portion 5012; the power supply electrode hollow portion 5012 is integrally provided with a part of the second hollow portion, and / or the ohmic electrode hollow portion 5011 is integrally provided with a part of the second hollow portion.

[0115] As a feasible implementation manner, continue to refer to Figure 5 , the power supply electrode hollow portion 5012 is integrally provided with a part of the second hollow portion. In this way, the power supply electrode hollow portion 5012 is communicated with the second hollow portion, that is, a larger hollow structure can be formed, and thus the alignment difficulty in the patterning process of the back electrode of the master can be reduced. As another feasible implementation manner, continue to refer to Figure 4 , the ohmic electrode hollow portion 5011 is integrally provided with a part of the second hollow portion 5012. In this way, the ohmic electrode hollow portion 5011 is communicated with the second hollow portion, that is, a larger hollow structure can be formed, and thus the alignment difficulty in the patterning process of the back electrode of the master can be reduced. As yet another feasible implementation manner, continue to refer to Figure 1, the power supply electrode hollow part 5012 is integrally provided with part of the second hollow part, and the ohmic electrode hollow part 5011 is integrally provided with part of the second hollow part. In this way, the power supply electrode hollow part 5012, the ohmic electrode hollow part 5011, and the second hollow part can form an integral hollow structure, which is beneficial to further reducing the alignment difficulty during the patterning of the back electrode of the master substrate, and is also beneficial to cutting the master substrate and the master substrate epitaxial structure.

[0116] S207. Cut the master substrate and the master substrate epitaxial structure through the second hollow part to obtain a plurality of semiconductor devices.

[0117] Specifically, processes such as laser cutting and grinding wheel blade cutting can be used to cut the master substrate and the master substrate epitaxial structure, and then a plurality of independent semiconductor devices can be obtained. The cutting technology for electronic devices in the embodiments of the present invention is not specifically limited.

[0118] The method for preparing a semiconductor device provided by the embodiment of the present invention includes providing a master substrate, and sequentially preparing a master substrate epitaxial structure, a source electrode structure, a drain electrode structure, a via, and a master substrate back electrode on one side of the master substrate, and then through patterning and cutting the master substrate back electrode, a plurality of independent semiconductor devices can be obtained. In addition, using one mask structure can achieve that the mask pattern corresponds to the first hollow part and the scribe area respectively, that is, the number of mask structures used is not increased. And the power supply electrode hollow part is integrally provided with part of the second hollow part, and / or the ohmic electrode hollow part is integrally provided with part of the second hollow part, so that the patterning difficulty and alignment difficulty of the master substrate back electrode can be reduced.

[0119] Optionally, Figure 10 is a schematic flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 10 Based on the above embodiment, the operation of patterning the back electrode to form a first hollow part penetrating the back electrode is elaborated in detail, as Figure 10 shown, the method for preparing a semiconductor device includes:

[0120] S301. Provide a substrate and prepare an epitaxial structure on one side of the substrate.

[0121] S302. Prepare a source electrode structure and a drain electrode structure on the side of the epitaxial structure away from the substrate.

[0122] S303. Prepare a via in the substrate and the epitaxial structure, the via penetrates the substrate and the epitaxial structure, and the via corresponds to the source electrode structure.

[0123] S304. Prepare a back electrode on the side of the substrate away from the epitaxial structure, and the back electrode is electrically connected to the source electrode structure through the via.

[0124] S305, pattern the back electrode to form a first hollow portion penetrating the back electrode and a plurality of electrode portions covering the substrate in the back electrode. The plurality of electrode portions are interconnected. Along the thickness direction of the semiconductor device, the first hollow portion overlaps with the drain electrode structure.

[0125] Specifically, continue to refer to Figure 2 , along the thickness direction Z of the semiconductor device, the first hollow portion 501 penetrates the back electrode 50, the electrode portion 502 covers the substrate 10, and the plurality of electrode portions 502 are interconnected. When the semiconductor device is a multi-cell structure, the plurality of electrode portions 502 are interconnected, rather than resulting in the plurality of electrode portions 502 being a plurality of isolated island structures due to the existence of the first hollow portion 501 in the back electrode 50, which in turn causes signal transmission failure. The interconnection of the plurality of electrode portions 502 is beneficial to ensuring the stability of signal transmission between the back electrode 50 and the source electrode structure 30.

[0126] In the manufacturing method of the semiconductor device provided by the embodiment of the present invention, by patterning the back electrode to form a first hollow portion penetrating the back electrode and a plurality of electrode portions covering the substrate, and the plurality of electrode portions are interconnected, which is beneficial to ensuring the stability of signal transmission between the back electrode and the source electrode structure.

[0127] Note that the above is only the preferred embodiment of the present invention and the applied technical principle. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments only. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate and an epitaxial structure located on one side of the substrate; A source electrode structure and a drain electrode structure, located on the side of the epitaxial structure away from the substrate; A back electrode, located on the side of the substrate away from the epitaxial structure; The back electrode is electrically connected to the source electrode structure through a via hole in the substrate and the epitaxial structure; a first hollow portion penetrating the back electrode is provided in the back electrode, and along the thickness direction of the semiconductor device, the first hollow portion overlaps with the drain electrode structure.

2. The semiconductor device according to claim 1, wherein Along the thickness direction of the semiconductor device, the first hollow portion covers the drain electrode structure.

3. The semiconductor device according to claim 1, characterized in that, The drain electrode structure includes a connected drain ohmic electrode and a drain power supply electrode; The first hollow portion includes a connected ohmic electrode hollow portion and a power supply electrode hollow portion. Along the thickness direction of the semiconductor device, the ohmic electrode hollow portion overlaps with the drain ohmic electrode, and the power supply electrode hollow portion overlaps with the drain power supply electrode.

4. The semiconductor device according to claim 3, wherein The ohmic electrode hollow portion extends to the edge of the semiconductor device, and / or, the power supply electrode hollow portion extends to the edge of the semiconductor device.

5. The semiconductor device according to claim 1, characterized in that, Along the thickness direction of the semiconductor device, the first hollow portion does not overlap with the via hole.

6. The semiconductor device according to claim 5, characterized in that, The back electrode includes a plurality of electrode portions; The plurality of electrode portions are connected to each other.

7. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a substrate and preparing an epitaxial structure on one side of the substrate; Preparing a source electrode structure and a drain electrode structure on the side of the epitaxial structure away from the substrate; Preparing a via hole in the substrate and the epitaxial structure, the via hole penetrating the substrate and the epitaxial structure, and the via hole corresponding to the source electrode structure; Preparing a back electrode on the side of the substrate away from the epitaxial structure, the back electrode being electrically connected to the source electrode structure through the via hole; Patterning the back electrode to form a first hollow portion penetrating the back electrode therein, and along the thickness direction of the semiconductor device, the first hollow portion overlaps with the drain electrode structure.

8. The preparation method according to claim 7, characterized in that, Providing a substrate and preparing an epitaxial structure on one side of the substrate, including: Providing a master substrate and preparing a master epitaxial structure on one side of the master substrate; the master substrate includes a plurality of the substrates, and the master epitaxial structure includes a plurality of the epitaxial structures; Preparing a source electrode structure and a drain electrode structure on the side of the epitaxial structure away from the substrate, including: Preparing multiple groups of source electrode structures and multiple groups of drain electrode structures on the side of the master epitaxial structure away from the master substrate, the source electrode structure and the drain electrode structure both corresponding to the epitaxial structure; Preparing a via hole in the substrate and the epitaxial structure, the via hole penetrating the substrate and the epitaxial structure, including: Preparing a via hole in the master substrate and the master epitaxial structure, the via hole penetrating the master substrate and the master epitaxial structure; Preparing a back electrode on the side of the substrate away from the epitaxial structure, including: Preparing a master back electrode on the side of the master substrate away from the master epitaxial structure, the master back electrode including a plurality of back electrodes; Patterning the back electrode to form a hollow portion penetrating the back electrode, including: Providing a mask structure, the mask structure including a first mask pattern and a second mask pattern, the first mask pattern corresponding to the first hollow portion, and the second mask pattern corresponding to a scribe region between two adjacent semiconductor devices; Patterning the master back electrode through the mask structure to form the first hollow portion in the region of the master back electrode corresponding to the back electrode, and forming a second hollow portion in the region of the master back electrode corresponding to the scribe region; After patterning the back electrode to form a hollow portion penetrating the back electrode, it further includes: Cutting the master substrate and the master epitaxial structure through the second hollow portion to obtain a plurality of the semiconductor devices.

9. The preparation method according to claim 8, wherein, The drain electrode structure includes a connected drain ohmic electrode and a drain power supply electrode; The first hollow portion includes a connected ohmic electrode hollow portion and a power supply electrode hollow portion; The power supply electrode hollow portion is integrally provided with a part of the second hollow portion, and / or, the ohmic electrode hollow portion is integrally provided with a part of the second hollow portion.

10. The preparation method according to claim 7, wherein Patterning the back electrode to form a first hollow portion penetrating the back electrode, including: Patterning the back electrode to form a first hollow portion penetrating the back electrode and a plurality of electrode portions covering the substrate, and the plurality of electrode portions are connected to each other.

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