Preparation method of metal SIN layer-semiconductor structure low-loss source-drain GaN power device

Abstract

The invention provides a preparation method of a metal SIN layer-semiconductor structure low-loss source-drain GaN power device, and belongs to the technical field of electronic elements, and the method comprises the steps: growing a high-purity GaN layer on a gallium nitride substrate through molecular beam epitaxy to control the point location density; depositing an SIN dielectric layer through radio frequency magnetron sputtering; depositing a metal gate electrode by electron beam evaporation and ensuring accurate alignment; defining source and drain regions through photoetching and plasma etching; forming a high-concentration doped region by adopting ion implantation; performing thermal annealing treatment according to the calculation result of the thermodynamic parameter equation set; determining the optimal annealing parameter of the ohmic contact by using a traveling salesman problem optimization algorithm; depositing a Ti / Al / Ni / Au multilayer metal source drain electrode; and carrying out a device packaging test, and analyzing and optimizing process parameters based on the loss matrix. According to the method, through accurate process control and multi-physical field coupling optimization, the problem of high loss of the source and drain regions of the GaN power device is effectively solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic components, and specifically relates to a method for fabricating a low-loss source-drain GaN power device with a metal SIN layer-semiconductor structure. Background Art

[0002] Gallium nitride (GaN) power devices have great potential in high-frequency and high-power electronic applications due to their excellent characteristics such as wide bandgap, high breakdown electric field, and high electron mobility. Traditional GaN power devices use a metal-semiconductor (MS) structure as the source-drain contact, or use ion implantation to form a highly doped region to reduce the contact resistance. These methods are widely used in high-voltage and high-frequency application scenarios such as new energy vehicles, smart grids, and data center power management systems.

[0003] However, traditional fabrication methods have defects such as large losses in the source-drain region and low thermal management efficiency. Especially under high-frequency switching operating conditions, the parasitic capacitance effect caused by the contact resistance and interface defects leads to significant power losses, which not only reduces the device efficiency but also accelerates the device aging process. At the same time, the difficulties in precisely controlling the gate position and optimizing the heat treatment parameters in traditional processes make it difficult to ensure the consistency of device performance in mass production.

[0004] Existing technologies are difficult to simultaneously solve the problems of forming a low-loss contact in the source-drain region of GaN power devices and controlling interface defects. Especially in high-current and high-frequency switching application scenarios, how to effectively reduce the power loss in the source-drain region has become a key technical challenge restricting the performance improvement of GaN power devices. Summary of the Invention

[0005] In view of this, the present invention provides a method for fabricating a low-loss source-drain GaN power device with a metal SIN layer-semiconductor structure, which can solve the technical problem of high losses in the source-drain region of GaN power devices in the existing technology.

[0006] The present invention is implemented as follows: The method for fabricating a low-loss source-drain GaN power device with a metal SIN layer-semiconductor structure provided by the present invention includes: growing a high-purity gallium nitride layer on a gallium nitride substrate; depositing a SIN layer on the high-purity gallium nitride layer; depositing a metal gate electrode on the SIN layer; defining the source-drain region and removing the SIN layer in the source-drain region; forming a high-concentration doping region in the source-drain region; performing a thermal annealing treatment to activate the doping ions and repair the lattice defects; forming an ohmic contact in the source-drain region; depositing multiple layers of metal as the source-drain electrodes; performing device packaging and testing, measuring the switching loss using the gate pulse testing method, and performing parameter optimization and adjustment according to the analysis results of the loss matrix; realizing the low-loss characteristics of the source-drain region by controlling the point density, precisely aligning the geometric center and the lateral representative center, optimizing the calculation of the thermodynamic parameter equations, and using the traveling salesman problem optimization algorithm to determine the annealing parameters.

[0007] Among them, growing a high-purity gallium nitride layer on a gallium nitride substrate is to grow a high-purity gallium nitride layer with a thickness of 20 nm by molecular beam epitaxy, control the site density to be below 10 16 cm -3 and measure the site density value for subsequent step calculations.

[0008] Among them, depositing a SIN layer on the high-purity gallium nitride layer is to deposit a SIN layer with a thickness of 5 nm on the high-purity gallium nitride layer by radio frequency magnetron sputtering, adjust the radio frequency power to 200 W and the sputtering pressure to 0.5 Pa to form a high-quality dielectric layer, and measure the interface energy of the SIN layer for the calculation of the thermodynamic parameter equations.

[0009] Among them, depositing a metal gate electrode on the SIN layer is to deposit a metal gate electrode with a thickness of 100 nm on the SIN layer by electron beam evaporation technology, ensure that the deviation between the geometric center and the lateral representative center is less than 50 nm, and record the deviation value for the calculation of the loss matrix.

[0010] Among them, defining the source-drain region and removing the SIN layer in the source-drain region is to define the source-drain region by photolithography process, use inductively coupled plasma etching to remove the SIN layer in the source-drain region, control the etching depth to be 5 ± 0.2 nm, and measure the actual thickness of the interface after etching for the calculation of the interface reaction equation.

[0011] Among them, forming a high-concentration doping region in the source-drain region is to form a high-concentration doping region in the source-drain region by ion implantation technology, the implantation dose is 5 × 10 15 cm -2 , and ensure a uniform doping distribution by positioning through the longitudinal representative center, and record the doping ion concentration for the calculation of the carrier activation equation.

[0012] Among them, performing thermal annealing treatment is based on the calculation results of the thermodynamic parameter equations, performing thermal annealing treatment in a nitrogen atmosphere at 750 °C, controlling the time to be 120 seconds, activating the doping ions and repairing the lattice defects, and measuring and recording the residual stress distribution and the effective carrier concentration after thermal annealing.

[0013] Among them, forming an ohmic contact in the source-drain region is to form an ohmic contact in the source-drain region by rapid thermal annealing technology, the annealing temperature is 850 °C, use the traveling salesman problem optimization algorithm to determine the optimal path between multiple annealing parameter nodes, determine the best annealing time to be 30 seconds by calculating the shortest temperature-time curve, and record the best annealing time for subsequent processes.

[0014] Among them, depositing multiple layers of metal as source and drain electrodes is based on the optimal annealing time parameter. Electron beam evaporation is used to deposit Ti / Al / Ni / Au multiple layers of metal as source and drain electrodes, with the thickness of each layer being 20 / 100 / 40 / 50 nm respectively. The resistivity of the source and drain electrodes is measured for loss matrix calculation.

[0015] Among them, the thermodynamic parameter equations include defect recovery equation, stress release equation, carrier activation equation, interface reaction equation, and heat conduction equation, which are used to calculate defect repair rate, stress release process, doping ion activation efficiency, interface reaction kinetics, and heat distribution and transfer.

[0016] Compared with the prior art, the present invention provides a method for fabricating a low-loss source and drain GaN power device with a metal-SIN layer-semiconductor structure. The present invention proposes a method for fabricating a low-loss source and drain GaN power device based on a metal-SIN layer-semiconductor (MIS) structure. By precisely controlling the growth of the high-purity GaN layer, optimizing the deposition of the SIN dielectric layer, precisely aligning the gate position, optimizing the ion implantation and heat treatment processes in the source and drain regions, etc., low-loss contact in the source and drain regions is achieved.

[0017] This method realizes precise control of heat treatment parameters through calculation based on the thermodynamic parameter equations and the traveling salesman problem optimization algorithm, effectively activates doping ions and repairs lattice defects, and simultaneously forms high-quality ohmic contacts. In addition, by precisely controlling the alignment of the geometric center and the lateral representative center, the source and drain resistance and parasitic capacitance of the device are significantly reduced, and the interface characteristics are improved.

[0018] The present invention successfully solves the technical problem of high loss in the source and drain regions of GaN power devices, realizes high-efficiency and low-loss GaN power devices, is particularly suitable for high-frequency and high-power electronic application scenarios, overcomes the limitations such as large loss in the source and drain regions, low thermal management efficiency, and poor performance consistency in traditional technologies, and provides an innovative solution for the performance improvement and industrial application of GaN power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a flowchart of the method of the present invention.

[0020] Figure 2 It is a schematic diagram of the GaN structure in Example 2. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0022] Such as Figure 1As shown in the figure, it is a flowchart of a method for fabricating a low-loss source-drain GaN power device with a metal SIN layer-semiconductor structure provided by the present invention. This method includes the following steps:

[0023] S01. Grow a 20-nm-thick high-purity gallium nitride layer on a gallium nitride substrate by molecular beam epitaxy, control the dislocation density below 10 16 cm -3 or less, and measure the dislocation density value for subsequent step calculations;

[0024] S02. Deposit a 5-nm-thick SIN layer on the high-purity gallium nitride layer by radio frequency magnetron sputtering, adjust the radio frequency power to 200 W and the sputtering pressure to 0.5 Pa to form a high-quality dielectric layer, and measure the interface energy of the SIN layer for calculating the thermodynamic parameter equations;

[0025] S03. Deposit a 100-nm-thick metal gate electrode on the SIN layer by electron beam evaporation, ensure that the deviation between the geometric center and the lateral representative center is less than 50 nm, and record the deviation value for calculating the loss matrix;

[0026] S04. Define the source-drain regions through photolithography, use inductively coupled plasma etching to remove the SIN layer in the source-drain regions, control the etching depth at 5 ± 0.2 nm, and measure the actual thickness of the etched interface for calculating the interface reaction equation;

[0027] S05. Form a high-concentration doping region in the source-drain regions by ion implantation technology, with an implantation dose of 5 × 10 15 cm -2 , ensure a uniform doping distribution by positioning through the longitudinal representative center, and record the doping ion concentration for calculating the carrier activation equation;

[0028] S06. According to the calculation results of the thermodynamic parameter equations, perform a thermal annealing treatment in a nitrogen atmosphere at 750 °C for 120 seconds, activate the doping ions and repair the lattice defects, and measure and record the residual stress distribution and the effective carrier concentration after the thermal annealing;

[0029] S07. Use rapid thermal annealing technology to form an ohmic contact in the source-drain regions, with an annealing temperature of 850 °C, use the traveling salesman problem optimization algorithm to determine the optimal path between multiple annealing parameter nodes, determine the optimal annealing time as 30 seconds by calculating the shortest temperature-time curve, and record the optimal annealing time for subsequent processes;

[0030] S08. According to the optimal annealing time parameter, use electron beam evaporation to deposit Ti / Al / Ni / Au multi-layer metal as the source and drain electrodes, with the thickness of each layer being 20 / 100 / 40 / 50 nm respectively, and measure the resistivity of the source and drain electrodes for loss matrix calculation;

[0031] S09. Conduct device packaging and testing, use the gate pulse testing method to measure the switching loss, and perform parameter optimization and adjustment according to the analysis results of the loss matrix, and output the final device fabrication process parameters.

[0032] Among them, the point position refers to the defect position in the gallium nitride material, including dislocations, vacancies and impurity atoms. Controlling the point position density is the key factor to reduce the device leakage current and improve the breakdown voltage.

[0033] Among them, the geometric center refers to the actual center position of the device physical structure, which has an important impact on the uniformity of the device electrical characteristics.

[0034] Among them, the lateral representative center refers to the center of the electric field distribution in the plane direction of the device. Precise alignment with the gate position can reduce the source and drain resistance.

[0035] Among them, the longitudinal representative center refers to the center of the charge distribution in the vertical direction of the device, which has a decisive effect on the threshold voltage stability of the device.

[0036] Among them, the loss matrix refers to a multi-dimensional data structure that describes the power loss of the device under different working conditions, including on-state loss, switching loss and thermal loss parameters, and is used for device performance optimization and parameter adjustment.

[0037] Among them, the traveling salesman problem optimization algorithm refers to an algorithm that determines the optimal combination of temperature, time and atmosphere by finding the shortest path connecting all annealing parameter nodes, and is used to optimize the annealing process parameters.

[0038] The thermodynamic parameter equations include a defect recovery equation, a stress release equation, a carrier activation equation, an interface reaction equation, and a heat conduction equation;

[0039] The defect recovery equation is used to calculate the relationship between the lattice defect repair rate and temperature and time. The inputs include the initial defect density, annealing temperature, defect type coefficient, lattice constant, and material activation energy, and the output is the residual defect density after a given time;

[0040] The stress release equation is used to simulate the dynamic process of stress release during the heat treatment process. The inputs include the initial stress distribution, temperature gradient, material Young's modulus, Poisson's ratio, and thermal expansion coefficient, and the output is the residual stress distribution after annealing;

[0041] The carrier activation equation is used to predict the activation efficiency of doped ions. The inputs include the doped ion concentration, annealing temperature, annealing time, ion species, and lattice position, and the output is the effective carrier concentration;

[0042] The interface reaction equation is used to describe the interface reaction kinetics between the SIN layer and the GaN layer. The inputs include the interface atomic diffusion coefficient, interface energy, reaction activation energy, temperature, and reaction time, and the output is the interface layer thickness and composition;

[0043] The heat conduction equation is used to calculate the heat distribution and transfer in the sample. The inputs include the material thermal conductivity, specific heat capacity, density, heating power, and boundary conditions, and the output is the temperature distribution of each point in the sample changing with time.

[0044] The following describes the specific implementation manners of the above steps in detail.

[0045] The specific implementation manner of step S01 is to grow a high-purity gallium nitride layer on a gallium nitride substrate by molecular beam epitaxy technology. First, place the gallium nitride substrate in an ultra-high vacuum chamber, and control the vacuum degree below 10 -9 Pa; then set the substrate temperature to 700 °C, form a molecular beam current by simultaneously supplying high-purity nitrogen and gallium source, and control the gallium / nitrogen ratio to 1.05 to ensure a two-dimensional layer growth mode; then use in-situ reflection high-energy electron diffraction to monitor the growth process to ensure that the root mean square roughness of the surface flatness is less than 0.5 nm; subsequently, deposit a 20-nm high-purity gallium nitride layer under the condition of a stable growth rate of 0.2 μm / h; finally, test the point density by deep level transient spectroscopy, and use Auger electron spectroscopy analysis technology to confirm that the impurity concentration is controlled below 10 16 cm -3 The control of the point density in this step is crucial for the subsequent device performance. Too high a point density will lead to an increase in leakage current and a decrease in breakdown voltage. The ideal threshold should be below 10 16 cm -3 , and the preferred range is 10 15 ~10 16 cm -3 .

[0046] The specific implementation manner of step S02 is to deposit a SIN dielectric layer by radio frequency magnetron sputtering technology. First, place the sample in the sputtering chamber, evacuate to a base pressure below 5×10 -4Pa; Then, a mixed gas of high-purity nitrogen and argon is introduced, and the flow ratio of nitrogen to argon is controlled at 3:1, with the total pressure stabilized at 0.5 Pa. Then, a high-purity (purity > 99.999%) Si target is used, the radio frequency power is set at 200 W, and sputtering is carried out at a substrate temperature of 300 °C. Subsequently, a SIN layer with a thickness of 5 nm is precisely deposited at a deposition rate of 15 nm / min. Finally, an ellipsometer is used to monitor the film thickness in real time, and X-ray photoelectron spectroscopy is used to analyze and determine the interface energy. The quality of the SIN dielectric layer formed in this step has a decisive impact on the device threshold voltage and gate leakage current, and the interface state density should be controlled within 10 11 cm -2 eV -1 Hereinafter, the interface roughness should be less than 0.3 nm.

[0047] The specific implementation of step S03 is to deposit a metal gate electrode using electron beam evaporation technology. First, the sample is placed in an electron beam evaporation device and evacuated to below 10 -5 Pa. Then, a laser alignment system is used to determine the gate area position, and the geometric center of the gate area is aligned with the center of the predetermined electric field distribution, with the deviation controlled within 50 nm. Then, the electron beam power is set at 3 kW, and a multi-point scanning technology is adopted to ensure the uniformity of the thermal distribution. Subsequently, a Ni / Au double-layer metal structure is deposited in sequence, with a total thickness of 100 nm, and the deposition rate is controlled at 0.2 nm / s. Finally, a high-precision scanning electron microscope is used to measure the deviation value between the geometric center of the gate and the lateral representative center, and this value is used for loss matrix calculation. The gate position accuracy in this step has an important impact on the switching characteristics of the device. The smaller the deviation value, the lower the device loss, and the ideal deviation threshold should be less than 30 nm.

[0048] The specific implementation of step S04 is to define and form the source and drain regions using photolithography and plasma etching technologies. First, a photoresist is spin-coated on the sample surface, with the thickness controlled at 1.5 μm, and soft baked at 90 °C for 60 seconds. Then, a mask aligner exposure machine is used for exposure, with the alignment accuracy better than 0.3 μm and the exposure dose of 120 mJ / cm 2 ; Then, after development, hard baking (120 °C, 90 seconds) is carried out to enhance the plasma resistance of the photoresist. Subsequently, an inductively coupled plasma device is used for SIN etching, using a CF4 / O2 mixed gas (ratio of 10:1), with the radio frequency power set at 100 W and the pressure at 1.3 Pa. The etching time is precisely controlled at 5 seconds according to the pre-calibrated etching rate (about 1 nm / s). Finally, an atomic force microscope is used to measure the etching depth to ensure that the requirement of 5 ± 0.2 nm is met, and the actual interface thickness is also determined. The precise control of the etching depth in this step is crucial for forming a low-resistance ohmic contact. Over-etching will damage the GaN layer, and under-etching will lead to an increase in the contact resistance. The ideal etching depth threshold should be controlled within the range of 5 ± 0.2 nm.

[0049] The specific implementation of step S05 is to form highly doped source and drain regions by ion implantation technology. First, the sample is mounted on the sample stage of the ion implanter, and the tilt angle is set to 7° to reduce the channeling effect; then Si ions are selected as the doping source, the acceleration energy is set to 80 keV, and the implantation dose is controlled to be 5×10 -15 cm -2 ; then the Monte Carlo ion transport simulation program is used to calculate the ion distribution depth to ensure that the peak position of the implanted ions coincides with the longitudinal representative center; subsequently, the lattice damage is reduced by multiple low-dose (1×10 -15 cm -2 / time) implantation methods; finally, the secondary ion mass spectrometer is used to measure the doping ion concentration distribution, and the record is used for the calculation of the carrier activation equation. The highly doped region formed in this step is the basis for realizing the low-resistance source and drain structure, and the doping concentration threshold should be controlled above 5×10 18 cm -3 , and the preferred range is 5×10 18 ~1×10 20 cm -3 .

[0050] The specific implementation of step S06 is to perform thermal annealing treatment to activate the doping ions and repair the lattice defects. First, according to the calculation results of the thermodynamic parameter equations, the optimal annealing temperature is determined to be 750 °C; then the sample is placed in the annealing furnace and heated to the target temperature at a heating rate of 10 °C / s; then high-purity nitrogen (purity > 99.999%) is introduced, the flow rate is 200 sccm, the pressure is 101 kPa, and the temperature is kept constant for 120 seconds; subsequently, it is cooled to room temperature at a rate of 5 °C / s; finally, the Raman spectroscopy is used to measure the residual stress distribution, and the effective carrier concentration is measured by the Hall effect. This step realizes the activation of doping ions and the repair of lattice defects through thermal annealing. The carrier activation rate threshold should reach above 80%, and the residual stress should be controlled below 300 MPa.

[0051] The specific implementation of step S07 is to form ohmic contacts in the source and drain regions using rapid thermal annealing technology. First, according to the traveling salesman problem optimization algorithm, multiple annealing parameter nodes are set, including temperature (800 °C, 825 °C, 850 °C, 875 °C, 900 °C), time (10 s, 20 s, 30 s, 40 s, 50 s), and atmosphere conditions (nitrogen, argon, nitrogen-argon mixture); then the nearest neighbor insertion heuristic algorithm is used to construct an initial path, and the path is optimized by the 2-opt local search algorithm; then the annealing simulation algorithm is used to avoid local optimal solutions, with the initial temperature set to 100 and the cooling coefficient to 0.95; subsequently, the "distance" between each node is calculated (a weighted function based on the temperature change rate, time consumption, and gas switching cost); finally, 850 °C, 30 s, and nitrogen atmosphere are determined as the optimal combination. This step realizes the formation of low-resistance ohmic contacts by optimizing the annealing parameters, and the contact resistivity threshold should be less than 1×10 -5 Ω·cm 2 , preferably in the range of 1×10 -6 ~5×10 -6 Ω·cm 2 .

[0052] The specific implementation of step S08 is to deposit multi-layer metal source and drain electrodes by electron beam evaporation. First, the sample is placed in an electron beam evaporation device, and the chamber vacuum is pumped to below 5×10 -5 Pa; then four layers of metals, Ti / Al / Ni / Au, are deposited in sequence, with thicknesses of 20 / 100 / 40 / 50 nm respectively; then the evaporation rate is controlled for each metal, 0.1 nm / s for Ti, 0.5 nm / s for Al, 0.2 nm / s for Ni, and 0.3 nm / s for Au; then alloying treatment is carried out according to the optimal annealing time parameters (850 °C, 30 s) determined in step S07; finally, the resistivity of the source and drain electrodes is measured by the four-probe method and recorded for loss matrix calculation. The multi-layer metal structure formed in this step has the following functions: the Ti layer provides good adhesion to GaN, the Al layer provides the main conduction channel, the Ni layer prevents the upward diffusion of Al, the Au layer prevents oxidation and provides good conductivity, and the total resistivity threshold after electrode alloying should be less than 3×10 -6 Ω·cm.

[0053] The specific implementation of step S09 is to perform device packaging testing and parameter optimization. First, the device die is connected to the test substrate using gold wire bonding technology, and the diameter of the bonding wire is 25 μm. Then, a gate pulse test circuit is designed with a gate voltage ranging from -5V to +10V, a rise / fall time of 10 ns, and a pulse width of 1 μs. Next, the switching losses are measured under different drain voltages (100V, 200V, 300V, 400V, 600V) and different current conditions (1A, 5A, 10A, 20A). Subsequently, a loss matrix is constructed, including conduction loss (R on ×I 2 ), switching loss (E on +E off ) and thermal loss (R th ×P total ). Finally, based on the analysis results of the loss matrix, the parameter points in the manufacturing process are optimized and adjusted using the gradient descent method to determine the final device manufacturing process parameters. This step realizes the performance optimization of the device through comprehensive testing and loss analysis. The specific on-resistance threshold of the optimized device should be less than 5 mΩ·cm 2 , and the switching loss threshold should be less than 10 μJ / A.

[0054] The following details the mathematical models or calculation processes involved in the present invention.

[0055] The thermodynamic parameter equations consist of five main equations, namely the defect recovery equation, the stress release equation, the carrier activation equation, the interface reaction equation, and the heat conduction equation. These equations together constitute a complete simulation system for the heat treatment process.

[0056] The defect recovery equation is specifically expressed as follows:

[0057] N d (t) = N d0 exp(-k0exp(-E a / k B T)t);

[0058] In the formula, N d (t) is the residual defect density at time t, with the unit of cm -3 ; N d0 is the initial defect density, that is, the point density value measured in step S01, with the unit of cm -3 ; k0 is the frequency factor, related to the defect type, ranging from 10 12 to 10 14 s -1 ; E a is the defect recovery activation energy, and the typical value for dislocation defects is 2.0 - 3.5 eV; k B is the Boltzmann constant, with a value of 8.617×10- 5 eV / K; T is the annealing temperature in K; t is the annealing time in s.

[0059] The defect recovery equation is established based on the principle of first-order reaction kinetics, considering the exponential decay characteristics of defect recovery during the thermal activation process. This equation introduces frequency factor and activation energy parameters to adapt to the recovery kinetics of different types of defects. In this way, the change of defect density in GaN materials under different annealing conditions can be accurately predicted, providing key parameters for subsequent steps.

[0060] The stress release equation is specifically expressed as follows:

[0061] σ(r, t) = σ0(r)exp(-αt n ) + σ r (1 - exp(-β(T - T0) m ));

[0062] In the formula, σ(r, t) is the stress value at position r and time t in Pa; σ0(r) is the initial stress distribution function obtained by Raman shift measurement in Pa; α is the stress release coefficient related to the material, and the typical value for GaN is 0.001 - 0.01 s -n ; t is the annealing time in s; n is the stress release exponent with a range of 0.3 - 0.7; σ r is the residual stress caused by thermal expansion mismatch with a typical value of 100 - 500 MPa; β is the temperature-related coefficient with a typical value of 0.01 - 0.05 K -m ; T is the annealing temperature in K; T0 is the reference temperature, usually room temperature, taken as 293 K; m is the temperature-dependent exponent with a range of 1.2 - 1.8.

[0063] The stress release equation comprehensively considers two competing processes: time-dependent stress relaxation and temperature-dependent thermal stress formation. The exponential form reflects the non-linear characteristics of stress release, and the power term considers the variation law of stress release rate in different temperature ranges. This equation accurately describes the stress distribution in different regions of the device by introducing the position parameter r, providing theoretical guidance for the preparation of low-stress devices.

[0064] The carrier activation equation is specifically expressed as follows:

[0065]

[0066] In the formula, N a (T, t) is the effective carrier concentration after annealing time t at temperature T in cm -3 ; N i is the doping ion concentration, that is, the value recorded in step S05, in cm-3 ; η i is the theoretical maximum activation efficiency, which is related to the type of doping ions. The typical value of Si ions in GaN is 0.8 - 0.95; C i is the activation reaction rate constant, ranging from 10 -3 to 10 -1 s -1 ; t is the annealing time, in s; T is the annealing temperature, in K; T r is the reference temperature, taken as 1000K; p i is the temperature-dependent exponent, ranging from 1.5 to 2.5; E i is the ion activation energy. The typical value of Si ions in GaN is 2.5 - 3.0 eV; k B is the Boltzmann constant, with a value of 8.617×10 -5 eV / K.

[0067] The carrier activation equation is established based on the kinetic characteristics of ion activation during the thermal activation process, and the exponential saturation function is used to describe the time evolution of the activation process. The temperature-dependent term adopts a composite form of exponential and power functions, accurately simulating the variation law of the activation rate at different temperatures. The key of this equation lies in introducing parameters related to the ion type to achieve accurate prediction of the carrier activation behavior under different doping conditions, providing a basis for optimizing the electrical characteristics of the device.

[0068] The interface reaction equation is specifically expressed as follows:

[0069]

[0070] In the formula, δ(t, T) is the thickness of the interface layer after annealing time t at temperature T, in nm; δ0 is the initial interface layer thickness, that is, the actual thickness of the etched interface measured in step S04, in nm; A is the diffusion coefficient, with a typical value of 0.5 - 2.0; D is the atomic diffusion constant, with a typical value of 10 -15 to 10 -13 cm 2 / s; t is the annealing time, in s; E d is the diffusion activation energy. The typical value at the SIN / GaN interface is 1.8 - 2.3 eV; k B is the Boltzmann constant, with a value of 8.617×10 -5 eV / K; T is the annealing temperature, in K; B is the interface reaction coefficient, with a typical value of 10 -3 to 10 -2 nm / (J / m 2 ·s); γ int is the interface energy, that is, the interface energy of the SIN layer measured in step S02, in J / m 2 , with a typical value of 0.5 - 2.0 J / m2 ; E r is the activation energy of the interface reaction, and the typical value is 2.0 - 2.5 eV.

[0071] The interface reaction equation comprehensively considers two competing processes: the thickening of the interface layer caused by atomic diffusion and the interface reconstruction driven by the interface energy. The diffusion term adopts the square root form of the classical Fick's law, reflecting the characteristics of the diffusion control process; the interface reconstruction term is proportional to the interface energy, reflecting the tendency of the system to reduce the total energy. By introducing the annealing temperature and time parameters, this equation can accurately describe the evolution of the SIN / GaN interface during the heat treatment process, providing a theoretical basis for obtaining a stable interface structure.

[0072] The heat conduction equation is specifically expressed as follows:

[0073]

[0074] where ρ is the material density, and the value of GaN is 6.15 g / cm 3 ; c p is the specific heat capacity, and the value of GaN at high temperature is 0.49 - 0.52 J / (g·K); T(x, y, z, t) is the temperature at time t at the spatial position (x, y, z), with the unit of K; k is the thermal conductivity, and the value of GaN is 130 - 230 W / (m·K), which varies with temperature; is the gradient operator, Q(x, y, z, t) is the internal heat source distribution function, with the unit of W / m 3 .

[0075] The heat conduction equation is established based on the principle of energy conservation. The left side represents the rate of change of thermal energy per unit volume with time, the first term on the right side represents the heat flow caused by heat conduction, and the second term represents the contribution of the internal heat source. This equation is in the form of a partial differential equation and can accurately describe the temperature field distribution in three-dimensional space and its time evolution, providing a theoretical basis for controlling the temperature uniformity during the annealing process.

[0076] The loss matrix is a multi-dimensional data structure that describes the power losses of a device under different operating conditions and can be expressed as:

[0077]

[0078] where L ij represents the value of the jth type of loss (conduction loss, switching loss, or thermal loss) under the ith operating condition (such as a specific voltage and current combination), with the unit of W; m is the number of operating conditions; n is the number of loss types, usually 3 (conduction, switching, thermal losses).

[0079] The conduction loss is specifically expressed as:

[0080]

[0081] In the formula, L con，i is the conduction loss under the i-th working condition, with the unit of W; R on，i is the conduction resistance under the corresponding condition, calculated from the source-drain electrode resistivity measured in step S08, with the unit of Ω; I i is the corresponding conduction current, with the unit of A.

[0082] The switching loss is specifically expressed as:

[0083] L sw，i = f i ·(E on，i + E off，i );

[0084] In the formula, L sw，i is the switching loss under the i-th working condition, with the unit of W; f i is the switching frequency, with the unit of Hz; E on，i is the turn-on energy, with the unit of J; E off，i is the turn-off energy, with the unit of J. Among them, the turn-on / turn-off energy is obtained through the gate pulse test in step S09:

[0085]

[0086] In the formula, v ds (t) is the drain-source voltage, with the unit of V; i d (t) is the drain current, with the unit of A; t on1 to t on2 is the turn-on time period; t off1 to t off2 is the turn-off time period.

[0087] The thermal loss is specifically expressed as:

[0088] L th，i = R th，i ·(L con，i + L sw，i );

[0089] In the formula, L th，i is the thermal loss under the i-th working condition, with the unit of W; R th，i is the thermal resistance coefficient, and the typical value is 0.01 - 0.05.

[0090] The loss matrix organizes various loss data under different working conditions through a multi-dimensional data structure, providing a comprehensive evaluation basis for device performance optimization. The conduction loss reflects the joule heat loss characteristic using a square relationship; the switching loss accurately captures the energy consumption during the transient process through time integration; the thermal loss considers the conversion process of power loss to temperature rise. This structured representation method facilitates the application of numerical optimization algorithms for parameter adjustment.

[0091] The optimization algorithm for the traveling salesman problem is used for annealing parameter optimization, and its objective function is:

[0092]

[0093] where P = (p1, p2,..., p k ) is the sequence of parameter nodes; k is the total number of nodes; d(p i , p j ) is the "distance" between nodes p i and p j , defined as:

[0094] d(p i , p j ) = w T |T i - T j | + w t |t i - t j | + w g δ(g i , g j );

[0095] where T i and T j are the temperatures of nodes i and j, in °C; t i and t j are the times of nodes i and j, in s; g i and g j are the atmosphere conditions of nodes i and j; w T is the temperature weight coefficient, with typical values of 0.01 - 0.05 °C -1 ; w t is the time weight coefficient, with typical values of 0.1 - 0.5 s -1 ; w g is the atmosphere switching cost coefficient, with typical values of 5 - 20; δ(g i , g j ) is the atmosphere switching indicator function, which takes 1 when g i ≠ g j , and 0 otherwise.

[0096] The optimization algorithm for the traveling salesman problem regards the combination of annealing parameters as nodes in a multi-dimensional space, and finds the optimal path in the parameter space by minimizing the "path length". The distance function adopts a weighted form, considering the costs of temperature change, time change, and atmosphere switching respectively. This method can effectively balance the influence of each parameter on the annealing quality and provide an efficient parameter search strategy for device performance optimization.

[0097] The 2-opt local search algorithm used in the optimization algorithm is specifically expressed as:

[0098] P′ = 2-opt(P, i, j) = (p1, p2,..., p i , p j , P j-1 ,..., p i+1 , p j+1 ,..., p k );

[0099] In the formula, P = (p1, p2,..., p k ) is the current parameter node sequence; P′ is the new sequence after performing the 2-opt operation; i and j are two selected positions, satisfying 1 ≤ i < j ≤ k.

[0100] The acceptance probability calculation of the annealing simulation algorithm during the optimization process is:

[0101]

[0102] In the formula, f(P) is the objective function value of the current solution; f(P′) is the objective function value of the new solution; T sim is the "temperature" parameter of the simulated annealing algorithm, with an initial value set to 100, and it decreases according to T sim = 0.95·T sim during the iteration process.

[0103] These two algorithms together constitute the core of the annealing parameter optimization. The 2-opt local search realizes the efficient exploration of the parameter space by reversing part of the path; the annealing simulation algorithm avoids falling into local optimal solutions through the probability acceptance mechanism. The acceptance probability function in exponential form reflects the Boltzmann distribution characteristics of the system energy change, enabling the algorithm to have strong random search ability in the initial stage and gradually turning to deterministic optimization as the "temperature" decreases, so as to efficiently find the global optimal solution in the complex parameter space.

[0104] Optionally, the gradient descent method is used for the loss matrix analysis and parameter optimization in step S09, and its iterative update formula can be expressed as:

[0105]

[0106] In the formula, θ i$\theta^{(i)}$ is the process parameter vector for the $i$-th iteration, containing the key parameters in each preparation step; $\theta$ i+1 is the updated parameter vector; $\eta$ is the learning rate, and typical values are from 0.01 to 0.1; $\nabla J(\theta)$ is the gradient of the objective function $J$ at $\theta$ i and is calculated as:

[0107]

[0108] where $n$ is the total number of parameters; the objective function $J$ is defined as the weighted sum of the loss matrices:

[0109]

[0110] where $m$ is the number of working conditions; $w$ j is the weight coefficient for the $j$-th working condition, determined by the application scenario; $L$ jk $(\theta)$ is the loss value of the $k$-th type under the $j$-th working condition with parameter $\theta$.

[0111] The gradient descent method iteratively updates the parameters along the negative gradient direction of the loss function to minimize the loss.

[0112] Specifically, the principle of the present invention is: The technical principle of the present invention is based on the method of combining a metal - SIN layer - semiconductor (MIS) structure with precise process control. Through multi - dimensional parameter optimization and calculation of thermodynamic equations, the low - loss characteristics of the source - drain region of GaN power devices are achieved.

[0113] First, the present invention grows a high - purity GaN layer by molecular beam epitaxy technology, strictly controlling the point density below $10^{ - 3}$, significantly reducing the defect density, which is the basis for improving the breakdown voltage and reducing the leakage current. The introduction of the SIN dielectric layer forms a metal - insulator - semiconductor structure, effectively suppressing the formation of interface states, reducing interface charge scattering and band bending, thereby reducing the interface resistance and parasitic capacitance. 16cm Secondly, the present invention adopts precise gate alignment technology to ensure that the deviation between the geometric center and the lateral representative center is less than 50 nm. This high - precision alignment optimizes the electric field distribution and reduces the source - drain resistance. At the same time, based on the calculation method of the thermodynamic parameter equations, the optimization of the heat treatment process is realized, including the precise control of multi - physical - field coupling processes such as defect recovery, stress release, carrier activation, interface reaction, and heat conduction, effectively reducing the material damage and residual stress during the heat treatment process.

[0114]

[0115] ​The present invention innovatively applies the traveling salesman problem optimization algorithm to optimize multi-parameter heat treatment. By finding the optimal path in the temperature, time, and atmosphere parameter space, efficient activation of doped ions and effective repair of lattice defects are achieved. The introduction of the Ti / Al / Ni / Au multi-layer metal structure further optimizes the ohmic contact characteristics of the source and drain electrodes and reduces the contact resistance.

[0116] Based on the analysis and optimization method of the loss matrix, the power loss data of the device under different working conditions is structured, realizing precise adjustment of device parameters. This systematic optimization method solves the core problem of high loss in the source and drain regions during the preparation of traditional GaN power devices, enabling the device to maintain low-loss characteristics under high-frequency switching conditions, improving energy conversion efficiency and device reliability.

[0117] A specific embodiment 1 of the present invention is provided below. The specific implementation of each step in this embodiment 1 is described in detail as follows.

[0118] The specific implementation of step S01 is to grow a high-purity gallium nitride layer on a gallium nitride substrate using molecular beam epitaxy technology. First, place the gallium nitride substrate in an ultra-high vacuum chamber with the vacuum degree controlled below 10 -9 Pa; then set the substrate temperature to 700 °C, and form a molecular beam current by simultaneously supplying high-purity nitrogen and gallium source, controlling the gallium / nitrogen ratio to 1.05 to ensure a two-dimensional layer growth mode; then use in-situ reflection high-energy electron diffraction to monitor the growth process to ensure that the root mean square roughness of the surface flatness is less than 0.5 nm; subsequently deposit a 20-nm high-purity gallium nitride layer under the condition of a stable growth rate of 0.2 μm / h; finally, test the point density by deep level transient spectroscopy and use Auger electron spectroscopy analysis technology to confirm that the impurity concentration is controlled below 10 16 cm -3 The control of the point density in this step is crucial for the subsequent device performance. Excessive point density will lead to an increase in leakage current and a decrease in breakdown voltage. The ideal threshold should be below 10 16 cm -3 , and the preferred range is 10 15 ~10 16 cm -3 . The point density value in this step will be used as the N d0 parameter in the subsequent defect recovery equation, and this parameter plays an important role in the heat treatment process simulation.

[0119] The specific implementation of step S02 is to deposit a SIN dielectric layer using radio frequency magnetron sputtering technology. First, place the sample in the sputtering chamber and evacuate it to a base pressure below 5×10 -4Pa; Then introduce a mixed gas of high-purity nitrogen and argon, control the flow ratio of nitrogen to argon to be 3:1, and keep the total pressure stable at 0.5 Pa; Next, use a high-purity (purity > 99.999%) Si target, set the RF power to 200 W, and the substrate temperature to 300 °C for sputtering; Subsequently, precisely control the deposition of a 5-nm-thick SIN layer at a deposition rate of 15 nm / min; Finally, use an ellipsometer to monitor the film thickness in real time, and use X-ray photoelectron spectroscopy to analyze and measure the interface energy. The quality of the SIN dielectric layer formed in this step has a decisive impact on the device threshold voltage and gate leakage current, and the interface state density should be controlled at 10 11 cm -2 eV -1 Below, the interface roughness should be less than 0.3 nm. The interface energy of the SIN layer measured in this step will be used as the γ int parameter in the interface reaction equation to predict the evolution of the interface layer during the heat treatment process.

[0120] The specific implementation of step S03 is to deposit the metal gate electrode using electron beam evaporation technology. First, place the sample in the electron beam evaporation equipment and evacuate it to below 10 -5 Pa; Then use a laser alignment system to determine the position of the gate area, align the geometric center of the gate area with the center of the predetermined electric field distribution, and control the deviation within 50 nm; Next, set the electron beam power to 3 kW and use a multi-point scanning technology to ensure the uniformity of the heat distribution; Subsequently, deposit a Ni / Au bilayer metal structure in sequence, with a total thickness of 100 nm, and control the deposition rate to be 0.2 nm / s; Finally, use a high-precision scanning electron microscope to measure the deviation value between the geometric center of the gate and the lateral representative center, and this value is used for the calculation of the loss matrix. The accuracy of the gate position in this step has an important impact on the switching characteristics of the device. The smaller the deviation value, the lower the device loss, and the ideal deviation threshold should be less than 30 nm. This deviation value will be used as an input parameter for the calculation of the loss matrix and affect the electrical performance evaluation of the device.

[0121] The specific implementation of step S04 is to define and form the source and drain regions using photolithography and plasma etching technologies. First, spin-coat a photoresist on the sample surface, control the thickness to be 1.5 μm, and perform soft baking at 90 °C for 60 seconds; Then use a mask aligner exposure machine for exposure, with an alignment accuracy better than 0.3 μm and an exposure dose of 120 mJ / cm 2; Then, after development, hard baking is carried out (at 120 °C for 90 seconds) to enhance the plasma resistance of the photoresist. Subsequently, inductively coupled plasma equipment is used for SIN etching. A CF4 / O2 mixed gas (with a ratio of 10:1) is used, the radio frequency power is set to 100 W, and the pressure is 1.3 Pa. According to the pre-calibrated etching rate (about 1 nm / s), the etching time is precisely controlled to be 5 seconds. Finally, an atomic force microscope is used to measure the etching depth to ensure that the requirement of 5 ± 0.2 nm is achieved, and at the same time, the actual thickness of the interface is measured. Precise control of the etching depth in this step is crucial for forming a low-resistance ohmic contact. Over-etching will damage the GaN layer, and under-etching will lead to an increase in contact resistance. The ideal etching depth threshold should be controlled within the range of 5 ± 0.2 nm. The actual thickness of the interface measured in this step will be used as the δ0 parameter in the interface reaction equation for precise simulation of interface changes during the heat treatment process.

[0122] The specific implementation of step S05 is to form a highly doped source-drain region using ion implantation technology. First, the sample is mounted on the sample stage of the ion implanter, and the tilt angle is set to 7° to reduce the channeling effect. Then, Si ions are selected as the doping source, the acceleration energy is set to 80 keV, and the implantation dose is controlled to be 5×10 15 cm -2 ; Next, a Monte Carlo ion transport simulation program is used to calculate the ion distribution depth to ensure that the peak position of the implanted ions coincides with the longitudinal representative center. Subsequently, multiple low-dose (1×10 15 cm -2 / time) implantation methods are used to reduce lattice damage. Finally, a secondary ion mass spectrometer is used to measure the doping ion concentration distribution and record it for the calculation of the carrier activation equation. The highly doped region formed in this step is the basis for realizing a low-resistance source-drain structure. The doping concentration threshold should be controlled above 5×10 18 cm -3 Above, the preferred range is 5×10 18 ~1×10 20 cm -3 . The doping ion concentration measured in this step will be used as the N i parameter in the carrier activation equation, which is the key input for predicting the effective carrier concentration.

[0123] The specific implementation of step S06 is to perform thermal annealing to activate the doped ions and repair the lattice defects, and this step is carried out based on the calculation results of the thermodynamic parameter equations. First, the optimal annealing parameters are calculated according to the thermodynamic parameter equations composed of the defect recovery equation, stress release equation, carrier activation equation, interface reaction equation, and heat conduction equation; then the sample is placed in an annealing furnace and heated to the target temperature of 750 °C at a heating rate of 10 °C / s; then high-purity nitrogen (purity > 99.999%) is introduced, with a flow rate of 200 sccm and a pressure of 101 kPa, and the temperature is kept constant for 120 seconds; subsequently, it is cooled to room temperature at a rate of 5 °C / s; finally, the residual stress distribution is measured using Raman spectroscopy, and the effective carrier concentration is measured through the Hall effect. This step realizes the activation of doped ions and the repair of lattice defects through thermal annealing. The carrier activation rate threshold should reach more than 80%, and the residual stress should be controlled below 300 MPa. During the thermal annealing process, the defect recovery follows the following equation:

[0124] N d (t) = N d0 exp(-k0exp(-E a / k B T)t);

[0125] In the formula, N d (t) is the residual defect density at time t, with the unit of cm -3 ; N d0 is the initial defect density, that is, the point density value measured in step S01, with the unit of cm -3 ; k0 is the frequency factor, related to the defect type, and the range is 10 12 ~10 14 s -1 ; E a is the defect recovery activation energy, and the typical value for dislocation defects is 2.0 - 3.5 eV; k B is the Boltzmann constant, with a value of 8.617×10 - 5 eV / K; T is the annealing temperature, with the unit of K; t is the annealing time, with the unit of s.

[0126] The stress release process follows the following equation:

[0127] σ(r, t) = σ0(r)exp(-αt n ) + σ r (1 - exp(-β(T - T0) m ));

[0128] Where, σ(r, t) is the stress value at position r at time t, with the unit of Pa; σ0(r) is the initial stress distribution function, obtained through Raman shift measurement, with the unit of Pa; α is the stress release coefficient, related to the material, and the typical value of GaN is 0.001 - 0.01 s -n ; t is the annealing time, with the unit of s; n is the stress release exponent, ranging from 0.3 to 0.7; σ r is the residual stress caused by thermal expansion mismatch, with a typical value of 100 - 500 MPa; β is the temperature - related coefficient, with a typical value of 0.01 - 0.05 K -m ; T is the annealing temperature, with the unit of K; T0 is the reference temperature, usually room temperature, taken as 293 K; m is the temperature - dependent exponent, ranging from 1.2 to 1.8.

[0129] The ion activation process follows the following equation:

[0130]

[0131] Where, N a (T, t) is the effective carrier concentration after annealing time t at temperature T, with the unit of cm -3 ; N i is the doping ion concentration, that is, the value recorded in step S05, with the unit of cm -3 ; η i is the theoretical maximum activation efficiency, related to the type of doping ions. The typical value of Si ions in GaN is 0.8 - 0.95; C i is the activation reaction rate constant, ranging from 10 -3 to 10 -1 s -1 ; t is the annealing time, with the unit of s; T is the annealing temperature, with the unit of K; T r is the reference temperature, taken as 1000 K; p i is the temperature - dependent exponent, ranging from 1.5 to 2.5; E i is the ion activation energy. The typical value of Si ions in GaN is 2.5 - 3.0 eV; k B is the Boltzmann constant, with a value of 8.617×10 -5 eV / K.

[0132] The interface reaction process follows the following equation:

[0133]

[0134] Wherein, δ(t, T) is the thickness of the interface layer after annealing time t at temperature T, with the unit of nm; δ0 is the initial interface layer thickness, i.e., the actual interface thickness after etching measured in step S04, with the unit of nm; A is the diffusion coefficient, and the typical value is 0.5 - 2.0; D is the atomic diffusion constant, and the typical value is 10 -15 ~10 -13 cm 2 / s; t is the annealing time, with the unit of s; E d is the diffusion activation energy, and the typical value at the SIN / GaN interface is 1.8 - 2.3 eV; k B is the Boltzmann constant, with the value of 8.617×10 -5 eV / K; T is the annealing temperature, with the unit of K; B is the interface reaction coefficient, and the typical value is 10 -3 ~10 -2 nm / (J / m 2 ·s); γ int is the interface energy, i.e., the interface energy of the SIN layer measured in step S02, with the unit of J / m 2 , and the typical value is 0.5 - 2.0 J / m 2 ; E r is the interface reaction activation energy, and the typical value is 2.0 - 2.5 eV.

[0135] The heat conduction process follows the following equation:

[0136]

[0137] Wherein, ρ is the material density, and the value of GaN is 6.15 g / cm 3 ; c p is the specific heat capacity, and the value of GaN at high temperature is 0.49 - 0.52 J / (g·K); T(x, y, z, t) is the temperature at time t at spatial position (x, y, z), with the unit of K; k is the thermal conductivity, and the value of GaN is 130 - 230 W / (m·K), which varies with temperature; is the gradient operator, Q(x, y, z, t) is the internal heat source distribution function, with the unit of W / m 3 .

[0138] The specific implementation of step S07 is to form ohmic contacts in the source and drain regions using rapid thermal annealing technology, and this step determines the optimal process parameters based on the traveling salesman problem optimization algorithm. First, according to the traveling salesman problem optimization algorithm, multiple annealing parameter nodes are set, including temperature (800 °C, 825 °C, 850 °C, 875 °C, 900 °C), time (10 s, 20 s, 30 s, 40 s, 50 s), and atmosphere conditions (nitrogen, argon, nitrogen-argon mixture); then the nearest neighbor insertion heuristic algorithm is used to construct an initial path, and the path is optimized through the 2-opt local search algorithm; then the annealing simulation algorithm is used to avoid local optimal solutions, with the initial temperature set to 100 and the cooling coefficient set to 0.95; subsequently, the "distance" between each node is calculated; finally, 850 °C, 30 s, and nitrogen atmosphere are determined as the optimal combination. This step realizes the formation of low-resistance ohmic contacts by optimizing the annealing parameters, and the contact resistivity threshold should be less than 1×10 -5 Ω·cm 2 , and the preferred range is 1×10 -6 ~5×10 -6 Ω·cm 2 . The objective function of the traveling salesman problem optimization algorithm is:

[0139]

[0140] In the formula, P = (p1, p2,..., p k ) is the parameter node sequence; k is the total number of nodes; d(p i , p j ) is the "distance" between nodes p i and p j , which is defined as:

[0141] d(p i , p j ) = w T |T i - T j | + w t |t i - t j | + w g δ(g i , g j );

[0142] In the formula, T i and T j are the temperatures of nodes i and j, in °C; t i and t j are the times of nodes i and j, in s; g i and g j are the atmosphere conditions of nodes i and j; w T is the temperature weight coefficient, and the typical value is 0.01~0.05 °C-1 ; w t is the time weight coefficient, and the typical value is 0.1 - 0.5 s -1 ; w g is the atmosphere switching cost coefficient, and the typical value is 5 - 20; δ(g i , g j ) is the atmosphere switching indication function, which takes 1 when g i ≠g j , and takes 0 otherwise.

[0143] The 2-opt local search algorithm used in the optimization algorithm is specifically expressed as:

[0144] P′ = 2-opt(P, i, j) = (p1, p2,..., p i , p j , p j-1 ,..., p i+1 , p j+1 ,..., p k );

[0145] In the formula, P = (p1, p2,..., p k ) is the current parameter node sequence; P′ is the new sequence after performing the 2-opt operation; i and j are two selected positions, satisfying 1 ≤ i < j ≤ k.

[0146] The acceptance probability calculation of the simulated annealing algorithm during the optimization process is:

[0147]

[0148] In the formula, f(P) is the objective function value of the current solution; f(P′) is the objective function value of the new solution; T sim is the "temperature" parameter of the simulated annealing algorithm, with the initial value set to 100, and it decreases according to T sim = 0.95·T sim during the iteration process.

[0149] The specific implementation of step S08 is to deposit multi-layer metal source and drain electrodes by electron beam evaporation. First, place the sample in the electron beam evaporation equipment, and pump the chamber vacuum to 5×10 -5Below Pa; then deposit four layers of metals, Ti / Al / Ni / Au, with thicknesses of 20 / 100 / 40 / 50 nm respectively; then control the evaporation rate for each metal, 0.1 nm / s for Ti, 0.5 nm / s for Al, 0.2 nm / s for Ni, and 0.3 nm / s for Au; subsequently, perform alloying treatment according to the optimal annealing time parameters (850 °C, 30 s) determined in step S07; finally, measure the resistivity of the source and drain electrodes by the four-probe method and record it for loss matrix calculation. The multi-layer metal structure formed in this step has the following functions: the Ti layer provides good adhesion to GaN, the Al layer provides the main conduction path, the Ni layer prevents the upward diffusion of Al, the Au layer prevents oxidation and provides good conductivity, and the total resistivity threshold after electrode alloying should be less than 3×10 -6 Ω·cm. The electrode resistivity measured in this step will be used for the calculation of conduction loss in the loss matrix.

[0150] The specific implementation of step S09 is to perform device packaging testing and parameter optimization. First, connect the device die to the test substrate using the gold wire bonding technique, with a bonding wire diameter of 25 μm; then design a gate pulse test circuit with a gate voltage ranging from -5 V to +10 V, a rise / fall time of 10 ns, and a pulse width of 1 μs; then measure the switching loss under different drain voltages (100 V, 200 V, 300 V, 400 V, 600 V) and different current conditions (1 A, 5 A, 10 A, 20 A); subsequently, construct a loss matrix and optimize the parameter points in the manufacturing process through the gradient descent method to determine the final device manufacturing process parameters. This step realizes device performance optimization through comprehensive testing and loss analysis. The specific on-resistance threshold of the optimized device should be less than 5 mΩ·cm 2 , and the switching loss threshold should be less than 10 μJ / A. The loss matrix can be expressed as:

[0151]

[0152] In the formula, L ij represents the value of the jth type of loss (conduction loss, switching loss, or thermal loss) under the ith working condition (such as a specific voltage and current combination), with the unit of W; m is the number of working conditions; n is the number of loss types, usually 3 (conduction, switching, thermal loss).

[0153] The conduction loss is specifically expressed as:

[0154]

[0155] In the formula, L con，i is the conduction loss under the ith working condition, with the unit of W; R on，iIs the on-resistance under corresponding conditions, calculated from the source-drain electrode resistivity measured in step S08, with the unit of Ω; I i Is the corresponding on-current, with the unit of A.

[0156] The switching loss is specifically expressed as:

[0157] L sw，i = f i ·(E on，i + E off，i );

[0158] In the formula, L sw，i Is the switching loss under the i-th working condition, with the unit of W; f i Is the switching frequency, with the unit of Hz; E on，i Is the turn-on energy, with the unit of J; E off，i Is the turn-off energy, with the unit of J. The turn-on / turn-off energy is obtained through gate pulse testing:

[0159]

[0160] In the formula, v ds (t) is the drain-source voltage, with the unit of V; i d (t) is the drain current, with the unit of A; t on1 To t on2 Is the turn-on time period; t off1 To t off2 Is the turn-off time period.

[0161] The thermal loss is specifically expressed as:

[0162] L th，i = R th，i ·(L con，i + L sw，i );

[0163] In the formula, L th，i Is the thermal loss under the i-th working condition, with the unit of W; R th，i Is the thermal resistance coefficient, and the typical value is 0.01 - 0.05.

[0164] The gradient descent method is used for parameter optimization, and its iterative update formula is:

[0165]

[0166] In the formula, θ i Is the process parameter vector of the i-th iteration, including the key parameters in each preparation step; θ i+1 Is the updated parameter vector; η is the learning rate, and the typical value is 0.01 - 0.1; Is the objective function J at θ iThe gradient at [location] is calculated as follows:

[0167]

[0168] In the formula, n is the total number of parameters; the objective function J is defined as the weighted sum of the loss matrices:

[0169]

[0170] In the formula, m is the number of working conditions; w j is the weight coefficient of the j-th working condition, which is determined by the application scenario; L jk (θ) is the loss value of the k-th type under the j-th working condition with parameter θ.

[0171] Through the specific implementation of the above nine steps in this embodiment, the preparation of a low-loss source-drain GaN power device can be achieved. This method combines precise material growth control, precise structure design, and optimized heat treatment process. Guided by a mathematical model to select process parameters, it ensures that the device has excellent performance of low on-resistance and low switching loss. The thermodynamic parameter equations provide theoretical guidance for the heat treatment process, the traveling salesman problem optimization algorithm efficiently determines the optimal annealing parameters, and the loss matrix analysis realizes the comprehensive evaluation and optimization of the device performance, and finally prepares a high-performance GaN power device.

[0172] To better understand and implement the present invention, the following provides Example 2 of a specific application scenario of the present invention: Researchers used the method of the present invention to prepare a low-loss source-drain GaN power device for high-frequency power electronics applications. The specific implementation process is as follows.

[0173] First, an n-type doped GaN substrate with a diameter of 2 inches and a thickness of 430 μm was selected. The resistivity of the substrate was 0.05 Ω·cm. After cleaning, it was loaded into the growth chamber of the molecular beam epitaxy system. Under ultra-high vacuum conditions (background vacuum degree of 3.2×10 -10 Pa), the substrate temperature was set to 685 °C. By precisely controlling the Ga cell temperature to 915 °C and the high-purity nitrogen flow rate to 1.5 sccm, a growth condition with a Ga / N ratio of 1.05 was formed, and a 20-nm-thick high-purity gallium nitride layer was deposited at a growth rate of 0.18 μm / h. Through deep level transient spectroscopy testing, the point density of this layer was 8.7×10 15 cm -3 , meeting the expected target.

[0174] Next, the researchers deposited a SIN dielectric layer using a radio frequency magnetron sputtering system. During the sputtering process, the background pressure was controlled at 4.3×10 -4Pa, with a working pressure of 0.5 Pa, a nitrogen-to-argon flow rate ratio of 3:1. A Si target with a purity of 99.999% was used, the RF power was set at 200 W, the substrate temperature was 300 °C, and a 5-nm-thick SIN layer was precisely controlled at a deposition rate of 15.5 nm / min. X-ray photoelectron spectroscopy analysis determined the interfacial energy of this SIN layer to be 1.35 J / m 2 , and the interface state density was 7.8×10 10 cm -2 eV -1 , and the interface roughness was 0.24 nm.

[0175] Subsequently, a metal gate electrode was deposited using electron beam evaporation technology. At a vacuum of 6.8×10 -6 Pa, a bilayer metal structure of 20 nm Ni and 80 nm Au was deposited in sequence, and the deposition rates were controlled at 0.2 nm / s and 0.25 nm / s respectively. The deviation value between the geometric center of the gate and the lateral representative center was measured using a high-precision scanning electron microscope to be 27 nm, and this value was recorded for subsequent loss matrix calculations.

[0176] The source and drain regions were defined and formed through photolithography and plasma etching technologies. A positive photoresist with a thickness of 1.5 μm was used in the photolithography process, the exposure dose was 125 mJ / cm 2 , and a hard bake was performed at 120 °C for 90 seconds after exposure. SIN etching was carried out using an inductively coupled plasma device, with a CF4 / O2 mixed gas (ratio of 10:1), an RF power of 95 W, a pressure of 1.3 Pa, an etching rate of 1.02 nm / s, and the etching time was controlled at 4.9 seconds. Measured by an atomic force microscope, the etching depth was 5.1 nm, and the actual interface thickness was 0.3 nm.

[0177] A highly doped region was formed in the source and drain regions using ion implantation technology. Si ions were selected as the doping source, the acceleration energy was 80 keV, and the total implantation dose was controlled at 5×10 15 cm -2 , and it was completed in 5 injections, with a dose of 1×10 15 cm -2 each time. The doping ion concentration distribution was measured by secondary ion mass spectrometry, with a peak concentration of 7.3×10 19 cm -3 , and the distribution depth was 68 nm.

[0178] The optimal annealing conditions were calculated according to the thermodynamic parameter equations, and the main parameters are shown in Table 1:

[0179] Table 1 Key parameter values of the thermodynamic parameter equations

[0180]

[0181]

[0182] Based on the above calculation results, thermal annealing treatment was carried out in a nitrogen atmosphere at 750 °C (purity > 99.999%, flow rate of 200 sccm, pressure of 101 kPa) for 120 seconds. After annealing, the average value of the residual stress distribution was measured to be 115 MPa by Raman spectroscopy, and the effective carrier concentration was measured to be 6.1×10 19 cm -3 , and the carrier activation rate reached 83.6%.

[0183] The optimal annealing conditions for the source-drain ohmic contact were determined using the traveling salesman problem optimization algorithm. As shown in Table 2, 5 temperature nodes, 5 time nodes, and 3 atmosphere conditions were set, constituting 75 parameter combination nodes:

[0184] Table 2 Annealing parameter node settings

[0185] Parameter type Node value Temperature node (°C) 800,825,850,875,900 Time node (s) 10,20,30,40,50 Atmosphere condition Nitrogen, argon, nitrogen-argon mixture (3:1)

[0186] Applying the traveling salesman problem optimization algorithm, the temperature weight coefficient w T was set to 0.03 °C -1 , the time weight coefficient w t was set to 0.2 s -1 , the atmosphere switching cost coefficient w g was set to 10, the initial "temperature" parameter T sim was set to 100, the cooling coefficient was 0.95. After 2000 iterations, the optimal combination of 850 °C, 30 seconds, and nitrogen atmosphere was obtained, and the predicted contact resistivity was 2.3×10 -6 Ω·cm 2 .

[0187] According to the optimization results, a Ti / Al / Ni / Au multi-layer metal source-drain electrode was deposited by electron beam evaporation, with thicknesses of 20 / 100 / 40 / 50 nm and evaporation rates of 0.1 / 0.5 / 0.2 / 0.3 nm / s respectively. Alloying treatment was carried out in a nitrogen atmosphere according to the determined parameters of 850 °C and 30 seconds, and the resistivity of the source-drain electrode was measured to be 2.5×10 -6 Ω·cm 2 , which is close to the algorithm prediction value.

[0188] The finally obtained structure is as shown in Figure 2 , and the specific description is as follows: The bottom is a gallium nitride substrate, serving as the basic carrier of the device; a 20-nm-thick high-purity gallium nitride layer is grown on the substrate, and the site density is controlled at 10 16 cm -3The following is used to improve the breakdown voltage of the device and reduce the leakage current; a 5-nm-thick SIN insulating layer is deposited on the high-purity gallium nitride layer to form a high-quality dielectric layer and reduce the formation of interface states; a 100-nm-thick metal gate electrode is deposited in the central region, and the deviation of its geometric center from the lateral representative center is controlled within 50 nm to optimize the electric field distribution; the SIN layer in the source-drain region is precisely etched away to form the source-drain contact window of the device; a high-concentration doping region is formed in the source-drain region by ion implantation, and the implantation dose is 5×10 15 cm -2 , and the doping uniformity is ensured by positioning through the longitudinal representative center; there is an optimized annealing-treated ohmic contact layer in the source-drain region; the source-drain electrodes are composed of multiple layers of metals Ti / Al / Ni / Au with thicknesses of 20 / 100 / 40 / 50 nm respectively to form high-quality electrical contacts.

[0189] Finally, device packaging tests and parameter optimizations were carried out. Gold wires with a diameter of 25 μm were used for bonding, a gate pulse test circuit was designed, and the loss characteristics of the device were measured under different working conditions. Table 3 shows some test results:

[0190] Table 3 Loss test results under different working conditions

[0191]

[0192]

[0193] Based on the analysis results of the loss matrix, the parameter points in the preparation process were optimized and adjusted using the gradient descent method. The learning rate η was set to 0.05, and the final process parameters were obtained after 100 iterations. The specific on-resistance of the optimized device is 3.2 mΩ·cm 2 , and the switching loss is 7.6 μJ / A (under the working conditions of 300 V / 10 A), which is much lower than that of the devices prepared by traditional processes.

[0194] Traditional preparation methods for GaN power devices mainly adopt the metal-insulator-semiconductor (MIS) structure or the metal-semiconductor (MS) structure. Usually, empirical parameters or single-objective optimization methods are used to determine the process conditions, lacking a systematic multi-parameter collaborative optimization mechanism. The specific on-resistance of the devices prepared by these traditional methods is usually 5 - 8 mΩ·cm 2Within the range, the switching loss is within the range of 15 - 25 μJ / A. Compared with the traditional method, the present invention adopts a metal - SIN layer - semiconductor structure, combines the thermodynamic parameter equations and the traveling salesman problem optimization algorithm to achieve multi - parameter collaborative optimization, and significantly reduces the power loss of the device. The GaN power device prepared by the method of the present invention has a conduction resistance reduced by about 40% and a switching loss reduced by about 60%, greatly improving the device efficiency, and is particularly suitable for high - frequency and high - power - density power electronics application scenarios. In addition, this method significantly improves the stability and reliability of the device by precisely controlling the interface reaction and the carrier activation process, effectively solving the problems of large leakage current, low breakdown voltage, and unstable threshold voltage existing in traditional GaN devices.

[0195] It should be noted that the detailed explanations of the variables involved in the present invention are shown in Tables 4 and 5 below.

[0196] Table 4 Variable Explanation Table (First Part)

[0197]

[0198]

[0199] Table 5 Variable Explanation Table (Second Part)

[0200]

[0201] As mentioned above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention.

Claims

1. A method for preparing a low-loss source-drain GaN power device of a metal SIN layer-semiconductor structure, characterized in that: include: Growing a high-purity gallium nitride layer on a gallium nitride substrate; Depositing a SIN layer on the high purity GaN layer; Depositing a metal gate electrode on the SIN layer; defining a source and drain region and removing the SIN layer in the source and drain region; forming a high-concentration doping region in the source and drain region; Perform thermal annealing to activate doped ions and repair lattice defects; form ohmic contacts in the source and drain regions; Depositing multiple layers of metal as source and drain electrodes; Device packaging tests are carried out, switching losses are measured using the gate pulse test method, and parameter optimization and adjustment are performed based on the loss matrix analysis results. Low-loss characteristics in the source and drain regions are achieved by controlling point density, accurately aligning the geometric center and the lateral representative center, optimizing the calculation of the thermodynamic parameter equation group, and determining the annealing parameters using the traveling salesman problem optimization algorithm.

2. The method for preparing a low-loss source-drain GaN power device of a metal SIN layer-semiconductor structure according to claim 1, characterized in that: The high-purity GaN layer is grown on the GaN substrate by molecular beam epitaxy to grow a 20nm thick high-purity GaN layer with a controlled point density of 10 16 cm -3 Below, the point density values ​​are measured for subsequent calculations.

3. The method for preparing a low-loss source-drain GaN power device of a metal SIN layer-semiconductor structure according to claim 2, characterized in that: The SIN layer is deposited on the high-purity GaN layer by using RF magnetron sputtering to deposit a 5 nm thick SIN layer on the high-purity GaN layer. The RF power is adjusted to 200 W and the sputtering pressure is adjusted to 0.5 Pa to form a high-quality dielectric layer. The interface energy of the SIN layer is measured and used for the calculation of the thermodynamic parameter equation group.

4. The method for preparing a low-loss source-drain GaN power device of a metal SIN layer-semiconductor structure according to claim 3, characterized in that: The metal gate electrode is deposited on the SIN layer by using electron beam evaporation technology to deposit a metal gate electrode with a thickness of 100 nm on the SIN layer, ensuring that the deviation between the geometric center and the lateral representative center is less than 50 nm, and the deviation value is recorded for loss matrix calculation.

5. The method for preparing a low-loss source-drain GaN power device of a metal SIN layer-semiconductor structure according to claim 4, characterized in that: Defining the source and drain regions and removing the SIN layer in the source and drain regions: The source and drain regions are defined by a photolithography process, and the SIN layer in the source and drain regions is removed by inductively coupled plasma etching. The etching depth is controlled at 5±0.2nm, and the actual thickness of the interface after etching is measured for calculation of the interface reaction equation.

6. The method for preparing a low-loss source-drain GaN power device of a metal SIN layer-semiconductor structure according to claim 5, characterized in that: The high concentration doping region is formed in the source and drain regions by using ion implantation technology, and the implantation dose is 5×10 15 cm -2 , uniform doping distribution is ensured by longitudinally representing the center positioning, and the doping ion concentration is recorded for carrier activation equation calculation.

7. The method for preparing a low-loss source-drain GaN power device of a metal SIN layer-semiconductor structure according to claim 6, characterized in that: The thermal annealing treatment is carried out in a nitrogen atmosphere at 750°C for 120 seconds based on the calculation results of the thermodynamic parameter equation group to activate the doped ions and repair the lattice defects. The residual stress distribution and effective carrier concentration after thermal annealing are measured and recorded.

8. The method for preparing a low-loss source-drain GaN power device of a metal SIN layer-semiconductor structure according to claim 7, characterized in that: The ohmic contact is formed in the source and drain regions by using rapid thermal annealing technology. The annealing temperature is 850°C. The traveling salesman problem optimization algorithm is used to determine the optimal path between multiple annealing parameter nodes. The optimal annealing time is determined to be 30 seconds by calculating the shortest temperature-time curve, and the optimal annealing time is recorded for subsequent processes.

9. The method for preparing a low-loss source-drain GaN power device of a metal SIN layer-semiconductor structure according to claim 8, characterized in that: The deposition of multilayer metal as source and drain electrodes is based on the optimal annealing time parameters. Electron beam evaporation is used to deposit Ti / Al / Ni / Au multilayer metal as source and drain electrodes. The thickness of each layer is 20 / 100 / 40 / 50nm respectively. The resistivity of the source and drain electrodes is measured for loss matrix calculation.

10. The method for preparing a low-loss source-drain GaN power device of a metal SIN layer-semiconductor structure according to claim 9, characterized in that: The thermodynamic parameter equations include defect recovery equation, stress release equation, carrier activation equation, interface reaction equation, and heat conduction equation, which are used to calculate defect repair rate, stress release process, doping ion activation efficiency, interface reaction kinetics, and heat distribution and transfer.

Images