Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a semiconductor layer, a trench gate, a deep trench structure, a column region, a protection region, a source region, a first electrode, a second electrode and a gate, and the semiconductor layer comprises a substrate, an epitaxial layer and a body region which are stacked in sequence; the trench gate structure penetrates through the body region; the deep trench structure is embedded in the epitaxial layer below the trench gate structure, and the sectional dimension of the trench gate structure perpendicular to the stacking direction of the substrate and the epitaxial layer is greater than the sectional dimension of the deep trench structure; the column region at least wraps the side wall of the deep groove structure in the epitaxial layer and is communicated with the body region; the protection region is located at the bottom of the trench gate structure; the source region is located on the upper surface of the body region; the first electrode is electrically connected with the source region; the second electrode is electrically connected with the bottom of the semiconductor layer; the gate is electrically connected with the trench gate structure. Through the arrangement of the deep groove structure, the manufacturing difficulty of the column region is reduced, meanwhile, the on resistance of the device is reduced, and the voltage resistance of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a semiconductor device and a preparation method thereof. Background Art

[0002] Due to its high-density conductive channels, low on-resistance, high critical breakdown electric field, high thermal conductivity, high electron saturation velocity and other properties, trench-gate silicon carbide (SiC) MOS devices are widely used in high-power scenarios. As Figure 1 shown, it is a schematic cross-sectional structure diagram of a trench-gate SiC MOS device, including a SiC substrate 01, a drift region 011, a body region 012, a source region 013, a source contact region 014, a shielding region 015, a gate trench 02, a gate oxide layer 021, a polysilicon gate 022, an interlayer dielectric layer 03, a source electrode 04, and a drain electrode 05. In the trench-gate SiC MOS device, due to the generally strong electric field intensity at the bottom of the trench-gate structure, breakdown is likely to occur, affecting the reliability of the device. In order to reduce the electric field at the bottom of the trench-gate structure, a shielding structure (shielding region) for protecting the bottom of the trench-gate structure needs to be introduced into the device. However, the introduction of the shielding structure also forms a parasitic JFET region in the device, resulting in an increase in the on-resistance of the device. In order to further reduce the on-resistance of the device, a superjunction structure is introduced into the epitaxial layer of the trench-gate SiC MOS device. As Figure 2 shown, it is a schematic cross-sectional structure diagram of a trench-gate superjunction MOS device, including a SiC substrate 01, a drift region 011, a body region 012, a source region 013, a source contact region 014, a shielding region 015, a column region 016, a gate trench 02, a gate oxide layer 021, a polysilicon gate 022, an interlayer dielectric layer 03, a source electrode 04, and a drain electrode 05. Although the introduction of the superjunction reduces the on-resistance of the device to a certain extent, the P-columns in the device require multiple epitaxial growths and multiple high-temperature and high-energy implantations, resulting in a complex process, high manufacturing cost, and difficult precise control of the dose of each implantation due to multiple epitaxial growths and multiple ion implantations, causing large process fluctuations and high reliability risks. In addition, since the trench-gate structure is located between two adjacent P-columns (column regions), it is difficult to reduce the cell size of the trench-gate superjunction MOS device, and thus it is difficult to significantly reduce the specific on-resistance of the device.

[0003] Therefore, there is an urgent need to find a semiconductor device that can reduce the on-resistance of the device, reduce the cell size of the device, and simplify the device manufacturing process at the same time. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor device and a preparation method thereof, which are used to solve the problems of large on-resistance of the trench-gate superjunction MOS device, difficult reduction of the cell size of the device, and complex device manufacturing process in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a semiconductor device, comprising:

[0006] A semiconductor layer, comprising a first-conductivity-type substrate, a first-conductivity-type epitaxial layer, and a second-conductivity-type body region stacked in sequence;

[0007] A trench gate structure, penetrating through the body region;

[0008] A deep trench structure, at least embedded in the epitaxial layer below the trench gate structure, and the cross-sectional dimension of the trench gate structure perpendicular to the stacking direction of the substrate and the epitaxial layer is larger than the cross-sectional dimension of the deep trench structure;

[0009] A second-conductivity-type column region, at least wrapping the sidewalls of the deep trench structure in the epitaxial layer and communicating with the body region;

[0010] A second-conductivity-type protection region, located at the bottom of the trench gate structure;

[0011] A first-conductivity-type source region, located on the upper surface layer of the body region and adjacent to the trench gate structure on one side close to the trench gate structure;

[0012] A first electrode, electrically connected to the source region;

[0013] A second electrode, electrically connected to the bottom of the semiconductor layer;

[0014] A gate electrode, electrically connected to the trench gate structure.

[0015] Optionally, a first-conductivity-type current spreading layer is further provided in the semiconductor layer, located on the upper surface layer of the epitaxial layer and having an upper surface adjacent to the bottom surface of the body region, and the trench gate structure penetrates through the current spreading layer.

[0016] Optionally, the first electrode penetrates through the body region between two adjacent trench gate structures and has a bottom surface lower than the bottom surface of the body region, and a preset barrier height exists between the first electrode and the current spreading layer.

[0017] Optionally, a second-conductivity-type doped region is further provided in the epitaxial layer at the bottom of the first electrode, and the doped region at least wraps the bottom of the first electrode extending into the epitaxial layer.

[0018] Optionally, the bottom surface of the deep trench structure is located in the epitaxial layer and is spaced from the upper surface of the substrate by a preset distance, and the column region also wraps the bottom surface of the deep trench.

[0019] Optionally, the deep trench structure penetrates through the epitaxial layer and the bottom surface extends into the substrate.

[0020] Optionally, the deep trench structure at least includes a deep trench and a dielectric layer, and the dielectric layer at least covers the inner wall and the bottom surface of the deep trench.

[0021] Optionally, the dielectric layer fills the deep trench.

[0022] Optionally, the deep trench structure further includes a filling conductive layer that fills the deep trench, the dielectric layer wraps the side wall and the bottom surface of the filling conductive layer, and the bottom surface of the gate conductive layer is adjacent to the top surface of the filling conductive layer.

[0023] Optionally, the conductivity type of the filling conductive layer includes one of a first conductivity type and a second conductivity type.

[0024] Optionally, the thickness of the dielectric layer located at the bottom of the deep trench is not less than 2 times the thickness of the dielectric layer covering the inner wall of the deep trench.

[0025] Optionally, the bottom surface of the filling conductive layer is not lower than the bottom surface of the column region.

[0026] Optionally, the protection region is located at the top of the column region, and the column region is connected to the body region through the protection region located at the bottom of the trench gate structure.

[0027] The present invention also provides a method for manufacturing a semiconductor device, including the following steps

[0028] Providing a semiconductor layer including a first conductivity type substrate, a first conductivity type epitaxial layer, and a second conductivity type body region stacked in layers in sequence;

[0029] Forming a trench gate structure, a deep trench structure, a second conductivity type column region, and a second conductivity type protection region, the trench gate structure penetrates the body region, the deep trench structure is at least embedded in the epitaxial layer below the trench gate structure, the cross-sectional dimension of the trench gate structure perpendicular to the stacking direction of the substrate and the epitaxial layer is larger than the cross-sectional dimension of the deep trench structure, the column region at least wraps the side wall of the deep trench structure in the epitaxial layer and is connected to the body region, and the protection region is located at the bottom of the trench gate structure;

[0030] Forming a first conductivity type source region on the upper surface of the body region and adjacent to the trench gate structure on one side close to the trench gate structure;

[0031] Forming a first electrode electrically connected to the source region, a second electrode electrically connected to the bottom of the semiconductor layer, and a gate electrode electrically connected to the trench gate structure.

[0032] As described above, in the semiconductor device and its manufacturing method of the present invention, a deep trench structure is provided in the epitaxial layer at the bottom of the gate trench, facilitating the formation of the column region communicating with the body region, reducing the manufacturing difficulty of the column region in the superjunction structure, simultaneously reducing the cell size of such superjunction devices, optimizing the electric field distribution in the epitaxial layer, reducing the on-resistance of the device, improving the breakdown voltage and power density of the device, enhancing the FOM value of the device, and since the column region is formed synchronously based on the deep trench, ensuring the consistency of the column region process and making the longitudinal electric field distribution in the epitaxial layer more uniform; by providing a filling conductive layer with a medium-low doping concentration and electrically connected to the gate conductive layer in the deep trench structure, using the filling conductive layer to assist the column region in consuming the charges in the epitaxial layer, depleting the epitaxial layer before the dielectric layer breaks down, further enhancing the breakdown voltage of the device and reducing the on-resistance of the device. In addition, by making the first electrode penetrate through the body region and the current spreading layer and form a Schottky contact with the current spreading layer, and simultaneously providing a doped region wrapping the bottom of the first electrode extending into the epitaxial layer at the bottom of the first electrode, the doped region and the protection regions on both sides thereof can jointly share the electric field in the epitaxial layer, thereby further reducing the electric field intensity at the bottom of the trench gate structure and enhancing the reliability of the device, having high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Shown is a schematic cross-sectional structure diagram of a trench gate SiC MOS device.

[0034] Figure 2 Shown is a schematic cross-sectional structure diagram of a trench gate superjunction MOS device.

[0035] Figure 3 Shown is a schematic cross-sectional structure diagram of a semiconductor device of the present invention.

[0036] Figure 4 Shown is another schematic cross-sectional structure diagram of a semiconductor device of the present invention.

[0037] Figure 5 Shown is a third schematic cross-sectional structure diagram of a semiconductor device of the present invention.

[0038] Figure 6 Shown is a fourth schematic cross-sectional structure diagram of a semiconductor device of the present invention.

[0039] Figure 7 Shown is a fifth schematic cross-sectional structure diagram of a semiconductor device of the present invention.

[0040] Figure 8 Shown as Figure 1 the device in Figure 3 and the longitudinal electric field intensity variation trend diagram of the device in

[0041] Figure 9 Shown asFigure 2 The longitudinal electric field strength variation trend diagram of the medium device and Figure 3 the medium device.

[0042] Figure 10 It is shown as the process flow chart of the preparation method of the semiconductor device of the present invention.

[0043] Figure 11 It is shown as the cross-sectional structure schematic diagram of the semiconductor layer of the preparation method of the semiconductor device of the present invention.

[0044] Figure 12 It is shown as the cross-sectional structure schematic diagram after forming the gate trench of the preparation method of the semiconductor device of the present invention.

[0045] Figure 13 It is shown as the cross-sectional structure schematic diagram after forming the protection area of the preparation method of the semiconductor device of the present invention.

[0046] Figure 14 It is shown as the cross-sectional structure schematic diagram after forming the deep trench of the preparation method of the semiconductor device of the present invention.

[0047] Figure 15 It is shown as the cross-sectional structure schematic diagram after forming the column area of the preparation method of the semiconductor device of the present invention.

[0048] Figure 16 It is shown as the cross-sectional structure schematic diagram after forming the filling conductive layer of the preparation method of the semiconductor device of the present invention.

[0049] Figure 17 It is shown as the cross-sectional structure schematic diagram after forming the gate conductive layer of the preparation method of the semiconductor device of the present invention.

[0050] Figure 18 It is shown as the cross-sectional structure schematic diagram after forming the source area of the preparation method of the semiconductor device of the present invention.

[0051] Figure 19 It is shown as the cross-sectional structure schematic diagram after forming the first contact hole of the preparation method of the semiconductor device of the present invention.

[0052] Explanation of the reference numerals in the drawings

[0053] 01 SiC substrate

[0054] 011 Drift region

[0055] 012 Body region

[0056] 013 Source region

[0057] 014 Source electrode contact region

[0058] 015 Shielding region

[0059] 016 Column area

[0060] 02 Gate trench

[0061] 021 Gate oxide layer

[0062] 022 Polysilicon gate

[0063] 03 Interlayer dielectric layer

[0064] 04 Source

[0065] 05 Drain

[0066] 1 Semiconductor layer

[0067] 11 Substrate

[0068] 12 Epitaxial layer

[0069] 13 Current spreading layer

[0070] 14 Body region

[0071] 15 Column area

[0072] 16 Protection region

[0073] 17 Source region

[0074] 18 Doped region

[0075] 2 Trench gate structure

[0076] 21 Gate trench

[0077] 22 Gate dielectric layer

[0078] 23 Gate conductive layer

[0079] 24 Deep trench structure

[0080] 25 Deep trench

[0081] 26 Dielectric layer

[0082] 27 Filled conductive layer

[0083] 3 Interlayer dielectric layer

[0084] 31 First contact hole

[0085] 32 Third contact hole

[0086] 4 First electrode

[0087] 5 Second electrode Detailed implementation manners

[0088] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0089] Please refer to Figures 3 to 19 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0090] Embodiment 1

[0091] This embodiment provides a semiconductor device. As Figures 3 to 7 shown, they are respectively schematic cross-sectional structures of several types of the semiconductor device, including a semiconductor layer 1, a trench gate structure 2, a deep trench structure 24, a second conductivity type pillar region 15, a second conductivity type protection region 16, a first conductivity type source region 17, a first electrode 4, a second electrode 5, and a gate. Among them, the semiconductor layer 1 includes a first conductivity type substrate 11, a first conductivity type epitaxial layer 12, and a second conductivity type body region 14 stacked in sequence; the trench gate structure 2 penetrates the body region 14; the deep trench structure 24 is at least embedded in the epitaxial layer 12 below the trench gate structure 2, and the cross-sectional dimension of the trench gate structure 2 perpendicular to the stacking direction of the substrate 11 and the epitaxial layer 12 is larger than the cross-sectional dimension of the deep trench structure 24; the pillar region 15 at least wraps the sidewalls of the deep trench structure 24 in the epitaxial layer 12 and communicates with the body region 14; the protection region 16 is located at the bottom of the trench gate structure 2; the source region 17 is located on the upper surface of the body region 14 and is adjacent to the trench gate structure 2 on one side close to the trench gate structure 2; the first electrode 4 is electrically connected to the source region 17; the second electrode 5 is electrically connected to the bottom of the semiconductor layer 1; the gate is electrically connected to the trench gate structure 2.

[0092] Specifically, the first conductivity type includes one of N-type or P-type, the second conductivity type includes one of N-type or P-type, and the conductivity types of the first conductivity type and the second conductivity type are opposite. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0093] Specifically, the substrate 11 in the semiconductor layer 1 is usually a process platform for fabricating the epitaxial layer 12 (the drift region of the device), and usually its doping concentration is greater than the doping concentration of the lightly doped epitaxial layer 12.

[0094] Specifically, while ensuring the device performance, the thickness, size, shape, and doping concentration of the substrate 11 can be selected according to the actual situation; the thickness, size, shape, and doping concentration of the epitaxial layer 12 can be selected according to the actual situation.

[0095] Specifically, the material of the substrate 11 includes silicon, silicon germanium, silicon carbide, or other suitable semiconductor materials. Preferably, a silicon carbide wafer is used as the substrate 11.

[0096] It should be noted that generally, the epitaxial layer 12 is a homoepitaxy of the substrate 11, that is, the material of the epitaxial layer 12 is the same as that of the substrate 11.

[0097] As an example, in the semiconductor layer 1, there is also a first-conductivity-type current spreading layer 13 located on the upper surface of the epitaxial layer 12 and adjacent to the bottom surface of the body region 14.

[0098] Specifically, the doping concentration of the current spreading layer 13 is greater than that of the epitaxial layer 12 to optimize the current flow path, reduce current crowding, and reduce the parasitic JFET resistance in the device, so that the device has a better FOM value.

[0099] Specifically, while ensuring the device performance, the thickness and doping concentration of the current spreading layer 13 can be selected according to the actual situation.

[0100] It should be noted that generally, the conductive channel of the device is formed in the body region 14, and the doping concentration of the body region 14 is usually lightly doped or normally doped. While ensuring the device performance, the thickness and doping concentration of the body region 14 can be selected according to the actual situation.

[0101] Specifically, the trench gate structure 2 includes a gate trench 21, a gate dielectric layer 22, and a gate conductive layer 23. The gate trench 21 penetrates through the body region 14 and the current spreading layer 13. The gate dielectric layer 22 covers at least the inner wall of the gate trench 21. The gate conductive layer 23 fills the gate trench 21, and the gate dielectric layer 22 wraps at least the sidewall of the gate conductive layer 23.

[0102] Specifically, the trench gate structure 2 penetrates through the current spreading layer 13, and there are multiple trench gate structures 2 arranged at intervals in the X direction on the upper surface of the semiconductor layer 1. While ensuring the device performance, the opening size, opening shape, and depth of the gate trench 21 can be selected according to the actual situation; the thickness of the gate dielectric layer 22 can be selected according to the actual situation; the number of trench gate structures 2 in the device and the distance between two adjacent trench gate structures 2 can be selected according to the actual situation. Here, the X direction refers to any direction parallel to the plane perpendicular to the stacking direction of the substrate 11 and the epitaxial layer 12, and the depth refers to the dimension in the stacking direction of the substrate 11 and the epitaxial layer 12.

[0103] Specifically, the material of the gate dielectric layer 22 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the material of the gate conductive layer 23 includes polysilicon or other suitable conductive materials. Preferably, N-type polysilicon is used as the gate conductive layer 23.

[0104] Specifically, the pillar region 15 is used to improve the electric field distribution of the device and enhance the breakdown voltage capability of the device. It is usually a normally doped region, and the projection pattern of the pillar region 15 in the stacking direction of the substrate 11 and the epitaxial layer 12 falls within the projection pattern of the gate trench 21 in this direction. Under the condition of ensuring the device performance, the doping concentration and thickness of the pillar region 15 can be selected according to the actual situation. The thickness here refers to the distance between the side wall of the pillar region 15 away from the deep trench structure 24 and the inner wall of the deep trench 25.

[0105] Specifically, the protection region 16 is usually a heavily doped region for protecting the bottom of the gate trench 21. It is used to share the high electric field in the epitaxial layer 12 to reduce the electric field intensity at the bottom of the trench gate structure 2 and the electric field pressure at the bottom of the trench gate structure 2. Under the condition of ensuring the device performance, the size, shape, and doping concentration of the protection region 16 can be selected according to the actual situation.

[0106] As an example, the protection region 16 is located on the top of the pillar region 15, and the pillar region 15 is connected to the body region 14 through the protection region 16 at the bottom of the trench gate structure 2, so as to form a superjunction between the pillar region 15 and the epitaxial layer 12, enhance the breakdown voltage capability of the device, and at the same time, the thickness of the epitaxial layer 12 can be relatively reduced and the doping concentration of the epitaxial layer 12 can be increased.

[0107] Specifically, since the protection region 16 is formed at the bottom of the trench gate structure 2, a parasitic JFET region is formed under the conductive channel of the device, and then a JFET resistance is introduced into the device. By forming a current spreading layer 13 with a relatively high doping concentration between the body region 14 and the epitaxial layer 12, the JFET resistance of the device can be reduced and the performance of the device can be improved.

[0108] As an example, the bottom surface of the deep trench structure 24 is located in the epitaxial layer 12 and is spaced from the upper surface of the substrate 11 by a preset distance. The pillar region 15 also wraps the bottom surface of the deep trench 25, that is, the deep trench structure 24 is embedded in the epitaxial layer 12 under the trench gate structure 2, as Figure 5 and Figure 6 shown.

[0109] Specifically, the deep trench structure 24 is embedded in the epitaxial layer 12 under the trench gate structure 2, and the bottom surface of the pillar region 15 is spaced from the upper surface of the substrate 11 by a preset distance. Under the condition of ensuring the device performance, the distance between the bottom surface of the deep trench structure 24 and the bottom surface of the epitaxial layer 12 can be selected according to the actual situation.

[0110] As an example, the deep trench structure 24 penetrates the epitaxial layer 12 and the bottom surface extends into the substrate 11, and the column region 15 only wraps the sidewalls of the deep trench structure 24 in the epitaxial layer 12, as Figure 3 , Figure 4 and Figure 7 shown.

[0111] Specifically, when the deep trench structure 24 penetrates the epitaxial layer 12, the distance between the bottom surface of the deep trench structure 24 and the bottom surface of the substrate 11 can be selected according to the actual situation while ensuring the device performance.

[0112] It should be noted that embedding the deep trench structure 24 in the epitaxial layer 12 below the trench gate structure 2 can reduce the process difficulty of fabricating the deep trench structure 24 compared with the structure where the deep trench structure 24 penetrates the epitaxial layer 12.

[0113] As an example, the deep trench structure 24 at least includes a deep trench 25 and a dielectric layer 26, and the dielectric layer 26 at least covers the inner wall and the bottom surface of the deep trench 25.

[0114] Specifically, the material of the dielectric layer 26 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

[0115] As an example, the dielectric layer 26 fills the deep trench 25, that is, the deep trench structure 24 is composed of the deep trench 25 and the dielectric layer 26 filling the deep trench 25, as Figure 7 shown.

[0116] Specifically, by filling the deep trench 25 with the dielectric layer 26, and then making the column region 15 interact with the drift region to form a superjunction structure, the process complexity of fabricating the column region 15 in the superjunction structure is reduced, and then the manufacturing cost can be reduced. At the same time, since the column regions 15 are formed synchronously, the longitudinal electric field fluctuation of the epitaxial layer 12 corresponding to the column regions 15 can be avoided, and the performance of the device is improved.

[0117] As an example, the deep trench structure 24 further includes a filling conductive layer 27 filling the deep trench 25, the dielectric layer 26 wraps the sidewalls and the bottom surface of the filling conductive layer 27, and the bottom surface of the gate conductive layer 23 is adjacent to the top surface of the filling conductive layer 27, that is, the gate conductive layer 23 is in electrical contact with the filling conductive layer 27.

[0118] As an example, the conductivity type of the filling conductive layer 27 includes one of the first conductivity type and the second conductivity type.

[0119] It should be noted that usually the doping concentration of the filling conductive layer 27 is a medium-low doping concentration, and its doping concentration is less than 5×10 -17 cm -3 .

[0120] Specifically, the conductivity type of the filling conductive layer 27 is the first conductivity type, asFigure 6 As shown, that is, the conductivity type of the filled conductive layer 27 is the same as that of the gate conductive layer 23, and the doping concentration of the filled conductive layer 27 is less than that of the gate conductive layer 23, which can reduce the process of the device. At the same time, it can avoid the generation of defects at the interface between the gate conductive layer 23 and the filled conductive layer 27, improve the breakdown voltage capability of the device while ensuring the performance of the device. In this embodiment, Figures 3 to 5 the conductivity type of the filled conductive layer 27 is the second conductivity type.

[0121] It should be noted that the filled conductive layer 27 is in electrical contact with the gate conductive layer 23, which can enable the filled conductive layer 27 in the deep trench structure 24 and the column region 15 outside the deep trench structure 24 to jointly act on the space charge region of the epitaxial layer 12, forming a dual auxiliary consumption structure combining a superjunction structure and charge balance, greatly improving the breakdown voltage capability of the device. At the same time, it greatly reduces the on-resistance of the device, improves the power density and FOM value of the device.

[0122] As an example, the thickness of the dielectric layer 26 at the bottom of the deep trench 25 is not less than 2 times the thickness of the dielectric layer 26 covering the inner wall of the deep trench 25.

[0123] Specifically, since the filled conductive layer 27 is electrically connected to the gate conductive layer 23, by making the dielectric layer 26 at the bottom of the deep trench 25 thicker, the breakdown voltage performance at the bottom of the deep trench 25 in the device can be ensured, and then the reliability of the device can be ensured.

[0124] Specifically, the dielectric layer 26 also covers the bottom surface of the gate trench 21, and the thickness of the dielectric layer 26 covering the bottom surface of the gate trench 21 is not less than the thickness of the gate dielectric layer 22, so as to utilize the thicker dielectric layer 26 at the bottom of the gate trench 21 and the protection region 16 at the bottom of the gate trench 21 to jointly resist the high electric field impact at the corner of the gate trench 21 and ensure the reliability of the device.

[0125] As an example, the bottom surface of the filled conductive layer 27 is not lower than the bottom surface of the column region 15, which reduces the filling process difficulty while enabling the filled conductive layer 27 to assist the column region 15 in consuming the charges in the epitaxial layer 12, optimizing the electric field distribution in the epitaxial layer 12, and improving the breakdown voltage performance of the device.

[0126] Specifically, under the condition of ensuring the device performance, the distance between the bottom surface of the filled conductive layer 27 and the bottom surface of the column region 15 can be selected according to the actual situation.

[0127] Specifically, the source region 17 is usually a heavily doped region. Under the condition of ensuring the device performance, the size, shape, thickness and doping concentration of the source region 17 can be selected according to the actual situation.

[0128] It should be noted that when the doping concentration of the body region 14 is relatively low and it is difficult to form a good ohmic contact with the first electrode 4, a second-conductivity-type contact region is further provided in the region where the body region 14 contacts the first electrode 4, and the contact region is adjacent to the side of the source region 17 away from the trench gate structure 2. The contact region is a heavily doped region, so as to form an ohmic contact between the first electrode 4 and the body region 14.

[0129] Specifically, under the condition of ensuring device performance, the thickness, size, shape, and doping concentration of the contact region can be selected according to the actual situation.

[0130] Specifically, an interlayer dielectric layer 3 covering the exposed upper surface of the semiconductor layer 1, the source region 17, and the trench gate structure 2 is further provided in the device. The interlayer dielectric layer 3 is usually used for insulation between the first electrode 4 and the gate in the front structure of the device. Under the condition of ensuring device performance, the thickness of the interlayer dielectric layer 3 can be selected according to the actual situation.

[0131] Specifically, a first contact hole 31 and a second contact hole penetrating the interlayer dielectric layer 3 are further provided in the interlayer dielectric layer 3. The bottom surface of the first contact hole 31 exposes the source region 17, and the bottom surface of the second contact hole exposes the gate conductive layer 23. The first electrode 4 fills the first contact hole 31 and covers a partial area on the upper surface of the interlayer dielectric layer 3. The gate fills the second contact hole and covers a partial area on the upper surface of the interlayer dielectric layer 3, and the gate is spaced from the first electrode 4 by a preset distance. The contact type between the first electrode 4 and the source region 17 is an ohmic contact.

[0132] It should be noted that when a contact region is provided in the body region 14, the bottom of the first contact hole 31 also exposes the contact region to realize the electrical connection between the first electrode 4 and the body region 14.

[0133] As an example, the first electrode 4 penetrates the body region 14 between two adjacent trench gate structures 2 and the bottom surface is lower than the bottom surface of the body region 14. There is a preset barrier height between the first electrode 4 and the current spreading layer 13.

[0134] It should be noted that when the first electrode 4 penetrates the body region 14 between two adjacent trench gate structures 2, a third contact hole 32 penetrating the body region 14 is further provided in the semiconductor layer 1 at the bottom of the first contact hole 31. The bottom surface of the third contact hole 32 extends at least into the current spreading layer 13, and the first electrode 4 also fills the third contact hole 32.

[0135] Specifically, on the premise of ensuring device performance, the opening size, shape, and depth of the third contact hole 32 can be selected according to actual circumstances. Preferably, the depth of the third contact hole 32 is the same as that of the gate trench 21, and the third contact hole 32 penetrates the middle region of the body region 14 between two adjacent gate trenches 21. Here, the depth refers to the distance between the bottom surface of the third contact hole 32 (gate trench 21) and the upper surface of the body region 14.

[0136] As an example, a second conductivity type doping region 18 is further provided in the epitaxial layer 12 at the bottom of the first electrode 4, and the doping region 18 at least wraps the bottom of the first electrode 4 extending into the epitaxial layer 12.

[0137] It should be noted that the first electrode 4 penetrates the body region 14 between two adjacent trench gate structures 2 and forms a Schottky contact with a low barrier with the current spreading layer 13, and the barrier height can be selected according to actual circumstances. At the same time, when a doping region 18 is provided in the epitaxial layer 12 at the bottom of the first electrode 4, that is, when the doping region 18 wraps the bottom of the third contact hole 32, at least part of the doping region 18 is usually in communication with the body region 14 (not shown), and the doping region 18 is a heavily doped region, so as to form an ohmic contact between the first electrode 4 and the doping region 18, and then realize the electrical connection between the first electrode 4 and the body region 14.

[0138] Specifically, through the setting of the doping region 18, the doping region 18 and the protection regions 16 on both sides thereof can jointly share the high electric field in the epitaxial layer 12, and then further reduce the electric field strength at the bottom of the trench gate structure 2 and improve the reliability of the device.

[0139] Specifically, when the first electrode 4 penetrates the body region 14, on the premise of ensuring device performance, the distance between the first electrode 4 and the bottom surface of the epitaxial layer 12 can be selected according to actual circumstances; the contact barrier height between the first electrode 4 and the current spreading layer 13 can be selected according to actual circumstances; the doping concentration, size, and shape of the doping region 18 at the bottom of the first electrode 4 can be selected according to actual circumstances.

[0140] Specifically, the gate is located on the upper surface of the interlayer dielectric layer 3 and is spaced a preset distance from the first electrode 4, and the gate penetrates the interlayer dielectric layer 3 and is electrically connected to the gate conductive layer 23 in the trench gate structure 2.

[0141] Specifically, a second conductivity type collector region with a preset thickness is further provided on the lower surface layer of the semiconductor layer 1, the second electrode 5 is electrically connected to the collector region, and the contact type between the second electrode 5 and the collector region is an ohmic contact, that is, the device is an IGBT device.

[0142] Specifically, when the device is an IGBT device, the doping concentration and thickness of the collector region can be selected according to actual circumstances.

[0143] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or other suitable dielectric materials; the materials of the first electrode 4, the gate electrode, and the second electrode 5 are usually common electrode materials, which will not be elaborated here.

[0144] Specifically, as Figure 8 and Figure 9 shown, respectively Figure 1 the longitudinal electric field intensity of the device in Figure 3 and the device in Figure 1 (the electric field intensity from the upper surface of the body region 14 to the bottom surface of the substrate 11, such as Figure 3 the AA cross-section in Figure 2 and the CC cross-section in Figure 3 ), and the longitudinal electric field intensity of the device in Figure 2 and the device in Figure 3 (the electric field intensity from the upper surface of the body region 14 to the bottom surface of the substrate 11, such as Figure 1 the BB cross-section in Figure 3 and the CC cross-section in Figure 3 ), where the parameters of the same parts of the device in Figure 1 and the device in Figure 3 are the same. Compared with the device in Figure 2 the device in Figure 3 only adds a deep trench structure 24 with a filled conductive layer 27 of the second conductivity type with low doping and a column region 15 communicating with the body region 14. The bottom of the deep trench 25 extends into the substrate 11 and the filled conductive layer 27 is electrically connected to the bottom of the gate conductive layer 23. It can be seen from the figure that by the combined action of the filled conductive layer 27 and the column region 15, Figure 3 the triangular electric field in the drift region of the device in Figure 3 is flattened, so that the electric field in the drift region is evenly distributed, and the longitudinal electric field of the entire device is trapezoidally distributed, thereby improving the breakdown voltage of the device and reducing the on-resistance of the device;

[0145] Specifically, by forming at least a deep trench structure 24 embedded in the epitaxial layer 12 at the bottom of the trench gate structure 2, the arrangement of the deep trench structure 24 can facilitate the formation of a column region 15 communicating with the body region 14 in the epitaxial layer 12, thereby forming a trench gate superjunction device, reducing its cell size, improving the electric field distribution in the epitaxial layer 12, enhancing the breakdown voltage capability of the device, reducing the on-resistance of the device, increasing the power density of the device, and improving the performance of the device.

[0146] Specifically, by forming a protection region 16 in the epitaxial layer 12 at the bottom of the trench gate structure 2, the combination of the protection region 16 and the relatively thick dielectric layer 26 at the bottom of the gate trench 21 is used to resist the high electric field impact at the bottom and corners of the gate trench 21, avoiding premature breakdown at the bottom of the trench gate structure 2 and enhancing the reliability of the device.

[0147] Specifically, by providing a current spreading layer 13 with a relatively high doping concentration below the body region 14, the JFET resistance introduced by the arrangement of the protection region 16 can be reduced, thereby reducing the on-resistance of the device and improving the performance of the device.

[0148] Specifically, by making the first electrode 4 penetrate through the body region 14 and form a Schottky contact with a preset barrier with the current spreading layer 13, and simultaneously forming a heavily doped doping region 18 at the bottom of the first electrode 4 in the epitaxial layer 12, the doping region 18 and the protection regions 16 on both sides thereof jointly share the electric field in the epitaxial layer 12, which can further reduce the electric field strength at the bottom of the trench gate structure 2 and enhance the reliability of the device.

[0149] Specifically, a filling conductive layer 27 with a medium-low doping concentration and electrically connected to the gate conductive layer 23 is provided in the deep trench structure 24. The filling conductive layer 27 assists the column region 15 to consume the charges in the epitaxial layer 12 of the device, reducing the electric field strength around the dielectric layer 26 and depleting the charges in the drift region before the dielectric layer 26 breaks down, enhancing the breakdown voltage capability of the device.

[0150] The semiconductor device of this embodiment improves the device structure by providing at least a deep trench structure 24 embedded in the epitaxial layer 12 below the trench gate structure 2, and at the same time providing a column region 15 that wraps the sidewalls of the deep trench structure 24 in the epitaxial layer 12. The column region 15 is connected to the body region 14 through a protection region 16 at the bottom of the trench gate structure 2, thereby forming a superjunction structure in the device, reducing the cell size of this type of device, optimizing the electric field distribution in the epitaxial layer 12, reducing the on-resistance of the device, and improving the power density of the device. At the same time, due to the use of the protection region 16, premature breakdown at the bottom of the trench gate structure 2 is avoided, improving the reliability of the device. Then, a current spreading layer 13 with a higher doping concentration is used to reduce the JFET resistance generated by the introduction of the protection region 16, improving the performance of the device; a filling conductive layer 27 with a medium-low doping concentration and electrically connected to the gate conductive layer 23 is provided in the deep trench structure 24, which can further optimize the electric field distribution in the epitaxial layer 12. At the same time, the filling conductive layer 27 can be used to assist the column region 15 in consuming the charges in the epitaxial layer 12, depleting the epitaxial layer 12 before the dielectric layer 26 breaks down, further improving the breakdown voltage capability of the device and reducing the on-resistance of the device. In addition, by making the first electrode 4 penetrate the body region 14 and the current spreading layer 13 provided between adjacent two trench gate structures 2 and form a Schottky contact with the current spreading layer 13, and making the doping region 18 wrap the bottom of the first electrode 4 extending into the epitaxial layer 12, the doping region 18 and the protection regions 16 on both sides thereof can jointly share the electric field in the epitaxial layer 12, thereby further reducing the electric field strength at the bottom of the trench gate structure 2 and improving the reliability of the device.

[0151] Embodiment 2

[0152] This embodiment also provides a method for manufacturing a semiconductor device. As Figure 10 shown, it is a process flow chart of the method for manufacturing the semiconductor device, including the following steps:

[0153] S1: Provide a semiconductor layer including a first-conductivity-type substrate, a first-conductivity-type epitaxial layer, and a second-conductivity-type body region stacked in layers in sequence;

[0154] S2: Form a trench gate structure, a deep trench structure, a second-conductivity-type column region, and a second-conductivity-type protection region. The trench gate structure penetrates the body region. The deep trench structure is at least embedded in the epitaxial layer below the trench gate structure. The cross-sectional dimension of the trench gate structure perpendicular to the stacking direction of the substrate and the epitaxial layer is larger than the cross-sectional dimension of the deep trench structure. The column region at least wraps the sidewalls of the deep trench structure in the epitaxial layer and is connected to the body region. The protection region is located at the bottom of the trench gate structure;

[0155] S3: Form a first-conductivity-type source region on the upper surface of the body region and adjacent to the trench gate structure on one side of the trench gate structure;

[0156] S4: Form a first electrode electrically connected to the source region, a second electrode electrically connected to the bottom of the semiconductor layer, and a gate electrode electrically connected to the trench gate structure.

[0157] Please refer to Figures 11 to 17 , and perform step S1 and step S2: Provide a semiconductor layer 1 including a first-conductivity-type substrate 11, a first-conductivity-type epitaxial layer 12, and a second-conductivity-type body region 14 stacked in sequence; form a trench gate structure 2, a deep trench structure 24, a second-conductivity-type column region 15, and a second-conductivity-type protection region 16. The trench gate structure 2 penetrates the body region 14, the deep trench structure 24 is at least embedded in the epitaxial layer 12 below the trench gate structure 2, the cross-sectional dimension of the trench gate structure 2 perpendicular to the stacking direction of the substrate 11 and the epitaxial layer 12 is larger than the cross-sectional dimension of the deep trench structure 24, the column region 15 at least wraps the sidewalls of the deep trench structure 24 in the epitaxial layer 12 and communicates with the body region 14, and the protection region 16 is located at the bottom of the trench gate structure 2.

[0158] Specifically, as Figure 11 shown, it is a schematic cross-sectional structure diagram of the semiconductor layer 1. A first-conductivity-type current spreading layer 13 is further provided in the semiconductor layer 1 on the upper surface of the epitaxial layer 12, and the upper surface of the current spreading layer 13 is adjacent to the bottom surface of the body region 14.

[0159] It should be noted that generally, the epitaxial layer 12 in the semiconductor layer 1 is epitaxially formed on the substrate 11 through a common epitaxial process. The current spreading layer 13 can be epitaxially obtained on the upper surface of the epitaxial layer 12, or corresponding ions can be implanted into the upper surface layer of the epitaxial layer 12 through an ion implantation process. The body region 14 can be epitaxially obtained on the upper surface of the current spreading layer 13, or corresponding ions can be implanted into the upper surface layer of the current spreading layer 13 through an ion implantation process. Preferably, corresponding ions are implanted into the upper surface layer of the epitaxial layer 12 through a high-temperature high-energy ion implantation process to form the current spreading layer 13, and annealing is performed after forming the current spreading layer 13. After annealing, corresponding ions are implanted into the upper surface layer of the current spreading layer 13 through an ion implantation process to form the body region 14.

[0160] Specifically, forming the trench gate structure 2, the deep trench structure 24, the column region 15 and the protection region 16 includes the following steps: forming a plurality of gate trenches 21 spaced along the X direction on the upper surface layer of the semiconductor layer 1, the gate trenches 21 penetrating through the body region 14 and the current spreading layer 13; forming the protection region 16 in the epitaxial layer 12 at the bottom of the gate trenches 21, and forming a deep trench 25 penetrating through the protection region 16 and having a bottom surface spaced from the bottom surface of the substrate 11 by a preset distance at the bottom of the gate trenches 21, the cross-sectional dimension of the deep trench 25 perpendicular to the stacking direction of the substrate 11 and the epitaxial layer 12 being smaller than the dimension of the gate trenches 21; forming the column region 15 at least covering the side walls of the deep trench 25 in the epitaxial layer 12 and having an upper surface adjacent to the bottom surface of the protection region 16; forming a dielectric layer 26 covering the inner wall and the bottom surface of the deep trench 25 to obtain the deep trench structure 24 including the deep trench 25; forming a gate dielectric layer 22 covering the inner wall of the gate trenches 21 and a gate conductive layer 23 filling the gate trenches 21.

[0161] Specifically, as Figure 12 and Figure 13 shown, they are respectively a schematic cross-sectional structure diagram after forming the gate trenches 21 and a schematic cross-sectional structure diagram after forming the protection region 16. The method for forming the gate trenches 21 includes dry etching, wet etching or other suitable methods; the method for forming the protection region 16 includes ion implantation or other suitable methods. Preferably, a corresponding high-energy ion is implanted into the bottom of the gate trenches 21 by an ion implantation process to form the heavily doped protection region 16.

[0162] It should be noted that, in order to facilitate the subsequent connection between the formed column region 15 and the body region 14 to form a superjunction structure, usually a part of the protection region 16 formed at the bottom of the gate trenches 21 also needs to be connected to the body region 14 (this region is not shown).

[0163] Specifically, usually after forming the protection region 16 and before forming the deep trench 25, a sacrificial layer covering the inner wall and the bottom surface of the gate trenches 21 and covering the exposed upper surface of the body region 14 needs to be formed to facilitate the subsequent spin coating of the photoresist for fabricating the deep trench 25.

[0164] It should be noted that usually a sacrificial layer is formed by a thermal oxidation process to remove the damage caused by ion implantation on the upper surface layer of the body region 14 while forming the sacrificial layer.

[0165] Specifically, as Figure 14 shown, it is a schematic cross-sectional structure diagram after forming the deep trench 25. The bottom surface of the deep trench 25 can extend into the substrate 11, that is, the deep trench 25 penetrates through the epitaxial layer 12 below the gate trenches 21, or can be located in the epitaxial layer 12 and be spaced from the bottom surface of the epitaxial layer 12 by a preset distance. And when the bottom surface of the deep trench 25 is located in the epitaxial layer 12, the difficulty of the etching process for forming the deep trench 25 can be reduced.

[0166] Specifically, the deep trench 25 also penetrates the sacrificial layer at the bottom of the gate trench 21. The method for forming the deep trench 25 includes dry etching, wet etching, or other suitable methods.

[0167] Specifically, as Figure 15 shown, it is a schematic cross-sectional structure diagram after the formation of the column region 15. The method for forming the column region 15 includes ion implantation or other suitable methods. In this embodiment, based on the photoresist layer for forming the deep trench 25, ion implantation is performed on the sidewalls of the deep trench 25 at a preset implantation angle to form the column region 15 that wraps the sidewalls of the deep trench 25 in the epitaxial layer 12. After the formation of the column region 15, the photoresist layer is removed by wet stripping or ashing process.

[0168] It should be noted that when the bottom surface of the deep trench 25 extends into the substrate 11, generally the column region 15 only covers the sidewalls of the deep trench 25 in the epitaxial layer 12. When the bottom surface of the deep trench 25 is located in the epitaxial layer 12, the column region 15 generally also wraps the bottom surface of the deep trench 25, and the bottom surface of the column region 15 is not lower than the upper surface of the substrate 11.

[0169] Specifically, the method for forming the dielectric layer 26 includes thermal oxidation or other suitable methods. Preferably, a thick oxide layer that covers at least the inner wall and the bottom surface of the deep trench 25 is formed by a high-temperature dry oxygen oxidation process as the dielectric layer 26.

[0170] Specifically, the deep trench structure 24 includes the deep trench 25, the dielectric layer 26, and the filling conductive layer 27 that fills the deep trench 25, or only includes the dielectric layer 26 and the deep trench 25.

[0171] Specifically, when the deep trench structure 24 only includes the deep trench 25 and the dielectric layer 26, the column region 15 that wraps the sidewalls of the deep trench 25 serves as a doped column for forming the superjunction structure, which can simplify the manufacturing process of the column region 15 of the superjunction device.

[0172] It should be noted that when the deep trench structure 24 includes the deep trench 25, the dielectric layer 26, and the filling conductive layer 27, during the formation of the dielectric layer 26, the process needs to be regulated so that the thickness of the dielectric layer 26 covering the bottom surface of the deep trench 25 is not less than 2 times the thickness of the dielectric layer 26 covering the inner wall of the deep trench 25 to ensure the breakdown voltage capability at the bottom of the deep trench structure 24.

[0173] Specifically, as Figure 16As shown, it is a schematic cross-sectional structure diagram after forming the filled conductive layer 27. When the deep trench structure 24 includes a deep trench 25, a dielectric layer 26, and a filled conductive layer 27, after forming the dielectric layer 26, it is also necessary to form the filled conductive layer 27 that fills the deep trench 25. The method of forming the filled conductive layer 27 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. Preferably, the LPCVD process is used to form the filled conductive layer 27.

[0174] Specifically, as Figure 17 shown, it is a schematic cross-sectional structure diagram after forming the gate conductive layer 23. The gate conductive layer 23 includes polysilicon or other suitable conductive materials. Preferably, polysilicon of the first conductivity type is used as the gate conductive layer 23.

[0175] It should be noted that when the filled conductive layer 27 is provided in the deep trench structure 24, the conductivity type of the filled conductive layer 27 can be the first conductivity type or the second conductivity type. When the conductivity type of the filled conductive layer 27 is the same as that of the gate conductive layer 23, under the condition of ensuring device performance, the filled conductive layer 27 can be formed synchronously with the gate conductive layer 23 or formed step by step. That is, the sacrificial layer covering the inner wall of the gate trench 21 can be removed first and the gate dielectric layer 22 covering the inner wall of the gate trench 21 can be formed, and then the filled conductive layer 27 located in the deep trench 25 and the gate conductive layer 23 filling the gate trench 21 are formed synchronously. Or the filled conductive layer 27 that fills the deep trench 25 can be formed first, and then the excess filled conductive layer 27 outside the deep trench 25 is removed, and the sacrificial layer covering the inner wall of the gate trench 21 is removed and the gate dielectric layer 22 covering the inner wall of the gate trench 21 is formed, and then the gate conductive layer 23 filling the gate trench 21 is formed, and the gate conductive layer 23 is in electrical contact with the filled conductive layer 27. When the conductivity types of the gate conductive layer 23 and the filled conductive layer 27 are different, it is necessary to form the filled conductive layer 27 first, and then form the gate dielectric layer 22 and the gate conductive layer 23.

[0176] Specifically, the method of forming the gate dielectric layer 22 includes thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods; the method of forming the gate conductive layer 23 includes chemical vapor deposition, physical vapor deposition, or other suitable methods; the method of removing the sacrificial layer covering the inner wall of the gate trench 21 includes dry etching, wet etching, or other suitable methods.

[0177] It should be noted that after removing the sacrificial layer covering the inner wall of the gate trench 21, the remaining thick sacrificial layer at the bottom of the gate trench 21 serves as a part of the dielectric layer 26 to jointly protect the bottom of the gate trench 21 with the protection area 16, avoiding premature breakdown at the corners of the gate trench 21 and improving the breakdown voltage performance of the device.

[0178] Please refer to Figures 18 to 19, perform step S3 and step S4: form a first conductive type source region 17 located on the upper surface of the body region 14 and adjacent to the trench gate structure 2 on one side close to the trench gate structure 2; form a first electrode 4 electrically connected to the source region 17, a second electrode 5 electrically connected to the bottom of the semiconductor layer 1, and a gate electrode electrically connected to the trench gate structure 2.

[0179] Specifically, as Figure 18 shown, it is a schematic cross-sectional structure diagram after forming the source region 17. The method for forming the source region 17 includes ion implantation or other suitable methods.

[0180] Specifically, after forming the source region 17 and before forming the first electrode 4, it further includes the step of forming an interlayer dielectric layer 3 covering the exposed surfaces of the body region 14, the source region 17, and the trench gate structure 2.

[0181] It should be noted that when the doping concentration of the body region 14 is relatively low and it is difficult to form an ohmic contact with the subsequent formed first electrode 4, usually after forming the trench gate structure 2 and before forming the interlayer dielectric layer 3, a second conductive type contact region adjacent to the side of the source region 17 far from the trench gate structure 2 and having a relatively high doping concentration needs to be formed to achieve an ohmic contact between the first electrode 4 and the body region 14.

[0182] Specifically, the method for forming the contact region includes ion implantation or other suitable methods.

[0183] Specifically, the method for forming the interlayer dielectric layer 3 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. In this embodiment, after forming the source region 17 and before forming the first electrode 4, a silicon oxide layer and a borophosphosilicate glass (BPSG) layer are sequentially deposited as the interlayer dielectric layer 3.

[0184] Specifically, as Figure 19 shown, it is a schematic cross-sectional structure diagram after forming the first contact hole 31. Forming the first electrode 4 and the gate electrode includes the following steps: forming a first contact hole 31 and a second contact hole (not shown) penetrating the interlayer dielectric layer 3. The bottom surface of the first contact hole 31 exposes the source region 17, and the bottom surface of the second contact hole exposes the gate conductive layer 23; forming a first electrode 4 and a gate electrode respectively filling the first contact hole 31 and the second contact hole.

[0185] Specifically, the method for forming the first contact hole 31 and the second contact hole includes dry etching, wet etching, or other suitable methods.

[0186] It should be noted that when the distance between two adjacent trench gate structures 2 is relatively large, a third contact hole 32 penetrating the body region 14 may be formed at the bottom of the first contact hole 31, and a second conductivity type doping region 18 may be formed at the bottom of the third contact hole 32. The bottom surface of the third contact hole 32 extends at least into the current spreading layer 13, and the doping region 18 is located in the epitaxial layer 12 and wraps the bottom of the third contact hole 32. Preferably, the doping concentration of the doping region 18 is the same as that of the protection region 16, and their bottom surfaces are on the same horizontal plane.

[0187] Specifically, the method for forming the third contact hole 32 includes dry etching, wet etching, or other suitable methods; the method for forming the doping region 18 includes ion implantation or other suitable methods.

[0188] Specifically, when ensuring the device performance, the opening size and shape of the first contact hole 31 can be selected according to the actual situation; the opening size and shape of the second contact hole can be selected according to the actual situation; the opening size and shape of the third contact hole 32 can be selected according to the actual situation.

[0189] Specifically, as Figure 3 shown, it is a schematic cross-sectional structure diagram after forming the second electrode 5. The methods for forming the first electrode 4, the gate electrode, and the second electrode 5 are common electrode formation methods and will not be elaborated here.

[0190] Specifically, when the device is an IGBT device, before forming the second electrode 5, a second conductivity type collector region needs to be formed on the lower surface layer of the substrate 11, and the second electrode 5 is electrically connected to the collector.

[0191] Specifically, the method for forming the collector region includes ion implantation or other suitable methods.

[0192] Specifically, by forming a deep trench 25 in the epitaxial layer 12 at the bottom of the gate trench 21 and forming a column region 15 based on the deep trench 25, the process complexity and difficulty of manufacturing the column region 15 of the superjunction structure are reduced. At the same time, the process of the column region 15 is made consistent, the longitudinal electric field distribution in the epitaxial layer 12 of the device is made more uniform, and the performance of the device is improved.

[0193] Specifically, by forming a filling conductive layer 27 with a medium and low doping concentration and electrically connected to the gate conductive layer 23 in the deep trench 25, the electric field distribution in the epitaxial layer 12 can be further optimized. At the same time, before the dielectric layer 26 breaks down, it can assist the column region 15 to deplete the charges in the epitaxial layer 12, further improving the breakdown voltage and reliability of the device.

[0194] The method for manufacturing a semiconductor device according to this embodiment forms a deep trench 25 in the epitaxial layer 12 at the bottom of the gate trench 21, and synchronously forms a column region 15 that wraps the sidewalls of the deep trench 25 based on the deep trench 25, reducing the process difficulty and process complexity of manufacturing the column region 15, ensuring the consistency of the doping process in each region of the column region 15, making the longitudinal electric field distribution in the epitaxial layer 12 more uniform. At the same time, a dielectric layer 26 and a filling conductive layer 27 with a medium and low doping concentration and electrically connected to the gate conductive layer 23 are formed in the deep trench 25, further improving the breakdown voltage capability and reliability of the device.

[0195] In summary, the semiconductor device and its manufacturing method according to the present invention improve the device structure, form a deep trench structure in the epitaxial layer at the bottom of the gate trench, which facilitates the formation of a column region connected to the body region, reduces the manufacturing difficulty of the column region, simplifies the manufacturing process of the column region. At the same time, since the column region is connected to the body region, a superjunction structure can be formed, reducing the cell size of this type of device, optimizing the electric field distribution in the epitaxial layer, reducing the on-resistance of the device, improving the breakdown voltage capability and power density of the device, enhancing the FOM value of the device. And because the column region is synchronously formed based on the deep trench, the consistency of the column region process is ensured, making the longitudinal electric field distribution in the epitaxial layer more uniform; by providing a filling conductive layer with a medium and low doping concentration and electrically connected to the gate conductive layer in the deep trench structure, the electric field distribution in the epitaxial layer can be further improved, using the filling conductive layer to assist the column region in consuming charges in the epitaxial layer, depleting the epitaxial layer before the dielectric layer breaks down, further enhancing the breakdown voltage capability of the device and reducing the on-resistance of the device; by making the first electrode penetrate through the body region and the current spreading layer provided between adjacent trench gate structures and form a Schottky contact with the current spreading layer, and at the same time making the doping region wrap around the bottom of the first electrode extending into the epitaxial layer, the doping region and the protection regions on both sides thereof can jointly share the electric field in the epitaxial layer, thereby further reducing the electric field intensity at the bottom of the trench gate structure and enhancing the reliability of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0196] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that: include: The semiconductor layer comprises a first conductive type substrate, a first conductive type epitaxial layer and a second conductive type body region stacked in sequence; A trench gate structure extending through the body region; A deep trench structure, at least embedded in the epitaxial layer below the trench gate structure, and the cross-sectional dimension of the trench gate structure perpendicular to the stacking direction of the substrate and the epitaxial layer is larger than the cross-sectional dimension of the deep trench structure; A second conductive type column region at least wraps around the sidewall of the deep trench structure in the epitaxial layer and is connected to the body region; A second conductive type protection zone is located at the bottom of the trench gate structure; A first conductive type source region, located on an upper surface layer of the body region and adjacent to a side of the trench gate structure close to the trench gate structure; a first electrode, electrically connected to the source region; a second electrode electrically connected to the bottom of the semiconductor layer; A gate is electrically connected to the trench gate structure.

2. The semiconductor device according to claim 1, wherein: The semiconductor layer is also provided with a first conductive type current spreading layer located on the upper surface of the epitaxial layer and having an upper surface adjacent to the bottom surface of the body region, and the trench gate structure penetrates the current spreading layer.

3. The semiconductor device according to claim 2, wherein: The first electrode penetrates the body region between two adjacent trench gate structures and has a bottom surface lower than a bottom surface of the body region. A preset barrier height is provided between the first electrode and the current spreading layer.

4. The semiconductor device according to claim 3, wherein: A second conductive type doped region is further provided in the epitaxial layer at the bottom of the first electrode, and the doped region at least wraps around the bottom of the first electrode extending into the epitaxial layer.

5. The semiconductor device according to claim 1, wherein: The bottom surface of the deep trench structure is located in the epitaxial layer and is spaced apart from the upper surface of the substrate by a preset distance, and the column region also wraps the bottom surface of the deep trench.

6. The semiconductor device according to claim 1, wherein: The deep trench structure penetrates the epitaxial layer and has a bottom surface extending into the substrate.

7. The semiconductor device according to claim 1, wherein: The deep trench structure at least includes a deep trench and a dielectric layer, and the dielectric layer at least covers the inner wall and bottom surface of the deep trench.

8. The semiconductor device according to claim 7, wherein: The dielectric layer fills the deep trench.

9. The semiconductor device according to claim 7, wherein: The deep trench structure further includes a filling conductive layer filling the deep trench, the dielectric layer wraps the sidewall and bottom surface of the filling conductive layer, and the bottom surface of the gate conductive layer is adjacent to the top surface of the filling conductive layer.

10. The semiconductor device according to claim 9, wherein: The conductive type of the filling conductive layer includes one of a first conductive type and a second conductive type.

11. The semiconductor device according to claim 9, wherein: The thickness of the dielectric layer at the bottom of the deep trench is not less than twice the thickness of the dielectric layer covering the inner wall of the deep trench.

12. The semiconductor device according to claim 9, wherein: The bottom surface of the filled conductive layer is not lower than the bottom surface of the column region.

13. The semiconductor device according to claim 1, wherein: The protection zone is located at the top of the column region, and the column region is connected with the body region through the protection zone located at the bottom of the trench gate structure.

14. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a semiconductor layer including a first conductive type substrate, a first conductive type epitaxial layer and a second conductive type body region stacked in sequence; A trench gate structure, a deep trench structure, a second conductive type column region and a second conductive type protection region are formed, wherein the trench gate structure penetrates the body region, the deep trench structure is at least embedded in the epitaxial layer below the trench gate structure, the cross-sectional dimension of the trench gate structure perpendicular to the stacking direction of the substrate and the epitaxial layer is larger than the cross-sectional dimension of the deep trench structure, the column region at least wraps around the sidewall of the deep trench structure in the epitaxial layer and is connected to the body region, and the protection region is located at the bottom of the trench gate structure; forming a first conductive type source region located on the upper surface of the body region and close to one side of the trench gate structure and adjacent to the trench gate structure; A first electrode electrically connected to the source region, a second electrode electrically connected to the bottom of the semiconductor layer, and a gate electrically connected to the trench gate structure are formed.

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