Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a source region; a drain region; a drift region between the source region and the drain region; a gate between the source region and the drain region; the doping concentration of the first conductive type buried region is larger than that of the drift region, and at least part of the drift region is located on the first conductive type buried region; the first groove structure is located on the side, away from the grid electrode, of the source electrode region, the bottom of the first groove structure extends into the first conductive type buried region, the first groove structure comprises a first conductive structure located in the first groove and a first insulating layer located on the side wall of the first groove, and the first insulating layer is used for conducting insulating isolation on the side face of the first conductive structure; the first conductive structure is shorted to the gate. Current can be introduced into the first conductive type buried region as much as possible, and the reliability of the device can be improved. And the arrangement of the first conductive type buried region can further reduce the specific on-resistance of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular, to a semiconductor device, and also relates to a manufacturing method of a semiconductor device. Background Art

[0002] The RESURF (Reduced Surface Field) technology of LDMOS (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) has evolved from single to double and then to triple RESURF, and the specific on-resistance advantage is getting greater and greater. However, at the same time, it will also bring other problems to the device. An exemplary LDMOS, when conducting, the current tends to concentrate on the surface of the device and flow, resulting in the re-modulation of the on-state space charge. High-density electrons cover the drift region, accelerating the depletion of the drift region, generating a strong electric field on the surface of the drain end of the device. The high electric field peak on the device surface makes the HCI (Hot Carrier Injection) degradation faster, and the surface of the drain end of the device is easily broken down in advance when the device is in the on-state, affecting the reliability of the device. Summary of the Invention

[0003] Based on this, it is necessary to provide a semiconductor device and a manufacturing method thereof that can improve the reliability of the device.

[0004] A semiconductor device includes: a source region having a first conductivity type; a drain region having a first conductivity type; a drift region, at least a part of the drift region is located between the source region and the drain region; a gate located above the region between the source region and the drain region; a buried region of the first conductivity type with a doping concentration higher than that of the drift region, at least a part of the drift region is located on the buried region of the first conductivity type; a first trench structure located on the side of the source region facing away from the gate, the bottom of the first trench structure extends into the buried region of the first conductivity type, the first trench structure includes a first conductive structure located in the first trench and a first insulating layer located on the side wall of the first trench, and the first insulating layer is used for insulating isolation of the side surface of the first conductive structure; the first conductive structure is short-circuited and connected to the gate.

[0005] In the above semiconductor device, the first conductive structure is short-circuited and connected to the gate, introducing a potential to the depth where the buried region of the first conductivity type is located inside the device when the device conducts. When conducting, an electron inversion layer is generated inside the device, which is equivalent to adding an in-device channel, so that the current can be introduced into the buried region of the first conductivity type as much as possible, thereby guiding the current path when the device conducts from the device surface to the device body, and improving the reliability of the device. And setting the buried region of the first conductivity type can further reduce the specific on-resistance of the device.

[0006] In one of the embodiments, the semiconductor device is a silicon-on-insulator semiconductor device, including a substrate and an insulating buried layer on the substrate, and the first conductive type buried region is in direct contact with the insulating buried layer.

[0007] In one embodiment, the substrate is a silicon substrate, and the material of the insulating buried layer is silicon oxide.

[0008] In one of the embodiments, the semiconductor device further includes a second conductivity type well region, the source region is located in the second conductivity type well region, the bottom of the second conductivity type well region extends to the first conductivity type buried region, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0009] In one embodiment, the semiconductor device further includes: a second conductivity type buried region located in the drift region between the source region and the drain region; a top doping located in the drift region between the source region and the drain region and above the second conductivity type buried region, the top doping having a first conductivity type and a doping concentration greater than a doping concentration of the drift region.

[0010] In one of the embodiments, the bottom of the first conductive structure and the bottom of the first insulating layer extend to the buried insulating layer.

[0011] In one of the embodiments, the semiconductor device also includes a second trench structure, which is located on the side of the drain region away from the gate, and the bottom of the second trench structure extends into the first conductive type buried region, and the second trench structure includes a second conductive structure located in the second trench and a second insulating layer located on the sidewall of the second trench; the second conductive structure is short-circuited to the drain region.

[0012] In one embodiment, the bottom of the second conductive structure and the bottom of the second insulating layer extend to the buried insulating layer.

[0013] In one embodiment, the bottom of the second conductive structure is deeper than the bottom of the second insulating layer, so as to be electrically connected to the first conductive type buried region.

[0014] In one of the embodiments, the semiconductor device further includes: a second conductivity type doped region located in the second conductivity type well region, and the source region is located on both sides of the second conductivity type doped region.

[0015] In one embodiment, the semiconductor device further includes: a field oxide layer located between the source region and the drain region, and the gate extends from an edge of the source region to the field oxide layer.

[0016] In one embodiment, the semiconductor device further includes a well region of a first conductivity type, and the drain region is located in the well region of the first conductivity type.

[0017] In one embodiment, the semiconductor device is an LDMOS.

[0018] In one embodiment, the semiconductor device is an N-channel LDMOS, the first conductivity type is N-type, and the second conductivity type is P-type.

[0019] A method for manufacturing a semiconductor device includes: obtaining a wafer formed with a buried region of a first conductivity type and a drift region, the drift region having a first conductivity type and the doping concentration of the buried region of the first conductivity type being greater than that of the drift region, and at least part of the drift region being located on the buried region of the first conductivity type; etching to form a first trench with a bottom extending into the buried region of the first conductivity type, and filling an insulating medium in the first trench; forming a gate; ion-implanting ions of the first conductivity type to form a source region and a drain region in the drift region below both sides of the gate; filling a conductive material into the first trench to form a first conductive structure, and the side surface of the first conductive structure being insulated and isolated by a first insulating layer formed by the insulating medium; short-circuiting the first conductive structure and the gate; wherein the step of etching to form a first trench with a bottom extending into the buried region of the first conductivity type and filling an insulating medium in the first trench is performed before the step of forming the gate, or after the step of forming a source region and a drain region in the drift region below both sides of the gate.

[0020] In the above method for manufacturing a semiconductor device, the formed first conductive structure is short-circuited with the gate, introducing a potential to the depth where the buried region of the first conductivity type is located inside the device when the device is turned on. When the device is turned on, an electron inversion layer is generated inside the device, which is equivalent to adding a channel inside the device body. In this way, the current can be introduced into the buried region of the first conductivity type as much as possible, so that the current path when the device is turned on is guided from the surface of the device to the inside of the device, which can improve the device reliability. And setting the buried region of the first conductivity type can further reduce the specific on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, and the currently understood best mode of these inventions.

[0022] Figure 1 It is a schematic structural diagram of a semiconductor device in an embodiment of the present application.

[0023] Figure 2 It is a schematic structural diagram of a semiconductor device in another embodiment of the present application.

[0024] Figure 3 It is a schematic structural diagram of a semiconductor device in yet another embodiment of the present application.

[0025] Figure 4 It is a flowchart of a method for manufacturing a semiconductor device in an embodiment of the present application.

[0026] Figure 5 It is a flowchart of a method for manufacturing a semiconductor device in still another embodiment of the present application. Detailed implementation manners

[0027] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0029] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be denoted as the second element, component, region, layer or part.

[0030] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0031] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0032] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shown shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present invention should not be limited to the particular shapes of regions shown herein but should include shape deviations due to, for example, manufacturing. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present invention.

[0033] The semiconductor field vocabulary used herein is common technical vocabulary for those skilled in the art. For example, for P-type and N-type impurities, to distinguish the doping concentration, simply P+ type represents P-type with a high doping concentration, P type represents P-type with a medium doping concentration, P- type represents P-type with a low doping concentration, N+ type represents N-type with a high doping concentration, N type represents N-type with a medium doping concentration, and N- type represents N-type with a low doping concentration.

[0034] Regarding the HCI (Hot Carrier Injection) and HTRB (High Temperature Reverse Bias) degradation problems of Triple RESURF, the inventors analyzed from the perspective of the device structure and believed that the essential reason was that the current tended to flow towards the device surface during conduction. Especially after introducing ntop (the n-type doped region near the device surface in the drift region, with a doping concentration higher than that of the drift region), 80% of the current flowed away through ntop. Although the specific on-resistance was significantly reduced, due to the re-modulation of the space charge in the on-state, the high-density electrons filled the drift region, resulting in an accelerated depletion of the drift region. A strong electric field was generated on the surface of the drain end of the device, and the high electric field peak on the device surface caused the HCI (Hot Carrier Injection) degradation to be relatively fast, and the surface of the drain end of the device was prone to premature breakdown during the on-state of the device.

[0035] This application provides a semiconductor device with better reliability. Figure 1 It is a schematic structural diagram of a semiconductor device in an embodiment of this application, including: a source region 134, a drain region 132, a gate 138, a drift region 110, a buried region 122 of the first conduction type, and a first trench structure 140. The source region 134 and the drain region 132 have the first conduction type. The gate 138 is located above the region between the source region 134 and the drain region 132. At least a part of the drift region 110 is located between the source region 134 and the drain region 132. The doping concentration of the buried region 122 of the first conduction type is higher than that of the drift region 110, and at least a part of the drift region 110 is located on the buried region 122 of the first conduction type. The first trench structure 140 is located on the side of the source region 134 facing away from the gate 138, and the bottom of the first trench structure 140 extends into the buried region 122 of the first conduction type. The first trench structure 140 includes a first conductive structure 144 located in the first trench ( Figure 1 not shown), and a first insulating layer 142 located on the sidewall of the first trench. The first insulating layer 142 is used for insulating isolation of the side surface of the first conductive structure 144. The first conductive structure 144 is short-circuited and connected to the gate 138. In Figure 1 the illustrated embodiment, the semiconductor device is an LDMOS, such as an N-channel LDMOS, the first conduction type is N-type, and the second conduction type is P-type; in other embodiments, the semiconductor device can also be a P-channel LDMOS. Correspondingly, the first conduction type is P-type, and the second conduction type is N-type.

[0036] In the above semiconductor device, the first conductive structure 144 is short-circuited to the gate 138, introducing a potential into the depth where the first conductive type buried region 122 is located inside the device when the device is turned on. When the device is turned on, the electric field of the first conductive structure 144 generates an electron inversion layer inside the device, which is equivalent to adding a channel in the device body. In this way, the current can be introduced into the first conductive type buried region 122 as much as possible, so that the current path when the device is turned on can be guided from the device surface to the device body, improving the device reliability. And setting the first conductive type buried region 122 can further reduce the specific on-resistance of the device.

[0037] In Figure 1 the illustrated embodiment, the bottom of the first conductive structure 144 extends to the bottom of the first conductive type buried region 122. The deeper the first conductive structure 144 extends into the first conductive type buried region 122, the better the effect of guiding the current path from the device surface to the device body when the device is turned on.

[0038] In Figure 1 the illustrated embodiment, the semiconductor device is a silicon-on-insulator (SOI) device. The device includes a substrate 10 and a buried insulating layer 20 on the substrate 10. The drift region 110 is located on the buried insulating layer 20. In Figure 1 the illustrated embodiment, the substrate 10 is a P-type silicon substrate, and the material of the buried insulating layer 20 is silicon oxide, such as silicon dioxide. The first conductive type buried region 122 is in direct contact with the buried insulating layer 20, which can play a role in dielectric field enhancement, not only further reducing the specific on-resistance of the device, but also improving the lateral breakdown voltage of the device, and the longitudinal breakdown voltage of the device can also break through the material limit.

[0039] In Figure 1 the illustrated embodiment, the semiconductor device further includes a second conductive type well region 116. The source region 134 is located in the second conductive type well region 116, and the bottom of the second conductive type well region 116 extends to the first conductive type buried region 122. The first trench structure 140 and the drift region 110 are separated by the second conductive type well region 116. The second conductive type well region 116 can play a role in preventing leakage when the device is turned off. When the device is turned off, the current path is cut off by the second conductive type well region 116, and the first conductive structure 144 can be used as a field plate to assist depletion. And the second conductive type well region 116 can improve the breakdown voltage (BV) of the device.

[0040] In Figure 1In the illustrated embodiment, the semiconductor device further includes a buried region 112 of a second conductivity type and a top doping 124. The buried region 112 of the second conductivity type and the top doping 124 are located in the drift region between the source region 134 and the drain region 132, and the top doping 124 is located above the buried region 112 of the second conductivity type. The top doping 124 has a first conductivity type and a doping concentration greater than that of the drift region 110. The provision of the buried region 112 of the second conductivity type can reduce the specific on-resistance of the device.

[0041] In Figure 1 the illustrated embodiment, the semiconductor device further includes a doped region 136 of a second conductivity type. The doped region 136 of the second conductivity type is located in the well region 116 of the second conductivity type, and the source region 134 is located on both sides of the doped region 136 of the second conductivity type.

[0042] In Figure 1 the illustrated embodiment, the semiconductor device further includes a field oxide layer 150. The field oxide layer 150 is located between the source region 134 and the drain region 132, and the gate 138 extends from the edge of the source region 134 to the field oxide layer 150.

[0043] In an embodiment of the present application, the semiconductor device further includes a well region 114 of a first conductivity type, and the drain region 132 is located in the well region 114 of the first conductivity type. In an embodiment of the present application, the buried region 112 of the second conductivity type and the top doping 124 are located between the well region 114 of the first conductivity type and the well region 116 of the second conductivity type.

[0044] In an embodiment of the present application, the material of the first insulating layer 142 is silicon dioxide. In an embodiment of the present application, the first conductive structure 144 is a tungsten plug.

[0045] In Figure 1 the illustrated embodiment, the source region 134 and the drain region 132 are N+ regions, and the doped region 136 of the second conductivity type is a P+ region.

[0046] In an embodiment of the present application, the semiconductor device further includes a second trench structure 160. The second trench structure 160 is located on the side of the drain region 132 facing away from the gate 138, and the bottom of the second trench structure 160 extends into the buried region 122 of the first conductivity type. The second trench structure 160 includes a second conductive structure 164 located in the second trench and a second insulating layer 162 located on the sidewall of the second trench. The second conductive structure 164 is short-circuited to the drain region 132.

[0047] Referring to Figure 2 , in Figure 2In the illustrated embodiment, the bottom of the second conductive structure 164 and the bottom of the second insulating layer 162 extend to the buried insulating layer 20, such that the second conductive structure 164 is insulated from the first conductive type buried region 122 by the second insulating layer 162. When the device is turned on, the second trench structure 160 can generate an electron accumulation layer on the sidewall of the second trench, creating a low-resistance path from the source to the drain. Since the high-density current is in the body, reliability problems are not easily caused.

[0048] Referring to Figure 3 , in Figure 3 the illustrated embodiment, the bottom of the second conductive structure 164 is deeper than the bottom of the second insulating layer 162, thereby making electrical connection with the first conductive type buried region 122. In this way, when the device is turned on, more than 50% of the current between the source and the drain flows through the first conductive type buried region 122, fundamentally avoiding the rise of the surface electric field at the drain end.

[0049] The present application correspondingly provides a manufacturing method of a semiconductor device. Figure 4 is a flowchart of the manufacturing method of a semiconductor device in an embodiment of the present application, including the following steps:

[0050] S410, obtaining a wafer formed with a first conductive type buried region and a drift region.

[0051] The drift region 110 has a first conductive type, the doping concentration of the first conductive type buried region 122 is greater than the doping concentration of the drift region 110, and at least a part of the drift region 110 is located on the first conductive type buried region 122.

[0052] In an embodiment of the present application, in step S410, an SOI wafer is first obtained. The SOI wafer includes a substrate 10, a buried insulating layer 20 on the substrate 10, and a top semiconductor layer on the buried insulating layer 20. Then, ion implantation (implanting first conductive type ions) is performed on the top semiconductor layer to form a first conductive type buried region 122 on the buried insulating layer 20. Then, a drift region 110 is epitaxially formed on the first conductive type buried region 122.

[0053] S420, etching to form a first trench and filling the first trench with an insulating medium.

[0054] The bottom of the first trench formed by photolithography and etching extends into the first conductive type buried region 122. In an embodiment of the present application, the insulating medium filled in the first trench is silicon dioxide.

[0055] S430, forming a gate.

[0056] In an embodiment of the present application, before forming the gate, a step of forming a field oxide layer 150 on the drift region 110 is further included. The formed gate 138 extends onto the field oxide layer 150.

[0057] In one embodiment of the present application, before forming the field oxide layer 150, it further includes steps of forming a first conductivity type well region 114, a second conductivity type well region 116, a top doping 124, and a second conductivity type buried region 112 by photolithography and ion implantation. The top doping 124 has a first conductivity type and a doping concentration greater than that of the drift region 110. Among them, the top doping 124 and the second conductivity type buried region 112 can be formed by high-energy ion implantation using the same implantation blocking layer, that is, the top doping 124 and the second conductivity type buried region 112 can be formed using one photomask.

[0058] S440, form a source region and a drain region in the drift region below both sides of the gate.

[0059] Inject first conductivity type ions through an ion implantation process to form a source region 134 and a drain region 132. In one embodiment of the present application, the source region 134 is formed in the second conductivity type well region 116 and is located between the first trench and the gate 138; the drain region 132 is formed in the first conductivity type well region 114.

[0060] S450, etch the insulating medium in the first trench to form a hole.

[0061] In one embodiment of the present application, a part of the insulating medium in the first trench is removed by photolithography and etching to form a hole extending to the bottom of the first trench, and the remaining insulating medium on the sidewall of the first trench serves as the first insulating layer 142.

[0062] S460, fill the hole with a conductive material to form a first conductive structure.

[0063] In one embodiment of the present application, the first conductive structure 144 is a tungsten plug.

[0064] S470, short-circuit connect the first conductive structure to the gate.

[0065] In one embodiment of the present application, an interlayer dielectric (ILD) layer is formed on the front side of the wafer, and through forming contact holes and metal interconnections penetrating the interlayer dielectric layer, the first conductive structure 144 is short-circuit connected to the gate 138.

[0066] The manufacturing method of the above semiconductor device forms a first conductive structure 144 that is short-circuited and connected to the gate 138, introducing a potential into the depth where the first conductive type buried region 122 is located inside the device when the device is turned on. When the device is turned on, the electric field of the first conductive structure 144 generates an electron inversion layer inside the device, which is equivalent to adding a channel in the device body. In this way, the current can be introduced into the first conductive type buried region 122 as much as possible, so that the current path when the device is turned on is guided from the device surface to the device body, which can improve the device reliability. And setting the first conductive type buried region 122 can further reduce the specific on-resistance of the device.

[0067] In an embodiment of the present application, S420 further includes the steps of etching to form a second trench extending into the first conductive type buried region 122 at the bottom, and filling an insulating medium in the second trench, that is, the first trench and the second trench are etched synchronously, and while filling the insulating medium into the first trench, the insulating medium is also filled into the second trench. Correspondingly, step S450 includes etching the insulating medium in the second trench to form a hole, and step S460 also forms a second conductive structure 164 in the second trench.

[0068] Figure 5 It is a flowchart of the manufacturing method of a semiconductor device in another embodiment of the present application, including the following steps:

[0069] S510, obtaining a wafer formed with a first conductive type buried region and a drift region.

[0070] Specifically, it can be the same as step S410.

[0071] S520, forming a gate.

[0072] Specifically, it can be the same as step S430.

[0073] S530, forming a source region and a drain region in the drift region below both sides of the gate.

[0074] Specifically, it can be the same as step S440.

[0075] S540, etching to form a first trench, and forming a first insulating layer on the sidewall of the first trench.

[0076] In an embodiment of the present application, an oxide layer can be deposited on the sidewall of the first trench by SACVD (sub-atmospheric chemical vapor deposition) to form the first insulating layer.

[0077] S550, filling a conductive material into the first trench to form a first conductive structure.

[0078] In an embodiment of the present application, the first conductive structure 144 is a tungsten plug.

[0079] S560, short-circuit the first conductive structure to the gate.

[0080] Specifically, it can be the same as step S470.

[0081] The manufacturing method of the semiconductor device of this application and the semiconductor device are based on the same inventive concept. For the content not specifically described in the manufacturing method of the semiconductor device, reference can be made to the description of the semiconductor device above.

[0082] In the description of this specification, the description with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0083] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0084] The above-described embodiments only represent several implementation manners of this application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of the patent of this application shall be subject to the appended claims.

Claims

1. A semiconductor device, characterized in that: include: a source region having a first conductivity type; a drain region having a first conductivity type; a drift region, at least a portion of the drift region being located between the source region and the drain region; a gate located above a region between the source region and the drain region; A first conductive type buried region, the doping concentration of which is greater than that of the drift region, and at least a portion of the drift region is located on the first conductive type buried region; A first trench structure is located on a side of the source region away from the gate, the bottom of the first trench structure extends into the first conductive type buried region, the first trench structure includes a first conductive structure located in the first trench and a first insulating layer located on the side wall of the first trench, the first insulating layer is used to insulate and isolate the side of the first conductive structure; the first conductive structure is short-circuited to the gate.

2. The semiconductor device according to claim 1, wherein: The semiconductor device is a silicon-on-insulator semiconductor device, comprising a substrate and an insulating buried layer on the substrate, and the first conductive type buried region is in direct contact with the insulating buried layer.

3. The semiconductor device according to claim 2, characterized in that It also includes a second conductivity type well region, the source region is located in the second conductivity type well region, the bottom of the second conductivity type well region extends to the first conductivity type buried region, and the first conductivity type and the second conductivity type are opposite conductivity types.

4. The semiconductor device according to claim 1, wherein: Also includes: A buried region of the second conductivity type, located in the drift region between the source region and the drain region; The top doping is located in the drift region between the source region and the drain region and above the second conductive type buried region, wherein the top doping has the first conductive type and a doping concentration greater than a doping concentration of the drift region.

5. The semiconductor device according to claim 2, wherein: The bottom of the first conductive structure and the bottom of the first insulating layer extend to the buried insulating layer.

6. The semiconductor device according to claim 1, wherein: Also includes a second trench structure, the second trench structure is located on a side of the drain region away from the gate, the bottom of the second trench structure extends into the first conductive type buried region, the second trench structure includes a second conductive structure located in the second trench and a second insulating layer located on a sidewall of the second trench; The second conductive structure is short-circuited to the drain region.

7. The semiconductor device according to claim 6, characterized in that The bottom of the second conductive structure and the bottom of the second insulating layer extend to the buried insulating layer; or The bottom of the second conductive structure is deeper than the bottom of the second insulating layer, so as to be electrically connected to the first conductive type buried region.

8. The semiconductor device according to claim 3, characterized in that Also includes: A second conductive type doped region, located in the second conductive type well region, and the source region is located on both sides of the second conductive type doped region; The field oxide layer is located between the source region and the drain region, and the gate extends from the edge of the source region to the field oxide layer.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: The semiconductor device is an N-channel LDMOS, the first conductivity type is an N-type, and the second conductivity type is a P-type.

10. A method for manufacturing a semiconductor device, comprising: Obtaining a wafer having a first conductivity type buried region and a drift region formed thereon, wherein the drift region has a first conductivity type and the doping concentration of the first conductivity type buried region is greater than that of the drift region, and at least a portion of the drift region is located on the first conductivity type buried region; Etching to form a first trench with a bottom extending into the first conductive type buried region, and filling the first trench with an insulating medium; forming a gate; Ion implantation of ions of a first conductivity type to form a source region and a drain region in the drift region below both sides of the gate; Filling the first trench with a conductive material to form a first conductive structure, wherein a side surface of the first conductive structure is insulated and isolated by a first insulating layer formed by the insulating medium; short-circuiting the first conductive structure to the gate; Among them, the step of etching to form a first trench whose bottom extends into the first conductive type buried area and filling the first trench with an insulating medium is performed before the step of forming a gate, or after the step of forming a source region and a drain region in the drift region below both sides of the gate.

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