Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors, and the semiconductor device comprises a substrate, a first epitaxial layer, a second epitaxial layer, a P well region, an N doped region, a P doped region, a gate oxide layer, a polycrystalline silicon layer, a barrier layer, an ohmic contact layer, a first metal layer and a second metal layer. A first-stage wide groove is formed in the second epitaxial layer, the side wall of the gate oxide layer, the side wall of the polycrystalline silicon layer and the side wall of the first-stage wide groove are flush, and the barrier layer extends to the bottom wall of the first-stage wide groove and covers the side wall of the polycrystalline silicon layer, the side wall of the gate oxide layer and the side wall of the first-stage wide groove at the same time. On one hand, liquid Al is prevented from permeating into the grid electrode at high temperature, and short-circuit failure and surge failure are avoided. And on the other hand, the liquid Al is prevented from permeating into the channel region, so that the problems of leakage current increase, breakdown voltage reduction, threshold voltage Vth drift, on-resistance increase and the like are avoided, and the reliability and robustness of avalanche, thermotics and the like of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] For traditional power MOSFETs, when abnormal problems such as short-circuit large current or surge large current occur, the device will generate extremely high temperatures, even exceeding the melting point of the source metal Al (660 °C). This will cause the source Al metal of the device to melt into liquid Al, and result in a sharp change in the coefficient of thermal expansion. In this case, a huge thermal mismatch stress difference will be generated at the interface position between the thermally oxidized gate SiO2 with certain stress differences and the deposited ILD, and then cracks will be generated, allowing the liquid Al to penetrate into the gate, causing short-circuit failure and surge failure.

[0003] In addition, for the thermally oxidized gate SiO2 with greater stress, larger cracks or gaps are likely to be generated, enabling the liquid Al to penetrate into the channel region, resulting in electrical property problems such as increased leakage current, reduced breakdown voltage, drift of the threshold voltage Vth, and increased on-resistance, as well as reliability and robustness problems such as avalanche and thermal properties of the device.

[0004] In summary, the existing power MOSFETs have problems of poor reliability and robustness in terms of thermal, short-circuit or surge, and poor stability of electrical characteristics. Summary of the Invention

[0005] The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can improve the stability of the electrical characteristics of the device and the reliability and robustness of the device in terms of thermal, short-circuit, surge, etc.

[0006] In a first aspect, the present invention provides a semiconductor device, comprising: A substrate; A first epitaxial layer located on the surface of the substrate; A second epitaxial layer located on the surface of the first epitaxial layer, and a first-stage wide trench is formed in the second epitaxial layer; A P-well region, an N-doped region, and a P-doped region located on the surface layer of the second epitaxial layer away from the substrate side. The two sides of the N-doped region are respectively in contact with the P-well region and the P-doped region. The N-doped region is in contact with the side wall and the bottom wall of the first-stage wide trench, and the P-doped region is in contact with the bottom wall of the first-stage wide trench; A gate oxide layer located on the surface of the second epitaxial layer away from the substrate side and in contact with the N-doped region; A polysilicon layer located on the surface of the gate oxide layer away from the substrate side; A barrier layer located on the surface of the polysilicon layer; An ohmic contact layer on the surfaces of the P-doped region and the N-doped region; A first metal layer on the surfaces of the blocking layer and the ohmic contact layer; A second metal layer on the surface of the substrate on the side away from the first epitaxial layer; Wherein, the sidewalls of the gate oxide layer, the polysilicon layer, and the sidewall of the first-stage wide trench are flush, the blocking layer extends to the bottom wall of the first-stage wide trench, and simultaneously covers the sidewalls of the polysilicon layer, the gate oxide layer, and the sidewall of the first-stage wide trench.

[0007] In an alternative embodiment, the second epitaxial layer is further provided with a second-stage narrow trench, the second-stage narrow trench is disposed on the bottom wall of the first-stage wide trench, and is located between the P-doped region and the sidewall of the first-stage wide trench, the blocking layer extends to the bottom wall of the second-stage narrow trench, and covers the sidewall of the second-stage narrow trench.

[0008] In an alternative embodiment, the blocking layer includes a first interlayer dielectric layer, a blocking dielectric layer, and a second interlayer dielectric layer, the first interlayer dielectric layer covers the surface of the polysilicon layer, the blocking dielectric layer is located on the surface of the first interlayer dielectric layer, and the second interlayer dielectric layer is located on the surface of the blocking dielectric layer.

[0009] In an alternative embodiment, the thickness L1 of the first interlayer dielectric layer is the same as the thickness L3 of the second interlayer dielectric layer, and the thickness L2 of the blocking dielectric layer is more than twice the thickness L1 of the first interlayer dielectric layer.

[0010] In an alternative embodiment, a first N-type doped region is formed on the surface layer of the first epitaxial layer on the side away from the substrate, a second N-type doped region, a third N-type doped region, and a fourth N-type doped region are formed in the second epitaxial layer, the second N-type doped region is located on the surface layer of the second epitaxial layer close to the substrate, the third N-type doped region contacts the side of the second N-type doped region away from the substrate, the fourth N-type doped region contacts the side of the third N-type doped region away from the substrate, and the P-well region contacts the side of the second N-type doped region away from the substrate.

[0011] In an alternative embodiment, the P-doped region includes a first P-type doped region and a second P-type doped region, the first P-type doped region contacts the first N-type doped region, and is located on the surface layer of the second epitaxial layer on the side away from the substrate, the second P-type doped region is located between the N-doped region and the second N-type doped region, and simultaneously contacts the first P-type doped region and the P-well region; The N-doped region includes a fifth N-type doped region and a sixth N-type doped region. Both the fifth N-type doped region and the sixth N-type doped region are located on the side of the second P-type doped region away from the substrate. One side of the fifth N-type doped region is in contact with the P-well region, and the other side is in contact with the sixth N-type doped region and the sidewall of the first-level wide trench. The side of the sixth N-type doped region away from the fifth N-type doped region is in contact with the first P-type doped region, and the sixth N-type doped region is in contact with the bottom wall of the first-level wide trench; The P-well region includes a third P-type doped region and a fourth P-type doped region. The third P-type doped region is located on the side of the second N-type doped region away from the substrate. One side of the third P-type doped region is in contact with the third N-type doped region, and the other side is in contact with both the fifth N-type doped region and the second P-type doped region at the same time. The fourth P-type doped region is located on the side of the third P-type doped region away from the substrate. One side of the fourth P-type doped region is in contact with the fourth N-type doped region, and the other side is in contact with the fifth N-type doped region.

[0012] In an alternative embodiment, the distance H1 between the second P-type doped region and the first N-type doped region and the distance H2 between the third P-type doped region and the surface of the second P-type doped region close to the substrate satisfy the following relationship: H1 > 3H2.

[0013] In an alternative embodiment, the fourth N-type doped region is lightly doped. The height H3 of the third N-type doped region, the height H4 of the fourth N-type doped region, and the width W of the fourth N-type doped region satisfy the following relationship: (H3 + H4) > 2W.

[0014] In an alternative embodiment, the thickness L1 of the first interlayer dielectric layer is the same as the thickness L3 of the second interlayer dielectric layer. The fifth N-type doped region is in contact with both the sidewall and the bottom wall of the first-level wide trench. The second-level narrow trench is located in the sixth N-type doped region. The distance L4 between the second-level narrow trench and the fifth N-type doped region is equal to the distance L5 between the second-level narrow trench and the first P-type doped region. The width W1 of the part of the fifth N-type doped region joined to the sidewall of the first-level wide trench, the height H6 of the part of the fifth N-type doped region joined to the bottom wall of the first-level wide trench, and the depth Hz of the second-level narrow trench are equal to each other in pairs. The height H5 of the part of the fifth N-type doped region joined to the sidewall of the first-level wide trench is the same as the width W2 of the part of the fifth N-type doped region joined to the bottom wall of the first-level wide trench.

[0015] In a second aspect, the present invention provides a method for manufacturing a semiconductor device for manufacturing the semiconductor device according to any one of the foregoing embodiments. The manufacturing method includes the following steps: Provide a substrate; Fabricate a first epitaxial layer based on the surface of the substrate; Fabricate a second epitaxial layer based on the surface of the first epitaxial layer, and fabricate a first-level wide trench based on the surface of the second epitaxial layer. Among them, P-well regions, N-doped regions, and P-doped regions are formed by ion implantation on the surface layer on the side of the second epitaxial layer away from the substrate. The two sides of the N-doped region are respectively in contact with the P-well region and the P-doped region. The N-doped region is in contact with the side wall and the bottom wall of the first-level wide trench, and the P-doped region is in contact with the bottom wall of the first-level wide trench; Fabricate a gate oxide layer in contact with the N-doped region based on the surface on the side of the second epitaxial layer away from the substrate; Fabricate a polysilicon layer based on the surface on the side of the gate oxide layer away from the substrate. The side walls of the gate oxide layer, the side walls of the polysilicon layer, and the side walls of the first-level wide trench are flush; Fabricate a barrier layer based on the surface of the polysilicon layer. The barrier layer extends to the bottom wall of the first-level wide trench and simultaneously covers the side walls of the polysilicon layer, the side walls of the gate oxide layer, and the side walls of the first-level wide trench; Fabricate an ohmic contact layer based on the surfaces of the P-doped region and the N-doped region; Fabricate a first metal layer based on the surfaces of the barrier layer and the ohmic contact layer; Fabricate a second metal layer based on the surface on the side of the substrate away from the first epitaxial layer.

[0016] The beneficial effects of the embodiments of the present invention include: The embodiments of the present invention provide a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate; a first epitaxial layer located on the surface of the substrate; a second epitaxial layer located on the surface of the first epitaxial layer, and a first-level wide trench is formed in the second epitaxial layer; P-well regions, N-doped regions, and P-doped regions on the surface layer on the side of the second epitaxial layer away from the substrate, the two sides of the N-doped region are respectively in contact with the P-well region and the P-doped region, the N-doped region is in contact with the side wall and the bottom wall of the first-level wide trench, and the P-doped region is in contact with the bottom wall of the first-level wide trench; a gate oxide layer located on the side of the second epitaxial layer away from the substrate and in contact with the N-doped region; a polysilicon layer located on the side of the gate oxide layer away from the substrate; a barrier layer located on the surface of the polysilicon layer; an ohmic contact layer located on the surfaces of the P-doped region and the N-doped region; a first metal layer located on the surfaces of the barrier layer and the ohmic contact layer; a second metal layer located on the surface on the side of the substrate away from the first epitaxial layer; wherein, the side walls of the gate oxide layer, the side walls of the polysilicon layer, and the side walls of the first-level wide trench are flush, and the barrier layer extends to the bottom wall of the first-level wide trench and simultaneously covers the side walls of the polysilicon layer, the side walls of the gate oxide layer, and the side walls of the first-level wide trench.

[0017] Compared with the prior art, in the embodiment of the present invention, by providing the first-level wide trench, on the one hand, it avoids the direct contact between the source metal Al and the interface position of the gate oxide layer and the barrier layer, prevents the liquid Al from penetrating into the gate (polycrystalline silicon layer) at high temperature, and avoids short-circuit failure and surge failure. On the other hand, the barrier layer completely covers the gate oxide layer, also avoiding the direct contact between Al and the gate oxide layer, and preventing the liquid Al from penetrating into the channel region, thereby avoiding electrical performance problems such as increased leakage current, reduced breakdown voltage, drift of the threshold voltage Vth, and increased on-resistance of the device, and also improving the reliability and robustness of the device in terms of avalanche, thermology, etc.

[0018] Meanwhile, by providing the first-level wide trench and making the gate oxide layer flush with the sidewalls of both the polycrystalline silicon layer and the first-level wide trench simultaneously, it avoids the large-area contact between the barrier layer and the gate oxide layer, thus minimizing problems such as drift of the device threshold voltage Vth, increased leakage current, reduced breakdown voltage, increased on-resistance, and even reduced reliability caused by positive and negative charges in the barrier layer.

[0019] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically gives preferred embodiments and, in conjunction with the accompanying drawings, detailed descriptions are as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0021] Figure 1 is a schematic structural diagram of an existing power MOSFET device; Figure 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention; Figure 3 is Figure 2 a partial enlarged schematic diagram at I in Figure 4 is a process schematic diagram of step S2 in the manufacturing method of a semiconductor device provided by an embodiment of the present invention; Figure 5 is a process schematic diagram of the first epitaxial growth in step S3 in the manufacturing method of a semiconductor device provided by an embodiment of the present invention; Figure 6 is a process schematic diagram of the second epitaxial growth in step S3 in the manufacturing method of a semiconductor device provided by an embodiment of the present invention; Figure 7Schematic diagram of the third epitaxial growth in step S3 of the method for manufacturing a semiconductor device provided by an embodiment of the present invention; Figure 8 Schematic diagram of the fourth epitaxial growth in step S3 of the method for manufacturing a semiconductor device provided by an embodiment of the present invention; Figure 9 Schematic diagram of the process for fabricating the first-stage wide trench in step S3 of the method for manufacturing a semiconductor device provided by an embodiment of the present invention; Figure 10 Schematic diagrams of steps S4 and S5 of the method for manufacturing a semiconductor device provided by an embodiment of the present invention; Figure 11 Schematic diagram of step S6 of the method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0022] Schematic diagram of the semiconductor device structure provided by an embodiment of the present invention; Reference numerals: 100 - semiconductor device; 110 - substrate; 120 - first epitaxial layer; 121 - first N-type doped region; 130 - second epitaxial layer; 131 - first-stage wide trench; 132 - second-stage narrow trench; 133 - second N-type doped region; 134 - third N-type doped region; 135 - fourth N-type doped region; 136 - first growth layer; 137 - second growth layer; 138 - third growth layer; 139 - fourth growth layer; 140 - P-well region; 141 - third P-type doped region; 142 - fourth P-type doped region; 150 - N-doped region; 151 - fifth N-type doped region; 152 - sixth N-type doped region; 160 - P-doped region; 161 - first P-type doped region; 162 - second P-type doped region; 170 - gate oxide layer; 171 - polysilicon layer; 172 - ohmic contact layer; 173 - barrier layer; 174 - first interlayer dielectric layer; 175 - barrier dielectric layer; 176 - second interlayer dielectric layer; 180 - first metal layer; 190 - second metal layer. Detailed implementation manners

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. Generally, the components of the embodiments of the present invention described and illustrated in the drawings here can be arranged and designed in various different configurations.

[0024] Accordingly, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0025] It should be noted that like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.

[0026] In the description of the present invention, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the present invention is customarily placed during use, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0027] In addition, terms such as "first", "second", etc. are only used for distinguishing descriptions and should not be construed as indicating or implying relative importance. It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0028] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the present application is customarily placed during use, and it is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present application.

[0029] As disclosed in the background art, traditional power MOSFETs have problems such as poor reliability and robustness in terms of thermals, short circuits, or surges, and poor stability of electrical characteristics.

[0030] For example, please refer to Figure 1 , where P+ represents P-type heavy doping and N+ represents N-type heavy doping. Figure 1It is a schematic cross-sectional view of a power MOSFET in the prior art. When abnormal problems such as short-circuit large current or surge large current occur, the device will generate extremely high temperature, even exceeding the melting point of the source metal Al (660 °C), which will cause the source Al metal of the device to melt to form liquid Al and result in a sharp change in the coefficient of thermal expansion. In this case, a huge thermal mismatch stress difference will be generated at the interface position between the thermally oxidized gate SiO2 and the deposited ILD, which originally has a certain stress difference, and then cracks will occur, allowing the liquid Al to penetrate into the gate, causing short-circuit failure and surge failure.

[0031] In addition, for the thermally oxidized gate SiO2 with greater stress, it is easier to generate larger cracks or gaps, enabling the liquid Al to penetrate into the channel region, resulting in electrical performance problems such as increased leakage current, reduced breakdown voltage, drift of the threshold voltage Vth, and increased on-resistance, as well as reliability and robustness problems such as avalanche and thermal properties of the device.

[0032] Moreover, due to reasons such as manufacturing processes, there may be positive and negative charges in the interlayer dielectric ILD. Since the interlayer dielectric is more porous than the gate oxide layer, the positive and negative charges are likely to enter the gate oxide layer and even reach the oxide-semiconductor interface position. At this time, the interface state traps existing at the interface will capture the corresponding positive and negative charges to form interface trap charges, and directly generate an electrical effect (such as Coulomb scattering) with the semiconductor, seriously affecting the channel mobility uch, and then leading to problems such as drift of the threshold voltage Vth, increased leakage current, reduced breakdown voltage, and increased on-resistance of the device.

[0033] To solve the above problems, embodiments of the present invention provide a novel semiconductor device and a manufacturing method thereof. By means of an additional trench design, the electrical characteristic stability of the device and the reliability and robustness of the device in terms of thermal, short-circuit, surge, etc. can be improved. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0034] The semiconductor device provided by the present application will be exemplarily described below: As an optional implementation manner, please refer to Figure 2 and Figure 3, the semiconductor device 100 includes: a substrate 110; a first epitaxial layer 120 located on the surface of the substrate 110; a second epitaxial layer 130 located on the surface of the first epitaxial layer 120, and a first-stage wide trench 131 is formed in the second epitaxial layer 130; a P-well region 140, an N-doped region 150, and a P-doped region 160 located on the surface layer on the side of the second epitaxial layer 130 away from the substrate 110. The two sides of the N-doped region 150 are respectively in contact with the P-well region 140 and the P-doped region 160. The N-doped region 150 is in contact with the side walls and the bottom wall of the first-stage wide trench 131, and the P-doped region 160 is in contact with the bottom wall of the first-stage wide trench 131; a gate oxide layer 170 located on the side of the second epitaxial layer 130 away from the substrate 110 and in contact with the N-doped region 150; a polysilicon layer 171 located on the side of the gate oxide layer 170 away from the substrate 110; a barrier layer 173 located on the surface of the polysilicon layer 171; an ohmic contact layer 172 located on the surfaces of the P-doped region 160 and the N-doped region 150; a first metal layer 180 located on the surfaces of the barrier layer 173 and the ohmic contact layer 172; a second metal layer 190 located on the surface of the substrate 110 on the side away from the first epitaxial layer 120; wherein, the side walls of the gate oxide layer 170, the side walls of the polysilicon layer 171, and the side walls of the first-stage wide trench 131 are flush. The barrier layer 173 extends to the bottom wall of the first-stage wide trench 131 and simultaneously covers the side walls of the polysilicon layer 171, the side walls of the gate oxide layer 170, and the side walls of the first-stage wide trench 131.

[0035] It should be noted that the semiconductor device 100 may be a MOSFET device. Here, the substrate 110 is an N+ substrate layer, the first epitaxial layer 120 is an N-type epitaxial layer, and both the first epitaxial layer 120 and the second epitaxial layer 130 may be SiC epitaxial layers. It should also be noted that in the embodiments of the present invention, "X is located on the surface layer of Y" means that X is located in Y and exposed above Y; while "X is located on the surface of Y" means that X and Y are two independent parts, X is located above Y, and X is in contact with Y.

[0036] It should be noted that the first metal layer 180 in the embodiment of the present invention can be used as the source metal, preferably made of aluminum material, and the polysilicon layer 171 can be used as the gate. The first-stage wide trench 131 extends from the middle of the second epitaxial layer 130 to both sides, thus leaving a stepped structure in the middle of the second epitaxial layer 130. The P-well region 140 and the N-doped region 150 are partially located in this stepped structure, while the gate oxide layer 170 and the polysilicon layer 171 are sequentially formed on this stepped structure. By setting the first-stage wide trench 131, on the one hand, it avoids the direct contact between the first metal layer 180 and the interface positions of the gate oxide layer 170 and the blocking layer 173, preventing the liquid Al from penetrating into the polysilicon layer 171 at high temperatures and avoiding short-circuit failure and surge failure. On the other hand, the blocking layer 173 completely covers the gate oxide layer 170, also avoiding the direct contact between the source metal Al and the gate oxide layer 170, and preventing the liquid Al from penetrating into the channel region, thereby avoiding electrical performance problems such as increased leakage current, reduced breakdown voltage, drift of the threshold voltage Vth, and increased on-resistance of the device, and also improving the reliability and robustness of the device in terms of avalanche, thermals, etc. At the same time, by setting the first-stage wide trench 131 and making the gate oxide layer 170 flush with the side walls of both the polysilicon layer 171 and the first-stage wide trench 131, it avoids the large-area contact between the blocking layer 173 and the gate oxide layer 170, thus minimizing problems such as drift of the device threshold voltage Vth, increased leakage current, reduced breakdown voltage, increased on-resistance, and even reduced reliability caused by positive and negative charges in the blocking layer 173.

[0037] In some embodiments, the second epitaxial layer 130 is further provided with a second-stage narrow trench 132. The second-stage narrow trench 132 is provided on the bottom wall of the first-stage wide trench 131 and is located between the P-doped region 160 and the side wall of the first-stage wide trench 131. The blocking layer 173 extends to the bottom wall of the second-stage narrow trench 132 and covers the side wall of the second-stage narrow trench 132. Specifically, the second-stage narrow trench 132 is spaced from the P-doped region 160. During actual fabrication, the first-stage wide trench 131 can be fabricated first, and then the second-stage narrow trench 132 is fabricated on the bottom wall of the first-stage wide trench 131, where the width of the second-stage narrow trench 132 is smaller than the width of the N-doped region 150.

[0038] By setting the second-stage narrow trench 132, it can avoid the direct contact between the first metal layer 180 and the interface positions of the deposited blocking layer 173 and the second epitaxial layer 130 when only the first-stage wide trench 131 is provided, thereby avoiding problems such as cracks or gaps in the deposited blocking layer 173 due to a large stress difference at the interface, and further improving the stability of the electrical characteristics of the device and the reliability and robustness of the device in terms of thermals, short circuits, surges, etc.

[0039] In some embodiments, the barrier layer 173 includes a first interlayer dielectric layer 174, a barrier dielectric layer 175, and a second interlayer dielectric layer. The first interlayer dielectric layer 174 covers the surface of the polysilicon layer 171. The barrier dielectric layer 175 is located on the surface of the first interlayer dielectric layer 174. The second interlayer dielectric layer is located on the surface of the barrier dielectric layer 175. Specifically, the barrier dielectric layer 175 can be made of a dielectric material with high thermal conductivity, excellent thermal stability, and a relatively high failure temperature, such as a novel multi-component material SiCH / SiCN, etc. By adopting a three-layer structure and using the barrier dielectric layer 175 as the core layer, on the one hand, it can further protect the interlayer dielectric material, reduce the probability of cracks or gaps, and further improve the electrical characteristic stability, reliability, and robustness of the device. On the other hand, it can increase the heat dissipation capacity of the device, prevent heat from concentrating at the two-level trenches, greatly improve the thermal stress of the device, and thus greatly improve the thermal stability and reliability of the device.

[0040] Furthermore, the thickness L1 of the first interlayer dielectric layer 174 is the same as the thickness L3 of the second interlayer dielectric layer, and the thickness L2 of the barrier dielectric layer 175 is more than twice the thickness L1 of the first interlayer dielectric layer 174. Among them, the thicknesses of the first interlayer dielectric layer 174 and the second interlayer dielectric layer are both greater than 0, and L1 = L3, L2 > 2L1, which can ensure that the barrier dielectric layer 175 is relatively thick. While further improving the heat dissipation performance of the device, it can flexibly adjust the thermal stress to balance the internal stress of the device, thereby making the device have better reliability and robustness.

[0041] In some embodiments, a first N-type doped region 121 (N1 region in the figure) is formed on the surface layer of the side of the first epitaxial layer 120 away from the substrate 110. A second N-type doped region 133 (N2 region in the figure), a third N-type doped region 134 (N3 region in the figure), and a fourth N-type doped region 135 (N4 region in the figure) are formed in the second epitaxial layer 130. The second N-type doped region 133 is located on the surface layer of the side of the second epitaxial layer 130 close to the substrate 110. The third N-type doped region 134 is in contact with the side of the second N-type doped region 133 away from the substrate 110. The fourth N-type doped region 135 is in contact with the side of the third N-type doped region 134 away from the substrate 110. The P-well region 140 is in contact with the side of the second N-type doped region 133 away from the substrate 110. Specifically, the first N-type doped region 121 is formed on the surface layer of the side of the first epitaxial layer 120 away from the substrate 110 by ion implantation, and the first N-type doped region 121 can cover the entire surface layer of the first epitaxial layer 120. The second epitaxial layer 130 can be formed by multiple epitaxial growths, and the second N-type doped region 133, the third N-type doped region 134, and the fourth N-type doped region 135 can be formed by multiple ion implantations with different concentrations. At the same time, the P-well region 140 and the P-doped region 160 can also be formed by multiple ion implantations. The specific formation process can refer to the subsequent process description. Among them, the fourth N-type doped region 135 is a low-doped region, which can reduce the peak electric field at the center position of the gate oxide layer 170. The gate oxide layer 170 is in contact with the fourth N-type doped region 135. When the ion concentration of the fourth N-type doped region 135 is the lowest (less than that of the first N-type doped region 121, the second N-type doped region 133, and the third N-type doped region 134), the peak electric field at the center position of the gate oxide layer 170 can be further reduced, improving the gate oxide reliability of the device.

[0042] In some embodiments, the P-doped region 160 includes a first P-type doped region 161 (P1 region in the figure) and a second P-type doped region 162 (P2 region in the figure). The first P-type doped region 161 is in contact with the first N-type doped region 121 and is located on the surface layer of the second epitaxial layer 130 away from the substrate 110. The second P-type doped region 162 is located between the N-doped region 150 and the second N-type doped region 133, and is in contact with both the first P-type doped region 161 and the P-well region 140. The N-doped region 150 includes a fifth N-type doped region 151 (N5 region in the figure) and a sixth N-type doped region 152 (N6 region in the figure). Both the fifth N-type doped region 151 and the sixth N-type doped region 152 are located on the side of the second P-type doped region 162 away from the substrate 110. One side of the fifth N-type doped region 151 is in contact with the P-well region 140, and the other side is in contact with the sixth N-type doped region 152 and the sidewall of the first-level wide trench 131. The side of the sixth N-type doped region 152 away from the fifth N-type doped region 151 is in contact with the first P-type doped region 161, and the sixth N-type doped region 152 is in contact with the bottom wall of the first-level wide trench 131. The P-well region 140 includes a third P-type doped region 141 (P3 region in the figure) and a fourth P-type doped region 142 (P4 region in the figure). The third P-type doped region 141 is located on the side of the second N-type doped region 133 away from the substrate 110. One side of the third P-type doped region 141 is in contact with the third N-type doped region 134, and the other side is in contact with both the fifth N-type doped region 151 and the second P-type doped region 162. The fourth P-type doped region 142 is located on the side of the third P-type doped region 141 away from the substrate 110. One side of the fourth P-type doped region 142 is in contact with the fourth N-type doped region 135, and the other side is in contact with the fifth N-type doped region 151.

[0043] It should be noted that the doping concentrations of the first P-type doped region 161, the second P-type doped region 162, the third P-type doped region 141, and the fourth P-type doped region 142 are different here, and the doping concentrations of the first N-type doped region 121, the second N-type doped region 133, the third N-type doped region 134, and the fourth N-type doped region 135 are different. By flexibly adjusting the concentrations and sizes of each doped region, an equivalent resistance capacitance of a PN junction depletion region with an automatic buffering and inhibiting effect can be introduced into the current path. When an abnormal working condition occurs, the device can automatically and flexibly expand the PN depletion regions at different positions, and then automatically generate different sizes of depletion layer equivalent resistance capacitances, automatically suppressing problems such as EMI electromagnetic interference, oscillation, and surge. Ultimately, the device has better anti-electromagnetic interference, oscillation, surge, voltage and current overshoot capabilities, stronger short-circuit withstand capability SCWT, and high device reliability.

[0044] In some embodiments, the distance H1 between the second P-type doped region 162 and the first N-type doped region 121, and the distance H2 between the third P-type doped region 141 and the surface of the second P-type doped region 162 closer to the substrate 110 satisfy the following relationship: H1 > 3H2. Specifically, when H1 > 3H2, the body diode PN junction can be formed into an equivalent arc surface structure as a whole, so that the depletion layer power lines at the corners of the P-well region 140 and the center position of the gate oxide layer are more dispersed, significantly reducing the peak electric field and enabling the device to have a higher gate oxide breakdown voltage and gate oxide reliability.

[0045] In some embodiments, the fourth N-type doped region 135 is a low-doped region, and the ion concentration of the fourth N-type doped region 135 is the lowest. The height H3 of the third N-type doped region 134, the height H4 of the fourth N-type doped region 135, and the width W of the fourth N-type doped region 135 satisfy the following relationship: (H3 + H4) > 2W. Specifically, when (H3 + H4) > 2W, and at the same time the fourth P-type doped region 142 is low-doped, and when the ion concentration of the fourth P-type doped region 142 is the lowest, the peak electric field at the center position of the gate oxide layer 170 can be further reduced, and the gate oxide reliability of the device can be further improved.

[0046] In some embodiments, the thickness L1 of the first interlayer dielectric layer 174 is the same as the thickness L3 of the second interlayer dielectric layer. The fifth N-type doped region 151 is in contact with both the sidewall and the bottom wall of the first-stage wide trench 131. The second-stage narrow trench 132 is located in the sixth N-type doped region 152. The distance L4 between the second-stage narrow trench 132 and the fifth N-type doped region 151 is equal to the distance L5 between the second-stage narrow trench 132 and the first P-type doped region 161. The width W1 of the fifth N-type doped region 151 joined to the sidewall portion of the first-stage wide trench 131, the height H6 of the fifth N-type doped region 151 joined to the bottom wall portion of the first-stage wide trench 131, and the depth Hz of the second-stage narrow trench 132 are equal to each other in pairs. The height H5 of the fifth N-type doped region 151 joined to the sidewall portion of the first-stage wide trench 131 is the same as the width W2 of the fifth N-type doped region 151 joined to the bottom wall portion of the first-stage wide trench 131. Specifically, the fifth N-type doped region 151 and the sixth N-type doped region 152 serve as high-doped source electrodes, and the doping concentrations of the two regions are not equal. The second-stage narrow trench 132 is provided in the middle of the sixth N-type doped region 152, so that the sixth N-type doped region 152 is provided on both the left and right sides of the second-stage narrow trench 132. At the same time, when L1 = L3, L4 = L5, W1 = H6 = Hz, and W2 = H5, the effect of the internal stress of the material generated by the lattice distortion of the semiconductor material after the etching of the second-stage narrow trench 132 can be balanced, and the electrical performance stability and reliability of the device can be improved.

[0047] Based on the above implementation manner, an embodiment of the present invention further provides a manufacturing method of a semiconductor device 100 for manufacturing the above semiconductor device 100, and the manufacturing method includes the following steps: S1: Provide a substrate 110.

[0048] S2: Fabricate a first epitaxial layer 120 on the surface of the substrate 110; S3: Fabricate a second epitaxial layer 130 on the surface of the first epitaxial layer 120, and fabricate a first-level wide trench 131 on the surface of the second epitaxial layer 130.

[0049] Among them, a P-well region 140, an N-doped region 150, and a P-doped region 160 are formed by ion implantation on the surface layer on the side of the second epitaxial layer 130 away from the substrate 110. The two sides of the N-doped region 150 are respectively in contact with the P-well region 140 and the P-doped region 160. The N-doped region 150 is in contact with the side wall and the bottom wall of the first-level wide trench 131, and the P-doped region 160 is in contact with the bottom wall of the first-level wide trench 131; S4: Fabricate a gate oxide layer 170 in contact with the N-doped region 150 on the surface of the second epitaxial layer 130 away from the substrate 110.

[0050] S5: Fabricate a polysilicon layer 171 on the surface of the gate oxide layer 170 away from the substrate 110.

[0051] Among them, the side walls of the gate oxide layer 170, the side walls of the polysilicon layer 171, and the side walls of the first-level wide trench 131 are flush.

[0052] S6: Fabricate a barrier layer 173 on the surface of the polysilicon layer 171.

[0053] Among them, the barrier layer 173 extends to the bottom wall of the first-level wide trench 131 and simultaneously covers the side walls of the polysilicon layer 171, the side walls of the gate oxide layer 170, and the side walls of the first-level wide trench 131.

[0054] S7: Fabricate an ohmic contact layer 172 on the surfaces of the P-doped region 160 and the N-doped region 150.

[0055] S8: Fabricate a first metal layer 180 on the surfaces of the barrier layer 173 and the ohmic contact layer 172.

[0056] S9: Fabricate a second metal layer 190 on the surface of the substrate 110 away from the first epitaxial layer 120.

[0057] The following is an exemplary description of the manufacturing method of the semiconductor device 100 provided by the present application with reference to the accompanying drawings: First, please refer to Figure 4, a first epitaxial layer 120 is deposited and formed on a substrate 110. Then, a first N-type ion implantation is performed on the surface layer of the first epitaxial layer 120 away from the substrate 110 to form a first N-type doped region 121, and the first N-type doped region 121 is located on the surface layer of the first epitaxial layer 120.

[0058] Secondly, please refer to Figure 5 , a first epitaxial growth is performed on the first epitaxial layer 120 to form a first growth layer 136. Then, a second N-type ion implantation is performed on the first growth layer 136 to form a second N-type doped region 133. Furthermore, a first P-type ion implantation is performed on the surface layer of the first growth layer 136 away from the substrate 110 to form a part of a second P-type doped region 162.

[0059] After that, please refer to Figure 6 , a second epitaxial growth is performed on the first growth layer 136 to form a second growth layer 137. Then, a second P-type ion implantation is performed on the second growth layer 137 to contact with the P-type ion doped region in the first growth layer 136, and together they form a second P-type doped region 162.

[0060] Then again, please refer to Figure 7 , a third epitaxial growth is performed on the second growth layer 137 to form a third growth layer 138. Then, a third N-type ion implantation is performed on the middle part of the third growth layer 138, and the implantation depth reaches the second N-type doped region 133, thereby forming a third N-type doped region 134 in contact with the second N-type doped region 133. Then, a fourth N-type ion implantation is performed to form a part of a fifth N-type doped region 151, and the fifth N-type doped region 151 is in contact with the second P-type doped region 162. Furthermore, a fifth N-type ion implantation is performed on the side of the fifth N-type doped region 151 away from the third N-type doped region 134 to form a sixth N-type doped region 152, and the sixth N-type doped region 152 is in contact with both the fifth N-type doped region 151 and the second P-type doped region 162. Finally, a third P-type ion implantation is performed on the region between the third N-type doped region 134 and the fifth N-type doped region 151, thereby forming a third P-type doped region 141, and the third P-type doped region 141 is in contact with both the fifth N-type doped region 151 and the second P-type doped region 162.

[0061] After that, please refer to Figure 8, the fourth epitaxial growth is carried out on the third growth layer 138 to form the fourth growth layer 139, and then the sixth N-type ion implantation is carried out to form the fourth N-type doped region 135, and the fourth N-type doped region 135 is in contact with the third N-type doped region 134 correspondingly. Then the seventh N-type ion implantation is carried out, and the ion implantation region is joined to contact the N-type ion doped region in the third growth layer 138 to jointly form the fifth N-type doped region 151. Finally, the fourth P-type ion implantation is carried out in the region between the fifth N-type doped region 151 and the fourth N-type doped region 135 to form the fourth P-type doped region 142, and the fourth P-type doped region 142 is in contact with the third P-type doped region 141 correspondingly.

[0062] It should be noted that here, the first growth layer 136, the second growth layer 137, the third growth layer 138, and the fourth growth layer 139 together constitute the second epitaxial layer 130.

[0063] Then, please refer to Figure 9 , the first etching is carried out on the fourth growth layer 139 to form the first-stage wide trench 131. The first-stage wide trench 131 can use the fifth N-type doped region 151 and the sixth N-type doped region 152 as the etching boundaries, so that after etching, the fifth N-type doped region 151 is in contact with both the side wall and the bottom wall of the first-stage wide trench 131, and the sixth N-type doped region 152 is in contact with the bottom wall of the first-stage wide trench 131. Then the fifth P-type ion implantation is carried out with the sixth N-type doped region 152 as the implantation boundary to form the first P-type doped region 161, and the first P-type doped region 161 is in contact with both the sixth N-type doped region 152 and the second P-type doped region 162. Finally, the second etching is carried out to etch the bottom wall of the first-stage wide trench 131 to form the second-stage narrow trench 132. The sixth N-type doped region 152 can be used as the etching positioning during etching, so that the second-stage narrow trench 132 is located in the middle of the sixth N-type doped region 152. High-temperature furnace annealing is required after etching.

[0064] After that, please refer to Figure 10 , after the annealing is completed, selective oxidation can be carried out on the second epitaxial layer 130 to form the gate oxide layer 170, and then a polysilicon layer 171 is deposited and etched according to a preset pattern to form the polysilicon layer 171 on the gate oxide layer 170. The polysilicon layer 171 is an N+-type polysilicon layer 171.

[0065] Then, please refer to Figure 11 , the manufacturing of the barrier layer 173 can be carried out. Specifically, first, an interlayer dielectric material is deposited, and after etching, the first interlayer dielectric layer is formed; then a dielectric material with high thermal conductivity, excellent thermal stability, and a relatively high failure temperature is deposited, and after etching, the barrier dielectric layer 175 is formed; finally, an interlayer dielectric material is deposited again, and after etching, the second interlayer dielectric layer 176 is formed.

[0066] Finally, please continue to refer to Figure 2 Figure 2 , the ohmic contact layer 172 can be prepared on the surfaces of the P-doped region 160 and the N-doped region 150 according to the conventional process, and then the front metal is fabricated to form the first metal layer 180. Finally, the back metal is fabricated to form the back metal layer.

[0067] In summary, the embodiment of the present invention provides a semiconductor device 100 and a manufacturing method thereof. The semiconductor device 100 includes: a substrate 110; a first epitaxial layer 120 located on the surface of the substrate 110; a second epitaxial layer 130 located on the surface of the first epitaxial layer 120, and the second epitaxial layer 130 is formed with a first-level wide trench 131; a P-well region 140, an N-doped region 150, and a P-doped region 160 located on the surface of the second epitaxial layer 130 away from the substrate 110. The two sides of the N-doped region 150 are respectively in contact with the P-well region 140 and the P-doped region 160. The N-doped region 150 is in contact with the sidewalls and the bottom wall of the first-level wide trench 131, and the P-doped region 160 is in contact with the bottom wall of the first-level wide trench 131; a gate oxide layer 170 located on the surface of the second epitaxial layer 130 away from the substrate 110 and in contact with the N-doped region 150; a polysilicon layer 171 located on the side of the gate oxide layer 170 away from the substrate 110; a barrier layer 173 located on the surface of the polysilicon layer 171; an ohmic contact layer 172 located on the surfaces of the P-doped region 160 and the N-doped region 150; a first metal layer 180 located on the surfaces of the barrier layer 173 and the ohmic contact layer 172; a second metal layer 190 located on the surface of the substrate 110 away from the first epitaxial layer 120; wherein, the sidewalls of the gate oxide layer 170, the sidewalls of the polysilicon layer 171, and the sidewalls of the first-level wide trench 131 are flush. The barrier layer 173 extends to the bottom wall of the first-level wide trench 131 and simultaneously covers the sidewalls of the polysilicon layer 171, the sidewalls of the gate oxide layer 170, and the sidewalls of the first-level wide trench 131.

[0068] In the embodiment of the present invention, by providing the first-level wide trench 131, on the one hand, it avoids the direct contact between the source metal Al and the interface position of the gate oxide layer 170 and the barrier layer 173, prevents the liquid Al from penetrating into the gate (polysilicon layer 171) at high temperature, and avoids short-circuit failure and surge failure. On the other hand, the barrier layer 173 completely covers the gate oxide layer 170, also avoiding the direct contact between the source metal Al and the gate oxide layer 170, and avoiding the penetration of liquid Al into the channel region, thereby avoiding electrical performance problems such as an increase in leakage current, a decrease in breakdown voltage, a drift of the threshold voltage Vth, and an increase in on-resistance of the device, and also improving the reliability and robustness of the device in terms of avalanche and thermals.

[0069] Meanwhile, by setting the first-level wide trench 131 and making the gate oxide layer 170 flush with the polysilicon layer 171 and the sidewall of the first-level wide trench 131 at the same time, the large-area contact between the barrier layer 173 and the gate oxide layer 170 is avoided, thus minimizing problems such as the drift of the device threshold voltage Vth, the increase in leakage current, the decrease in breakdown voltage, the increase in on-resistance, and even the decrease in reliability caused by the positive and negative charges in the barrier layer 173. By adopting the structure of the three-layer barrier layer 173 and using the barrier dielectric layer 175 as the core layer, on the one hand, the interlayer dielectric material can be further protected, the probability of cracks or gaps generation can be reduced, and the electrical characteristics stability of the device, as well as the reliability and robustness of the device, can be further improved. On the other hand, the heat dissipation capacity of the device can be increased, the concentration of heat at the two-level trenches can be prevented, the thermal stress of the device can be significantly improved, and thus the thermal stability and reliability of the device can be significantly improved. In addition, by flexibly adjusting the concentration and size of each doping region, an equivalent resistance capacitance of the PN junction depletion region with an automatic buffering and suppressing effect can be introduced into the current path. When an abnormal working condition occurs, the device can automatically and flexibly expand the PN depletion regions at different positions, and then automatically generate equivalent resistance capacitances of depletion layers with different sizes, automatically suppressing problems such as EMI electromagnetic interference, oscillation, and surge. Eventually, the device has better anti-electromagnetic interference, oscillation, surge, voltage and current overshoot capabilities, stronger short-circuit withstand capability SCWT, and high device reliability.

[0070] As described above, the above are only the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; A first epitaxial layer located on the surface of the substrate; A second epitaxial layer located on the surface of the first epitaxial layer, the second epitaxial layer being formed with a first-level wide trench; A P-well region, an N-doped region, and a P-doped region located on the surface layer on the side of the second epitaxial layer away from the substrate, the two sides of the N-doped region being in contact with the P-well region and the P-doped region respectively, the N-doped region being in contact with the side walls and the bottom wall of the first-level wide trench, and the P-doped region being in contact with the bottom wall of the first-level wide trench; A gate oxide layer located on the side of the second epitaxial layer away from the substrate and in contact with the N-doped region; A polysilicon layer located on the side of the gate oxide layer away from the substrate; A barrier layer located on the surface of the polysilicon layer; An ohmic contact layer located on the surfaces of the P-doped region and the N-doped region; A first metal layer located on the surfaces of the barrier layer and the ohmic contact layer; A second metal layer located on the surface of the substrate on the side away from the first epitaxial layer; Wherein, the side walls of the gate oxide layer, the side walls of the polysilicon layer, and the side walls of the first-level wide trench are flush, the barrier layer extends to the bottom wall of the first-level wide trench, and simultaneously covers the side walls of the polysilicon layer, the side walls of the gate oxide layer, and the side walls of the first-level wide trench.

2. The semiconductor device according to claim 1, wherein The second epitaxial layer is further provided with a second-level narrow trench, the second-level narrow trench is provided on the bottom wall of the first-level wide trench and is located between the P-doped region and the side wall of the first-level wide trench, the barrier layer extends to the bottom wall of the second-level narrow trench and covers the side wall of the second-level narrow trench.

3. The semiconductor device according to claim 2, wherein, The barrier layer includes a first interlayer dielectric layer, a barrier dielectric layer, and a second interlayer dielectric layer, the first interlayer dielectric layer covers the surface of the polysilicon layer, the barrier dielectric layer is located on the surface of the first interlayer dielectric layer, and the second interlayer dielectric layer is located on the surface of the barrier dielectric layer.

4. The semiconductor device according to claim 3, wherein The thickness L1 of the first interlayer dielectric layer is the same as the thickness L3 of the second interlayer dielectric layer, and the thickness L2 of the barrier dielectric layer is more than twice the thickness L1 of the first interlayer dielectric layer.

5. The semiconductor device according to claim 3, wherein A first N-type doped region is formed on the surface layer on the side of the first epitaxial layer away from the substrate, a second N-type doped region, a third N-type doped region, and a fourth N-type doped region are formed in the second epitaxial layer, the second N-type doped region is located on the surface layer on the side of the second epitaxial layer close to the substrate, the third N-type doped region is in contact with the side of the second N-type doped region away from the substrate, the fourth N-type doped region is in contact with the side of the third N-type doped region away from the substrate, and the P-well region is in contact with the side of the second N-type doped region away from the substrate.

6. The semiconductor device according to claim 5, wherein The P-doped region includes a first P-type doped region and a second P-type doped region, the first P-type doped region is in contact with the first N-type doped region and is located on the surface layer on the side of the second epitaxial layer away from the substrate, the second P-type doped region is located between the N-doped region and the second N-type doped region and is in contact with the first P-type doped region and the P-well region simultaneously; The N-doped region includes a fifth N-type doped region and a sixth N-type doped region. Both the fifth N-type doped region and the sixth N-type doped region are located on the side of the second P-type doped region away from the substrate. One side of the fifth N-type doped region is in contact with the P-well region, and the other side is in contact with the sixth N-type doped region and the sidewall of the first-stage wide trench. The side of the sixth N-type doped region away from the fifth N-type doped region is in contact with the first P-type doped region, and the sixth N-type doped region is in contact with the bottom wall of the first-stage wide trench; The P-well region includes a third P-type doped region and a fourth P-type doped region. The third P-type doped region is located on the side of the second N-type doped region away from the substrate. One side of the third P-type doped region is in contact with the third N-type doped region, and the other side is simultaneously in contact with the fifth N-type doped region and the second P-type doped region. The fourth P-type doped region is located on the side of the third P-type doped region away from the substrate. One side of the fourth P-type doped region is in contact with the fourth N-type doped region, and the other side is in contact with the fifth N-type doped region.

7. The semiconductor device according to claim 6, wherein, The distance H1 between the second P-type doped region and the first N-type doped region and the distance H2 between the third P-type doped region and the surface of the second P-type doped region close to the substrate satisfy the following relationship: H1 > 3H2.

8. The semiconductor device according to claim 6, wherein The fourth N-type doped region is lightly doped. The height H3 of the third N-type doped region, the height H4 of the fourth N-type doped region, and the width W of the fourth N-type doped region satisfy the following relationship: (H3 + H4) > 2W.

9. The semiconductor device according to claim 6, characterized in that, The thickness L1 of the first interlayer dielectric layer is the same as the thickness L3 of the second interlayer dielectric layer. The fifth N-type doped region is simultaneously in contact with the sidewall and the bottom wall of the first-stage wide trench. The second-stage narrow trench is located in the sixth N-type doped region. The distance L4 between the second-stage narrow trench and the fifth N-type doped region is equal to the distance L5 between the second-stage narrow trench and the first P-type doped region. The width W1 of the part of the fifth N-type doped region joined to the sidewall of the first-stage wide trench, the height H6 of the part of the fifth N-type doped region joined to the bottom wall of the first-stage wide trench, and the depth Hz of the second-stage narrow trench are pairwise equal. The height H5 of the part of the fifth N-type doped region joined to the sidewall of the first-stage wide trench is the same as the width W2 of the part of the fifth N-type doped region joined to the bottom wall of the first-stage wide trench.

10. A method for manufacturing a semiconductor device, for manufacturing the semiconductor device according to any one of claims 1-9, characterized in that, The manufacturing method includes the following steps: Providing a substrate; Fabricating a first epitaxial layer based on the surface of the substrate; Fabricating a second epitaxial layer based on the surface of the first epitaxial layer, and fabricating a first-stage wide trench based on the surface of the second epitaxial layer. Among them, a P-well region, an N-doped region, and a P-doped region are formed by ion implantation on the surface layer of the second epitaxial layer away from the substrate. Both sides of the N-doped region are in contact with the P-well region and the P-doped region respectively. The N-doped region is in contact with the sidewall and the bottom wall of the first-stage wide trench. The P-doped region is in contact with the bottom wall of the first-stage wide trench; A gate oxide layer in contact with the N-doped region is fabricated on the surface of the second epitaxial layer away from the substrate side; A polysilicon layer is fabricated on the surface of the gate oxide layer away from the substrate side, and the sidewalls of the gate oxide layer, the polysilicon layer, and the sidewalls of the first-level wide trench are flush; A barrier layer is fabricated on the surface of the polysilicon layer, the barrier layer extends to the bottom wall of the first-level wide trench, and simultaneously covers the sidewalls of the polysilicon layer, the sidewalls of the gate oxide layer, and the sidewalls of the first-level wide trench; An ohmic contact layer is fabricated on the surfaces of the P-doped region and the N-doped region; A first metal layer is fabricated on the surfaces of the barrier layer and the ohmic contact layer; A second metal layer is fabricated on the surface of the substrate away from the first epitaxial layer side.

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