Transverse SIC-JFET device and preparation method thereof
By optimizing the structure of the lateral SIC-JFET device and reducing the thickness of the connection area between the source region and the drift region, the problem of large control voltage in traditional devices is solved, and the control voltage reduction and the device structure are achieved.
Patent Information
- Application Number
- CN202510279670.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-06-24
AI Technical Summary
The control voltage of the traditional lateral SIC-JFET device structure is large, resulting in difficult voltage problems in applications in RF and power fields.
By optimizing the device structure, the thickness of the connection region between the source region and the drift region is reduced so that the control voltage depends on the thickness of the region. The specific implementation method is to form an epitaxial layer of the first doped type on a substrate of the second doped type, then form a drift region and a source region of the second doped type in the epitaxial layer, and form a gate of the first doped type in the drift region to ensure that the second side of the source region is connected to the gate and the drift region, thereby achieving a reduction in the control voltage.
The control voltage reduction is achieved, making the device more flexible and efficient in the RF and power fields, while simplifying the device structure and preparation process.
Smart Images
Figure CN120201756A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular, to a lateral SIC-JFET device and a method for preparing the same. Background Art
[0002] The lateral SIC-JFET device is a semiconductor device that is very suitable for use in the RF and power fields. First of all, SiC, as a wide bandgap semiconductor material, has a higher breakdown field strength than Si, so it is possible to achieve the same breakdown voltage level in SiC, but with a shorter drift region and a smaller on-resistance. Secondly, the current of the lateral SIC-JFET device is conducted in the SiC body, rather than through the SiC-SiO2 interface like SiC MOS devices, so many problems such as low carrier mobility and poor reliability caused by defects at the interface can be avoided. In addition, SiC material has a high thermal conductivity and has a natural heat dissipation advantage in power applications.
[0003] Figure 1 It is a cross-sectional view of a lateral SIC-JFET device of the authorized patent CN116759464B.
[0004] For this device, its source region 111 and the first body region 107 are both grounded. Its basic working principle is to turn off the entire device by depleting the channel region 109 through the potential on the gate 110. The device is turned on by gradually returning the potential on the gate 110 to 0.
[0005] From the perspective of device control, it is hoped that the control voltage is smaller.
[0006] Taking the negative voltage shutdown device commonly seen in current industrial scenarios as an example, the device shutdown voltage is generally required to be around -5V. A shutdown voltage that is too negative will make the design of the device gate power supply circuit difficult.
[0007] for Figure 1 For the device, if you want to reduce the turn-on voltage as much as possible, you can only do so by continuously reducing the length of the gate 110, that is, the lateral size of the channel region 109. A smaller gate 110 length can also be exhausted at a smaller voltage. However, this method is limited by the lithography resolution limit of the lithography machine. For example, the lithography line width limit of the current i-line lithography machine is 0.4μm, which determines that it is impossible to use this type of lithography machine to manufacture the device with a gate 110 length less than 0.4μm.
[0008] Meanwhile, to ensure the integrity of the connection between the source region 111, channel region 109, and drift region 104 of the device, the lithography window positions of these three regions of the device are generally set to overlap with each other. The size of this overlapping region is the minimum alignment accuracy of the lithography machine, which is generally half of the lithography limit line width of the lithography machine. In the previous example, it is ±0.2 μm. However, the actual size of the overlapping region of the device manufactured actually will float within 0 - 0.4 μm. This causes the doping concentration of the channel region 109 to be affected by the injection from the drift region 104 and the source region 111. And the proportion of this influence will increase rapidly as the length of the gate 110 decreases. Due to the alignment problem of the lithography machine on the same wafer, the channel region concentrations of the devices at different positions vary greatly, and thus the device parameters are very different, greatly reducing the large-scale mass production potential and manufacturability of this device. That is, it is difficult to achieve by reducing the control voltage by reducing the length of the gate 110, and the mass production difficulty is great.
[0009] Therefore, the control voltage of the traditional lateral SIC-JFET device structure is relatively large, which is a technical problem that needs to be urgently solved by those skilled in the art.
[0010] The above information disclosed in the background art is only used to enhance the understanding of the background of the present application. Therefore, it may contain information on the prior art that has not been known to those of ordinary skill in the art. Summary of the Invention
[0011] The present application provides a lateral SIC-JFET device and a manufacturing method thereof to solve the technical problem of the relatively large control voltage of the traditional lateral SIC-JFET device structure.
[0012] The present application provides a lateral SIC-JFET device, including:
[0013] A substrate of a second doping type;
[0014] An epitaxial layer of a first doping type;
[0015] A source region of a second doping type, formed in the epitaxial layer, and the source region has two sides which are a first side and a second side respectively;
[0016] A drift region of a second doping type, formed in the epitaxial layer, and the drift region is connected to the position of the second side of the source region;
[0017] A gate of a first doping type, formed in the drift region and the gate is connected to the position of the second side of the source region;
[0018] Wherein, the upper part of the second side of the source region is connected to the gate, and the lower part of the second side of the source region is directly connected to the drift region.
[0019] The present application also provides a method for manufacturing a lateral SIC-JFET device, including:
[0020] The method includes the following steps:
[0021] Forming an epitaxial layer of a first doping type on a substrate of a second doping type;
[0022] Forming a base of a drift region of a second doping type within the epitaxial layer;
[0023] Forming a gate of a first doping type within the base of the drift region, and one side surface of the gate being flush with one side surface of the base of the drift region;
[0024] Forming a source region of a second doping type within the epitaxial layer, the source region having two side surfaces which are a first side surface and a second side surface respectively, the second side surface of the source region being connected to the base of the drift region; the second side surface of the source region being connected to the gate;
[0025] Wherein, the upper part of the second side surface of the source region is connected to the gate, and the lower part of the second side surface of the source region is directly connected to the drift region.
[0026] Due to the adoption of the above technical solutions, the present application has the following technical effects:
[0027] The control voltage of the lateral SIC-JFET device of the present application depends on the thickness of the connection region between the source region and the drift region. Therefore, for the lateral SIC-JFET device of the present application, the thickness of the connection region between the source region and the drift region is relatively small. Therefore, it can be realized that the control voltage is determined by the thickness of the connection region between the source region and the drift region. The lateral SIC-JFET device of the present application can achieve a relatively small control voltage, and at the same time, the structure is also easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:
[0029] Figure 1 It is a cross-sectional view of a lateral SIC-JFET device of an authorized patent CN116759464B.
[0030] Figure 2 It is a schematic diagram of the lateral SIC-JFET device of the present application;
[0031] Figure 3 It is a schematic diagram of the completion of step 1 of the method for manufacturing the lateral SIC-JFET device of the present application;
[0032] Figure 4Schematic diagram for completing Step 2 of the preparation method of the lateral SIC-JFET device of the present application;
[0033] Figure 5 Schematic diagram for completing Step 3 of the preparation method of the lateral SIC-JFET device of the present application;
[0034] Figure 6 Schematic diagram for completing Step 4 of the preparation method of the lateral SIC-JFET device of the present application;
[0035] Figure 7 Schematic diagram for completing Step 5 of the preparation method of the lateral SIC-JFET device of the present application;
[0036] Figure 8 Schematic diagram for completing Step 6 of the preparation method of the lateral SIC-JFET device of the present application;
[0037] Figure 9 Schematic diagram for completing Step 7 of the preparation method of the lateral SIC-JFET device of the present application;
[0038] Figure 10 Schematic diagram for completing Step 8 of the preparation method of the lateral SIC-JFET device of the present application;
[0039] Figure 11 Simulation diagram of the lateral SIC-JFET device of the present application;
[0040] Figure 12 Id-Vg curve graph of the lateral SIC-JFET device of the present application.
[0041] Reference numerals:
[0042] Substrate 101, first epitaxial layer 102, second epitaxial layer 103,
[0043] Drift region 104, first region of the drift region 104-1, drain region 105,
[0044] Drain 106, first body region 107, body region contact region 108, channel region 109, gate 110,
[0045] Source region 111, second body region 112,
[0046] Oxide layer 206,
[0047] Source contact metal compound 201-1, gate contact metal compound 201-2, drain contact metal compound 201-3,
[0048] Gate shielding plate 202,
[0049] Source contact via 203-1, gate contact via 203-2, drain contact via 203-3,
[0050] Source metal layer 204-1, drain metal layer 204-3,
[0051] Ground back hole 205,
[0052] Drift region base 104-0, first photoresist 302-1, second photoresist 302-2,
[0053] First hard mask plate 301, second hard mask plate base 303-0, second hard mask plate 303. Detailed implementation mode
[0054] In order to make the technical solutions and advantages in this application clearer and more understandable, the following further details the exemplary embodiments of this application with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other.
[0055] Embodiment 1
[0056] As Figure 2 shown, the lateral SIC-JFET device of this application includes:
[0057] A substrate 101 of a second doping type;
[0058] An epitaxial layer of a first doping type;
[0059] A source region 111 of a second doping type, formed in the epitaxial layer, and the source region 111 has two sides which are a first side and a second side respectively;
[0060] A drift region 104 of a second doping type, formed in the epitaxial layer; the drift region 104 is connected to the position of the second side of the source region 111;
[0061] A gate 110 of a first doping type, formed in the drift region 104 and the gate 110 is connected to the position of the second side of the source region 111;
[0062] Wherein, the upper part of the second side of the source region 111 is connected to the gate 110, and the lower part of the second side of the source region 111 is directly connected to the drift region 104; the turn-off of the connection region between the source region 111 and the drift region 104 is realized by the PN junction formed by the gate 110 and the source region 111.
[0063] In the lateral SIC-JFET device of the present application, the lower part of the second side of the source region 111 of the second doping type is directly connected to the drift region 104 of the second doping type, achieving the following effects:
[0064] On the one hand, the connection between the source region 111 and the drift region 104 of the same second doping type is realized. Since both are of the second doping type, it is a conduction channel similar to a conductor. That is, under normal conditions, the source region 111 and the drift region 104 are in a conducting state. Therefore, a turn-off method needs to be set to turn off the normal conduction mode between the source region 111 and the drift region 104, so as to realize the conduction and turn-off of the lateral SIC-JFET device.
[0065] On the other hand, the connection area between the source region 111 and the drift region 104 is only the lower part of the second side of the source region 110. That is, as long as the position of the connection area between the source region 111 and the drift region 104 is turned off, the source region 110 and the drift region 104 can be disconnected. Therefore, the position that needs to be turned off is only the connection area between the source region 111 and the drift region 104.
[0066] The following takes the first doping type as P-type and the second doping type as N-type as an example to illustrate the lateral SIC-JFET device of the present application:
[0067] The N-type source region 111 is connected to the N-type drift region 104, which is a conduction channel similar to a conductor, and the connection area between the source region 111 and the drift region 104 is only the lower part of the second side of the source region 110.
[0068] When the lateral SIC-JFET device of the present application is conducting, the source region 111 is connected to the N-type drift region 104, and carriers are conducted through the N-type source region 111 and the N-type drift region 104.
[0069] The connection area between the source region 111 and the drift region 104 is only the lower part of the second side of the source region 110. As long as the connection area between the source region 111 and the drift region 104 (i.e., the lower part of the second side of the source region 110) in the source region 111 and the drift region 104 is depleted, the turn-off can be achieved.
[0070] When the lateral SIC-JFET device of the present application is turned off, the potential applied to the gate 110 (i.e., the control voltage) only needs to widen the depletion region of the PN junction formed by the gate 110 and the source region 111 so that the connection region between the source region 111 and the drift region 104 is not conducting to achieve turning off. That is, the connection region between the source region 111 and the drift region 104 is depleted. Since the connection region between the source region 111 and the drift region 104 actually plays a role in controlling turning off and on, the lateral SIC-JFET device of the present application no longer requires an additional channel region for controlling conduction and turning off. Compared with the background art, the lateral SIC-JFET device of the present application no longer requires the channel region 109 to be provided, and thus does not require the portion of the first body region 107 located below the channel region 109 for assisting in depleting the channel region 109. Therefore, the structure of the lateral SIC-JFET device of the present application is simple, and the manufacturing process is relatively simple.
[0071] In the background art Figure 1 For the lateral SIC-JFET device, the entire left side of the source region 111 is connected to the channel region 109, and the entire right side of the channel region 109 is connected to the drift region 104. When the lateral SIC-JFET device is conducting, the source region 111, the channel region 109, and the drift region 104 are conducting. To turn off the device, the potential applied to the gate 110 needs to widen the depletion region of the entire thickness of the channel region 109 (i.e., deplete the entire thickness of the channel region 109) to achieve turning off.
[0072] The control voltage of the lateral SIC-JFET device of the present application depends on the thickness of the connection region between the source region 111 and the drift region 104. Therefore, for the lateral SIC-JFET device of the present application, the thickness of the connection region between the source region 111 and the drift region 104 is small. Therefore, it can be achieved that the control voltage is determined by the thickness of the connection region between the source region 111 and the drift region 104. The lateral SIC-JFET device of the present application can achieve a small control voltage, and at the same time, the structure is also easy to implement.
[0073] It should be noted that the actually effective region of the gate 110 of the lateral SIC-JFET device of the present application is only the connection position of the connection region between the source region 111 and the drift region 104. The size of the connection region of the source region 111 can be very small, so as to achieve a very small control voltage and improve the overall performance of the device.
[0074] In implementation, the value range of the ratio of the thickness of the connection region between the source region 111 and the drift region 104 to the thickness of the source region 111 is greater than 0 and less than or equal to 0.5;
[0075] Wherein, the thickness of the connection region between the source region 111 and the drift region 104 is the dimension of the connection region in the thickness direction of the lateral SIC-JFET device.
[0076] During implementation, as Figure 2 shown, the lateral SIC-JFET device of the present application further includes:
[0077] A second body region 112 of the first doping type, formed under the source region 111, and the second body region 112 is connected to the drift region 104;
[0078] Wherein, the turn-off of the connection region between the source region 111 and the drift region 104 is realized by a gate 110 of the first doping type, a source region 111 of the second doping type, and a second body region 112 of the first doping type.
[0079] Hereinafter, taking the first doping type as P-type and the second doping type as N-type as an example for illustration, the turn-off of the connection region between the N-type source region 111 and the N-type drift region 104 is realized by a PNP junction formed by a P-type gate 110, an N-type source region 111, and a P-type second body region 112. When the lateral SIC-JFET device of the present application is turned off, the potential (i.e., the control voltage) applied to the gate 110 needs to widen the depletion region of the PNP junction formed by the P-type gate 110, the N-type source region 111, and the P-type second body region 112 so that the connection region between the source region 111 and the drift region 104 is not conducting, thereby realizing turn-off. That is, the connection region between the source region 111 and the drift region 104 is depleted.
[0080] During implementation, as Figure 2 shown, the region of the drift region 104 located under the gate 110 is the first drift region 104-1; correspondingly, the lower part of the second side surface of the source region 111 is directly connected to the first drift region 104-1;
[0081] The upper surface of the first drift region 104-1 is higher than the lower surface of the source region 111 and lower than the upper surface of the source region 111.
[0082] In this way, it can be ensured that the lower part of the second side surface of the source region 111 is directly connected to the first drift region 104-1.
[0083] During implementation, as Figure 2 shown, the second body region 112 and the side surface of the source region 111 are flush;
[0084] The side surface of the gate 110 and the drift region 104 connecting the source region 111 are flush.
[0085] The side surfaces of the two-layer structure of the second body region 112 and the source region 111 arranged from bottom to top are flush. In this way, the structure is simple and convenient for preparation.
[0086] The side surface of the gate 110 and the drift region 104 connecting the source region 111 are flush. In this way, the structure is simple and convenient for preparation.
[0087] In the prior art Figure 1 in the lateral SIC-JFET device, there needs to be a gap between the gate 110 and the source region 111, and there needs to be a gap between the gate 110 and the drift region 104. The gap position is part of the epitaxial layer. The reason is that in the prior art Figure 1 in the lateral SIC-JFET device, in order to turn off the device, the potential applied to the gate 110 needs to widen the depletion region of the entire thickness of the channel region 109 (i.e., deplete the entire thickness of the channel region 109) to achieve turning off. In this way, the voltage that needs to be applied to the gate 110 is 15 volts to deplete the entire thickness of the channel region 109. Therefore, it is necessary to ensure that the breakdown voltage of the gate 110 is greater than 15 volts. A PN junction is formed between the part of the epitaxial layer at the gap position and the gate 110 to increase the breakdown voltage of the gate 110, such as the breakdown voltage of the gate 110 being 20V.
[0088] In the lateral SIC-JFET device of the present application, due to the small thickness of the connection region between the source region 111 and the drift region 104, the control voltage for turning off the connection region between the source region 111 and the drift region 104 (i.e., the voltage applied to the gate 110) can be made smaller, such as 5V. And in the lateral SIC-JFET device of the present application, due to the high breakdown voltage ability of the SIC material itself, regardless of the doping concentration of the source region 111 and the drift region 104 on both sides of the gate 110, the breakdown voltage of the gate 110 can be maintained at 10 volts. At this time, the breakdown voltage of the gate 110 is already higher than the control voltage for turning off the connection region between the source region 111 and the drift region 104 (i.e., the voltage applied to the gate 110). Therefore, there is no need to further increase the breakdown voltage of the gate 110; furthermore, there is no need for a gap between the gate 110 and the source region 111, and between the gate 110 and the drift region 104.
[0089] Therefore, the second body region 112 of the lateral SIC-JFET device of the present application is flush with the side surface of the source region 111, the gate 110 is flush with the side surface of the drift region 104 connecting the source region 111, and the gate 110 and the drift region 104 can be directly connected without a gap. The reason for the corresponding simple manufacturing process is still due to the small thickness of the connection region between the source region 111 and the drift region 104, which enables the control voltage for turning off the connection region between the source region 111 and the drift region 104 (i.e., the voltage applied to the gate 110) to be made smaller.
[0090] Specifically, as Figure 2 shown, the source region 111 is formed downward from the upper surface of the epitaxial layer.
[0091] Specifically, as Figure 2As shown, the drift region 104 is formed downward from the upper surface of the epitaxial layer, and the gate 110 is formed downward from the upper surface of the drift region 104.
[0092] Specifically, as Figure 2 shown, the thickness of the drift region 104 is greater than the thickness of the source region 111, and the thickness of the gate 110 is less than the thickness of the source region 111.
[0093] Specifically, as Figure 2 shown, the lateral SiC-JFET device of the present application further includes:
[0094] An oxide layer 206, formed on the epitaxial layer;
[0095] A body region contact region 108, formed downward from the epitaxial layer and disposed adjacent to the source region 111 and the second body region 112;
[0096] A source contact metal compound 201-1 located within the oxide layer 206 and above the body region contact region 108 and the source region 111;
[0097] A source contact via hole 203-1 located within the oxide layer and above the source contact metal compound 201-1;
[0098] A source metal layer 204-1 located within the oxide layer and above the source contact via hole 203-1;
[0099] A ground back hole 205, connected to the source metal layer 204-1 and penetrating through to the bottom of the substrate 101 from top to bottom;
[0100] Wherein, the bottom of the substrate is grounded and connected to a heat dissipation structure.
[0101] The source end includes the source region 111, the second body region 112, and the body region contact region 108. In this way, grounding of the source end is achieved through the source contact metal compound 201-1, the source contact via hole 203-1, the source metal layer 204-1, and the ground back hole 205, and connection of the source end to the heat dissipation structure is also achieved. Heat generated at the source end can be quickly dissipated, enabling the lateral SiC-JFET device of the embodiment of the present application to be applicable to radio frequency applications.
[0102] Specifically, as Figure 2 shown, the lateral SiC-JFET device of the present application further includes:
[0103] A drain 106, located within the drift region 104 and spaced apart from the gate 110;
[0104] A drain region 105 located below the drain 106.
[0105] The drain contact metal compound 201-3 located within the oxide layer and above the drain 106;
[0106] The drain contact via 203-3 located within the oxide layer and above the drain contact metal compound 201-3;
[0107] The drain metal layer 204-3 located within the oxide layer and above the drain contact via 203-3.
[0108] The drain end includes the drain region 105 and the drain 106. The connection of the drain end is realized through the drain contact metal compound 201-3, the drain contact via 203-3, and the drain metal layer 204-3.
[0109] Specifically, as Figure 2 shown, the lateral SIC-JFET device of the present application further includes:
[0110] The gate contact metal compound 201-2 located within the oxide layer and above the gate 110;
[0111] The gate contact via (not shown in the figure) located within the oxide layer and above the gate contact metal compound 201-2.
[0112] The gate end includes the gate 110 and the gate contact metal compound 201-1. The connection of the gate end is realized through the gate contact metal compound 201-2 and the gate contact via.
[0113] Specifically, as Figure 2 shown, the epitaxial layer includes:
[0114] The first epitaxial layer 102 formed on the substrate;
[0115] The second epitaxial layer 103 formed on the first epitaxial layer 102;
[0116] Wherein, the doping concentration of the first epitaxial layer 102 is greater than that of the second epitaxial layer 103.
[0117] The drain region 105, the drain 106, the body region contact area 108, the gate 110, the source region 111, and the second body region 112 are formed in the second epitaxial layer 103.
[0118] Embodiment 2
[0119] The embodiment of the present application provides a method for manufacturing a lateral SIC-JFET device, including the following steps:
[0120] Form a first-doped epitaxial layer on a second-doped substrate 101;
[0121] A drift region base 104-0 of a second doping type is formed within the epitaxial layer;
[0122] A gate 110 of a first doping type is formed within the drift region base 104-0, and one side surface of the gate 110 is flush with one side surface of the drift region base 104-0; correspondingly, the drift region base 104-0 becomes a drift region 104;
[0123] A source region 111 of a second doping type is formed within the epitaxial layer. The source region 111 has two side surfaces which are a first side surface and a second side surface respectively. The second side surface of the source region 111 is connected to the drift region 104; the second side surface of the source region 111 is connected to the gate 110;
[0124] Wherein, the upper part of the second side surface of the source region 111 is connected to the gate 110, and the lower part of the second side surface of the source region 111 is directly connected to the drift region 104.
[0125] In implementation, the step of forming a drift region base 104-0 of a second doping type within the epitaxial layer specifically includes:
[0126] Deposit a whole layer of a first hard mask plate base on the epitaxial layer through a deposition process;
[0127] According to the pattern and position of the drift region implantation, etch away a part of the first hard mask plate base to form a window to expose the position where the drift region needs to be formed, and the first hard mask plate base becomes a first hard mask plate 301;
[0128] Taking the window of the first hard mask plate 301 as a boundary, form the drift region base 104-0 through an implantation process.
[0129] In implementation, the step of forming a gate 110 of a first doping type within the drift region base 104-0, and one side surface of the gate 110 being flush with one side surface of the drift region base 104-0 specifically includes:
[0130] Form a whole layer of a first photoresist base, etch away a part according to the pattern and position of the gate formation to form a window, and the first photoresist base becomes a first photoresist 302-1;
[0131] Taking the window of the first photoresist 302-1 and the edge of the first hard mask plate 301 as boundaries, form the gate 110 through an implantation process.
[0132] During the formation of the gate 110, with the window of the first photoresist 302-1 and the edge of the first hard mask 301 as the boundary, the relatively large-sized first photoresist 302-1 and the relatively large-sized first hard mask 301 serve as the covers for the self-alignment process. In this way, the preparation process of the relatively large-sized covers has very little difficulty, making the implementation of the preparation method of the lateral SIC-JFET device in the embodiments of the present application relatively feasible.
[0133] In implementation, a source region 111 of a second doping type is formed in the epitaxial layer. The source region 111 has two sides, namely a first side and a second side. The second side of the source region 111 is connected to the drift region base 104-0); the step of connecting the second side of the source region 111 to the gate 110 specifically includes:
[0134] Completely wash off the first photoresist 302-1; then, form a whole-layer second hard mask base 303-0; among them, different chemicals are required for etching the second hard mask base 303-0 and the first hard mask 301.
[0135] Use a chemical to etch the second hard mask base 303-0. At this time, this chemical cannot etch the first hard mask until the first hard mask 301 is exposed; at this time, the second hard mask base 303-0 becomes the second hard mask 303; then, use another chemical to completely etch away the first hard mask 303.
[0136] Form a whole-layer second photoresist base, etch away a part to form a window according to the pattern and position of the source region, and the second photoresist base becomes the second photoresist 302-2; then, with the window of the second photoresist 302-2 and the edge of the second hard mask 303 as the boundary, form the source region 111 through an implantation process.
[0137] During the formation of the source region 111, with the window of the second photoresist 302-2 and the edge of the second hard mask 303 as the boundary, the relatively large-sized second photoresist 302-2 and the relatively large-sized second hard mask 303 serve as the covers for the self-alignment process. In this way, the preparation process of the relatively large-sized covers has very little difficulty, making the implementation of the preparation method of the lateral SIC-JFET device in the embodiments of the present application relatively feasible.
[0138] In addition, during the formation of the gate 110, the first photoresist 302-1 and the first hard mask 301 are used as the covers for self-alignment;
[0139] During the formation of the source region 111, the second photoresist 302-2 and the second hard mask 303 are used as the covers for self-alignment.
[0140] The covers are independent of each other and do not affect each other.
[0141] If the same mask is used, during multiple etching processes, this same mask will inevitably be gradually eroded, affecting the shape of the mask and further affecting the masking effect. Additionally, especially for masks with small sizes (such as slender strip masks), the manufacturing process of masks with small sizes is already difficult. At the same time, the possibility of erosion of masks with small sizes and the impact on the masks cannot be ignored.
[0142] In implementation, in the step of forming the source region 111 by an implantation process with the window of the second photoresist 302-2 and the edge of the second hard mask 303 as the boundary, it further includes:
[0143] Forming the second body region 112 by an implantation process.
[0144] Taking the first doping type as P-type and the second doping type as N-type as an example below, a preparation method of a lateral SIC-JFET device according to an embodiment of the present application will be described in chronological order:
[0145] As Figure 3 shown, step 1: First, grow a heavily doped P-type first epitaxial layer 102 on a heavily doped N-type substrate 101; subsequently, grow a lightly doped P-type second epitaxial layer 103 on this basis.
[0146] As Figure 4 shown, step 2: First, deposit a whole layer of the first hard mask base on the second epitaxial layer 103 by a deposition process; then, according to the pattern and position of the drift region implantation, etch away a part of the first hard mask base to form a window to expose the position where the drift region needs to be formed, and the first hard mask base becomes the first hard mask 301; finally, with the window of the first hard mask 301 as the boundary, form the drift region base 104-0 by an implantation process.
[0147] As Figure 5 shown, step 3: First, form a whole layer of the first photoresist base, etch away a part according to the pattern and position of the gate formation to form a window, and the first photoresist base becomes the first photoresist 302-1; then, with the window of the first photoresist 302-1 and the right edge of the first hard mask 301 as the boundary, form the gate 110 by an implantation process. Correspondingly, the drift region base 104-0 becomes the drift region 104;
[0148] In this process, the left boundary of the gate 110 and the drift region 104 is completely determined by the right edge of the first hard mask 301.
[0149] As Figure 6As shown, step 4: First, wash away all of the first photoresist 302-1; then, form a whole layer of the second hard mask base 303-0; wherein, different chemicals are required for etching the second hard mask base 303-0 and the first hard mask 301.
[0150] As Figure 7 shown, step 5: First, use a chemical to etch the second hard mask base 303-0. At this time, this chemical cannot etch the first hard mask; until the first hard mask 301 is exposed, and at this time the second hard mask base 303-0 becomes the second hard mask 303; then, use another chemical to completely etch away the first hard mask 301.
[0151] As Figure 8 shown, step 6: First, form a whole layer of the second photoresist base, and etch away part to form a window according to the pattern and position of the source region. The second photoresist base becomes the second photoresist 302-2; then, taking the window of the second photoresist 302-2 and the left edge of the second hard mask 303 as boundaries, form the source region 111 and the second body region 112 through an implantation process. Note that the right edges of the source region 111 and the second body region 112 are completely aligned with the left edge of the second hard mask 303, and at the same time are also completely aligned with the left edges of the gate 110 and the drift region 104.
[0152] As Figure 9 shown, step 7: First, remove the second photoresist 302-2 and the second hard mask 303; then, implant to form the body region contact area 108, the drain region 105, and the drain electrode 106.
[0153] As Figure 10 shown, step 8: On the above basis, form the oxide layer 206, the gate shielding plate 202, the source contact via 203-1, the gate contact via 203-2, the drain contact via 203-3, the source metal layer 204-1, the drain metal layer 204-3, and the ground back hole 205.
[0154] The requirement for the device structure is that the right end of the source region 111, the left end of the gate 110, and the left end of the drift region 104 are completely aligned and can be connected. In the manufacturing method of the lateral SIC-JFET device of the present application, there is no problem of lithography misalignment, so it can be achieved. The specific reasons are as follows:
[0155] For the "non-self-alignment process" in the prior art to achieve the connection between the source region 111 and the drift region 104, the injection window positions of these two regions cannot be aligned by lithography. Since there will be an alignment deviation as long as it is a lithography process, which is abbreviated as alignment deviation, in the device design process of the prior art, especially in the layout design (such as the main patent), there will be a little overlap between the injection window positions of the source region 111 and the drift region 104, that is, overlay. The size of this overlay depends on the accuracy limit of the lithography machine. For most of the lithography machines of power chips currently, this size is about 0.2μm.
[0156] For the fully self-aligned process of this application, the two-time injection alignment of the source region 111 and the drift region 104 is achieved through a hard mask, without the problem of lithography error, so there is no need to consider the problem of overlay.
[0157] Figure 11 It is a simulation diagram of the lateral SIC-JFET device of this application. Figure 11 It shows that under the conventional process means, the device has manufacturability and the device solution is feasible.
[0158] Figure 12 It is the Id-Vg curve diagram of the lateral SIC-JFET device of this application. As Figure 12 shown, as the gate voltage Vg increases, the drain current Id of the device starts to increase significantly near -2.5V, and the device turns on. It shows that the device can achieve a good turn-on and turn-off function.
[0159] Those skilled in the art should understand that the embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can adopt the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, this application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0160] This application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of this application. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate for implementing in the process Figure 1 each process or multiple processes and / or blocksFigure 1 means for the functions specified in one or more boxes.
[0161] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce a manufacture including an instruction means that implements the functions specified in one Figure 1 one or more processes and / or boxes Figure 1 or more boxes.
[0162] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in one Figure 1 one or more processes and / or boxes Figure 1 or more boxes.
[0163] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present application.
[0164] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.
Claims
1. A lateral SIC-JFET device, characterized in that: include:: A substrate (101) of a second doping type; an epitaxial layer of a first doping type; A source region (111) of a second doping type is formed in the epitaxial layer, the source region (111) having two side surfaces, namely a first side surface and a second side surface; A drift region (104) of a second doping type is formed in the epitaxial layer, and the drift region (104) is connected to a position on a second side surface of the source region (111); A gate (110) of a first doping type is formed in the drift region (104) and the gate (110) is connected to a position on the second side of the source region (111); The upper portion of the second side surface of the source region (111) is connected to the gate (110), and the lower portion of the second side surface of the source region (111) is directly connected to the drift region (104).
2. The lateral SIC-JFET device according to claim 1, characterized in that: The ratio of the thickness of the connecting region between the source region (111) and the drift region (104) to the thickness of the source region (111) is in the range of greater than 0 and less than or equal to 0.5; The thickness of the connection region between the source region (111) and the drift region (104) is the dimension of the connection region in the thickness direction of the lateral SIC-JFET device.
3. The lateral SIC-JFET device according to claim 1 or 2, characterized in that: The region of the drift region (104) located below the gate (110) is the first region (104-1) of the drift region; correspondingly, the lower portion of the second side surface of the source region (111) is directly connected to the first region (104-1) of the drift region; The upper surface of the first region (104-1) of the drift region is higher than the lower surface of the source region (111) and lower than the upper surface of the source region (111).
4. The lateral SIC-JFET device according to claim 1 or 2, characterized in that: Also includes: A second body region (112) of a first doping type is formed below the source region (111), and the second body region (112) is connected to the drift region (104); The connection region between the source region (111) and the drift region (104) is turned off by a gate (110) of the first doping type, a source region (111) of the second doping type, and a second body region (112) of the first doping type.
5. The lateral SIC-JFET device according to claim 4, characterized in that: The side surfaces of the second body region (112) and the source region (111) are flush; The gate (110) is flush with a side surface of the drift region (104) connected to the source region (111).
6. A method for preparing a lateral SIC-JFET device, characterized in that: The steps include: forming an epitaxial layer of a first doping type on a substrate (101) of a second doping type; forming a drift region foundation (104-0) of a second doping type in the epitaxial layer; A gate (110) of a first doping type is formed in the drift region base (104-0), and one side surface of the gate (110) is flush with one side surface of the drift region base (104-0); correspondingly, the drift region base becomes the drift region (104); A source region (111) of a second doping type is formed in the epitaxial layer, the source region (111) having two side surfaces, namely a first side surface and a second side surface, the second side surface of the source region (111) being connected to the drift region (104); and the second side surface of the source region (111) being connected to the gate (110); The upper portion of the second side surface of the source region (111) is connected to the gate (110), and the lower portion of the second side surface of the source region (111) is directly connected to the drift region (104).
7. The method for preparing a lateral SIC-JFET device according to claim 6, characterized in that: The step of forming a drift region foundation (104-0) of a second doping type in the epitaxial layer specifically comprises: Depositing a first hard mask base of a whole layer on the epitaxial layer by a deposition process; According to the pattern and position of the drift region implantation, a portion of the first hard mask base is etched away to form a window to expose the position where the drift region needs to be formed, and the first hard mask base becomes a first hard mask (301); A drift region foundation (104-0) is formed by an implantation process with the window of the first hard mask (301) as the boundary.
8. The method for preparing a lateral SIC-JFET device according to claim 7, characterized in that: The step of forming a gate (110) of a first doping type in the drift region base (104-0), wherein one side surface of the gate (110) is flush with one side surface of the drift region base (104-0), specifically comprises: A first photoresist base of the entire layer is formed, and a portion is etched away to form a window according to the pattern and position formed by the gate, and the first photoresist base becomes a first photoresist (302-1); A gate (110) is formed by an implantation process with the window of the first photoresist (302-1) and the edge of the first hard mask (301) as boundaries.
9. The method for preparing a lateral SIC-JFET device according to claim 8, characterized in that: A source region (111) of a second doping type is formed in the epitaxial layer, the source region (111) having two side surfaces, namely a first side surface and a second side surface, the second side surface of the source region (111) being connected to the drift region (104); and the step of connecting the second side surface of the source region (111) to the gate (110) specifically comprises: The first photoresist (302-1) is completely washed off; then, a second hard mask base (303-0) of a whole layer is formed; wherein the second hard mask base (303-0) and the first hard mask (301) require two different solutions for etching; The second hard mask base (303-0) is etched using a chemical solution, at which time the chemical solution cannot etch the first hard mask, until the first hard mask (301) is exposed; at this time, the second hard mask base (303-0) becomes the second hard mask (303); then, another chemical solution is used to completely etch away the first hard mask (303); A second photoresist base is formed as a whole layer, and a part is etched away to form a window according to the pattern and position formed in the source region, and the second photoresist base becomes a second photoresist (302-2); then, with the window of the second photoresist (302-2) and the edge of the second hard mask (303) as the boundary, a source region (111) is formed through an implantation process.
10. The method for preparing a lateral SIC-JFET device according to claim 8, characterized in that: The step of forming a source region (111) by an implantation process with the window of the second photoresist (302-2) and the edge of the second hard mask (303) as the boundary also includes: The second body region (112) is formed by an implantation process.