Transverse SIC-JFET device and preparation method thereof
By optimizing the connection structure of the channel region and the source region in the lateral SIC-JFET device, the problem of large control voltage when traditional devices maintain high saturation current Idsat is solved, and the control voltage reduction and device performance improvement are achieved.
Patent Information
- Application Number
- CN202510280606.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-06-24
AI Technical Summary
The traditional lateral SIC-JFET device structure is difficult to achieve a small control voltage while maintaining a large saturation current Idsat, resulting in a low manufacturingability and mass production potential of the device.
By optimizing the connection structure of the channel region and the source region in the transverse SIC-JFET device, the thickness of the channel region and the source region connection region is much smaller than the entire thickness of the channel region, thereby achieving a reduction in control voltage.
While achieving a large saturation current Idsat, the control voltage is reduced, which improves the overall performance of the device, simplifies the preparation process, improves manufacturability and mass production feasibility.
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Figure CN120201757A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a lateral SIC-JFET device and a method for manufacturing the same. Background Art
[0002] The lateral SIC-JFET device is a semiconductor device that is very suitable for applications in the radio frequency and power fields.
[0003] First, as a wide bandgap semiconductor material, SiC has a higher breakdown field strength compared to Si. Therefore, devices with the same breakdown voltage rating can be achieved in SiC, but with a shorter drift region and a smaller on-resistance.
[0004] Second, the current conduction of the lateral SIC-JFET device occurs within the SiC body, rather than flowing through the SiC-SiO2 interface as in SiC MOS devices. Therefore, many problems such as low carrier mobility and poor reliability caused by defects at the interface can be avoided. In addition, the SiC material has a high thermal conductivity coefficient, providing a natural heat dissipation advantage in power applications.
[0005] Figure 1 is a cross-sectional view of a currently disclosed SiC L-JFET device.
[0006] For this device, its source region 111 and body region 107-0 are both grounded. Its basic working principle is to turn off the entire device by depleting the channel region 109 with the potential on the gate 110. By gradually returning the potential on the gate 110 to 0, the device conducts.
[0007] In order to achieve an as small as possible on-resistance Rdson and an as large as possible saturation current Idsat when the device is conducting, the doping concentration of the channel region 109 should be as large as possible. That is, in order to make the saturation current Idsat a little larger, it is desired that the doping concentration of the channel region 109 is larger.
[0008] However, if the doping concentration of the channel region 109 is larger, it will result in a higher potential being required on the gate 110 to deplete the channel region 109. That is, if the doping concentration of the channel region 109 is larger, the control voltage of the device is larger. If the device is a normally-off device, the control voltage is the turn-on voltage, and if the device is a normally-on device, the control voltage is the turn-off voltage. Therefore, Figure 1 when the saturation current Idsat of the device is larger, the device requires a larger control voltage.
[0009] However, from the perspective of device control, a smaller control voltage is desired.
[0010] Taking the common negative voltage turn-off device in the current industrial scenario as an example, generally, the turn-off voltage of the device is required to be around -5V. A too negative turn-off voltage will lead to difficulties in the design of the device gate power supply circuit, excessive gate input power, and thus a lower device gain. In addition, while ensuring that the device can be turned off at -5V, the saturation current Idsat of the device is preferably able to reach 1000 mA / mm to ensure the power density of the device.
[0011] For Figure 1 such a device, to alleviate the contradictory relationship between the turn-on voltage and the saturation current Idsat as much as possible, it can only be achieved by continuously reducing the length of the gate 110, that is, the lateral dimension of the channel region 109. A smaller length of the gate 110 can also be depleted at a smaller voltage, which is beneficial to the saturation current Idsat of the device. However, this method is limited by the lithography resolution limit of the lithography machine. For example, the current lithography line width limit of the i-line lithography machine is 0.4 μm, which determines that such a lithography machine cannot be used to manufacture this device with a gate 110 length less than 0.4 μm.
[0012] At the same time, to ensure the integrity of the connection between the source region 111, the channel region 109, and the drift region 104 of the device, the lithography window positions of these three regions of the device are generally set to overlap each other. The size of this overlapping region is the minimum alignment accuracy of the lithography machine, which is generally half of the lithography limit line width of the lithography machine. In the previous example, it is ±0.2 μm. However, the actual size of the overlapping region of the device actually manufactured will float within 0 - 0.4 μm, which causes the doping concentration of the channel region 109 to be affected by the drift region 104 and the source region 111. And the proportion of this influence will increase rapidly with the reduction of the length of the gate 110. Due to the alignment problem of the lithography machine on the same wafer, the channel region concentrations of the devices at different positions vary greatly, and thus the device parameters are very different, greatly reducing the large-scale mass production potential and manufacturability of this device. That is, it is difficult to achieve the method of reducing the control voltage by reducing the length of the gate 110, and the mass production difficulty is large.
[0013] Therefore, it is difficult to achieve a relatively small control voltage while maintaining a relatively large saturation current Idsat in the traditional lateral SIC-JFET device structure, which is a technical problem that those skilled in the art urgently need to solve.
[0014] The above information disclosed in the background art is only used to strengthen the understanding of the background of the present application. Therefore, it may contain information on the prior art that has not been known to those of ordinary skill in the art. Summary of the Invention
[0015] The present application provides a lateral SIC-JFET device and a manufacturing method thereof, so as to solve the technical problem that it is difficult to achieve a relatively small control voltage while maintaining a relatively large saturation current Idsat in the structure of a traditional lateral SIC-JFET device.
[0016] The present application provides a lateral SIC-JFET device, including:
[0017] A substrate of a second doping type;
[0018] An epitaxial layer of a first doping type, formed on the substrate;
[0019] A channel region of a first doping type, formed in the epitaxial layer, and the channel region has two side surfaces which are a first side surface and a second side surface respectively;
[0020] A source region of a second doping type, formed in the epitaxial layer; the source region is connected to the upper part of the first side surface of the channel region, so that the channel region is connected to the source region only through a part of the first side surface of the channel region;
[0021] A gate of a first doping type, formed on the channel region;
[0022] A drift region of a second doping type, formed in the epitaxial layer, and the drift region is connected to the second side surface of the channel region.
[0023] The present application also provides a manufacturing method of a lateral SIC-JFET device, including the following steps:
[0024] Forming an epitaxial layer of a first doping type on a substrate of a second doping type;
[0025] Forming a channel region of a first doping type in the epitaxial layer, and the channel region has two side surfaces which are a first side surface and a second side surface respectively;
[0026] Forming a gate of a first doping type on the channel region;
[0027] Forming a drift region of a second doping type in the epitaxial layer, and the drift region is connected to the second side surface of the channel region;
[0028] Forming a source region of a second doping type in the epitaxial layer; the source region is connected to the upper part of the first side surface of the channel region, so that the channel region is connected to the source region only through a part of the first side surface of the channel region.
[0029] Due to the above technical solutions adopted by the present application, the following technical effects are achieved:
[0030] The control voltage of the lateral SIC-JFET device of the present application depends on the thickness of the channel region and the source region connection region. Therefore, in the lateral SIC-JFET device of the present application, the thickness of the channel region and the source region connection region is much smaller than the entire thickness of the channel region. Therefore, it is possible to achieve that the doping concentration of the channel region is determined by the saturation current Idsat, and the control voltage is determined by the thickness of the channel region and the source region connection region. The lateral SIC-JFET device of the present application can achieve a larger saturation current Idsat while achieving a smaller control voltage. At the same time, the structure is also easy to implement. Description of the Drawings
[0031] The drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:
[0032] Figure 1 is a cross-sectional view of a currently disclosed SiC L-JFET device;
[0033] Figure 2 is a schematic diagram of the lateral SIC-JFET device of the present application;
[0034] Figure 3 is a schematic diagram of the completion of Step 1 of the manufacturing method of the lateral SIC-JFET device of the present application;
[0035] Figure 4 is a schematic diagram of the completion of Step 2 of the manufacturing method of the lateral SIC-JFET device of the present application;
[0036] Figure 5 is a schematic diagram of the completion of Step 3 of the manufacturing method of the lateral SIC-JFET device of the present application;
[0037] Figure 6 is a schematic diagram of the completion of Step 4 of the manufacturing method of the lateral SIC-JFET device of the present application;
[0038] Figure 7 is a schematic diagram of the completion of Step 5 of the manufacturing method of the lateral SIC-JFET device of the present application;
[0039] Figure 8 is a schematic diagram of the completion of Step 6 of the manufacturing method of the lateral SIC-JFET device of the present application;
[0040] Figure 9 is a schematic diagram of the completion of Step 7 of the manufacturing method of the lateral SIC-JFET device of the present application;
[0041] Figure 10Schematic diagram for completing step 8 of the preparation method of the lateral SIC-JFET device of the present application;
[0042] Figure 11 Simulation diagram of the lateral SIC-JFET device of the present application;
[0043] Figure 12 Id-Vg curve graph of the lateral SIC-JFET device of the present application.
[0044] Reference numerals:
[0045] Substrate 101, first epitaxial layer 102, second epitaxial layer 103, drift region 104, drain region 105,
[0046] Drain 106, body region 107-0, first body region 107, body contact region 108, channel region 109,
[0047] Gate 110, source region 111, second body region 112,
[0048] Oxide layer 206,
[0049] Source contact metal compound 201-1, gate contact metal compound 201-2, drain contact metal compound 201-3,
[0050] Gate shielding plate 202,
[0051] Source contact via 203-1, gate contact via 203-2, drain contact via 203-3,
[0052] Source metal layer 204-1, drain metal layer 204-3,
[0053] Ground back hole 205,
[0054] Mask plate 301, dummy gate 302, gate injection pattern window 110-1, photoresist 303. Detailed implementation manners
[0055] In order to make the technical solutions and advantages in the present application clearer and more understandable, the following further details the exemplary embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
[0056] Embodiment 1
[0057] As Figure 2 shown, a lateral SIC-JFET device of the present application includes:
[0058] A substrate 101 of a second doping type;
[0059] An epitaxial layer of a first doping type, formed on the substrate 101;
[0060] A channel region 109 of a first doping type, formed in the epitaxial layer, the channel region 109 having two sides which are a first side and a second side respectively;
[0061] A source region 111 of a second doping type, formed in the epitaxial layer; the source region 111 is closely connected to the upper part of the first side of the channel region 109, such that the channel region 109 is connected to the source region 111 only through a part of the first side of the channel region 109;
[0062] A gate 110 of a first doping type, formed on the channel region 109;
[0063] A drift region 104 of a second doping type, formed in the epitaxial layer, the drift region 107 is closely connected to the second side of the channel region 109.
[0064] For the lateral SIC-JFET device of the present application, the source region 111 is closely connected to the upper part of the first side of the channel region 109. In this way, it is realized that the channel region 109 is connected to the source region 111 only through a part of the first side of the channel region 109. That is, the thickness of the connection region between the channel region 109 and the source region 111 is less than the overall thickness of the channel region 109 itself. Wherein, the thickness of the connection region between the channel region 109 and the source region 111 is the dimension of the connection region in the thickness direction of the lateral SIC-JFET device.
[0065] Hereinafter, taking the first doping type as P-type and the second doping type as N-type as an example, the lateral SIC-JFET device of the present application will be described:
[0066] The N-type source region 111, the P-type channel region 109, and the N-type drift region 104 are connected to form an NPN junction, and the connection region between the channel region 109 and the source region 111 only occupies the upper part of the first side of the P-type channel region 109.
[0067] When the lateral SIC-JFET device of the present application is turned on, the depletion region of the PN junction formed by the source region 111 and the channel region 109 becomes narrower, and the depletion region of the PN junction formed by the channel region 109 and the drift region 104 becomes narrower. Carriers are conducted through the N-type source region 111, the P-type channel region 109, and the N-type drift region 104.
[0068] The connection area between the source region 111 and the channel region 109 only occupies the upper part of the first side surface of the channel region 109. That is, the thickness of the connection area between the channel region 109 and the source region 111 is much smaller than the thickness of the channel region 109. In the N-type source region 111, P-type channel region 109, and N-type drift region 104, as long as the connection area between the source region 111 and the channel region 109 is depleted, the device can be turned off.
[0069] When the lateral SIC-JFET device of the present application is turned off, the potential (i.e., the control voltage) applied to the gate 110 only needs to widen the depletion region of the PN junction formed by the source region 111 and the channel region 109 so that the PN junction is non-conductive. That is, the connection area between the region 111 and the channel region 109 is depleted. Since the thickness of the connection area between the channel region 109 and the source region 111 is small, in this way, only a small potential needs to be applied to the gate 110 to deplete the connection area between the source region 111 and the channel region 109.
[0070] In the background art Figure 1 For the lateral SIC-JFET device, the entire left side surface of the source region 111 is connected to the channel region 109, and the entire right side surface of the channel region 109 is connected to the drift region 104. When the lateral SIC-JFET device is turned on, the source region 111, the channel region 109, and the drift region 104 are conductive. To turn off the device, the potential applied to the gate 110 needs to widen the depletion region of the entire thickness of the channel region 109 (i.e., deplete the entire thickness of the channel region 109) to achieve turning off.
[0071] The control voltage of the lateral SIC-JFET device of the present application depends on the thickness of the connection area between the channel region 109 and the source region 111. Therefore, for the lateral SIC-JFET device of the present application, the thickness of the connection area between the channel region 109 and the source region 111 is much smaller than the entire thickness of the channel region 109. Therefore, it can be achieved that the doping concentration of the channel region 109 is determined by the saturation current Idsat, and the control voltage is determined by the thickness of the connection area between the channel region 109 and the source region 111. The lateral SIC-JFET device of the present application can achieve a larger saturation current Idsat while achieving a smaller control voltage, and at the same time, the structure is also easy to implement.
[0072] It should be noted that the actually effective area of the gate 110 of the lateral SIC-JFET device of the present application is no longer the entire channel region 109, but only the connection position of the connection area between the channel region 109 and the source region 111. The size of the connection area between the channel region 109 and the source region 111 can be very small, so as to achieve a very small control voltage, greatly alleviating the contradictory relationship between the control voltage of the device and the saturation current Idsat, and improving the overall performance of the device.
[0073] In implementation, such as Figure 2As shown, the lower surface of the channel region 109 is lower than the lower surface of the source region 111, and the upper surface of the channel region 109 is higher than the lower surface of the source region 111.
[0074] In this way, it is ensured that the thickness of the connection region between the channel region 109 and the source region 111 is less than the overall thickness of the channel region 109 itself. That is, only a part of the channel region 109 is connected to the source region 111 in the thickness direction.
[0075] In implementation, further, as Figure 2 shown, the upper surface of the channel region 109 is lower than the upper surface of the source region 111.
[0076] In this way, on the basis that only a part of the channel region 109 is connected to the source region 111 in the thickness direction, it is also required that only a part of the source region 111 is connected to the channel region 109 in the thickness direction. It is realized that the thickness of the connection region between the channel region 109 and the source region 111 can be completely set according to needs, and can be independent of the thickness of the channel region 109 and the thickness of the source region 111.
[0077] In implementation, as Figure 2 shown, the value range of the ratio of the thickness of the connection region between the channel region 109 and the source region 111 to the thickness of the channel region 109 is greater than 0 and less than 1.
[0078] In implementation, as Figure 2 shown, the lateral SIC-JFET device of the present application further includes:
[0079] A first body region 107 formed under the channel region 109;
[0080] Wherein, the sides of the gate 110, the channel region 109, and the first body region 107 are flush.
[0081] The sides of the three-layer structure of the first body region 107, the channel region 109, and the gate 110 arranged from bottom to top are flush. In this way, the structure is simple and convenient for preparation. Specifically, the same mask can be used, and the gate injection pattern window is etched on this mask through the etching process. The first body region 107, the channel region 109, and the gate 110 are all formed by the injection process through this gate injection pattern window. That is, the preparation of the first body region 107, the channel region 109, and the gate 110 can be realized through a completely self-aligned process, without being affected by the lithography limit of any type of lithography equipment, greatly improving the manufacturability and mass production feasibility of the device.
[0082] In the background art Figure 1In the lateral SIC-JFET device, there needs to be a gap between the gate 110 and the source region 111, and there needs to be a gap between the gate 110 and the drift region 104. The gap position is part of the epitaxial layer. The reason is the background art Figure 1 In the lateral SIC-JFET device of the background art, in order to turn off the device, the potential applied to the gate 110 needs to widen the depletion region of the entire thickness of the channel region 109 (i.e., deplete the entire thickness of the channel region 109) to achieve turning off. In this way, the voltage that needs to be applied to the gate 110 is 15 volts to deplete the entire thickness of the channel region 109. Therefore, it is necessary to ensure that the breakdown voltage of the gate 110 is greater than 15 volts. A PN junction is formed between the part of the epitaxial layer at the gap position and the gate 110 to increase the breakdown voltage of the gate 110, such as the breakdown voltage of the gate 110 is 20V.
[0083] In the lateral SIC-JFET device of the present application, since the thickness of the connection region between the channel region 109 and the source region 111 is much smaller than the entire thickness of the channel region 109, the control voltage (i.e., the voltage applied to the gate 110) for turning off the connection region between the channel region 109 and the source region 111 can be made smaller, such as 5V. And in the lateral SIC-JFET device of the present application, due to the relatively high voltage withstand capacity of the SIC material itself, regardless of the doping concentration of the source region 111 and the drift region 104 on both sides of the gate 110, the breakdown voltage of the gate 110 can be maintained at 10 volts. At this time, the breakdown voltage of the gate 110 is already higher than the control voltage (i.e., the voltage applied to the gate 110) for turning off the connection region between the channel region 109 and the source region 111. Therefore, there is no need to further increase the breakdown voltage of the gate 110; furthermore, there is no need for a gap between the gate 110 and the source region 111, and between the gate 110 and the drift region 104.
[0084] Therefore, the sides of the gate 110, the channel region 109, and the first body region 107 of the lateral SIC-JFET device of the present application can be flush structurally. The reason corresponding to the simple manufacturing process is still due to the fact that the thickness of the connection region between the channel region 109 and the source region 111 is much smaller than the entire thickness of the channel region 109, making the control voltage (i.e., the voltage applied to the gate 110) for turning off the connection region between the channel region 109 and the source region 111 can be made smaller.
[0085] In implementation, as Figure 2 shown, the lateral SIC-JFET device of the present application further includes:
[0086] A second body region 112, formed under the source region 111, and the side of the second body region 112 is connected to the side of the first body region 107; wherein, the sides of the source region 111 and the second body region 112 are flush;
[0087] The drift region 104 of the second doping type is formed downward from the upper surface of the epitaxial layer; wherein, the drift region 104 is adjacent to the flush second side surfaces of the gate 110, the channel region 109, and the first body region 107.
[0088] The side surfaces of the two-layer structures of the second body region 112 and the source region 111 arranged from bottom to top are flush. In this way, the structure is simple and easy to fabricate. Specifically, the second body region 112 and the source region 111 can be formed by implantation through the same window.
[0089] Since there is no longer a need for a gap between the gate 110 and the drift region 104, therefore, the adjacent drift region 104 can be formed at the position where the gate 110, the channel region 109, and the first body region 107 are flush. That is, the connection and alignment between the channel region 109 and the drift region 104 are independent of the lithography process, and the connection and alignment between the second body region 112, the source region 111, and the channel region 109 are also independent of the lithography process, and are not affected by the lithography limit of any type of lithography equipment, greatly improving the manufacturability and mass production feasibility of the device.
[0090] Specifically, as Figure 2 shown, the lateral SIC-JFET device of the present application further includes:
[0091] An oxide layer 206 is formed on the epitaxial layer;
[0092] A body region contact region 108 is formed downward from the epitaxial layer and is arranged adjacent to the source region 111 and the second body region 112;
[0093] A source contact metal compound 201-1 located in the oxide layer 206 and above the body region contact region 108 and the source region 111;
[0094] A source contact via 203-1 located in the oxide layer and above the source contact metal compound 201-1;
[0095] A source metal layer 204-1 located in the oxide layer and above the source contact via 203-1;
[0096] A ground back hole 205 is connected to the source metal layer 204-1 and penetrates from top to bottom to the bottom of the substrate 101;
[0097] Wherein, the bottom of the substrate is grounded and connected to a heat dissipation structure.
[0098] The source terminal includes a source region 111, a second body region 112, a first body region 107, and a body region contact region 108. In this way, grounding of the source terminal is achieved through the source contact metal compound 201-1, the source contact via 203-1, the source metal layer 204-1, and the ground back hole 205, and connection of the source terminal to the heat dissipation structure is also realized. Heat generated at the source terminal can be quickly dissipated, enabling the lateral SiC-JFET device in the embodiment of the present application to be applicable to radio frequency applications.
[0099] Specifically, as Figure 2 shown, the lateral SIC-JFET device of the present application further includes:
[0100] A drain 106, located within the drift region 104 and spaced apart from the gate 110;
[0101] A drain region 105 located below the drain 106.
[0102] A drain contact metal compound 201-3 located within the oxide layer and above the drain 106;
[0103] A drain contact via 203-3 located within the oxide layer and above the drain contact metal compound 201-3;
[0104] A drain metal layer 204-3 located within the oxide layer and above the drain contact via 203-3.
[0105] The drain terminal includes the drain region 105 and the drain 106. Connection of the drain terminal is achieved through the drain contact metal compound 201-3, the drain contact via 203-3, and the drain metal layer 204-3.
[0106] Specifically, as Figure 2 shown, the lateral SIC-JFET device of the present application further includes:
[0107] A gate contact metal compound 201-2 located within the oxide layer and above the gate 110;
[0108] A gate contact via (not shown in the figure) located within the oxide layer and above the gate contact metal compound 201-2.
[0109] The gate terminal includes the gate 110 and the gate contact metal compound 201-1. Connection of the gate terminal is achieved through the gate contact metal compound 201-2 and the gate contact via.
[0110] Specifically, as Figure 2 shown, the epitaxial layer includes:
[0111] A first epitaxial layer 102, formed on the substrate;
[0112] A second epitaxial layer 103 is formed on the first epitaxial layer 102;
[0113] Among them, the doping concentration of the first epitaxial layer 102 is greater than that of the second epitaxial layer 103.
[0114] A drain region 105, a drain electrode 106, a first body region 107, a body region contact region 108, a channel region 109, a gate electrode 110, a source region 111, and a second body region 112 are formed in the second epitaxial layer 103.
[0115] Embodiment 2
[0116] A preparation method of a lateral SIC-JFET device according to an embodiment of the present application is used to prepare the lateral SIC-JFET device of Embodiment 1. A preparation method of a lateral SIC-JFET device according to an embodiment of the present application includes the following steps:
[0117] Step 1: Form a first-doped epitaxial layer on a second-doped substrate 101;
[0118] Step 2: Form a first-doped channel region 109 in the epitaxial layer. The channel region 109 has two sides, namely a first side and a second side;
[0119] Step 3: Form a first-doped gate electrode 110 on the channel region 109;
[0120] Step 4: Form a second-doped drift region 104 in the epitaxial layer. The drift region 107 is connected to the second side of the channel region 109;
[0121] Step 5: Form a second-doped source region 111 in the epitaxial layer; the source region 111 is connected to the upper part of the first side of the channel region 109, so that the channel region 109 is only connected to the source region 111 through a part of the first side of the channel region 109.
[0122] In implementation, steps 2 and 3 specifically include the following steps:
[0123] Form a hard mask foundation on the epitaxial layer;
[0124] Through an etching process, etch a gate injection pattern window in the hard mask foundation to form a mask plate 301 with a gate injection pattern window;
[0125] At the position of the gate injection pattern window 110-1, sequentially form a gate electrode 110, a channel region 109, and a first body region 107 from the upper surface of the epitaxial layer downward by an injection method.
[0126] In implementation, step 4 specifically includes the following steps:
[0127] Form a dummy gate 302 in the gate injection pattern window 110-1, then remove the mask 301, and then form a photoresist 303;
[0128] Through selective etching, the dummy gate 302 is retained, and the injection position of the drift region in the photoresist is opened through a lithography process, exposing the position in the epitaxial layer where the drift region needs to be formed;
[0129] Form a drift region 104 by injection. The boundary of the drift region close to the channel region 109 is defined by the dummy gate 302.
[0130] In implementation, step five specifically includes:
[0131] Form a photoresist 303 again on the drift region 104;
[0132] Open the injection position of the source region 111 through a lithography process, and inject the source region 111 and the second body region 112 downward in sequence from the upper surface of the epitaxial layer at the injection position of the source region. The boundaries of the source region 111 and the second body region 112 close to the channel region 109 are defined by the dummy gate 302.
[0133] In the preparation method of a lateral SIC-JFET device of the present application, the reason for the way of separately arranging the first body region 107 and the second body region 112 is as follows:
[0134] Form a gate 110, a channel region 109, and a first body region 107 at the position of the gate injection pattern window 110-1. The gate injection pattern window 110-1 directly defines the boundaries of the gate 110, the channel region 109, and the first body region 107, and there is no need to separately control the boundary of the first body region 107.
[0135] Form a source region 111 and a second body region 112 at the injection position of the source region. The injection position of the source region directly defines the boundaries of the source region 111 and the second body region 112, and there is no need to separately control the boundary of the second body region 112.
[0136] Background Art Figure 1 The body region 107-0 in it is relatively long and is located below the body region contact region 108, the source region 111, and the channel region 109. During preparation, it is necessary to separately control the boundary of the body region 107-0, which leads to a complex preparation process.
[0137] The body region (including the first body region 107 and the second body region 112 in the present application) in a semiconductor device is not only a physical support structure but also a core control part of electrical performance. Its design directly affects the threshold voltage, isolation characteristics, power consumption, reliability, and anti-interference ability of the device.
[0138] Taking the first doping type as P-type and the second doping type as N-type as an example, the preparation method of a lateral SIC-JFET device according to an embodiment of the present application will be described in chronological order:
[0139] As Figure 3 shown, Step 1: First, grow a heavily doped P-type first epitaxial layer 102 on a heavily doped N-type substrate 101; then grow a lightly doped P-type second epitaxial layer 103 on this basis; then deposit a hard mask base through a deposition process, and then etch a gate injection pattern window 110-1 through an etching process to form a mask plate 301 with a gate injection pattern window; then inject a first body region 107, a channel region 109, and a gate 110 in sequence through an injection process.
[0140] As Figure 4 shown, Step 2: Form a dummy gate 302 at the window opening position of the gate injection pattern window through a deposition and etch-back process.
[0141] As Figure 5 shown, Step 3: Remove the mask plate 301; and form a photoresist 303.
[0142] As Figure 6 shown, Step 4: On the basis of the above structure, through selective etching, retain the dummy gate 302, open the injection position of the drift region 104 through a photolithography process, and expose the position in the epitaxial layer where the drift region needs to be formed; form the drift region 104 by an injection method. At this time, the injection boundary of the drift region is defined by the right boundary of the dummy gate, and the right boundaries of the drift region 104 and the channel region 109 are completely aligned, and there is no mutual overlap of the injection regions caused by photolithography alignment.
[0143] As Figure 7 shown, Step 5: On the basis of the above structure, form a photoresist 303 again on the drift region 104; then, open the injection position of the source region 111 through a photolithography process, and inject a second body region 112 and a source region 111. At this time, the injection boundary of the source region 111 is defined by the left boundary of the dummy gate, and the right boundary of the source region 111 is completely aligned with the left boundary of the 109 channel, and there is no mutual overlap of the injection regions caused by photolithography alignment.
[0144] As Figure 8 shown, Step 6: On the above basis, first remove the dummy gate 302; then form a body region contact region 108, a drain region 105, and a drain electrode 106 through photolithography injection.
[0145] As Figure 9 shown, Step 7: On the above basis, form a source contact metal compound 201-1, a gate contact metal compound 201-2, and a drain contact metal compound 201-3.
[0146] As Figure 10As shown in the figure, step 8: On the basis above, form an oxide layer 206, a gate shielding plate 202, a source contact through-hole 203-1, a gate contact through-hole 203-2, a drain contact through-hole 203-3, a source metal layer 204-1, a drain metal layer 204-3, and a ground back-hole 205.
[0147] Figure 11 This is a simulation diagram of the lateral SIC-JFET device of the present application. Figure 11 It shows that under the condition of conventional process means, the device has manufacturability and the device solution is feasible.
[0148] Figure 12 This is the Id-Vg curve diagram of the lateral SIC-JFET device of the present application. As Figure 12 shown, as the gate voltage Vg increases, the drain current Id of the device starts to increase significantly near -3V and the device turns on. This shows that the device can achieve a good turn-on and turn-off function.
[0149] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.
[0150] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the processes and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.
[0151] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device implements the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.
[0152] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable apparatus to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in one process or a plurality of processes and / or blocks Figure 1 one process or a plurality of processes and / or blocks Figure 1 or steps of the functions specified in a plurality of blocks.
[0153] Although the preferred embodiments of the present application have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once they learn of the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present application.
[0154] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.
Claims
1. A lateral SIC-JFET device, characterized in that: include: A substrate (101) of a second doping type; An epitaxial layer of a first doping type is formed on the substrate (101); A channel region (109) of a first doping type is formed in the epitaxial layer, and the channel region (109) has two side surfaces, namely a first side surface and a second side surface; A source region (111) of a second doping type is formed in the epitaxial layer; the source region (111) is connected to an upper portion of a first side surface of the channel region (109), so that the channel region (109) is connected to the source region (111) only through a portion of the first side surface of the channel region (109); A gate (110) of a first doping type formed on the channel region (109); A drift region (104) of a second doping type is formed in the epitaxial layer, and the drift region (107) is connected to a second side surface of the channel region (109).
2. The lateral SIC-JFET device according to claim 1, characterized in that: The lower surface of the channel region (109) is lower than the lower surface of the source region (111), and the upper surface of the channel region (109) is higher than the lower surface of the source region (111).
3. The lateral SIC-JFET device according to claim 1, characterized in that: The upper surface of the channel region (109) is lower than the upper surface of the source region (111).
4. The lateral SIC-JFET device according to claim 1, characterized in that: The ratio of the thickness of the connection region between the channel region (109) and the source region (111) to the thickness of the channel region (109) is in the range of greater than 0 and less than 1; The thickness of the connection region between the channel region (109) and the source region (111) is the dimension of the connection region in the thickness direction of the lateral SIC-JFET device.
5. The lateral SIC-JFET device according to any one of claims 1 to 4, characterized in that: Also includes: A first body region (107) formed below the channel region (109); Wherein, the side surfaces of the gate (110), the channel region (109), and the first body region (107) are flush.
6. The lateral SIC-JFET device according to claim 5, characterized in that: Also includes: A second body region (112) is formed below the source region (111), and a side surface of the second body region (112) is connected to a side surface of the first body region (107); wherein the side surfaces of the source region (111) and the second body region (112) are flush; A drift region (104) of the second doping type is formed downward from the upper surface of the epitaxial layer; wherein the drift region (104) is adjacent to the gate (110), the channel region (109), and the flush second side surface of the first body region (107).
7. A method for preparing a lateral SIC-JFET device, characterized in that: The steps include: forming an epitaxial layer of a first doping type on a substrate (101) of a second doping type; Forming a first doping type channel region (109) in the epitaxial layer, wherein the channel region (109) has two side surfaces, namely a first side surface and a second side surface; forming a gate (110) of a first doping type on the channel region (109); forming a drift region (104) of a second doping type in the epitaxial layer, wherein the drift region (107) is connected to a second side surface of the channel region (109); A source region (111) of a second doping type is formed in the epitaxial layer; the source region (111) is connected to an upper portion of a first side surface of the channel region (109), so that the channel region (109) is connected to the source region (111) only through a portion of the first side surface of the channel region (109).
8. The method for preparing a lateral SIC-JFET device according to claim 7, characterized in that: The steps of forming a channel region (109) of a first doping type in the epitaxial layer and forming a gate (110) of the first doping type on the channel region (109) specifically include: forming a hard mask base over the epitaxial layer; Etching a gate injection pattern window on the hard mask base through an etching process to form a mask plate (301) with a gate injection pattern window; A gate (110), a channel region (109), and a first body region (107) are sequentially formed from the upper surface of the epitaxial layer downwards by an injection method at the position of the gate injection pattern window (110-1).
9. The method for preparing a lateral SIC-JFET device according to claim 8, characterized in that: The step of forming a drift region (104) of a second doping type in the epitaxial layer specifically comprises: forming a dummy gate (302) in the gate injection pattern window (110-1), then removing the mask (301), and then forming a photoresist (303); Retaining the dummy gate (302) by selective etching, opening the implantation position of the drift region in the photoresist by photolithography, and exposing the position where the drift region needs to be formed in the epitaxial layer; A drift region (104) is formed by implantation, and a boundary of the drift region close to the channel region (109) is defined by the dummy gate (302).
10. The method for preparing a lateral SIC-JFET device according to claim 9, characterized in that: The step of forming a source region (111) of a second doping type in the epitaxial layer specifically comprises: forming a photoresist (303) again on the drift region (104); The injection position of the source region (111) is opened by a photolithography process, and the source region (111) and the second body region (112) are injected in sequence from the upper surface of the epitaxial layer downward at the injection position of the source region, and the boundary of the source region (111) and the second body region (112) close to the channel region (109) is defined by the dummy gate (302).