Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure (100), the method comprising: forming a layer stack (110); forming a gate structure (250) on the layer stack; forming at least one cavity (135) by removing at least one second sacrificial layer (132b) of the layer stack (110); depositing a first dielectric material (201), thereby filling the at least one cavity (135) with the first dielectric material (201); providing a dielectric-free gate surface devoid of the first dielectric material (201); and depositing a second dielectric material (202) on the dielectric-free gate surface, wherein the second dielectric material (202) is different from the first dielectric material (201).

Description

Technical Field

[0001] The present inventive concept generally relates to semiconductor structures. In particular, it relates to a method for forming semiconductor structures for use in field effect transistors or stacks of field effect transistors. Background Art

[0002] Modern semiconductor integrated circuit technology includes field effect transistors, such as nanowire FETs (NWFETs) and nanosheet FETs (NSHFETs). In addition, FETs can be stacked on top of each other to form a stack of FETs. A notable example is a FET stack including a complementary pair of FETs (i.e., a p-type FET (PFET) on top of an n-type FET (NFET), or vice versa) stacked on top of each other. Such a stack of complementary FETs can be referred to as a CFET.

[0003] Dielectric materials are used to electrically insulate a portion of a FET from another portion of the FET, or to electrically insulate one FET from another FET. Summary of the Invention

[0004] An object of the present inventive concept is to facilitate high-quality semiconductor structures and / or FETs.

[0005] Another object of the present inventive concept is to facilitate densely packaged semiconductor structures and / or FETs.

[0006] Another object of the present inventive concept is to facilitate FETs that operate quickly and / or at high frequencies.

[0007] Another object of the present inventive concept is to facilitate FETs having low parasitic capacitance.

[0008] These and other objects of the present inventive concept are at least partially met by the present invention as defined in the independent claims. Preferred embodiments are listed in the dependent claims.

[0009] According to a first aspect, there is provided a method for forming a semiconductor structure, the method comprising:

[0010] forming a layer stack on a substrate, the layer stack comprising:

[0011] a first sub-stack comprising a first sacrificial layer and a channel layer defining the topmost layer of the first sub-stack on the first sacrificial layer;

[0012] a second sub-stack on the first sub-stack and comprising a plurality of sacrificial layers alternating between a first sacrificial layer and a second sacrificial layer, wherein the first sacrificial layer defines the bottommost and topmost layers of the second sub-stack, and the second sub-stack comprises at least one second sacrificial layer;

[0013] A third sub-stack, the third sub-stack being located on the second sub-stack and including a channel layer defining a bottommost layer of the third sub-stack and a first sacrificial layer on the channel layer;

[0014] wherein the first sacrificial layer is formed of a first sacrificial semiconductor material and the second sacrificial layer is formed of a second sacrificial semiconductor material different from the first sacrificial semiconductor material,

[0015] Forming a gate structure on the layer stack;

[0016] Forming at least one cavity by removing the at least one second sacrificial layer of the second sub-stack; depositing a first dielectric material, wherein the act of depositing the first dielectric material includes filling the at least one cavity with the first dielectric material;

[0017] Providing a dielectric-free gate surface, the dielectric-free gate surface being an end face of the gate structure without the first dielectric material; and

[0018] Depositing a second dielectric material on the dielectric-free gate surface, wherein the second dielectric material is different from the first dielectric material;

[0019] wherein the act of depositing the second dielectric material is performed after the act of depositing the first dielectric material.

[0020] The term "layer stack" herein refers to a structure of layers formed sequentially on top of each other. The device layer stack can in particular be fin-shaped.

[0021] The first sub-stack designates a first subset of the coherent layers of the layer stack, the second sub-stack designates a second subset of the coherent layers of the layer stack, and the third sub-stack designates a third subset of the coherent layers of the layer stack.

[0022] Unless otherwise specified, the phrase "the first layer on the second layer" with respect to any layer (or sub-stack) of the layer stack herein means that the first layer is directly disposed on the second layer (i.e., adjacent to the second layer).

[0023] Relative spatial terms such as "topmost", "bottom", "lower", "vertical", "stacked on top of" are understood herein to represent a position or orientation within the reference frame of the semiconductor device. Specifically, these terms can be understood with respect to the normal direction of the substrate on which the device layer stack is formed, or equivalently with respect to the bottom-up direction of the device layer stack. Accordingly, terms such as "lateral" and "horizontal" should be understood as positions or orientations parallel to the substrate.

[0024] The term "thickness" shall be understood as the dimension of a structure (e.g., a layer of a sub-stack) as seen along the normal to the surface underlying the structure (e.g., a layer of a sub-stack). For example, the thickness of a layer of a device layer stack or the thickness of a second sub-stack may refer to the thickness dimension of the layer / sub-stack as seen along the bottom-to-top direction of the device layer.

[0025] The semiconductor structure can be a semiconductor structure for generating a stack of FETs including top and bottom field-effect transistors (FETs). The stack of FETs can be a CFET, where the top FET is an NFET and the bottom FET is a PFET, or vice versa. Thus, the semiconductor structure can be a semiconductor structure suitable for conversion into a stack of FETs (e.g., a CFET).

[0026] The layer stack can be a layer stack for producing a stack of FETs.

[0027] The channel layer of the first sub-stack can be the channel layer for the bottom FET. Similarly, the channel layer of the third sub-stack can be the channel layer for the top FET. Thus, the channel layer can be the channel layer of an FET. The channel layer can be a Si layer.

[0028] The first sacrificial layer can be a layer that can be replaced by a gate stack during the production of a stack of FETs.

[0029] The second sacrificial layer is a layer that is replaced by a first dielectric material during the production of a stack of FETs. Then, the first dielectric material can act as electrical isolation between the bottom and top FETs. This electrical isolation between the bottom and top FETs can be referred to as intermediate dielectric isolation.

[0030] The material of the channel layer can be Si 1-a Ge a , the first sacrificial semiconductor material can be Si 1-c Ge c , and the second sacrificial semiconductor material can be Si 1-d Ge d , where 0 ≤ a < c < d. By way of example:

[0031] a can be less than 0.05, typically a = 0;

[0032] c can be in the range of 0.1 - 0.25;

[0033] d can be in the range of 0.35 - 0.5.

[0034] Typical material selections are:

[0035] The material of the channel layer is Si;

[0036] The first sacrificial semiconductor material is Si 0.8 Ge0.2 ;

[0037] The second sacrificial semiconductor material is Si 0.6 Ge 0.4 .

[0038] The channel layer may be a silicon layer (as described above). The first and third sub-stacks may each include a single channel layer or multiple channel layers, such as at least two channel layers.

[0039] Adjacent channel layers of the first sub-stack may be separated by a first sacrificial layer. Thus, the first sub-stack may include multiple repetitions of a first sub-stack unit that includes a first sacrificial layer and a channel layer on the first sacrificial layer. For example, two repetitions from bottom to top may be: first sacrificial layer / channel layer / first sacrificial layer / channel layer.

[0040] Adjacent channel layers of the third sub-stack may be separated by a first sacrificial layer. Thus, the third sub-stack may include multiple repetitions of a third sub-stack unit that includes a channel layer and a first sacrificial layer on the channel layer. For example, two repetitions from bottom to top may be: channel layer / first sacrificial layer / channel layer / first sacrificial layer.

[0041] The semiconductor structure may be considered to extend between two ends. When the FET stack is completed, the source region may be disposed at one end in a direction perpendicular to the gate structure, and the drain region may be disposed at the other end.

[0042] As described above, the second sub-stack includes multiple sacrificial layers alternating between first and second sacrificial layers, where the first sacrificial layer defines the respective bottommost and topmost layers of the second sub-stack.

[0043] For example, the second sub-stack may include a first sacrificial layer as the bottommost layer and a first sacrificial layer as the topmost layer, with a single second sacrificial layer therebetween. This would correspond to the case where the second sub-stack includes only one second sacrificial layer.

[0044] However, the second sub-stack may include multiple second sacrificial layers, such as at least two second sacrificial layers or at least three second sacrificial layers, each second sacrificial layer being separated by a corresponding first sacrificial layer.

[0045] Thus, the method may be configured such that the second sub-stack includes at least two second sacrificial layers, such that at least two cavities are formed and filled with a first dielectric material.

[0046] For example, a second sub-stack including exactly two second sacrificial layers may correspond to the following layer sequence from bottom to top: first sacrificial layer / second sacrificial layer / first sacrificial layer / second sacrificial layer / first sacrificial layer. A second sub-stack including at least two second sacrificial layers is advantageous because it provides good electrical isolation between the top and bottom FETs. It may be advantageous to use a second sub-stack including a plurality of thin second sacrificial layers instead of a second sub-stack including one thick second sacrificial layer. If a thick second sacrificial layer is used, the lattice mismatch between the first and second sacrificial layers may cause dislocations.

[0047] A plurality of sacrificial layers alternating between a first sacrificial layer and a second sacrificial layer may also be represented as a plurality of sacrificial layers switching between the first and second sacrificial layers.

[0048] The gate structure may be a sacrificial gate body. During the production process of the FET stack, this sacrificial gate body may be replaced by a gate stack at a later time. The sacrificial gate body may include amorphous silicon. In addition, the first sacrificial layer may also be replaced by a gate stack.

[0049] Alternatively, the gate structure may be part of the final gate of the FET stack.

[0050] As previously mentioned, the semiconductor structure may be considered to extend between two ends. The layer stack of the semiconductor structure may be fin-shaped. Therefore, these two ends may be the ends of the fin-shaped layer stack. The direction between the two ends of the semiconductor structure may be perpendicular to the gate structure. The direction between the two ends of the semiconductor structure may be parallel to the fin-shaped layer stack. Therefore, the gate structure may also have two ends. One end face of the gate structure may be a surface (e.g., a vertical surface) facing the surface that will become the source region at the end of the production of the FET stack. The other end face of the gate structure may be a surface (e.g., a vertical surface) facing the surface that will become the drain region at the end of the production of the FET stack. Therefore, the end faces of the gate structure may be surfaces in a vertical plane.

[0051] Removing at least one second sacrificial layer of the second sub-stack may be performed by selective etching, e.g., selectively etching with respect to the other layers of the layer stack. Thus, when at least one second sacrificial layer of the second sub-stack is removed, the other layers of the layer stack may be retained.

[0052] The first dielectric material may be deposited by various deposition methods to fill at least one cavity with the first dielectric material. For example, depositing the first dielectric material may be performed by atomic layer deposition (ALD), such as plasma-enhanced ALD (PEALD). Alternatively, the first dielectric material may be deposited by chemical vapor deposition (CVD). For example, a first CVD method may be used. The first CVD method will be further discussed below.

[0053] A dielectric-free gate surface can be provided in various ways. The dielectric-free gate surface is the end face of the gate structure that does not have the first dielectric material.

[0054] A first way to provide a dielectric-free gate surface can be to remove the first dielectric material from the gate surface. As will be further described below, when the first dielectric material is deposited, there may also be the first dielectric material deposited on the gate structure. In this case, a dielectric-free gate surface can be provided by removing the first dielectric material from the end face of the gate structure.

[0055] A second way to provide a dielectric-free gate surface can be to deposit the first dielectric material by a method that does not deposit on the gate surface. As will be further described below, the first dielectric material can be preferentially deposited in at least one cavity such that no first dielectric material is deposited on the end face of the gate structure. For example, a first CVD method can be used to preferentially deposit the first dielectric material in at least one cavity.

[0056] As described above, a second dielectric material is deposited on the dielectric-free gate surface. In addition, the second dielectric material is different from the first dielectric material. The second dielectric material deposited on the dielectric-free gate surface can act as a gate spacer in the finished device.

[0057] The deposition of the second dielectric material can be performed by atomic layer deposition.

[0058] It is recognized that it is advantageous to use different dielectric materials within the layer stack and on the end face of the gate structure. Thus, in the finished stack of the FET, the intermediate dielectric isolation can include one dielectric material (the first dielectric material), while the gate spacer includes another dielectric material (the second dielectric material). Regarding the dielectric materials, there may be various factors to consider. One factor can be the capacitance between the components separated by the dielectric material. The capacitance can be related to the dielectric constant of the dielectric material. Another factor can be the surface state between the dielectric material and its arranged surface. Yet another factor can be the amount of voids in the dielectric constant. It is recognized that the factors constraining the intermediate dielectric isolation dielectric material can be different from the factors constraining the gate spacer dielectric material. By using the method of the present invention, the intermediate dielectric isolation dielectric material and the gate spacer dielectric material can be customized separately.

[0059] For example, it is recognized that it may be advantageous to use a gate spacer with a low dielectric constant. Thus, the second dielectric material can have a low dielectric constant. This can also be expressed as the second dielectric material being a low-k material. This can reduce the parasitic capacitance. Thus, it facilitates the FET to operate quickly and / or at high frequencies. In addition, if the parasitic capacitance is reduced, the FET can be more densely packaged.

[0060] For example, the second dielectric material may have a dielectric constant lower than 6.5. This can provide low parasitic capacitance. It should be understood that the second dielectric material may have an even lower dielectric constant. Thus, the second dielectric material may have a dielectric constant lower than 6, or lower than 5.5, or lower than 5, or lower than 4.5.

[0061] The second dielectric material may include SiOCN and / or SiOC. Such materials may have a low dielectric constant and benefit from the above advantages. In addition, these materials can be hard and durable. The above materials can be deposited, for example, by ALD.

[0062] The first dielectric material may be or include, for example, SiN. SiN is a material that is very compatible with the production of FET stacks and has many suitable deposition and etching methods. Alternatively, the first dielectric material may be or include SiOC, SiOCN, or SiCN. The above materials can be deposited, for example, by ALD. Alternatively, the above materials can be deposited by a first CVD method.

[0063] In the following, a first way to provide a dielectric-free gate surface will be discussed.

[0064] The method can be configured such that during the action of filling at least one cavity with the first dielectric material, the first dielectric material is also deposited on the end face of the gate structure;

[0065] The action of forming a dielectric-free gate surface includes removing the first dielectric material from the end face of the gate structure.

[0066] For example, the first dielectric material can be removed from the end face of the gate structure by dry isotropic etching. Dry isotropic etching allows the first dielectric material to be etched at a uniform (at least substantially uniform) rate. In addition, such etching can also be used in other steps during the manufacture of FET stacks, such as during the formation of internal spacers. Thus, dry isotropic etching can be easily obtained.

[0067] After removing the first dielectric material from the end face of the gate structure, a second dielectric material can be deposited.

[0068] In the following, a second way to provide a dielectric-free gate surface will be discussed. Here, the first dielectric material is deposited in at least one cavity without being deposited on the gate surface. A suitable method for doing this is the first CVD method.

[0069] Thus, the method for forming a semiconductor structure can be configured such that the action of depositing the first dielectric material is performed by a first chemical vapor deposition method (CVD method), and the first CVD method includes:

[0070] In a state where at least a non-oxidizing hydrogen-containing gas is being plasma-ized, an oxygen-containing silicon compound gas is reacted with the non-oxidizing hydrogen-containing gas as a film-forming gas to form a film of a flowable silanol compound; and

[0071] Subsequently, the film of the flowable silanol compound is annealed into a first dielectric material,

[0072] wherein the oxygen-containing silicon compound gas includes Si α O β (O-C m H n ) Γ C x H y , where m, n, and α are integers of 1 or greater; and where β, Γ, x, and y are integers of 0 or greater; and β and Γ are not both 0.

[0073] The first CVD method is described in Patent Publication US20220235456A1, which is incorporated herein by reference. Specifically, the detailed description of US20220235456A1 is incorporated herein by reference.

[0074] The first CVD method may be referred to as ultra chemical vapor deposition (UCVD) or chemical vapor liquid deposition. In the following description, the term UCVD will be mainly used.

[0075] The UCVD method can mainly deposit materials in cavities and / or trenches. Therefore, the dielectric material can be mainly deposited in the cavities formed by removing the second sacrificial layer. Therefore, after depositing the first dielectric material, the end face of the gate structure may be free of the first dielectric material.

[0076] The UCVD method has other advantages. The dielectric material deposited by the UCVD method can have a flat profile. In this context, it can be noted that a flat profile generally means that the end face of the dielectric material may have few or no rounded corners. The rounded corners of the end face corners are sometimes referred to as curvature. Providing such a flat-profile dielectric material can reduce processing steps because separate steps such as pre-cleaning may not be required. The reduction of the pre-cleaning step can enable the reduction of the erosion of the dielectric layer / sacrificial layer or any other layer of the layer stack that is usually subject to erosion. In addition, the UCVD method can provide a dielectric material compound with few voids, such as a void-free dielectric material, thereby providing a high-quality dielectric material.

[0077] The method may further include:

[0078] Removing the end of the layer stack and the second dielectric material on the end by vertical slitting;

[0079] Subsequently, the end face of the first sacrificial layer of the layer stack is laterally grooved to form a groove; and

[0080] An internal spacer is formed in the groove.

[0081] The term "internal spacer" herein means a dielectric layer portion formed in the groove to cover the end face of the first sacrificial layer. The vertical grooving can be source / drain grooving. The vertical grooving can be performed by anisotropic etching (e.g., dry anisotropic etching). The lateral grooving of the end face of the first sacrificial layer of the layer stack can be performed by an isotropic etching process. Forming the internal spacer can include depositing an internal spacer material to a certain thickness such that the groove is pinched off (i.e., closed). The internal spacer material can be conformally deposited, for example, by ALD.

[0082] The method for forming a semiconductor structure can include further steps towards the finished stack of the FET.

[0083] In the case where the gate structure is a sacrificial gate body, the method can further include:

[0084] Replacing the sacrificial gate body with a gate stack.

[0085] The method can include:

[0086] Forming source / drain regions at opposite ends of the channel layer of the first sub-stack; and

[0087] Forming source / drain regions at opposite ends of the channel layer of the third sub-stack;

[0088] Such that the semiconductor structure forms a stack of field effect transistors FETs, including:

[0089] A first FET, including the channel layer of the first sub-stack; and

[0090] A second FET, including the channel layer of the second sub-stack.

[0091] It is also recognized that a liner layer can be advantageously used. Thus, the method can be configured such that adjacent first and second sacrificial layers of the second sub-stack are separated by a liner layer, and the liner layer of the second sub-stack is formed of a semiconductor material different from the first and second sacrificial semiconductor materials.

[0092] The liner layer can be a layer resistant to the etchant used for etching the second sacrificial layer. The liner layer can be a layer resistant to the etchant used for grooving the first sacrificial layer. The liner layer can be thin, for example, thinner than the first and second sacrificial layers.

[0093] As described above, the first and second sacrificial layers are formed of different semiconductor materials. Accordingly, an etchant may have different etch rates for the first and second sacrificial layers. Thus, the first and second sacrificial layers may be selectively etched at different points during the manufacturing process, or if they are etched simultaneously, they will be etched by different amounts. The channel layer, the liner layer, the first sacrificial layer, and the second sacrificial layer may all be made of different materials. Alternatively, the channel layer and the liner layer are formed of the same material different from the first and second sacrificial semiconductor materials. Advantageously, the channel layer and the liner layer are formed of Si, while the first and second sacrificial layers are formed of SiGe, wherein the first and second sacrificial layers have different Ge contents.

[0094] Due to the liner layer, even if isotropic etching is performed on the end face of the first sacrificial layer, rounding of the corners of the first sacrificial layer can be avoided. In other words, using the liner layer enables isotropic selective etching while avoiding rounding of the corners of the first sacrificial layer. Since the first sacrificial layer may be replaced by a gate stack later, using the liner layer can facilitate a well-defined gate stack.

[0095] Due to the liner layer, a smaller compositional difference between the first and second sacrificial layers can be used compared to the case without the liner layer. For example, when using the liner layer, the difference in Ge content between the first and second sacrificial layers can be very small. Even when the etch selectivity is small with a small difference in Ge content, the liner layer helps protect the first sacrificial layer during removal of the second sacrificial layer. A small compositional difference between the first and second sacrificial layers can reduce strain-related problems such as strain-related dislocation formation.

[0096] According to a second aspect, there is provided a semiconductor structure, comprising:

[0097] A layer stack, comprising:

[0098] A first sub-stack including a first sacrificial layer and a channel layer defining the topmost layer of the first sub-stack on the first sacrificial layer;

[0099] A second sub-stack on the first sub-stack and including a plurality of layers alternating between the first sacrificial layer and a first dielectric material layer, wherein the first sacrificial layer defines the respective bottommost and topmost layers of the second sub-stack;

[0100] A third sub-stack on the second sub-stack and including a channel layer defining the bottommost layer of the third sub-stack and a first sacrificial layer on the channel layer;

[0101] wherein the first sacrificial layer is formed of a first sacrificial semiconductor material;

[0102] A gate structure disposed on the layer stack;

[0103] A second dielectric material disposed on an end face of the gate structure;

[0104] wherein the second dielectric material is different from the first dielectric material.

[0105] The device according to the second aspect may have the same or similar advantages as those described in connection with the first aspect.

[0106] Based on the discussion of the method according to the first aspect, the second dielectric material of the device may have a dielectric constant lower than 6.5. Thus, the second dielectric material may have a dielectric constant lower than 6, or lower than 5.5, or lower than 5, or lower than 4.5. Description of the Drawings

[0107] The above and other objects, features and advantages of the inventive concept will be better understood from the following detailed description, which is illustrative and non - limiting, with reference to the accompanying drawings. Unless otherwise indicated, the same reference numerals will be used for the same elements in the drawings.

[0108] Figure 1a -g illustrates a method for forming a semiconductor structure according to some embodiments.

[0109] Figure 2a -b to 8a - b show some alternative steps for implementing the FET finished stack.

[0110] Figure 9a -c illustrates the use of a liner. Detailed Description of the Preferred Embodiments

[0111] In conjunction with the accompanying drawings, the technical content and detailed description of the present invention are described below according to preferred embodiments, which are not used to limit the scope of the claimed invention. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided for thoroughness and completeness and to fully convey the scope of the present invention to those skilled in the art.

[0112] Figure 1a -g shows one implementation of a method for forming a semiconductor structure. Figure 2a -b to 8a - b show some alternative steps for implementing the FET finished stack.

[0113] Axes X, Y, and Z represent a first direction, a second direction transverse to the first direction, and a vertical or bottom - to - top direction, respectively. Specifically, the X and Y directions may be referred to as transverse or horizontal directions because they are parallel to the main plane of the substrate 102 of the structure 100. The Z direction is parallel to the normal direction of the substrate 102.

[0114] Figure 1a-b depicts corresponding cross-sectional views of the layer stack 110 taken along vertical planes B-B’ (parallel to the XZ plane) and A-A’ (parallel to the YZ plane). Figure 1c is a schematic diagram of the first, second, and third sub-stacks. Unless otherwise specified, Figure 1d -g's cross-sectional view corresponds to Figure 1a the cross-sectional view of, i.e., along the vertical plane B-B’. As Figure 1a shown, the layer stack 110 has a first end 111 and a second end 112.

[0115] The layer stack 110 is disposed on a substrate 102. The substrate 102 can be a conventional semiconductor substrate suitable for complementary FETs. The substrate 102 can be a single-layer semiconductor substrate, for example, formed of a bulk substrate such as a Si substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. However, multi-layer / composite substrates are also possible, such as a semiconductor layer epitaxially grown on a bulk substrate or a semiconductor-on-insulator (SOI) substrate, such as a Si-on-insulator substrate, a Ge-on-insulator substrate, or a SiGe-on-insulator substrate.

[0116] The layer stack 110 includes a first sub-stack 120, a second sub-stack 130 on the first sub-stack 120, and a third sub-stack 140 on the second sub-stack 130.

[0117] For clarity of illustration, Figure 1c the first sub-stack 120 (bottom), the second sub-stack 130 (middle), and the third sub-stack 140 (top) are depicted separately.

[0118] The first sub-stack 120 includes a first sacrificial layer 122a and a channel layer 124 on the first sacrificial layer 122a. The channel layer 124 forms the top (i.e., the uppermost) layer of the first sub-stack 120. The layers 122a and 124 can be referred to as a unit of the first sub-stack 120. Although Figure 1c only one such unit (i.e., a single one) of the first sub-stack 120 is depicted, it should be understood that the first sub-stack 120 can include more than just a single unit. For example, the first sub-stack 120 can include, for example, two, three, or four etc. units. Thus, the first sub-stack 120 can include two, three, or four etc. first sacrificial layers 122a and channel layers 124 respectively. In the case where the first sub-stack 120 includes multiple such units, the units can be arranged coherently. For example, these units can be stacked on top of each other.

[0119] The second sub-stack 130 includes a plurality of sacrificial layers alternating between a first sacrificial layer 132a and a second sacrificial layer 132b.

[0120] Figure 1cThe second sub-stack 130 is shown, which includes (in a bottom-up direction) a bottommost first sacrificial layer 132a, a second sacrificial layer 132b, a first sacrificial layer 132a, a second sacrificial layer 132b, and a topmost first sacrificial layer 132a. Thus, the bottommost first sacrificial layer 132 is disposed on the first sub-stack 120, i.e., on the channel layer 124. Although Figure 1c only two second sacrificial layers 132b of the second sub-stack 130 are depicted, it should be understood that the second sub-stack 130 may include more than two second sacrificial layers 132b. It is also conceivable that the second sub-stack 130 may include one (i.e., a single) second sacrificial layer 132b.

[0121] The third sub-stack 140 includes a channel layer 144 and a first sacrificial layer 142a on the channel layer 144. The channel layer 144 forms the bottom layer (i.e., the bottommost layer) of the third sub-stack 140. Thus, the channel layer 144 is disposed on the second sub-stack 130, i.e., on the topmost first sacrificial layer 132a. The layers 144 and 142a may be referred to as a unit of the third sub-stack 140. Although Figure 1c only one such unit (i.e., a single) of the third sub-stack 140 is depicted, it should be understood that the third sub-stack 140 may include more than just a single unit. For example, the third sub-stack 140 may include, for example, two, three, or four etc. units. Thus, the third sub-stack 140 may include two, three, or four etc. first sacrificial layers 142a and channel layers 144 respectively. In the case where the third sub-stack 140 includes a plurality of such units, the units may be arranged coherently. For example, these units may be stacked on top of each other.

[0122] The first sacrificial layers (122a, 132a, 142a) of the first to third sub-stacks 120, 130, 140 and the second sacrificial layers of the first to third sub-stacks 120, 130, 140 may be formed to have a uniform or at least similar thickness. It is also conceivable that the second sacrificial layer may be formed to have a greater thickness than each of the first sacrificial layers of the first to third sub-stacks 120, 130, 140 (122a, 132a, 142a). The total thickness of the second sub-stack 130 may accordingly exceed the thickness of each of the first sacrificial layers of the first sub-stack 120 and the third sub-stack 140.

[0123] The channel layers 124 of the first and third sub-stacks 120, 140 may also have a uniform or at least similar thickness, for example a thickness different from or the same as that of the first sacrificial layer of the layer stack 110.

[0124] For example, the channel layers of the first and third sub-stacks 120, 140 can each be formed to have a thickness of 3 - 10 nm, the first sacrificial layers (122a, 132a, 142a) of the first to third sub-stacks 120, 130, 140 can each be formed to have a thickness of 3 - 10 nm, and the second sacrificial layer 132b can be formed to have a thickness of 5 - 30 nm. The total thickness of the second sub-stack 130 can be, for example, 20 - 50 nm.

[0125] The material of the channel layer can be Si 1-a Ge a , the first sacrificial material can be Si 1-c Ge c , and the second sacrificial material can be Si 1-d Ge d , where 0 ≤ a < c < d. For example, c can be in the range of 0.1 - 0.25. In addition, d can be in the range of 0.35 - 0.5. In a more specific example, the channel material can be Si (i.e., a = 0), the first sacrificial material can be Si 0.75 Ge 0.25 , and the second sacrificial material can be Si 0.5 Ge 0.5 . These relative differences in Ge content facilitate the selective processing (e.g., selective etching) of the different sacrificial layers and channel layers (as well as the liner layer discussed in connection with FIG. 9) of the layer stack 110.

[0126] Each layer of the device layer stack 110 can be an epitaxial layer, for example, epitaxially grown using deposition techniques known per se such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). This results in high-quality material layers with favorable compositional and dimensional control.

[0127] The deposited layers can be formed sequentially and then patterned to define an elongated fin-shaped layer stack extending in the X direction. The dashed line 110' schematically indicates the contour of the layer stack 110 after fin patterning and before fin slotting, as described below. Although the drawings depict only a single layer stack, it should be understood that multiple parallel fin-shaped layer stacks can be formed. Conventional fin patterning techniques can be used, such as single patterning techniques such as lithography and etching ("litho-etching") or multiple patterning techniques such as (litho-etching) x , self-aligned double or quadruple patterning (SADP or SAQP)).

[0128] Each layer of the layer stack 110 can be formed as a nanosheet, for example, the ratio of the width (along Y) to the thickness (along Z) is greater than 1, for example, the width is in the range of 10 nm to 30 nm, and the thickness is in the range of 3 nm to 10 nm. The layer stack can also be patterned such that the channel layer forms a layer in the shape of a nanowire. For example, the nanowire can have a thickness similar to that of the example nanosheet, but a smaller width, for example, 3 nm to 10 nm.

[0129] As Figure 1a -b shows, after fin patterning, the lower part of the device layer stack 110 can be surrounded by a shallow trench isolation (STI) 104 such as SiO2.

[0130] As Figure 1a -b further shows, a gate structure 250 in the form of a sacrificial gate body 152 can be formed to extend across the layer stack 110. As shown in the figure, the gate structure 250 includes two end faces 255. The sacrificial gate bodies 250, 152 can be formed by depositing a sacrificial gate body material (such as amorphous silicon) on the layer stack 110 and then patterning the sacrificial gate bodies 250, 152 therein. Although the drawings only depict the sacrificial gate bodies 250, 152, it should be understood that multiple parallel sacrificial gate structures can be formed across the layer stack 110. Conventional patterning techniques can be used, such as a single patterning technique, such as photolithography and etching ("litho-etching") or multiple patterning techniques, such as (lithography-etching) x , SADP or SAQP.

[0131] On top of the sacrificial gate bodies 250, 152, there can be a capping layer 156, for example, formed by one or more remaining hard mask materials from the sacrificial gate body patterning.

[0132] As Figure 1a -b shows, the layer stack 110 can also include a bottom second sacrificial layer 116. The bottom second sacrificial layer 116 can be disposed between the substrate 102 and the first sub-stack 120.

[0133] The bottom second sacrificial layer 116 can undergo the same processing steps as the second sacrificial layer 132b of the second sub-stack 130 (and the first sacrificial layer of the sub-stacks 120, 130, 140).

[0134] During the manufacturing process, the bottom second sacrificial layer 116 can be replaced with a dielectric material, for example, replaced with a first dielectric material 201, as shown later. The dielectric material replacing the bottom second sacrificial layer 116 can form the bottom dielectric isolation of the FET finished stack.

[0135] The use of the bottom dielectric isolation is optional. Therefore, the use of the bottom second sacrificial layer 116 is optional.

[0136] Figure 1d shows the removal of the second sacrificial layer 132b of the second sub-stack 130. In Figure 1d , the second sacrificial layer 132b of the second sub-stack 130 has been removed by selectively etching the second sacrificial semiconductor material, thereby forming a cavity 135 in the second sub-stack 130. An isotropic etching process (wet or dry) can be used to etch the second sacrificial semiconductor material to etch back the end face of the second sacrificial layer 132b laterally from the opposite ends of the layer stack 110. For example, HCl-based dry etching can be used to remove the second sacrificial layer material, such as a second sacrificial material having a higher Ge content than the first sacrificial material. However, other suitable etching processes (such as wet etching processes) are also known in the art and can also be used for this purpose.

[0137] After forming the cavity 135, a first dielectric material 201 is deposited to fill the cavity 135. A first dielectric material 201 having a dielectric constant lower than 6.5 can be used. The first dielectric material 201 can be or include, for example, SiN, or SiOC, or SiOCN, or SiCN.

[0138] As Figure 1e shown, the first dielectric material 201 can be deposited to fill the cavity 135 and also cover the end face 255 of the gate structure 250. In this case, as Figure 1f shown, a dielectric-free gate surface can be provided by removing the first dielectric material 201 from the end face of the gate structure 250. This corresponds to the first way of providing a dielectric-free gate surface described above.

[0139] Alternatively, the first dielectric material 201 can be deposited by a method that does not deposit on the end face 255 of the gate structure 250. In this case, the situation shown in Figure 1e will not occur. Instead, after depositing the first dielectric material 201, the layer stack 110 can be directly as Figure 1f shown, without the need to remove the first dielectric material 201 from the end face 255 of the gate structure 250. This corresponds to the second way of providing a dielectric-free gate surface described above.

[0140] In the first way of providing a dielectric-free gate surface, the first dielectric material 201 can be deposited by a conformal deposition method (such as ALD). Alternatively, the first dielectric material 201 can be deposited by the first CVD method discussed below.

[0141] In the second way of providing a dielectric-free gate surface, the first dielectric material 201 can be deposited by a deposition method configured to preferentially deposit in the cavity 135. Such a deposition method can be the first CVD method.

[0142] The first CVD method may include:

[0143] reacting an oxygen-containing silicon compound gas as a film-forming gas with the non-oxidizing hydrogen-containing gas in a state where at least the non-oxidizing hydrogen-containing gas is plasmaized to form a film of a flowable silanol compound; and

[0144] subsequently annealing the film of the flowable silanol compound into a first dielectric material,

[0145] wherein the oxygen-containing silicon compound gas includes Si α O β (O-C m H n ) Γ C x H y , where m, n, and α are integers of 1 or greater; and where β, Γ, x, and y are integers of 0 or greater; and β and Γ are not both 0.

[0146] If the first dielectric material 201 has been deposited on the end face 255 of the gate structure 250, it can be removed by etching. For example, any suitable isotropic etching process (wet or dry) for etching a dielectric material (such as SiN) can be used.

[0147] Figure 1g It shows that the second dielectric material 202 is deposited on the dielectric-free gate surface. Here, the second dielectric material 202 is different from the first dielectric material 201. The second dielectric material 202 can be deposited by a conformal deposition method (such as ALD). The second dielectric material 202 can include SiOCN and / or SiOC. As shown, the second dielectric material 202 can also cover the ends 111, 112 of the layer stack 110.

[0148] Hereinafter, some alternative further steps for implementing the FET finished stack will be discussed in conjunction with Figure 2a -b to 8a-b. Figure 2a -b depicts corresponding cross-sectional views of the layer stack 110 taken along the vertical planes B-B' (parallel to the XZ plane) and A-A' (parallel to the YZ plane). Unless otherwise specified, the cross-sectional views of the subsequent figures correspond to Figure 2a the cross-sectional views in -b.

[0149] Figure 2a-b shows that the ends 111, 112 of the layer stack 110 can be removed by vertical slitting. Thus, vertical grooves 103 are formed, which may be referred to as source / drain grooves 103. The vertical slitting can be performed by anisotropic etching (e.g., dry anisotropic etching). As shown, the second dielectric material 202 covering the ends 111, 112 of the layer stack 110 can also be removed by the vertical slitting.

[0150] Figure 3a -b shows that after the source / drain grooves 103 are formed, the end faces of the first sacrificial layers 122a, 132a, 142a of the layer stack 110 can be laterally slit to form grooves 160.

[0151] In Figure 3a -b, by selectively etching the end faces of each first sacrificial layer of the layer stack 110 from opposite ends of the layer stack 100 (e.g., along the X direction and the negative X direction), grooves 160 have been formed in the layer stack 110. The lateral etching-back can be achieved by an isotropic etching process. Any suitable dry etching process or wet etching process (e.g., HCl or APM) that allows selective etching of the first sacrificial material can be used. As Figure 3a shown, the degree of lateral etching-back can correspond to the thickness of the first dielectric material 201 on the corresponding end faces 255 of the gate structure 250.

[0152] In Figure 4a -b, the grooves 160 have been filled with one or more conformally deposited inner spacer materials. Examples of inner spacer materials include conformally deposited dielectric materials such as oxides, nitrides, or carbides. In one example, a single inner spacer material (e.g., SiN) can be deposited to fill the grooves 160. In another example, a first inner spacer material (e.g., SiOC) can be deposited to partially fill the grooves 160, where a second inner spacer material (e.g., SiN) can be deposited to fill the remaining space in the grooves 160 (by pinching off). By subjecting the inner spacer material to an isotropic etching process to remove the portions of the inner spacer material deposited outside the grooves 160, inner spacers 162 have been formed in the grooves 160. Any suitable isotropic etching process (wet or dry) for etching dielectric materials (e.g., SiN or SiN and SiOC) can be used. As shown, when the end faces of the channel layer of the device layer stack 110 are exposed, the etching can stop, and discrete portions of the inner spacer material remain in the grooves 160 to form the inner spacers 162.

[0153] In Figure 5a-b, source and drain regions 164 and 166 have been formed on the channel layers of the first sub-stack 120 and the third sub-stack 140, respectively. The source and drain regions 164, 166 have been formed by epitaxially growing a semiconductor material on the end faces of the channel layers exposed at opposite ends of the sacrificial gate structure 150.

[0154] The source and drain regions 164 formed on the end face of the channel layer of the first sub-stack 120 may be of a first conductivity type, while the source and drain regions 166 formed on the end face of the channel layer of the third sub-stack 140 may be of a second opposite conductivity type. The first and second conductivity types may be p-type and n-type, or vice versa. Doping may be achieved by in-situ doping. When epitaxy is performed on the end face of the channel layer of the first sub-stack 120, source and drain regions 164 of different conductivity types and source and drain regions 166 may be achieved by masking the end face of the channel layer of the third sub-stack 140. Masking of the end face of the channel layer of the third sub-stack may be provided, for example, by forming a temporary capping spacer along the third sub-stack. After the epitaxy of the source and drain regions 164 is completed, the temporary capping spacer may be removed, and the source and drain regions 164 may be covered with one or more dielectric materials (e.g., ALD-deposited SiN and an interlayer dielectric such as SiO2). Then epitaxy may be performed on the end face of the channel layer of the third sub-stack 140. However, this is merely an example, and other process techniques facilitating the formation of source and drain regions 164, 166 of different conductivity types may also be used.

[0155] As shown, the source and drain regions 164, 166 may subsequently be embedded in an insulating layer 170 or covered by the insulating layer 170. The insulating layer 170 may be formed of an insulating material such as an oxide, e.g., SiO2, or another interlayer dielectric, and may be deposited, planarized, and grooved by chemical mechanical polishing (CMP) and / or etchback. CMP and / or etchback may continue to also remove any capping 156 of the sacrificial gate structure 150. However, it is also possible to stop CMP and / or etchback on the capping 156 and subsequently use a separate etching step to open the capping.

[0156] In Figure 6a -b, a gate trench 172 has been formed by removing the sacrificial gate bodies 250, 152 between the opposing second dielectric materials 202. Any conventional suitable etching process (isotropic or anisotropic, wet or dry) allowing selective removal of the sacrificial gate bodies 250, 152 (e.g., amorphous silicon) may be used.

[0157] In Figure 7a-b, the first sacrificial layer of the device layer stack 110 has been removed by selectively etching the first sacrificial semiconductor material from the gate trench 172. The same type of etching process as during the formation of the recess 160 can be used for this step. By removing the first sacrificial layer, the channel layer of the device layer stack 110 can be released in the sense that its upper and lower surfaces can be exposed within the gate trench 172.

[0158] In FIG. 8-b, the gate stack 180 has replaced the sacrificial gate body 152 and the first sacrificial layer.

[0159] The gate stack 180 includes a gate dielectric layer (not shown); one or more work function metals WFM; and a gate fill metal 178. Hereinafter, the gate stack 180 including the first WFM 174 and the second WFM 176 will be described. For the FET stack 1000 including both NFET and PFET, at least two WFMs may be required. Figure 8a FIG. 8-b shows a FET stack 1000 including a first FET 1001 and a second FET 1002. In the illustration, one of the first FET 1001 and the second FET 1002 is a NFET, and the other is a PFET. Thus, the FET stack 1000 forms a CFET.

[0160] The gate dielectric layer can be conformally deposited in the gate trench 172 to conformally coat the channel layer. The gate dielectric layer can be formed of a conventional high-k dielectric, such as HfO2, HfSiO, LaO, AlO, or ZrO.

[0161] Subsequently, the first WFM 174 can be conformally deposited in the gate trench 172. The first WFM 174 can be formed of one or more effective WFMs (e.g., an n-type WFM such as TiAl or TiAlC and / or a p-type WFM such as TiN or TaN). The first WFM 174 can thus surround the channel layer of the first sub-stack 120.

[0162] Subsequently, for example, using a blocking mask as an etch mask, the first WFM 174 can be removed from the channel layer of the third sub-stack 140. The first WFM 174 surrounding the channel layer of the first sub-stack 120 can be retained. The second WFM 176 can be deposited on the gate dielectric surrounding the channel layer of the third sub-stack 140 and on portions of the first dielectric material 201. The second WFM 176 can thus surround the channel layer of the third sub-stack 140. The second WFM 176 can thus surround the first WFM 174 of the first sub-stack 120.

[0163] The gate dielectric layer and / or the first WFM 174 and / or the second WFM 176 can be conformally deposited, for example, by ALD.

[0164] Subsequently, a gate fill metal 178 (such as W or Al) can be deposited to fill the remaining space of the gate trench 172. The gate fill metal 176 can be deposited, for example, by CVD or PVD.

[0165] In the above discussion, the layer stack 110 without the liner 133 was used. However, the liner 133 can be advantageously used. Thus, the adjacent first sacrificial layer 132a and the second sacrificial layer 132b of the second sub-stack 130 can be separated by the liner 133, and the liner 133 of the second sub-stack 130 is formed of a semiconductor material different from the first sacrificial semiconductor material 201 and the second sacrificial semiconductor material 202.

[0166] Figure 9a -c illustrates the principle of the liner 133.

[0167] Figure 9a A cross-sectional view of the layer stack 110 including the liner 133 is depicted. The layer stack 110 includes a first sub-stack 120, a second sub-stack 130 on the first sub-stack 120, and a third sub-stack 140 on the second sub-stack 130. The first sub-stack 120 and the third sub-stack 140 can be described similar to the first sub-stack 120 and the third sub-stack 140 discussed in conjunction with Figure 1a discussion. The second sub-stack 130 can be described similar to the second sub-stack 130 discussed in conjunction with Figure 1a discussion, but a liner 133 is added between the adjacent first sacrificial layer 132a and the second sacrificial layer 132b of the second sub-stack 130. Thus, it can be said that each liner 133 can be adjacent to the corresponding first sacrificial layer 132a and the second sacrificial layer 132b separated by it.

[0168] For clarity of illustration, Figure 9b the first sub-stack 120 (bottom), the second sub-stack 130 (middle), and the third sub-stack 140 (top) are depicted separately.

[0169] As described above, the liner 133 is formed of a semiconductor material different from the first and second semiconductor materials. For example, the channel material can be Si 1-a Ge a , the liner material can be Si 1-b Ge b , the first sacrificial material can be Si 1-c Ge c , and the second sacrificial material can be Si 1-d Ge d, where 0 ≤ a ≤ b < c < d. For example, b can be in the range of 0 - 0.05. In addition, c can be in the range of 0.1 - 0.25. In addition, d can be in the range of 0.35 - 0.5. In a more specific example, the channel material can be Si (i.e., a = 0), the liner material can be Si (i.e., b = 0), the first sacrificial material can be Si 0.75 Ge 0.25 , and the second sacrificial material can be Si 0.5 Ge 0.5 . These relative differences in Ge content facilitate the selective processing (e.g., selective etching) of the different sacrificial layers, liner 133, and channel layer of the layer stack 110.

[0170] The liner 133 can be formed by epitaxial growth. The liner 133 can be formed to a thickness of 1 - 5 nm.

[0171] Figure 9c FIG. depicts a cross-sectional view of the layer stack 110 including the liner 133 after removing the second sacrificial layer 132b of the second sub-stack 130.

[0172] As Figure 9c further shown, the liner 133 can prevent the rounding of the corners of the first sacrificial layer 132a of the second sub-stack 130. When the second sacrificial layer 132b of the second sub-stack 130 is etched, due to the protective liner 133, the etchant cannot attack the first sacrificial layer 132a via the formed cavity 135. Therefore, the first sacrificial layer 132a of the second sub-stack 130 can be attacked laterally only via the groove 160 of the second sub-stack 130.

[0173] Above, the inventive concept has been described mainly with reference to a limited number of examples. However, as will be readily understood by those skilled in the art, within the scope of the inventive concept defined by the appended claims, other examples besides the ones disclosed above are equally possible.

Claims

1. A method for forming a semiconductor structure (100), the method comprising: A layer stack (110) is formed on a substrate (102), the layer stack comprising: A first sub-stack (120), the first sub-stack comprising a first sacrificial layer (122a) and a channel layer (124) on the first sacrificial layer (122a) defining a topmost layer of the first sub-stack (120); a second substack (130) on the first substack (120) and comprising a plurality of sacrificial layers alternating between first sacrificial layers (132a) and second sacrificial layers (132b), wherein the first sacrificial layers (132a) define the bottommost and topmost layers of the second substack (130), the second substack comprising at least one second sacrificial layer (132b); A third sub-stack (140) located on the second sub-stack (130) and comprising a channel layer (144) defining the bottommost layer of the third sub-stack (140) and a first sacrificial layer (142a) on the channel layer (144); The first sacrificial layer is formed of a first sacrificial semiconductor material, and the second sacrificial layer is formed of a second sacrificial semiconductor material different from the first sacrificial semiconductor material, forming a gate structure (250) on the layer stack; forming at least one cavity (135) by removing the at least one second sacrificial layer (132b) of the second sub-stack (130); depositing a first dielectric material (201), wherein the act of depositing the first dielectric material (201) comprises filling the at least one cavity (135) with the first dielectric material (201); Providing a dielectric-free gate surface, the dielectric-free gate surface being an end surface (255) of the gate structure (250) that is free of the first dielectric material (201); and Depositing a second dielectric material (202) on the dielectric-free gate surface, wherein the second dielectric material (202) is different from the first dielectric material (201); The action (202) of depositing the second dielectric material is performed after the action (201) of depositing the first dielectric material.

2. The method according to claim 1, characterized in that: The dielectric constant of the second dielectric material is lower than 6.

5.

3. The method according to claim 1 or 2, characterized in that: The second dielectric material (202) includes SiOCN and / or SiOC.

4. The method according to any one of the preceding claims, characterized in that The first dielectric material (201) is SiN, or SiOC, or SiOCN or SiCN.

5. The method according to any one of the preceding claims, characterized in that During said act of filling said at least one cavity (135) with said first dielectric material (201), said first dielectric material (201) is also deposited on said end surface (255) of said gate structure (250); and The act of forming the dielectric-free gate surface includes removing a first dielectric material (201) from the end surface (255) of the gate structure (250).

6. The method according to claim 5, characterized in that Removing the first dielectric material (201) from the end surface (255) of the gate structure (250) is performed by dry isotropic etching.

7. The method according to any one of the preceding claims, characterized in that The step of depositing the first dielectric material (201) is performed by a first chemical vapor deposition (CVD) method, wherein the first CVD method comprises: In a state where at least the non-oxidizing hydrogen-containing gas is plasmatized, reacting an oxygen-containing silicon compound gas as a film-forming gas with the non-oxidizing hydrogen-containing gas to form a flowable silanol compound film; and subsequently annealing the film of flowable silanol compound into the first dielectric material, The oxygen-containing silicon compound gas includes Si α O β (OC m H n ) Γ C x H y , wherein m, n and α are integers of 1 or greater; and wherein β, Γ, x and y are integers of 0 or greater; and β and Γ are not 0 at the same time.

8. The method according to any one of the preceding claims, characterized in that The act of depositing the second dielectric material (202) is performed by atomic layer deposition.

9. The method according to any one of the preceding claims, characterized in that The method further comprises: Removing the end of the layer stack (110) and the second dielectric material (202) on the end by vertically slotting; Subsequently, the end surface of the first sacrificial layer (122a, 132a, 142a) of the layer stack (110) is grooved in a transverse direction to form a groove (160); and An inner spacer (162) is formed in the groove (160).

10. The method according to any one of the preceding claims, characterized in that The second sub-stack (130) includes at least two second sacrificial layers (132b), so that at least two cavities (135) are formed and filled with the first dielectric material (201).

11. The method according to any one of the preceding claims, characterized in that The gate structure (250) is a sacrificial gate body (152), and the method further comprises: The sacrificial gate body (152) is replaced with a gate stack (180).

12. The method according to claim 11, characterized in that The method further comprises: forming source / drain regions (164) at opposite ends of the channel layer (124) of the first sub-stack (120); and forming source / drain regions (166) at opposite ends of the channel layer (144) of the third sub-stack (140); The semiconductor structure (100) forms a stack of field effect transistors FET (1000), the stack comprising: A first FET (1001) comprising a channel layer (124) of the first sub-stack (120); and A second FET (1002) includes a channel layer (144) of the second sub-stack (140).

13. The method according to any one of the preceding claims, characterized in that The adjacent first sacrificial layer (132a) and second sacrificial layer (132b) of the second sub-stack (130) are separated by a liner (133), and the liner (133) of the second sub-stack (130) is formed of a semiconductor material different from the first sacrificial semiconductor material (201) and the second sacrificial semiconductor material (202).

14. A semiconductor structure (100), comprising: A layer stack (110) comprising: A first sub-stack (120), the first sub-stack comprising a first sacrificial layer (122a) and a channel layer (124) on the first sacrificial layer (122a) defining a topmost layer of the first sub-stack (120); a second substack (130) on the first substack (120) and comprising a plurality of layers alternating between first sacrificial layers (132a) and layers of a first dielectric material (201), wherein the first sacrificial layers (132a) define respective bottom-most and top-most layers of the second substack (130); A third sub-stack (140) located on the second sub-stack (130) and comprising a channel layer (144) defining the bottommost layer of the third sub-stack (140) and a first sacrificial layer (142a) on the channel layer (144); wherein the first sacrificial layer (122a, 132a, 142a) is formed of a first sacrificial semiconductor material (201); a gate structure (250) arranged on the layer stack (110); A second dielectric material (202) disposed on an end surface (255) of the gate structure (250); The second dielectric material (202) is different from the first dielectric material (201).

15. The semiconductor structure (100) according to claim 14, characterized in that: The dielectric constant of the second dielectric material (202) is lower than 6.5.

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